ST72324Bxx
8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI
Features
Memories
8 to 32 Kbyte dual voltage High Density Flash (HDFlash) or ROM with readout protection capability. In-application programming and Incircuit programming for HDFlash devices 384 bytes to 1 Kbyte RAM HDFlash endurance: 1 kcycles at 55 C, data retention 40 years at 85C
LQFP44 10 x 10
LQFP32 7x7
SDIP42 600 mil
SDIP32 400 mil
Clock, reset and supply management
4 timers
Enhanced low voltage supervisor (LVD) with programmable reset thresholds and auxiliary voltage detector (AVD) with interrupt capability Clock sources: crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input PLL for 2x frequency multiplication 4 power saving modes: Slow, Wait, Active Halt, and Halt
Main clock controller with Real-time base, Beep and Clock-out capabilities Configurable watchdog timer 16-bit Timer A with 1 input capture, 1 output compare, ext. clock input, PWM and pulse generator modes 16-bit Timer B with 2 input captures, 2 output compares, PWM and pulse generator modes
Interrupt management
2 communication interfaces
Nested interrupt controller. 10 interrupt vectors plus TRAP and RESET. 9/6 ext. interrupt lines (on 4 vectors)
SPI synchronous serial interface SCI asynchronous serial interface
Up to 32 I/O ports
1 analog peripheral (low current coupling)
32/24 multifunctional bidirectional I/Os, 22/17 alternate function lines, 12/10 high sink outputs Device summary
Memory Flash/ROM 8 Kbytes Flash/ROM 16 Kbytes Flash/ROM 32 Kbytes Flash/ROM 8 Kbytes Flash/ROM 16 Kbytes Flash/ROM 32 Kbytes
10-bit ADC with up to 12 input ports
Development tools
In-circuit testing capability
Voltage range Temp. range Package LQFP32 7x7/ SDIP32 LQFP44 10x10/ SDIP42
Table 1.
Device
RAM (stack) 384 (256) bytes 512 (256) bytes 1024 (256) bytes 384 (256) bytes 512 (256) bytes 1024 (256) bytes
ST72324BK2 ST72324BK4 ST72324BK6 ST72324BJ2 ST72324BJ4 ST72324BJ6
3.8 to 5.5V
up to -40 to 125C
October 2007
Rev 6
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www.st.com 1
Contents
ST72324B
Contents
1 2 3 4 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 4.2 4.3 4.4 4.5 4.6 4.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3.1 Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.7.1 Flash Control/Status Register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5
Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1 5.2 5.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Condition Code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Stack Pointer register (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6
Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1 6.2 6.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PLL (phase locked loop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.3.1 6.3.2 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Cr ystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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Contents Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4 6.5
Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.4.1 Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.5.1 6.5.2 6.5.3 6.5.4 LVD (low voltage detector) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 AVD (auxiliary voltage detector) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.6
SI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.6.1 System integrity (SI) control/status register (SICSR) . . . . . . . . . . . . . . . 34
7
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2.1 7.2.2 7.2.3 7.2.4 Servicing pending interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Different interrupt vector sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Non-maskable sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Maskable sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.3 7.4 7.5
Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.5.1 7.5.2 CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Interrupt software priority registers (ISPRx) . . . . . . . . . . . . . . . . . . . . . . 41
7.6
External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.6.1 7.6.2 I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . 44
8
Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.1 8.2 8.3 8.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Active Halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.4.1 8.4.2 Active Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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9.1 9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.2.1 9.2.2 9.2.3 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.3 9.4 9.5
I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.5.1 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
10.1 Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
10.1.1 10.1.2 10.1.3 10.1.4 10.1.5 10.1.6 10.1.7 10.1.8 10.1.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 How to program the Watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . 61 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Hardware Watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Using Halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . 63 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10.2
Main clock controller with real-time clock and beeper (MCC/RTC) . . . . . 64
10.2.1 10.2.2 10.2.3 10.2.4 10.2.5 10.2.6 10.2.7 Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Real-time clock (RTC) timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 MCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.3
16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 10.3.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
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Contents 16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
10.4
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 10.4.6 10.4.7 10.4.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.5
Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.5.1 10.5.2 10.5.3 10.5.4 10.5.5 10.5.6 10.5.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 SCI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
10.6
10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
10.6.1 10.6.2 10.6.3 10.6.4 10.6.5 10.6.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
11
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
11.1 CPU addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
11.1.1 11.1.2 11.1.3 11.1.4 11.1.5 11.1.6 11.1.7 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
11.2
Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
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12
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
12.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
12.1.1 12.1.2 12.1.3 12.1.4 12.1.5 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
12.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
12.2.1 12.2.2 12.2.3 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.3 12.4
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 LVD/AVD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
12.4.1 12.4.2 Operating conditions with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . 140
12.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
12.5.1 12.5.2 12.5.3 12.5.4 ROM current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Flash current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Supply and clock managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12.6
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.6.1 12.6.2 12.6.3 12.6.4 12.6.5 General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Cr ystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 145 RC oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.7
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
12.7.1 12.7.2 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
12.8
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
12.8.1 12.8.2 12.8.3 Functional electromagnetic susceptibility (EMS) . . . . . . . . . . . . . . . . . 150 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 152
12.9
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.9.1 12.9.2 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
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ST72324B
Contents
12.10 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.10.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12.10.2 ICCSEL/VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.11 Timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.11.1 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.12 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 161
12.12.1 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
12.13 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
12.13.1 Analog power supply and reference pins . . . . . . . . . . . . . . . . . . . . . . . 165 12.13.2 General PCB design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 12.13.3 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
13
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
13.1 13.2 13.3 13.4 13.5 13.6 LQFP44 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 SDIP42 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 LQFP32 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 SDIP32 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
14
Device configuration and ordering information . . . . . . . . . . . . . . . . 172
14.1 Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
14.1.1 14.1.2 Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Flash ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
14.2 14.3
ROM device ordering information and transfer of customer code . . . . . 176 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
14.3.1 14.3.2 14.3.3 14.3.4 14.3.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Evaluation tools and starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Socket and emulator adapter information . . . . . . . . . . . . . . . . . . . . . . 179
14.4
ST7 Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
15
Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
15.1 All Flash and ROM devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
15.1.1 Safe connection of OSC1/OSC2 pins . . . . . . . . . . . . . . . . . . . . . . . . . 180
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Contents 15.1.2 15.1.3 15.1.4 15.1.5 15.1.6 15.1.7
ST72324B External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . 182 16-bit timer PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 TIMD set simultaneously with OC interrupt . . . . . . . . . . . . . . . . . . . . . 183 SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
15.2
8/16 Kbyte Flash devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
15.2.1 15.2.2 39-pulse ICC entry mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Negative current injection on pin PB0 . . . . . . . . . . . . . . . . . . . . . . . . . 184
15.3
8/16 Kbyte ROM devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
15.3.1 15.3.2 Readout protection with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 I/O Port A and F configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
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ST72324B
Description
1
Description
The ST72324B devices are members of the ST7 microcontroller family designed for midrange applications running from 3.8 to 5.5V. Different package options offer up to 32 I/O pins. All devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set and are available with Flash or ROM program memory. The ST7 family architecture offers both power and flexibility to software developers, enabling the design of highly efficient and compact application code. The on-chip peripherals include an A/D converter, two general purpose timers, an SPI interface and an SCI interface. For power economy, the microcontroller can switch dynamically into, Slow, Wait, Active Halt or Halt mode when the application is in idle or stand-by state. Typical applications include consumer, home, office and industrial products. Figure 1. Device block diagram
8-bit CORE ALU
Program memor y (8 - 32 Kbytes) RAM (384 - 1024 bytes)
RESET VPP VSS VDD
CONTROL
LVD WATCHDOG OSC ADDRESS AND DATA BUS MCC/RTC/BEEP
OSC1 OSC2
PORT A
PORT F
PF7:6, 4, 2:0 (6 bits on J devices) (5 bits on K devices)
PA7:3 (5 bits on J devices) (4 bits on K devices)
TIMER A BEEP PORT E
PORT B
PB4:0 (5 bits on J devices) (3 bits on K devices)
PE1:0 (2 bits)
SCI
PORT C TIMER B PORT D
PC7:0 (8 bits)
PD5:0 (6 bits on J devices) (2 bits on K devices) V ARE F VSSA
SPI 10-bit ADC
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Pin description
ST72324B
2
Pin description
Figure 2. 44-pin LQFP package pinout
PE0/TDO VDD_2 OSC1 OSC2 VSS_2 RESET VPP/ICCSEL PA7 (HS) PA6 (HS) PA5 (HS) PA4 (HS) RDI / PE1 PB0 PB1 PB2 PB3 (HS) PB4 AIN0/PD0 AIN1/PD1 AIN2/PD2 AIN3/PD3 AIN4/PD4
44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 3 ei0 31 ei2 4 30 5 29 ei3 6 28 7 27 8 26 9 25 ei1 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22
V SS_1 VDD_1 PA3 (HS) PC7/SS/AIN15 PC6/SCK/ICCCLK PC5/MOSI/AIN14 PC4 / MISO/ICCDATA PC3 (HS)/ICAP1_B PC2 (HS)/ICAP2_B PC1/OCMP1_B/AIN13 PC0/OCMP2_B/AIN12
AIN5/PD5 VAREF VSSA MCO/AIN8/PF0 BEEP/(HS) PF1 (HS) PF2 OCMP1_A/AIN10/PF4 ICAP1_A/(HS) PF6 EXTCLK_A/(HS) PF7 VDD_0 V SS_0
(HS) 20mA high sink capability eix associated external interrupt vector
Figure 3.
42-pin SDIP package pinout
(HS) PB4 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4 AIN5 / PD5 VAREF VSSA MCO / AIN8 / PF0 BEEP / (HS) PF1 (HS) PF2 AIN10 / OCMP1_A / PF4 ICAP1_A / (HS) PF6 EXTCLK_A / (HS) PF7 AIN12 / OCMP2_B / PC0 AIN13 / OCMP1_B / PC1 ICAP2_B/ (HS) PC2 ICAP1_B / (HS) PC3 ICCDATA / MISO / PC4 AIN14 / MOSI / PC5
1 ei3 2 3 4 5 6 7 8 9 10 11 ei1 12 13 14 15 16 17 18 19 20 21
ei2
ei0
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
PB3 PB2 PB1 PB0 PE1 / RDI PE0 / TDO VDD_2 OSC1 OSC2 VSS_2 RESET VPP / ICCSEL PA7 (HS) PA6 (HS) PA5 (HS) PA4 (HS) VSS_1 VDD_1 PA3 (HS) PC7 / SS / AIN15 PC6 / SCK / ICCCLK
(HS) 20mA high sink capability eix associated external interrupt vector
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ST72324B Figure 4. 32-pin LQFP package pinout
Pin description
VAREF VSSA MCO/AIN8/PF0 BEEP/(HS) PF1 OCMP1_A/AIN10/PF4 ICAP1_A/(HS) PF6 EXTCLK_A/(HS) PF7 AIN12/OCMP2_B/PC0
32 31 30 29 28 27 26 25 24 1 ei3 ei2 23 2 22 3 ei1 21 4 20 5 19 6 18 7 ei0 17 8 9 10 11 12 13 14 15 16
PD1/AIN1 PD0/AIN0 PB4 (HS) PB3 PB0 PE1/RDI PE0/TDO VDD_2 OSC1 OSC2 VSS_2 RESET VPP/ICCSEL PA7 (HS) PA6 (HS) PA4 (HS) AIN13/OCMP1_B/PC1 ICAP2_B/(HS) PC2 ICAP1_B/(HS) PC3 ICCDATA/MISO/PC4 AIN14/MOSI/PC5 ICCCLK/SCK/PC6 AIN15/SS/PC7 (HS) PA3
(HS) 20mA high sink capability eix associated external interrupt vector
Figure 5.
32-pin SDIP package pinout
(HS) PB4 AIN0 / PD0 AIN1 / PD1 VAREF VSSA MCO / AIN8 / PF0 BEEP / (HS) PF1 OCMP1_A / AIN10 / PF4 ICAP1_A / (HS) PF6 EXTCLK_A / (HS) PF7 AIN12 / OCMP2_B / PC0 AIN13 / OCMP1_B / PC1 ICAP2_B / (HS) PC2 ICAP1_B / (HS) PC3 ICCDATA/ MISO / PC4 AIN14 / MOSI / PC5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
ei3
32 ei2 31 30 29 28
PB3 PB0 PE1 / RDI PE0 / TDO VDD_2 OSC1 OSC2 V SS_2 RESET VPP / ICCSEL PA7 (HS) PA6 (HS) PA4 (HS) PA3 (HS) PC7 / SS / AIN15 PC6 / SCK / ICCCLK
ei1
27 26 25 24 23 22 21 20 ei0 19 18 17
(HS) 20mA high sink capability eix associated external interrupt vector
See Section 12: Electrical characteristics on page 136 for external pin connection guidelines. Refer to Section 9: I/O ports on page 53 for more details on the software configuration of the I/O ports. The reset configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state.
11/188
Pin description Legend / Abbreviations for Table 1: Type: Input level: I = input, O = output, S = supply A = Dedicated analog input
ST72324B
In/Output level: C = CMOS 0.3VDD/0.7DD CT = CMOS 0.3VDD/0.7DD with input trigger Output level: Input: HS = 20mA high sink (on N-buffer only) float = floating, wpu = weak pull-up, int = interrupt(a), ana = analog ports Por t and control configuration: Output: OD = open drain(b), PP = push-pull Table 1.
Pin No. LQFP44 LQFP32 Type SDIP42 SDIP32 Pin Name
Device pin description
Level Output Input Port Input float wpu ana int Output OD PP Main function (after reset) Por t B4 Por t D0 Por t D1 Por t D2 Por t D3 Por t D4 Por t D5 ADC Analog Input 0 ADC Analog Input 1 ADC Analog Input 2 ADC Analog Input 3 ADC Analog Input 4 ADC Analog Input 5
Alternate Function
6 7 8 9 10 11 12 13 14
1 2 3 4 5 6 7 8 9
30 31 32
1 2 3
PB4 (HS) PD0/AIN0 PD1/AIN1 PD2/AIN2 PD3/AIN3 PD4/AIN4 PD5/AIN5
I/O CT HS I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT S S
X X X X X X X
ei3 X X X X X X X X X X X X
X X X X X X X
X X X X X X X
1 2 3 4
4 5 6 7
VAREF
(1)
Analog Reference Voltage for ADC Analog Ground Voltage X X X X ei1 ei1 ei1 X X X X X X X X X X X Por t F0 Por t F1 Por t F2 Por t F4 Timer A Output Compare 1 ADC Analog Input 10 Main clock out (fCPU) ADC Analog Input 8
VSSA(1)
15 10 16 11 17 12 18 13
PF0/MCO/AIN8 I/O CT PF1 (HS)/BEEP I/O CT HS PF2 (HS) I/O CT HS
Beep signal output
5
8
PF4/OCMP1_A/ I/O CT AIN10 PF6 (HS)/ICAP1_A PF7 (HS)/ EXTCLK_A I/O CT HS I/O CT HS
19 14 20 15
6 7
9 10
X X
X X
X X
X X
Por t F6 Por t F7
Timer A Input Capture 1 Timer A External Clock Source
a. In the interrupt input column, "eiX" defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input. b. In the open drain output column, `T' defines a true open drain I/O (P-Buffer and protection diode to VDD are not implemented). See Section 9: I/O ports and Section 12.9: I/O port pin characteristics for more details.
12/188
ST72324B Table 1.
Pin No. LQFP44 LQFP32 Type SDIP42 SDIP32 Pin Name
Pin description Device pin description (continued)
Level Output Input Port Input float wpu ana int Output OD PP Main function (after reset)
Alternate Function
21 22 23 16 8 11
VDD_0(1) VSS_0
(1)
S S X X X X X
Digital Main Supply Voltage Digital Ground Voltage Por t C0 Timer B Output Compare 2 Timer B Output Compare 1 ADC Analog Input 12 ADC Analog Input 13
PC0/OCMP2_B I/O CT /AIN12 PC1/OCMP1_B I/O CT /AIN13 PC2 (HS)/ ICAP2_B PC3 (HS)/ ICAP1_B PC4/MISO/ICC DATA PC5/MOSI/ AIN14 PC6/SCK/ ICCCLK I/O CT HS I/O CT HS
24 17
9
12
X
X
X
X
X
Por t C1
25 18 10 13 26 19 11 14
X X
X X
X X
X X
Por t C2 Por t C3
Timer B Input Capture 2 Timer B Input Capture 1 SPI Master In / Slave Out Data SPI Master Out / Slave In Data SPI Serial Clock SPI Slave Select (active low) ICC Data Input ADC Analog Input 14 ICC Clock Output ADC Analog Input 15
27 20 12 15
I/O CT
X
X
X
X
Por t C4
28 21 13 16
I/O CT
X
X
X
X
X
Por t C5
29 22 14 17
I/O CT
X
X
X
X
Por t C6
30 23 15 18 PC7/SS/AIN15
I/O CT
X
X ei 0
X
X
X
Por t C7
31 24 16 19 PA3 (HS) 32 25 33 26 VDD_1(1) VSS_1
(1)
I/O CT HS S S I/O CT HS I/O CT HS I/O CT HS I/O CT HS
X
X
X
Por t A3 Digital Main Supply Voltage Digital Ground Voltage
34 27 17 20 PA4 (HS) 35 28 PA5 (HS)
X X X X
X X
X X T T
X X
Por t A4 Por t A5 Por t A6 (2) Por t A7 (2) Must be tied low. In the flash programming mode, this pin acts as the programming voltage input VPP. See Section 12.10.2 for more details. High voltage must not be applied to ROM devices. Top priority non maskable interrupt. Digital Ground Voltage
36 29 18 21 PA6 (HS) 37 30 19 22 PA7 (HS)
38 31 20 23 VPP /ICCSEL
I
39 32 21 24 RESET 40 33 22 25 VSS_2
(1)
I/O CT S
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Pin description Table 1.
Pin No. LQFP44 LQFP32 Type SDIP42 SDIP32 Pin Name
ST72324B
Device pin description (continued)
Level Output Input Port Input float wpu ana int Output OD PP Main function (after reset)
Alternate Function
41 34 23 26 OSC2(3) 42 35 24 27 OSC1(3) 43 36 25 28 VDD_2(1) 44 37 26 29 PE0/TDO 1 2 3 4 5 38 27 30 PE1/RDI 39 28 31 PB0 40 41 PB1 PB2
O I S I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT X X X X X X X X ei2 ei2 ei2 ei 2 X X X X X X X X X X X X
Resonator oscillator inverter output External clock input or Resonator oscillator inverter input Digital Main Supply Voltage Por t E0 Por t E1 Por t B0 Por t B1 Por t B2 Por t B3 SCI Transmit Data Out SCI Receive Data In Caution: Negative current injection not allowed on this pin(4)
42 29 32 PB3
1. It is mandatory to connect all available VDD and VREF pins to the supply voltage and all VSS and VSSA pins to ground. 2. On the chip, each I/O port has eight pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption. 3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section 1: Description and Section 12.6: Clock and timing characteristics for more details. 4. For details refer to Section 12.9.1 on page 153
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ST72324B
Register and memory map
3
Register and memory map
As shown in Figure 6, the MCU is capable of addressing 64 Kbytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, up to 1024 bytes of RAM and up to 32 Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh. The highest address bytes contain the user reset and interrupt vectors.
Caution:
Never access memory locations marked as `Reserved'. Accessing a reserved area can have unpredictable effects on the device. Figure 6. Memory map
0000h 007Fh 0080h
HW registers (see Table 2)
0080h 00FFh 0100h Short addressing RAM (zero page)
RAM (1024, 512 or 384 bytes) 047Fh 0480h 7FFFh 8000h Program memory (32, 16 or 8 Kbytes) FFDF h FFE0h Interrupt and reset vectors (see Table 24) FFFF h
256 bytes stack 01FFh 0200h 027Fh or 047Fh 16-bit addressing RAM 8000h C000h E000h 8 Kbytes FFFFh
Reserved
32 Kbytes 16 Kbytes
Table 2.
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh
Hardware register map
Block Por t A(1) Register label PADR PADDR PAOR PBDR PBDDR PBOR PCDR PCDDR PCOR PDADR PDDDR PDOR PEDR PEDDR PEOR Register name Por t A data register Por t A data direction register Por t A option register Por t B data register Por t B data direction register Por t B option register Por t C data register Por t C data direction register Por t C option register Por t D data register Por t D data direction register Por t D option register Por t E data register Por t E data direction register Por t E option register Reset status 00h(2) 00h 00h 00h(2) 00h 00h 00h(2) 00h 00h 00h(2) 00h 00h 00h(2) 00h 00h Remarks R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W(1) R/W(1)
Por t B(1)
Por t C
Por t
D(1)
Por t E(1)
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Register and memory map Table 2.
Address 000Fh 0010h 0011h 0012h to 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh to 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h TACR2 TACR1 TACSR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR Flash Watchdog SI MCC SPI SPIDR SPICR SPICSR ISPR0 ISPR1 ISPR2 ISPR3 EICR FCSR WDGCR SICSR MCCSR MCCBCR
ST72324B
Hardware register map (continued)
Block Por t F(1) Register label PFDR PFDDR PFOR Register name Por t F data register Por t F data direction register Por t F option register Reserved area (15 bytes) SPI data I/O register SPI control register SPI control/status register Interrupt software priority register 0 Interrupt software priority register 1 Interrupt software priority register 2 Interrupt software priority register 3 External interrupt control register Flash control/status register Watchdog control register System integrity control/status register Main clock control/status register Main clock controller: beep control register Reser ved area (3 bytes) Timer A control register 2 Timer A control register 1 Timer A control/status register Timer A input capture 1 high register Timer A input capture 1 low register Timer A output compare 1 high register Timer A output compare 1 low register Timer A counter high register Timer A counter low register Timer A alternate counter high register Timer A alternate counter low register Timer A input capture 2 high register Timer A input capture 2 low register Timer A output compare 2 high register Timer A output compare 2 low register Reserved area (1 byte) 00h 00h xxxx x0xxb xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W R/W Read only Read only R/W R/W Read only Read only Read only Read only Read only Read only R/W R/W xxh 0xh 00h FFh FFh FFh FFh 00h 00h 7Fh 000x 000xb 00h 00h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset status 00h 00h 00h
(2)
Remarks R/W R/W R/W
ITC
Timer A
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ST72324B Table 2.
Address 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h to 006Fh 0070h 0071h 0072h 0073h 007Fh ADC ADCCSR ADCDRH ADCDRL
Register and memory map Hardware register map (continued)
Block Register label TBCR2 TBCR1 TBCSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR SCIETPR Register name Timer B control register 2 Timer B control register 1 Timer B control/status register Timer B input capture 1 high register Timer B input capture 1 low register Timer B output compare 1 high register Timer B output compare 1 low register Timer B counter high register Timer B counter low register Timer B alternate counter high register Timer B alternate counter low register Timer B input capture 2 high register Timer B input capture 2 low register Timer B output compare 2 high register Timer B output compare 2 low register SCI status register SCI data register SCI baud rate register SCI control register 1 SCI control register 2 SCI extended receive prescaler register Reserved area SCI extended transmit prescaler register Reserved area (24 bytes) Control/status register Data high register Data low register Reserved area (13 bytes) 00h 00h 00h R/W Read only Read only Reset status 00h 00h xxxx x0xxb xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h C0h xxh 00h x000 0000b 00h 00h --00h Remarks R/W R/W R/W Read only Read only R/W R/W Read only Read only Read only Read only Read only Read only R/W R/W Read only R/W R/W R/W R/W R/W R/W
Timer B
SCI
1. The bits associated with unavailable pins must always keep their reset value. 2. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.
Legend: x = undefined, R/W = read/write
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Flash program memory
ST72324B
4
4.1
Flash program memory
Introduction
The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a byte-bybyte basis using an external VPP supply. The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (in-circuit programming) or IAP (in-application programming). The array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors.
4.2
Main features
3 Flash programming modes: Inser tion in a programming tool. In this mode, all sectors including option bytes can be programmed or erased. ICP (in-circuit programming). In this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board. IAP (in-application programming). In this mode, all sectors, except Sector 0, can be programmed or erased without removing the device from the application board and while the application is running.
ICT (in-circuit testing) for downloading and executing user application test patterns in RAM Readout protection Register Access Security System (RASS) to prevent accidental programming or erasing
4.3
Structure
The Flash memory is organized in sectors and can be used for both code and data storage. Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (seeTable 3). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required. The first two sectors have a fixed size of 4 Kbytes (see Figure 7). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000h-FFFFh). Table 3. Sectors available in Flash devices
Flash size (bytes) 4K 8K >8K Available sectors Sector 0 Sectors 0, 1 Sectors 0, 1, 2
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ST72324B
Flash program memory
4.3.1
Readout protection
Readout protection, when selected, provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. In Flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased. Readout protection selection depends on the device type:
In Flash devices it is enabled and removed through the FMP_R bit in the option byte. In ROM devices it is enabled by mask option specified in the option list. Memory map and sector address
8K 16K 32K Flash memory size
Figure 7.
7FFFh BFFFh DFFFh EFFFh FFFFh 8 Kbytes 4 Kbytes 4 Kbytes 24 Kbytes Sector 1 Sector 0 Sector 2
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Flash program memory
ST72324B
4.4
ICC interface
ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see Figure 8). These pins are: Figure 8. RESET: device reset VSS: device power supply ground ICCCLK: ICC output serial clock pin ICCDATA: ICC input/output serial data pin ICCSEL/VPP: programming voltage OSC1 (or OSCIN): main clock input for external source (optional) VDD: application board power supply (optional, see Figure 8, Note 3). Typical ICC interface
Programming tool ICC connector Mandatory for 8/16 Kbyte Flash devices (see note 4) (See note 3) 9 10 7 8 5 6 3 4 1 2 ICC cable Application board ICC connector HE10 connector type Application reset source See note 2 1 0 k Application power supply ICCSEL/VPP OSC2 OSC1 ICCDATA VDD VSS RESET See note 1 ICCCLK Application I/O
ST7
1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the programming tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values. 2. During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (PUSH-pull output or pull-up resistor <1K). A schottky diode can be used to isolate the application reset circuit in this case. When using a classical RC network with R>1K or a reset management IC with open drain output and pull-up resistor >1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session. 3. The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be connected when using most ST programming tools (it is used to monitor the application power supply). Please refer to the programming tool manual. 4. Pin 9 has to be connected to the OSC1 (OSCIN) pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multioscillator capability need to have OSC2 grounded in this case.
Caution:
External clock ICC entry mode is mandatory in ST72F324B 8/16 Kbyte Flash devices. In this case pin 9 must be connected to the OSC1 (OSCIN) pin of the ST7 and OSC2 must be grounded. 32 Kbyte Flash devices may use external clock or application clock ICC entry mode.
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ST72324B
Flash program memory
4.5
ICP (in-circuit programming)
To perform ICP the microcontroller must be switched to ICC (in-circuit communication) mode by an external controller or programming tool. Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 8). For more details on the pin locations, refer to the device pinout description.
4.6
IAP (in-application programming)
This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool). This mode is fully controlled by user software. This allows it to be adapted to the user application, (such as user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored). For example, it is possible to download code from the SPI, SCI, USB or CAN interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.
4.7
Related documentation
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual.
4.7.1
Flash Control/Status Register (FCSR)
This register is reserved for use by programming tool software. It controls the Flash programming and erasing operations.
FCSR 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W Reset value:0000 0000 (00h) 2 0 R/W 1 0 R/W 0 0 R/W
Table 4.
Flash control/status register address and reset value
Register label FCSR reset value 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Address (Hex) 0029h
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Central processing unit (CPU)
ST72324B
5
5.1
Central processing unit (CPU)
Introduction
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation.
5.2
Main features
Enable executing 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) Two 8-bit index registers 16-bit stack pointer Low power Halt and Wait modes Priority maskable hardware interrupts Non-maskable software/hardware interrupts
5.3
CPU registers
The six CPU registers shown in Figure 9 are not present in the memory mapping and are accessed by specific instructions. Figure 9. CPU registers
7 Reset value = XXh 7 Reset value = XXh 7 Reset value = XXh 15 PCH 87 PCL 0 Program counter Reset value = reset vector @ FFFEh-FFFFh 7 0 1 1 I1 H I0 N Z C Reset value = 1 1 1 X 1 X X X 15 87 0 Stack pointer Reset value = stack higher address X = undefined value 0 X index register 0 Y index register 0 Accumulator
Condition code register
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ST72324B
Central processing unit (CPU)
5.3.1
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.
5.3.2
Index registers (X and Y)
These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures.
5.3.3
Program counter (PC)
The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
5.3.4
Condition Code register (CC)
The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions.
CC 7 1 R/W 6 1 R/W 5 I1 R/W 4 H R/W 3 I0 R/W 2 N R/W Reset value: 111x1xxx 1 Z R/W 0 C R/W
Table 5.
BIt Name
Arithmetic management bits
Function Half carry This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Negative This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the result 7th bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic 1. This bit is accessed by the JRMI and JRPL instructions.
4
H
2
N
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Central processing unit (CPU) Table 5.
BIt Name
ST72324B
Arithmetic management bits (continued)
Function Zero (Arithmetic Management bit) This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Carr y/borrow This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the `bit test and branch', shift and rotate instructions.
1
Z
0
C
Table 6.
BIt Name
Software interrupt bits
Function Software Interrupt Priority 1 The combination of the I1 and I0 bits determines the current interrupt software priority (see Table 7). Software Interrupt Priority 0 The combination of the I1 and I0 bits determines the current interrupt software priority (see Table 7).
5
I1
3
I0
Table 7.
Interrupt software priority selection
Interrupt software priority Level Low I1 1 0 0 High 1 I0 0 1 0 1
Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable)
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See Section 7: Interrupts on page 36 for more details.
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ST72324B
Central processing unit (CPU)
5.3.5
Stack Pointer register (SP)
SP 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 1 7 6 5 4 3 Reset value: 01 FFh 2 1 0
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 10). Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address. The least significant byte of the Stack Pointer (called S) can be directly accessed by an LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 10.
When an interrupt is received, the SP is decremented and the context is pushed on the stack. On return from interrupt, the SP is incremented and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area. Figure 10. Stack manipulation example
Call subroutine @ 0100h Interrupt event P u sh Y P op Y I RE T RET or RSP
SP SP CC A X PCH SP PCH @ 01FFh PCL PCL PCH PCL Y CC A X PCH PCL PCH PCL SP CC A X PCH PCL PCH PCL SP PCH PCL SP
Stack Higher Address = 01FFh Stack Lower Address = 0100h
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Supply, reset and clock management
ST72324B
6
6.1
Supply, reset and clock management
Introduction
The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 12. For more details, refer to dedicated parametric section.
Main features
Optional Phase Locked Loop (PLL) for multiplying the frequency by 2 (not to be used with internal RC oscillator in order to respect the max. operating frequency) Multi-Oscillator clock management (MO) 5 crystal/ceramic resonator oscillators 1 Internal RC oscillator
Reset Sequence Manager (RSM) System Integrity management (SI) Main supply low voltage detection (LVD) Auxiliar y voltage detector (AVD) with interrupt capability for monitoring the main supply
6.2
PLL (phase locked loop)
If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to multiply the frequency by two to obtain an fOSC2 of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL is disabled, then fOSC2 = fOSC/2.
Caution:
The PLL is not recommended for applications where timing accuracy is required. Furthermore, it must not be used with the internal RC oscillator. Figure 11. PLL block diagram
fOSC
PLL x 2 /2
0 fOSC2 1 PLL option bit
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ST72324B Figure 12. Clock, reset and supply block diagram
Supply, reset and clock management
OSC2 OSC1
MultiOscillator (MO)
fOSC
PLL (option)
fOSC2
Main Clock fCPU C ontroller with Real-time Clock (MCC/RTC)
System Integrity Management
RESET
Reset Sequence Manager (RSM)
AVD Interrupt Request SICSR
0 AVD AVD LVD F RF IE 0 0 0 WDG RF
Watchdog timer (WDG)
VSS VDD
Low Voltage Detector (LVD) Auxiliary Voltage Detector (AVD)
6.3
Multi-oscillator (MO)
The main clock of the ST7 can be generated by three different source types coming from the multi-oscillator block:
an external source 4 crystal or ceramic resonator oscillators an internal high frequency RC oscillator
Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in Table 8. Refer to the electrical characteristics section for more details. Caution: The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left unconnected, the ST7 main oscillator may start and, in this configuration, could generate an fOSC clock frequency in excess of the allowed maximum (> 16 MHz.), putting the ST7 in an unsafe/undefined state. The product behavior must therefore be considered undefined when the OSC pins are left unconnected.
6.3.1
External clock source
In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.
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ST72324B
6.3.2
Crystal/ceramic oscillators
This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of four oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to Section 14.1 on page 172 for more details on the frequency ranges). In this mode of the multi-oscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator. These oscillators are not stopped during the reset phase to avoid losing time in the oscillator start-up phase.
6.3.3
Internal RC oscillator
This oscillator allows a low cost solution for the main clock of the ST7 using only an internal resistor and capacitor. Internal RC oscillator mode has the drawback of a lower frequency accuracy and should not be used in applications that require accurate timing. In this mode, the two oscillator pins have to be tied to ground. In order not to exceed the maximum operating frequency, the internal RC oscillator must not be used with the PLL. Table 8. ST7 clock sources
Hardware configuration
External clock
OSC1
ST7 OSC2
External source
Crystal/ceramic resonators
OSC1
ST7 OSC2
CL1
Load capacitors
CL2
Internal RC oscillator
ST7 OSC1 OSC2
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ST72324B
Supply, reset and clock management
6.4
Reset sequence manager (RSM)
The reset sequence manager includes three reset sources as shown in Figure 14:
External reset source pulse Internal LVD reset Internal Watchdog reset
These sources act on the RESET pin and it is always kept low during the delay phase. The reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic reset sequence consists of three phases as shown in Figure 13:
Active Phase depending on the reset source 256 or 4096 CPU clock cycle delay (selected by option byte) Reset vector fetch
Caution:
When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is not programmed. For this reason, it is recommended to keep the RESET pin in low state until programming mode is entered, in order to avoid unwanted behavior. The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that recovery has taken place from the reset state. The shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application. The reset vector fetch phase duration is two clock cycles. Figure 13. Reset sequence phases
RESET ACTIVE PHASE INTERNAL RESET 256 or 4096 CLOCK CYCLES FETCH VECTOR
6.4.1
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See the Electrical characteristics section for more details. A reset signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized (see Figure 15). This detection is asynchronous and therefore the MCU can enter reset state even in Halt mode.
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Supply, reset and clock management Figure 14. Reset block diagram
VDD
ST72324B
RON RESET Filter Internal reset
Pulse generator
Watchdog reset LVD reset
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section.
External power-on reset
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency. A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin.
Internal LVD reset
Two different reset sequences caused by the internal LVD circuitry can be distinguished:
Power-On reset Voltage Drop reset
The device RESET pin acts as an output that is pulled low when VDD < VIT+ (rising edge) or VDD < VIT- (falling edge) as shown in Figure 15. The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets.
Internal Watchdog reset
The reset sequence generated by a internal Watchdog counter overflow is shown in Figure 15. Star ting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out.
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ST72324B Figure 15. RESET sequences
VDD VIT+(LVD) VIT-(LVD) LVD reset Run
Active phase
Supply, reset and clock management
External reset Run
Active phase
Watchdog reset Run
Active phase
Run
th(RSTL)in
External RESET source RESET pin Watchdog reset
tw(RSTL)out
Watchdog underflow Internal reset (256 or 4096 TCPU) Vector fetch
6.5
System integrity management (SI)
The system integrity management block contains the LVD and auxiliary voltage detector (AVD) functions. It is managed by the SICSR register.
6.5.1
LVD (low voltage detector)
The LVD function generates a static reset when the VDD supply voltage is below a VITreference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The VIT- reference value for a voltage drop is lower than the VIT+ reference value for poweron in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD reset circuitry generates a reset when VDD is below: VIT+ when VDD is rising VIT- when VDD is falling
The LVD function is illustrated in Figure 15. The voltage threshold can be configured by option byte to be low, medium or high.
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Supply, reset and clock management
ST72324B
Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-, the MCU can only be in two modes: under full software control in static safe reset
In these conditions, secure operation is always ensured for the application without the need for external reset hardware. During an LVD reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Note: 1 2 3 4 The LVD allows the device to be used without any external reset circuitry. If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range. Below 3.8V, device operation is not guaranteed. The LVD is an optional function which can be selected by option byte. It is recommended to make sure that the VDD supply voltage rises monotonously when the device is exiting from reset, to ensure the application functions properly. Figure 16. Low voltage detector vs reset
VDD Vhys V IT+ V IT-
RESET
6.5.2
AVD (auxiliary voltage detector)
The AVD is based on an analog comparison between a VIT-(AVD) and VIT+(AVD) reference value and the VDD main supply. The VIT- reference value for falling voltage is lower than the VIT+ reference value for rising voltage in order to avoid parasitic detection (hysteresis). The output of the AVD comparator is directly readable by the application software through a real-time status bit (AVDF) in the SICSR register. This bit is read only.
Caution:
The AVD function is active only if the LVD is enabled through the option byte (see Section 14.1 on page 172).
Monitoring the VDD main supply
The AVD voltage threshold value is relative to the selected LVD threshold configured by option byte (see Section 14.1 on page 172). If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the VIT+(AVD) or VIT-(AVD) threshold (AVDF bit toggles). In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing software to shut down safely before the LVD resets the microcontroller. See Figure 17.
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ST72324B
Supply, reset and clock management The interrupt on the rising edge is used to inform the application that the VDD warning state is over. If the voltage rise time trv is less than 256 or 4096 CPU cycles (depending on the reset delay selected by option byte), no AVD interrupt will be generated when VIT+(AVD) is reached. If trv is greater than 256 or 4096 cycles then:
If the AVD interrupt is enabled before the VIT+(AVD) threshold is reached, then 2 AVD interrupts will be received: the first when the AVDIE bit is set, and the second when the threshold is reached. If the AVD interrupt is enabled after the VIT+(AVD) threshold is reached then only one AVD interrupt will occur.
Figure 17. Using the AVD to monitor VDD
VDD Early warning interrupt (power has dropped, MCU not not yet in reset) Vhyst
VIT+(AVD) V IT-(AVD) VIT+(LVD) VIT-(LVD)
trv Voltage rise time
AVDF bit AVD Interrupt Request if AVDIE bit = 1
0
1
Reset value
1
0
Interrupt process LVD RESET
Interrupt process
6.5.3
Low power modes
Table 9.
Mode Wait Halt
Effect of low power modes on SI
Description No effect on SI. AVD interrupt causes the device to exit from Wait mode. The CRSR register is frozen.
6.5.4
Interrupts
The AVD interrupt event generates an interrupt if the AVDIE bit is set and the interrupt mask in the CC register is reset (RIM instruction). Table 10.
M
AVD interrupt control/wake-up capability
Event flag AVDF Enable Control bit Exit from WAIT AVDIE Yes Exit from HALT No
Interrupt event AVD event
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Supply, reset and clock management
ST72324B
6.6
6.6.1
SI registers
System integrity (SI) control/status register (SICSR)
SICSR 7 Res 6 AVDIE R/W 5 AVDF RO 4 LVDRF R/W 3 2 Reser ved Reset value: 000x 000x (00h) 1 0 WDGRF R/W
Table 11.
Bit 7 Name -
SICSR register description
Function Reserved, must be kept cleared Voltage Detector Interrupt Enable This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag changes (toggles). The pending interrupt information is automatically cleared when software enters the AVD interrupt routine 0: AVD interrupt disabled 1: AVD interrupt enabled Voltage Detector Flag This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt request is generated when the AVDF bit changes value. Refer to Figure 17 and to Section 6.5.2: AVD (auxiliary voltage detector) for additional details. 0: VDD over VIT+(AVD) threshold 1: VDD under VIT-(AVD) threshold
6
AVDIE
5
AVDF
4
LVD Reset Flag This bit indicates that the last reset was generated by the LVD block. It is set by LVDRF hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag description for more details. When the LVD is disabled by option byte, the LVDRF bit value is undefined. Reserved, must be kept cleared
3:1
0
Watchdog Reset Flag This bit indicates that the last reset was generated by the Watchdog peripheral. It is WDGRF set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD reset (to ensure a stable cleared state of the WDGRF flag when CPU starts). Combined with the LVDRF information, the flag description is given in Table 12.
Table 12.
Reset source flags
Reset sources External RESET pin Watchdog LVD LVDRF 0 0 1 WDGRF 0 1 X
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ST72324B Application notes
Supply, reset and clock management
The LVDRF flag is not cleared when another reset type occurs (external or watchdog); the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can be detected by software while an external reset cannot. Caution: When the LVD is not activated with the associated option byte, the WDGRF flag can not be used in the application.
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Interrupts
ST72324B
7
7.1
Interrupts
Introduction
The ST7 enhanced interrupt management provides the following features:
Hardware interrupts Software interrupt (TRAP) Nested or concurrent interrupt management with flexible interrupt priority and level management: up to 4 software programmable nesting levels up to 16 interrupt vectors fixed by hardware 2 non-maskable events: reset, TRAP
This interrupt management is based on:
Bit 5 and bit 3 of the CPU CC register (I1:0) Interrupt software priority registers (ISPRx) Fixed interrupt vector addresses located at the high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order
This enhanced interrupt controller guarantees full upward compatibility with the standard (not nested) ST7 interrupt controller.
7.2
Masking and processing flow
The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector (see Table 13). The processing flow is shown in Figure 18. When an interrupt request has to be serviced:
Normal processing is suspended at the end of the current instruction execution. The PC, X, A and CC registers are saved onto the stack. I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx registers of the serviced interrupt vector. The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to Table 24: Interrupt mapping for vector addresses).
The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume.
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ST72324B Table 13. Interrupt software priority levels
Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) High Level Low I1 1 0 0 1
Interrupts
I0 0 1 0 1
Figure 18. Interrupt processing flowchart
Pending
Interrupt
Reset
Y Interrupt has the same or a lower software priority than current one The interrupt stays pending
TRAP N I1:0
Y
N
Fetch next Instruction Y
"IRET" N
RESTORE PC, X, A, CC from st ac k
Execute instruction
Stack PC, X, A, CC load I1:0 from interrupt SW reg. load PC from interrupt vector
7.2.1
Servicing pending interrupts
As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process:
the highest software priority interrupt is serviced, if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first.
Figure 19 describes this decision process. Figure 19. Priority decision process flowchart
PENDING INTERRUPTS
Same
SOFTWARE PRIORITY
Different
HIGHEST SOFTWARE PRIORITY SERVICED HIGHEST HARDWARE PRIORITY SERVICED
Interrupt has a higher software priority than current one
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Interrupts
ST72324B When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one.
Note:
1 2
The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt. Reset and TRAP can be considered as having the highest software priority in the decision process.
7.2.2
Different interrupt vector sources
Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable type (reset, TRAP) and the maskable type (external or from internal peripherals).
7.2.3
Non-maskable sources
These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see Figure 18). After stacking the PC, X, A and CC registers (except for reset), the corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level 3). These sources allow the processor to exit Halt mode.
TRAP (non-maskable software interrupt)
This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the flowchart in Figure 18.
Reset
The reset source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See the reset chapter for more details.
7.2.4
Maskable sources
Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending.
External interrupts
External interrupts allow the processor to Exit from Halt low power mode. External interrupt sensitivity is software selectable through the External Interrupt Control register (EICR). External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ORed.
Peripheral interrupts
Usually the peripheral interrupts cause the MCU to Exit from Halt mode except those mentioned in Table 24: Interrupt mapping. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the
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ST72324B
Interrupts peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register.
Note:
The clearing sequence resets the internal latch. A pending interrupt (that is, waiting to be serviced) is therefore lost if the clear sequence is executed.
7.3
Interrupts and low power modes
All interrupts allow the processor to exit the Wait low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the Halt modes (see column Exit from HALT in Table 24: Interrupt mapping). When several pending interrupts are present while exiting Halt mode, the first one serviced can only be an interrupt with Exit from Halt mode capability and it is selected through the same decision process shown in Figure 19.
Note:
If an interrupt, that is not able to exit from Halt mode, is pending with the highest priority when exiting Halt mode, this interrupt is serviced after the first one serviced.
7.4
Concurrent and nested management
Figure 20 and Figure 21 show two different interrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in Figure 21. The interrupt hardware priority is given in order from the lowest to the highest as follows: MAIN, IT4, IT3, IT2, IT1, IT0. Software priority is given for each interrupt.
Warning:
A stack overflow may occur without notifying the software of the failure.
Figure 20. Concurrent interrupt management
TRAP Software priority level 3 I T0 I T1 IT2 IT3 RIM IT4 Main 11/10 Main 10 I T1 3 3 3 3 3 3/0 IT2 IT1 IT4 IT3 I T0 I1 I0
11 11 11 11 11
Used stack = 10 bytes
TRAP Hardware priority
11
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Interrupts Figure 21. Nested interrupt management
TRAP Software priority level 3 I T0 IT1 IT2 I T3 RIM IT4 Main 11 / 10 IT4 Main IT1 IT2 3 2 1 3 3 3/0 I T2 I T1 I T4 I T3 I T0 I1
ST72324B
I0
11 00 01 11 11
10
7.5
7.5.1
Interrupt registers
CPU CC register interrupt bits
CPU CC 7 1 R/ W 6 1 R/ W 5 I1 R/ W 4 H R/ W 3 I0 R/ W 2 N R/ W Reset value: 111x 1010(xAh) 1 Z R/ W 0 C R/ W
Table 14.
Bit Name 5 3 I1 I0
CPU CC register interrupt bits description
Function Software Interrupt Priority 1 Software Interrupt Priority 0
Table 15.
Interrupt software priority levels
Interrupt software priority Level Low I1 1 0 0
(1)
I0 0 1 0 1
Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable)
High
1
1. TRAP and RESET events can interrupt a level 3 program.
These two bits indicate the current interrupt software priority (see Table 15) and are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see Table 17: Dedicated interrupt instruction set).
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Used stack = 20 bytes
TRAP Hardware priority
11
ST72324B
Interrupts
7.5.2
Interrupt software priority registers (ISPRx)
ISPRx 7 ISPR0 ISPR1 ISPR2 I 1_3 I 1_7 I1_11 R/W ISPR3 1 RO 6 I0_3 I0_7 I0_11 R/W 1 RO 5 I1_2 I1_6 I1_10 R/W 1 RO 4 I0_2 I0_6 I0_10 R/W 1 RO 3 I1_1 I1_5 I1_9 R/W I1_13 R/W Reset value: 1111 1111 (FFh) 2 I0_1 I0_5 I0_9 R/W I0_13 R/W 1 I1_0 I1_4 I1_8 R/W I1_12 R/W 0 I0_0 I0_4 I0_8 R/W I0_12 R/W
These four registers contain the interrupt software priority of each interrupt vector.
Each interrupt vector (except reset and TRAP) has corresponding bits in these registers where its own software priority is stored. This correspondence is shown in the following Table 16. ISPRx interrupt vector correspondence
Vector address FFFBh-FFFAh FFF9h-FFF8h ... FFE1h-FFE0h ISPRx bits I1_0 and I0_0 bits I1_1 and I0_1 bits ... I1_13 and I0_13 bits
Table 16.
Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits in the CC register. Level 0 cannot be written (I1_x = 1, I0_x = 0). In this case, the previously stored value is kept (for example, previous value = CFh, write = 64h, result = 44h).
The reset, and TRAP vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set. Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behavior has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x). Table 17.
Instruction HALT IRET JRM JRNM
Dedicated interrupt instruction set(1)
New description Entering HALT mode Interrupt routine return Jump if I1:0=11 (level 3) Jump if I1:0<>11 POP CC, A, X, PC I1:0=11 ? I1:0<>11 ? Function/example I1 1 I1 H H I0 0 I0 N Z C N Z C
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Interrupts Table 17.
Instruction POP CC RIM SIM TRAP WFI
ST72324B Dedicated interrupt instruction set(1) (continued)
New description POP CC from the Stack Function/example Mem => CC I1 I1 1 1 1 1 H H I0 I0 0 1 1 0 N N Z Z C C
Enable interrupt (level 0 set) Load 10 in I1:0 of CC Disable interrupt (level 3 set) Load 11 in I1:0 of CC Software TRAP WAIT for interrupt Software NMI
1. During the execution of an interrupt routine, the HALT, POP CC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions.
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ST72324B
Interrupts
7.6
7.6.1
External interrupts
I/O port interrupt sensitivity
The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR register (Figure 22). This control allows up to four fully independent external interrupt source sensitivities. Each external interrupt source can be generated on four (or five) different events on the pin:
Falling edge Rising edge Falling and rising edge Falling edge and low level Rising edge and high level (only for ei0 and ei2)
To guarantee correct functionality, the sensitivity bits in the EICR register can be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that interrupts must be disabled before changing sensitivity. The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits of the EICR. Figure 22. External interrupt control bits
Port A3 interrupt PAOR.3 PADDR.3 PA3 EICR IS20 IS21 ei0 interrupt source
Sensitivity control IPA BIT
Port F [2:0] interrupts PFOR.2 PFDDR.2 PF2
EICR IS20 IS21 PF2 PF1 PF0 ei1 interrupt source
Sensitivity control
Port B [3:0] interrupts PBOR.3 PBDDR.3 PB3
EICR IS10 IS11 PB3 PB2 PB1 PB0 ei2 interrupt source
Sensitivity control IPB BIT
Port B4 interrupt PBOR.4 PBDDR.4 PB4
EICR IS10 IS11 ei3 interrupt source
Sensitivity control
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Interrupts
ST72324B
7.6.2
External interrupt control register (EICR)
EICR 7 IS11 R/W 6 IS10 R/W 5 IPB R/W 4 IS21 R/W 3 IS20 R/W 2 IPA R/W Reset value: 0000 0000 (00h) 1 Reserved 0
Table 18.
Bit Name
EICR register description
Function
ei2 and ei3 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external interrupts: 7:6 IS1[1:0] - ei2 for port B [3:0] (see Table 19) - ei3 for port B4 (see Table 20) Bits 7 and 6 can only be written when I1 and I0 of the CC register are both set to 1 (level 3). Interrupt Polarity (for port B) This bit is used to invert the sensitivity of port B [3:0] external interrupts. It can be set and cleared by software only when I1 and I0 of the CC register are both set to 1 (level 3). 0: No sensitivity inversion 1: Sensitivity inversion
5
IPB
ei0 and ei1 sensitivity The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following external interrupts: 4:3 IS2[1:0] - ei0 for port A[3:0] (see Table 21) - ei1 for port F[2:0] (see Table 22) Bits 4 and 3 can only be written when I1 and I0 of the CC register are both set to 1 (level 3). Interrupt Polarity (for port A) This bit is used to invert the sensitivity of port A [3:0] external interrupts. It can be set and cleared by software only when I1 and I0 of the CC register are both set to 1 (level 3). 0: No sensitivity inversion. 1: Sensitivity inversion. Reserved, must always be kept cleared
2
IPA
1:0
-
Table 19.
IS11 0 0 1 1
Interrupt sensitivity - ei2
External interrupt sensitivity IS10 IPB bit = 0 0 1 0 1 Falling edge and low level Rising edge only Falling edge only IPB bit = 1 Rising edge and high level Falling edge only Rising edge only
Rising and falling edge
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ST72324B Table 20.
IS11 0 0 1 1
Interrupts Interrupt sensitivity - ei3
IS10 0 1 0 1 External interrupt sensitivity Falling edge and low level Rising edge only Falling edge only Rising and falling edge
Table 21.
IS21 0 0 1 1
Interrupt sensitivity - ei0
External interrupt sensitivity IS20 IPA bit = 0 0 1 0 1 Falling edge and low level Rising edge only Falling edge only Rising and falling edge IPA bit = 1 Rising edge and high level Falling edge only Rising edge only
Table 22.
IS21 0 0 1 1
Interrupt sensitivity - ei1
IS20 0 1 0 1 External interrupt sensitivity Falling edge and low level Rising edge only Falling edge only Rising and falling edge
Table 23.
Nested interrupts register map and reset values
Register label 7 ei1 6 5 ei0 I0_3 1 I1_2 1 I0_2 1 4 3 2 1 0
Address (Hex.)
MCC + SI I1_1 1 ei3 I0_1 1 1 ei2 I0_5 1 I1_4 1 I0_4 1 1
0024h
ISPR0 reset value
I1_3 1
SPI 0025h ISPR1 reset value I1_7 1 I0_7 1 I1_6 1 I0_6 1 I1_5 1
AVD 0026h ISPR2 reset value ISPR3 reset value EICR reset value I1_11 1 1 IS11 0 I0_11 1 1 IS10 0
SCI I1_10 1 1 IPB 0 I0_10 1 1 IS21 0
Timer B I1_9 1 I1_13 1 IS20 0 I0_9 1 I0_13 1 IPA 0
T imer A I1_8 1 I1_12 1 0 I0_8 1 I0_12 1 0
0027h 0028h
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Interrupts Table 24.
No.
ST72324B Interrupt mapping
Description Reset N/A Software interrupt Not used Register Priority Exit from label order Halt/Active Halt yes no Address vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh MCCSR Higher priority yes yes yes N/A yes yes FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh SPICSR TASR TBSR SCISR SICSR Lower priority yes no no no no FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h
Source block Reset TRAP
0 1 2 3 4 5 6 7 8 9 10 11 SPI Timer A Timer B SCI AVD MCC/RTC ei0 ei1 ei2 ei3
Main clock controller time base interrupt External interrupt port A3..0 External interrupt port F2..0 External interrupt port B3..0 External interrupt port B7..4 Not used SPI peripheral interrupts Timer A peripheral interrupts Timer B peripheral interrupts SCI peripheral interrupts Auxiliar y voltage detector interrupt
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ST72324B
Power saving modes
8
8.1
Power saving modes
Introduction
To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 23): Slow, Wait (Slow Wait), Active Halt and Halt. After a reset the normal operating mode is selected by default (Run mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided or multiplied by 2 (fOSC2). From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. Figure 23. Power saving mode transitions
High Run Slow Wait Slow Wait Active Halt Halt Low Power consumption
8.2
Slow mode
This mode has two targets:
To reduce power consumption by decreasing the internal clock in the device, To adapt the internal clock frequency (fCPU) to the available supply voltage.
Slow mode is controlled by three bits in the MCCSR register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (fCPU). In this mode, the master clock frequency (fOSC2) can be divided by 2, 4, 8 or 16. The CPU and peripherals are clocked at this lower frequency (fCPU). Note: Slow-Wait mode is activated when entering the Wait mode while the device is already in Slow mode.
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Power saving modes Figure 24. Slow mode clock transitions
fOSC2/2 fCPU fOSC2 MCCSR CP1:0 SMS Normal Run mode request New Slow frequency request 00 01 fOSC2/4 fOSC2
ST72324B
8.3
Wait mode
Wait mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the `WFI' instruction. All peripherals remain active. During Wait mode, the I[1:0] bits of the CC register are forced to `10', to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in Wait mode until an interrupt or reset occurs, whereupon the Program Counter branches to the starting address of the interrupt or reset service routine. The MCU will remain in Wait mode until a reset or an interrupt occurs, causing it to wake up. Refer to Figure 25. Figure 25. Wait mode flowchart
Oscillator Peripherals CPU I[1:0] bits on on off 10
WFI instruction
N Reset N Interrupt Y Oscillator Peripherals CPU I[1:0] bits on off on 10 Y
256 or 4096 CPU clock c ycle delay
Oscillator Peripherals CPU I[1:0] bits
on on on XX(1)
Fetch reset vector or service interrupt
1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.
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ST72324B
Power saving modes
8.4
Active Halt and Halt modes
Active Halt and Halt modes are the two lowest power consumption modes of the MCU. They are both entered by executing the `HALT' instruction. The decision to enter either in Active Halt or Halt mode is given by the MCC/RTC interrupt enable flag (OIE bit in the MCCSR register). Table 25. MCC/RTC low power mode selection
Power saving mode entered when HALT instruction is executed Halt mode Active Halt mode
MCCSR OIE bit 0 1
8.4.1
Active Halt mode
Active Halt mode is the lowest power consumption mode of the MCU with a real-time clock available. It is entered by executing the `HALT' instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is set (see Section 10.2: Main clock controller with realtime clock and beeper (MCC/RTC) on page 64 for more details on the MCCSR register). The MCU can exit Active Halt mode on reception of either an MCC/RTC interrupt, a specific interrupt (see Table 24: Interrupt mapping) or a reset. When exiting Active Halt mode by means of an interrupt, no 256 or 4096 CPU cycle delay occurs. The CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 27). When entering Active Halt mode, the I[1:0] bits in the CC register are forced to `10b' to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In Active Halt mode, only the main oscillator and its associated counter (MCC/RTC) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). The safeguard against staying locked in Active Halt mode is provided by the oscillator interrupt.
Note:
As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set), entering Active Halt mode while the Watchdog is active does not generate a reset. This means that the device cannot spend more than a defined delay in this power saving mode. When exiting Active Halt mode following an interrupt, OIE bit of MCCSR register must not be cleared before tDELAY after the interrupt occurs (tDELAY = 256 or 4096 tCPU delay depending on option byte). Otherwise, the ST7 enters Halt mode for the remaining tDELAY period. Figure 26. Active Halt timing overview
Run Active Halt 256 or 4096 CPU cycle delay(1) Reset or interrupt Ru n
Caution:
Halt instruction [MCCSR.OIE = 1]
Fetch vector
1. This delay occurs only if the MCU exits Active Halt mode by means of a reset.
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Power saving modes Figure 27. Active Halt mode flowchart
Halt instruction (MCCSR.OIE = 1) Oscillator Peripherals(1) CPU I[1:0] bits N N Reset Y Oscillator Peripherals CPU I[1:0] bits on off on XX(3) on off off 10
ST72324B
Interrupt(2) Y
256 or 4096 CPU clock cy cle d elay Oscillator Peripherals CPU I[1:0] bits on on on XX(3)
Fetch reset vector or service interrupt
1. Peripheral clocked with an external clock source can still be active. 2. Only the MCC/RTC interrupt and some specific interrupts can exit the MCU from Active Halt mode (such as external interrupt). Refer to Table 24: Interrupt mapping on page 46 for more details. 3. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and restored when the CC register is popped.
8.4.2
Halt mode
The Halt mode is the lowest power consumption mode of the MCU. It is entered by executing the `HALT' instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is cleared (see Section 10.2: Main clock controller with real-time clock and beeper (MCC/RTC) on page 64 for more details on the MCCSR register). The MCU can exit Halt mode on reception of either a specific interrupt (see Table 24: Interrupt mapping) or a reset. When exiting Halt mode by means of a reset or an interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 29). When entering Halt mode, the I[1:0] bits in the CC register are forced to `10b' to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In Halt mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of Watchdog operation with Halt mode is configured by the "WDGHALT" option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog reset (see Section 14.1 on page 172) for more details.
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ST72324B Figure 28. HALT timing overview
Power saving modes
Run
Halt
256 or 4096 CPU cycle delay Reset or interrupt
Run
Halt instruction [MCCSR.OIE = 0]
Fetch vector
Figure 29. Halt mode flowchart
Halt instruction (MCCSR.OIE = 0) Enable WDGHALT(1) 1 Watchdog reset Oscillator Peripherals(2) CPU I[1:0] bits off off off 10 0 Watchdog Disable
N Reset N Y Interrupt(3) Y Oscillator Peripherals CPU I[1:0] bits on off on XX(4)
256 or 4096 CPU clock cycle delay Oscillator Peripherals CPU I[1:0] bits on on on XX(4)
Fetch reset vector or service interrupt
1. WDGHALT is an option bit. See Section 14.1 on page 172 for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to Table 24: Interrupt mapping for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.
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Power saving modes
ST72324B
Halt mode recommendations
Make sure that an external event is available to wake up the microcontroller from Halt mode. When using an external interrupt to wake u |
