STE2004S
102 x 65 single-chip LCD controller/driver
Features
Description
The STE2004S is a low power CMOS LCD controller driver. Designed to drive a 65 rows by 102 columns graphic display, it provides all necessary functions in a single chip, including on-chip LCD supply and bias voltages generators, resulting in a minimum of externals components and in a very low power consumption. STE2004S features six standard interfaces (3-lines Serial, 3-lines SPI, 4-lines SPI, 68000 Parallel, 8080 parallel and I2C) for interfacing with the host micro-controller.
102 x 65 bits display data RAM Programmable MUX rate Programmable frame rate X,Y programmable carriage return Dual partial display mode Row by row scrolling N-line inversion Automatic data RAM blanking procedure Selectable input interface: I2C Bus Fast and Hs-mode (read and write) 8000 and 8080 Parallel Interfaces (read and write) 3-lines and 4-lines SPI Interface (read and write) 3-lines 9 bit Serial Interface (read and write) Fully integrated configurable LCD bias voltage generator with: Selectable multiplication factor (up to 5X) Effective sensing for high precision output Eight selectable temperature compensation coefficients CMOS compatible inputs Fully integrated oscillator requires no external components Designed for chip-on-glass (COG) applications. Low power consumption, suitable for battery operated systems Logic supply voltage range from 1.7 to 3.6V High voltage generator supply voltage range from 1.75 to 4.5V Display supply voltage range from 4.5 to 14.5V Backward compatibility with STE2001/2/4
CO to C101
R0 to R64
OSC_IN OSC_OUT FR_IN FR_OUT
OSC MASTER SLAVE SYNC BIAS VOLTAGE GENERATOR
TIMING GENERATOR CLOCK
COLUMN DRIVERS
ROW DRIVERS
DATA LATCHES
SHIFT REGISTER
VSENSE SLAVE VLCD VLCDSENSE RES
HIGH VOLTAGE GENERATOR
RESET
65 x 102 RAM
SCROLL LOGIC TEST TEST_MODE TEST_VREF ICON_MODE EXT
VSSAUX VDD1,2 VSS DATA REGISTER INSTRUCTION REGISTER
DISPLAY CONTROL LOGIC
SEL 3
I2C BUS
9 Bit SERIAL
3 & 4 Line SPI
Parallel 8080
Parallel 68K
SEL 2 SEL 1
SA1 SAO SDOUT SCLK/SCL SDIN/SDA_IN SDA_OUT DB0 E/WR R/W- RD to DB7
D/C
CS
LR0047
January 2007
Rev 3
1/7979
www.st.com
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Contents
STE2004S
Contents
1 2 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 3.2 3. 3 3.4 3. 5 3.6 3. 7 3. 8 Supplies voltages and grounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Internal supply voltage generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Master/slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bias levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 LCD voltage generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Temperature coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Display data RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4
Bus interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4. 1 4. 2 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.1.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.2.1 4.2.2 4.2.3 4-lines SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3-lines SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3-lines 9 bits serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4. 3
Parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.3.1 4.3.2 68000-series parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8080-series parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.1 5. 2 5.3 5.4 5. 5 5. 6 Reset (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Power down (PD = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Memory blanking procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Checker board procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Scrolling function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Dual partial display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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STE2004S
Contents
6 7
ID-number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7. 1 7.2 7.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8 9 10
Pad coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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Block diagram
STE2004S
1
Figure 1.
Block diagram
STE2004S block diagram
CO to C101 R0 to R64
OSC_IN OSC_OUT FR_IN FR_OUT
OSC MASTER SLAVE SYNC BIAS VOLTAGE GENERATOR
TIMING GENERATOR CLOCK
COLUMN DRIVERS
ROW DRIVERS
DATA LATCHES
SHIFT REGISTER
VSENSE SLAVE VLCD VLCDSENSE RES VSSAUX VDD1,2 VSS
HIGH VOLTAGE GENERATOR
RESET
65 x 102 RAM
SCROLL LOGIC TEST TEST_MODE TEST_VREF ICON_MODE EXT
DATA REGISTER
INSTRUCTION REGISTER
DISPLAY CONTROL LOGIC
SEL 3
I2C BUS
9 Bit SERIAL
3 & 4 Line SPI
Parallel 8080
Parallel 68K
SEL 2 SEL 1
SA1 SAO SDOUT SCLK/SCL SDIN/SDA_IN SDA_OUT DB0 E/WR R/W- RD to DB7
D/C
CS
LR0047
4/79
STE2004S
Pin description
2
Pin description
Table 1. Pin description
N R0 to R64 C0 to C101 VSS VDD1 VDD2 VLCD VLCDSENSE VSENSE_SLAVE VSSAUX VDD1AUX Pad 1-6 109-141 6-107 192-203 156-163 164-171 205-209 204 145 190-177-147 142 Type O O GND LCD row driver output LCD column driver output Ground pads. Function
Supply IC positive power supply Supply Internal generator supply voltages. Supply Voltage multiplier output Supply Voltage multiplier regulation input. VLCDOUT sensing for output voltage fine tuning
Supply Voltage reference for slave charge pump O O Ground reference for pins configuration VDD1 reference for pins configuration Interface mode selection - cannot be left floating SEL3 SEL2 SEL1 Interface I2C SPI 4-Lines 8 bit SPI 3-Lines 8 bit Serial 3-Lines 9 bit Parallel 8080-series Parallel 68000-series
GND/VSSAUX GND/VSSAUX GND/VSSAUX SEL1,2,3 152 153 154 GND/VSSAUX GND/VSSAUX I GND/VSSAUX GND/VSSAUX VDD1 VDD1 VDD1 VDD1 VDD1 GND/VSSAUX VDD1
GND/VSSAUX GND/VSSAUX GND/VSSAUX VDD1
Extended instruction set selection - cannot be left floating Ext pad config EXT_SET 151 I GND or VSSAUX VDD1 BASIC EXTENDED Instruction set selected
Extended instruction set selection - cannot be left floating Icon mode pad config ICON_MODE 155 I GND or VSSAUX VDD1 SDOUT SDIN - SDAIN 180 179 I O I Icon mode status DISBLED ENABLED
Serial and SPI data output - if unused must be left floating SDIN - Serial and SPI interface data input - cannot be left floating SDAIN - I2C bus data in - cannot be left floating
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Pin description Table 1. Pin description (continued)
N SCLK - SCL SDA_OUT SA0 SA1 DB0 to DB7 Pad 181 I 178 149 148 182-189 O I I I/O I R/W - RD 175 I E / WR E / WR RES D/C CS TEST_MODE TEST_VREF 176 176 172 174 173 191 146 I I I I I I O RD - 8080 Series Parallel interface read enable clock input - cannot be left floating E - 68000 Series Parallel interface read and write clock input - cannot be left floating WR - 8080 Series Parallel interface - write enable clock input - cannot be left floating Reset input. Active Low. Interface data/command selector- cannot be left floating Type I Function SCLK - Serial and SPI interface clock - cannot be left floating SCL - I2C bus clock - cannot be left floating I2C Bus data out - if unused must be left floating I2C slave address BIT 0 - cannot be left floating I2C slave address BIT 1- cannot be left floating Parallel interface 8 bit data bus - cannot be left floating
STE2004S
R/W - 68000 Series Parallel interface read and write control input - cannot be left floating
Serial and Parallel interfaces ENABLE. When Low the incoming data are clocked In. Cannot be left floating Test Pad - 50 kohm internal pull-down must be connected to VSS/VSSAUX Test Pad - must be left floating Oscillator Input: OSC_IN Configuration Internal oscillator enabled Internal oscillator disabled Internal oscillator disabled
OSCIN
144
I
High Low External Oscillator
OSCOUT FR_OUT FR_IN
210 211 143
O O I
Internal/external oscillator out - if unused must be left floating Master slave frame inversion synchronization - f unused must be left floating Master slave frame inversion synchronization - cannot be left floating Master/slave configuration bit:- cannot be left floating M/S PIN OSC_OUT ENABLED ENABLED FR_OUT Enabled Enabled FR_IN Disabled Enabled Charge Pump AuxVsense disabled Charge pump in slave mode or ext power
M/S
100
I
High Low
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STE2004S Figure 2. Chip mechanical drawing
ROW 27 ROW 6
Pin description
MARK_1
ROW 5
ROW28 ROW31
ROW 0 COL 0 FR_OUT OSC_OUT
MARK_3
STE2004S
VLCD VLCDSENSE
VSS
TEST_MODE
VSSAUX D0 D1 D2 D3 D4 D5 D6 D7 SCLK - SCL SDOUT SDIN - SDAIN SDAOUT COL 50 VSSAUX E - WR
(0,0)
COL 51
Y
R/W - RD D/C
CS
X
MARK_4
RES
VDD2
VDD1
ICON SEL1 SEL2 SEL3 EXT_SET M/S SA0 SA1 VSSAUX TEST VREF
VSENSE_SLAVE OSC_IN FR_IN VDD1_AUX COL 101 ROW 32 ROW64/ICON ROW63 ROW60
MARK_2
ROW 37
LR0048
ROW 38
ROW 59
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Pin description Figure 3.
VLCD V2 V3 ROW 0 R0 (t) V4 V5 VSS VLCD V2 V3 ROW 1 R1 (t) V4 V5 VSS VLCD V2 V3 COL 0 C0 (t) V4 V5 VSS VLCD V2 V3 COL 1 C1 (t) V4 V5 VSS VLCD - VSS V3 - VSS VLCD - V2 0V V3 - VSS V4 - V5 0V VSS - V5 V4 - VLCD VSS - VLCD
STE2004S Improved ALTH and PLESKO driving method
V1(t) V2(t)
Vstate1(t)
VLCD - VSS V3 - VSS VLCD - V2 0V V3 - VSS
Vstate2(t)
V4 - V5 0V VSS - V5
V4 - VLCD VSS - VLCD
0 1 2 3 4 5 6 7 8 9 . . ... . . . 64 0 1 2 3 4 5 6 7 8 9 . . ... . . . 64
FRAME n V1(t) = C1(t) - R0(t) V2(t) = C1(t) - R1(t)
FRAME n + 1
D00IN1154
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STE2004S
Circuit description
3
3.1
Circuit description
Supplies voltages and grounds
VDD2 supplies voltages to the internal voltage generator (see below). If the internal voltage generator is not used, this should be connected to VDD1 pad. VDD1 supplies the rest of the IC. VDD1 supply voltage could be different form VDD2.
V DD2 2---------------------- + 200 m V --- - V L C D (n + 4)
3.2
Internal supply voltage generator
The IC has a fully integrated (no external capacitors required) charge pump for the liquid crystal display (LCD) supply voltage generation. The multiplying factor can be programmed to be: Auto, X5, X4, X3, X2, using the 'set CP multiplication' command. If auto is set, the multiplying factor is automatically selected to have the lowest current consumption in every condition, allowing an input voltage that changes over time and a constant VLCD voltage. The output voltage (VLCD) is tightly controlled through the VLCDSENSE pad. For this voltage, eight different temperature coefficients (TC, rate of change with temperature) can be programmed using the bits TC1, TC0, T2, T1, T0, to ensure there is no contrast degradation over the LCD operating range. An external supply could be connected to VLCD to supply the LCD without using the internal generator. In such event the internal voltage generator must be programmed to zero (PRS = [0;0], Vop = 0 - reset condition) and the charge pump (CP[0;0]) set to 5x or quto mode.
3.3
Oscillator
A fully integrated oscillator (requires no external components) is present to provide the clock for the display system. When used the OSC pad must be connected to VDD1 pad. An external oscillator could be used and fed into the OSC pin. If an external oscillator is used, it must be always present when STE2004S is not in power down mode. An oscillator out is provided on the OSCOUT Pad to cascade two or more drivers.
3.4
Master/slave mode
STE2004S supports the master slave working mode for both control logic and charge pump. This function allows to drive matrix such as 204x65 or 102x130 using two synchronized STE2004S and the internal charge pump of both devices. If M/S is connected to VDD1, the driver is configured to work in master mode. When STE2004S is in master mode, the Vsense_Slave pin is disabled and the VLCD value can be controlled using Vop bits. The master time generator outputs the relevant timing references on FR_OUT and OSC_OUT. If M/S is connected to GND, the driver is configured to work in slave mode. When STE2004S is in slave mode, the VLCD configuration set by Vop registers and the thermal compensation slope set by TC register, are neglected. The VLCD value generated is equal to the voltage value present on the Vsense_Slave pin so the slave configuration can follow
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Circuit description
STE2004S
the master configuration. The only recognized configuration is Vop=0 that forces the charge pump to be in off state whatever is the value of Vsense_aux. To synchronize the master and slave timing circuits, the slave driver FR_IN pad must be connected to master driver FR_OUT pad, and slave driver OSC_IN pad must be connected to the master driver OSC_OUT Pad (Figure 4.). This connection ensures a synchronization at both frame level (R0 on the master is driven together with the Slave R0 driver) and at oscillator level (same frame frequency on the master and on the slave). If the synchronization at frame level is not required, FR_IN pin must be connected toVDD1 or to VDD1_aux (Figure 5.). During the power up procesure, the master device must be forced to exit from power down before the slave device. To enter into PowerDown mode, the slave device must be forced into power down state before master device. Figure 4. Master slave logic connection with frame synchronization
STE2004S
VDD1AUX OSCIN FRIN OSCOUT FROUT
STE2004S
FRIN OSCIN OSCOUT FROUT
LR0219
Figure 5.
Master slave logic connection without frame synchronization
STE2004S
VDD1AUX OSCIN FRIN OSCOUT FROUT
STE2004S
OSCIN VDD1AUX FRIN OSCOUT FROUT
LR0220
3.5
Bias levels
To properly drive the LCD, six (Including VLCD and VSS) different voltage (Bias) levels are generated. The ratios among these levels and VLCD, should be selected according to the MUX ratio (m). They are established according to the following (Figure 6.)
V n+3 n+2 2 1 , ------------ V , ------------ V , ------------ V , ------------ V ,V LCD n + 4 LCD n + 4 L CD n + 4 LCD n + 4 LCD SS
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STE2004S Figure 6. Bias level generator
VLCD n+3 ·VLCD n+4 R n+2 ·VLCD n+4 nR 2 ·VLCD n+4 R 1 ·VLCD n+4 R VSS
D00IN1150
Circuit description
R
providing an 1/(n+4) ratio, with n calculated from:
n=
For m = 65, n = 5, a 1/9 ratio is set. For m = 49, n =4, a 1/8 ratio is set.
m3
The STE2004S provides three bits (BS0, BS1, BS2) for programming the bias ratio as shown below: Table 2. Bias ratio programmable bits
BS2 0 0 0 0 1 1 1 1 BS1 0 0 1 1 0 0 1 1 BS0 0 1 0 1 0 1 0 1 n 7 6 5 4 3 2 1 0
The following table shows the bias level for m = 65 and m = 49:
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Circuit description Table 3. Bias level m=65 and m=49
Symbol V1 V2 V3 V4 V5 V6 m = 65 (1/9) VLCD 8/9*VLCD 7/9*VLCD 2/9*V VLCD 1/9 *VLCD VSS
STE2004S
m = 49 (1/8) VLCD 7/8*VLCD 6/8*VLCD 2/8*VLCD 1/8*VLCD VSS
3.6
LCD voltage generation
The LCD voltage at reference temperature (To = 27C) can be set using the VOP register content according to the following formula: VLCD(T=To) = VLCDo = (Ai+VOP · B) with the following values: Table 4. LCD voltage generation
Symbol Ao A1 A2 B To Value 2.95 6.83 10.71 0.0303 27 Unit V V V V C Note PRS = [0;0] PRS = [0;1] PRS = [1;0]
(i=0,1,2)
Note that the three PRS values produce three adjacent ranges for VLCD. If the VOP register and PRS bits are set to zero the internal voltage generator is switched off. The proper value for the VLCD is a function of the liquid crystal threshold voltage (Vth) and of the multiplexing rate. A general expression for this is:
1+ m V L C D = -------------------------------------- V t h 2 1 ---1-- -- m
For MUX Rate m = 65 the ideal VLCD is: VLCD(to) = 6.85 · Vth than:
( 6.85 Vt h A i ) V o p = -------------------------------------------0.03
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STE2004S
Circuit description
3.7
Temperature coefficients
As the viscosity, and therefore the contrast, of the LCD are subject to change with temperature, the LCD voltage must be varied with temperature. STE2004S provides eight different temperature coefficients to change the VLCD in a linear fashion against temperature. selectable through T2, T1 and T0 bits. Only four of the temperature coefficients are available through the basic instruction set. Table 5. Temperature coefficients with basic instruction set
NAME TC0 TC2 TC3 TC6 TC1 0 0 1 1 TC0 0 1 0 1 Value -0.0· 10-3 -0.7 · 10
-3
Unit 1/ C 1/C 1/C 1/C
-1.05· 10-3 -2.1 · 10-3
Table 6. Temperature coefficients
NAME TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 T2 0 0 0 0 1 1 1 1 T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 Value -0.0· 10-3 -0.35 · -0.7 · -1.05· 10-3 10-3 10-3 Unit 1/ C 1/C 1/C 1/C 1/C 1/C 1/C 1/C
-1.4 · 10-3 -1.75· -2.1 · -2.3· 10-3 10-3 10-3
Figure 7.
VLCD
Temperature coefficients
B A0 + B A1
00h 01h 02h 03h 04h 05h .... 7Ch 7Dh 7Eh 7Fh 00h 01h 02h 03h 04h 05h ....
A2 A1
7Ch 7Dh 7Eh 7Fh 00h 01h 02h 03h 04h 05h .... 7Ch 7Dh 7Eh 7Fh
PRS = [0;0]
PRS = [0;1]
PRS = [1;0]
VO
Finally, the VLCD voltage at a given (T) temperature can be calculated as: VLCD(T) = VLCDo · [1 + (T-To) · TC]
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Circuit description
STE2004S
3.8
Display data RAM
The STE2004S, provides an 102X65 bits static RAM to store display data. This is organized into 9 (Bank0 to Bank8) banks with 102 bytes. One of these banks can be used for icons. RAM access is accomplished in either one of the bus interfaces provided (see below). Allowed addresses are X0 to X101 (Horizontal) and Y0 to Y8 (Vertical). There are four address mode provided to write to RAM:
Normal Horizontal (MX=0 and V=0), having the column with address X= 0 located on the left of the memory map. The X pointer is increased after each byte written. After the last column address (X=X-Carriage), Y address pointer jumps to the following bank and X restarts from X=0. (Figure 8.) Normal Vertical (MX=0 and V=1), having the column with address X= 0 located on the left of the memory map. The Y pointer is increased after each byte written. After the last Y bank address (Y=Y-Carriage), X address pointer jumps to next column and Y restarts from Y=0 (Figure 9). Mirrored Horizontal (MX=1 and V=0), having the column with address X= 0 located on the right of the memory map. The X pointer is increased after each byte written. After the last column address (X=X-Carriage), Y address pointer jumps to the next bank and X restarts from X=0 (Figure 10.). Mirrored Vertical (MX=1 and V=1), having the column with address X= 0 located on the right of the memory map. The Y pointer is increased after each byte written. After the last Y bank address (Y=Y-Carriage), the X pointer jumps to next column and Y restarts from Y=0 (Figure 11.).
After the last allowed address (X;Y)=(X-Carriage; Y-Carriage), the address pointers always jumps to the cell with address (X;Y) = (0;0) (Figure 12. Figure 13. Figure 14. Figure 15.). Data bytes in the memory could have the MSB either on top (D0 = 0, Figure 16.) or on the bottom (D0=1, Figure 17.). The STE2004S also allows the normal output address to be altered. The display is mirrored along the X axis if a logic one MY bit is set. Only the memory read process is altered, the content is not affected in memory. When ICON MODE=1 the icon row is not mirrored with MY and is not scrolled. When ICON MODE=0 the icon row is like an other graphic line and is mirrored and scrolled. When the partial display mode is disabled, there are three multiplex ratios available (MUX 33, MUX 49 and MUX 65). Only a subset of writable rows are output on row drivers in MUX 33,49 and 65 modes. When Y-CarriageMUX/8, only lines 33 and 49 are visualized. The lines of DDRAM connected on the output drivers using the scrolling function (Range: 0Y-Carriage*8) are selectable. When Y-Carriage>MUX/8 lines, the icon row is moved in DDRAM to the first row of the bank, corresponding to the Y-CARRIAGE Return value, being always connected on the same output Driver.
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STE2004S
Circuit description When MY=0, the icon Row is output on R64 in MUX 65 mode, on R56 in MUX 49, and on R48 in MUX33. When MY=1, and ICON MODE=0, the icon Row is output on R0 whatever the MUX rate. Figure 8. Automatic data RAM writing sequence with V=0 and data RAM normal format (MX=0)(a)
0 BANK BANK BANK BANK BANK BANK BANK BANK BANK 0 1 2 3 4 5 6 7 8
1
2
3
98
99
100
101
LR0049
Figure 9.
Automatic data RAM writing sequence with V=1 and data RAM normal format (MX=0)(a)
0 BANK BANK BANK BANK BANK BANK BANK BANK BANK 0 1 2 3 4 5 6 7 8
1
2
3
98
99
100
101
LR0050
a. X Carriage=101; Y-Carriage = 8
15/79
Circuit description
STE2004S
Figure 10. Automatic data RAM writing sequence with V=0 and data RAM mirrored format (MX=1)(a)
101 BANK BANK BANK BANK BANK BANK BANK BANK BANK 0 1 2 3 4 5 6 7 8
100
99
98
3
2
1
0
LR0051
Figure 11. Automatic data RAM writing sequence with V=1 and data RAM mirrored format (MX=1)(a)
101 BANK BANK BANK BANK BANK BANK BANK BANK BANK 0 1 2 3 4 5 6 7 8
100
99
98
3
2
1
0
LR0052
Figure 12. Automatic data RAM writing sequence with X-Y carriage return (V=0; MX=0)
0 BANK 0 BANK 1 BANK 2
1
2
3
X CARR
98
99
100
101
Y CARR
BANK 7 BANK 8
LR0053
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STE2004S
Circuit description Figure 13. Automatic data RAM writing sequence with X-Y carriage return (V=1; MX=0)
X CARR 0 BANK 0 BANK 1 BANK 2 1 2 3 98 99 100 101
Y CARR
BANK 7 BANK 8
LR0054
Figure 14. Automatic data RAM writing sequence with X-Y carriage return (V=0; MX=1)
X CARR 101 BANK 0 BANK 1 BANK 2 100 99 98 3 2 1 0
Y CARR
BANK 7 BANK 8
LR0055
Figure 15. Automatic data RAM writing sequence with X-Y carriage return (V=1; MX=1)
X CARR 101 BANK 0 BANK 1 BANK 2 100 99 98 3 2 1 0
Y CARR
BANK 7 BANK 8
LR0056
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Circuit description Figure 16. Data RAM Byte organization with D0 = 0
STE2004S
MSB 0 BANK BANK BANK BANK BANK BANK BANK BANK BANK 0 1 2 3 4 5 6 7 8 1 2 3 98 99 100 101
LSB
LR0057
Figure 17. Data RAM byte organization with D0 = 1
LSB 0 BANK BANK BANK BANK BANK BANK BANK BANK BANK 0 1 2 3 4 5 6 7 8 1 2 3 98 99 100 101
MSB
LR0058
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STE2004S
Circuit description Figure 18. Memory rows vs. row drivers mapping ICON_MODE=1 and MUX 65
Y Address D3 D2 D1 D0 D a t a D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 5FH 60H 61H 62H 63H 64H 65H ROW Output Normal Reverse direction direction R0 R63 R1 R62 R2 R61 R3 R60 R4 R59 R5 R58 R6 R57 R7 R56 R8 R55 R9 R54 R10 R53 R11 R52 R12 R51 R13 R50 R14 R49 R15 R48 R16 R47 R17 R46 R18 R45 R19 R44 R20 R43 R21 R42 R22 R41 R23 R40 R24 R39 R25 R38 R26 R37 R27 R36 R28 R35 R29 R34 R30 R33 R31 R32 R32 R31 R33 R30 R34 R29 R35 R28 R36 R27 R37 R26 R38 R25 R39 R24 R40 R23 R41 R22 R42 R21 R43 R20 R44 R19 R45 R18 R46 R17 R47 R16 R48 R15 R49 R14 R50 R13 R51 R12 R52 R11 R53 R10 R54 R9 R55 R8 R56 R7 R57 R6 R58 R5 R59 R4 R60 R3 R61 R2 R62 R1 R63 R0 R64 R64
0
0
0
0
Page 0
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
Scrolling Pointer
Y-CARRIAGE
0 1 0 0
Page 4
0
1
0
1
Page 5
0
1
1
0
Page 6
0
1
1
1
Page 7
0 0 1 X address
0
Page 8
lr0268
COL Output
Normal Direction Reverse Direction
C C O O L L 0 1 C C O O L L 101 100
C O L 2 C O L 99
C O L 3 C O L 98
C O L 4 C O L 97
C O L 5 C O L 96
C O L 6 C O L 95
C O L 95 C O L 6
C O L 96 C O L 5
C O L 97 C O L 4
C O L 98 C O L 3
C O L 99 C O L 2
C O L 100 C O L 1
C O L 101 C O L 0
19/79
Circuit description
STE2004S
Figure 19. Memory rows vs. row drivers mapping ICON_MODE=0 and MUX 65
Y Address D3 D2 D1 D0 D a t a D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 5FH 60H 61H 62H 63H 64H 65H ROW Output Normal Reverse direction direction R0 R64 R1 R63 R2 R62 R3 R61 R4 R60 R5 R59 R6 R58 R7 R57 R8 R56 R9 R55 R10 R54 R11 R53 R12 R52 R13 R51 R14 R50 R15 R49 R16 R48 R17 R47 R18 R46 R19 R45 R20 R44 R21 R43 R22 R42 R23 R41 R24 R40 R25 R39 R26 R38 R27 R37 R28 R36 R29 R35 R30 R34 R31 R33 R32 R32 R33 R31 R34 R30 R35 R29 R36 R28 R37 R27 R38 R26 R39 R25 R40 R24 R41 R23 R42 R22 R43 R21 R44 R20 R45 R19 R46 R18 R47 R17 R16 R48 R49 R15 R50 R14 R51 R13 R52 R12 R53 R11 R54 R10 R55 R9 R56 R8 R57 R7 R58 R6 R59 R5 R60 R4 R61 R3 R62 R2 R63 R1 R64 R0
0
0
0
0
Page 0
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
Scrolling Pointer
Y-CARRIAGE
0 1 0 0
Page 4
0
1
0
1
Page 5
0
1
1
0
Page 6
0
1
1
1
Page 7
00 1 X address
0
Page 8
COL Output
Normal Direction Reverse Direction
C C O O L L 0 1 C C O O L L 101 100
C O L 2 C O L 99
C O L 3 C O L 98
C O L 4 C O L 97
C O L 5 C O L 96
C O L 6 C O L 95
C O L 95 C O L 6
C O L 96 C O L 5
C O L 97 C O L 4
C O L 98 C O L 3
C O L 99 C O L 2
C O L 100 C O L 1
C O L 101 C O L 0
lr0269
20/79
STE2004S
Circuit description Figure 20. Memory rows vs. Row drivers mapping ICON_MODE=1, Y-Carriage<=6 and MUX 49
Y Address D3 D2 D1 D0 D a t a D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 5FH 60H 61H 62H 63H 64H 65H ROW Output Normal Reverse direction direction R0 R55 R1 R54 R2 R53 R3 R52 R4 R51 R5 R50 R6 R49 R7 R48 R8 R47 R9 R46 R10 R45 R11 R44 R12 R43 R13 R42 R14 R41 R15 R40 R16 R39 R17 R38 R18 R37 R19 R36 R20 R35 R21 R34 R22 R33 R23 R32 R23 R32 R22 R33 R21 R34 R20 R35 R19 R36 R18 R37 R17 R38 R16 R39 R15 R40 R14 R41 R13 R42 R12 R43 R11 R44 R10 R45 R9 R46 R8 R47 R7 R48 R6 R49 R5 R50 R4 R51 R3 R52 R2 R53 R1 R54 R0 R55 R56 R56
0
0
0
0
Page 0
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
Scrolling Pointer
0
1
0
0
Page 4
0
1
0
1
Page 5
Y-CARRIAGE
0 1 1 0
Page 6
0
1
1
1
Page 7
00 1 X address
0
Page 8
COL Output
Normal Direction Reverse Direction
C C O O L L 0 1 C C O O L L 101 100
C O L 2 C O L 99
C O L 3 C O L 98
C O L 4 C O L 97
C O L 5 C O L 96
C O L 6 C O L 95
C O L 95 C O L 6
C O L 96 C O L 5
C O L 97 C O L 4
C O L 98 C O L 3
C O L 99 C O L 2
C O L 100 C O L 1
C O L 101 C O L 0
lr0270
21/79
Circuit description
STE2004S
Figure 21. Memory rows vs. row drivers ;apping ICON_MODE=0, Y-Carriage<=6 and MUX 49
Y Address D3 D2 D1 D0 D a t a D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 5FH 60H 61H 62H 63H 64H 65H ROW Output Normal Reverse direction direction R0 R56 R1 R55 R2 R54 R3 R53 R4 R52 R5 R51 R6 R50 R7 R49 R8 R48 R9 R47 R10 R46 R11 R45 R12 R44 R13 R43 R14 R42 R15 R41 R16 R40 R17 R39 R18 R38 R19 R37 R20 R36 R21 R35 R22 R34 R23 R33 R32 R32 R23 R33 R22 R34 R21 R35 R20 R36 R19 R37 R18 R38 R17 R39 R16 R40 R15 R41 R14 R42 R13 R43 R12 R44 R11 R45 R10 R46 R9 R47 R8 R48 R7 R49 R6 R50 R5 R51 R4 R52 R3 R53 R2 R54 R1 R55 R0 R56
0
0
0
0
Page 0
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
Scrolling Pointer
0
1
0
0
Page 4
0
1
0
1
Page 5
Y-CARRIAGE
0 1 1 0
Page 6
0
1
1
1
Page 7
00 1 X address
0
Page 8
COL Output
Normal Direction Reverse Direction
C C O O L L 1 0 C C O O L L 101 100
C O L 2 C O L 99
C O L 3 C O L 98
C O L 4 C O L 97
C O L 5 C O L 96
C O L 6 C O L 95
C O L 95 C O L 6
C O L 96 C O L 5
C O L 97 C O L 4
C O L 98 C O L 3
C O L 99 C O L 2
C O L 100 C O L 1
C O L 101 C O L 0
lr0271
22/79
STE2004S
Circuit description Figure 22. Memory rows vs. row drivers mapping ICON_MODE=0, Y-carriage=7, scrolling pointer>07h and MUX 49
Y Address D3 D2 D1 D0 D a t a D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 5FH 60H 61H 62H 63H 64H 65H ROW Output Normal Reverse direction direction R0 R56 R1 R55 R2 R54 R3 R53 R4 R52 R5 R51 R6 R50 R7 R49 R8 R48 R9 R47 R10 R46 R11 R45 R12 R44 R13 R43 R14 R42 R15 R41 R16 R40 R17 R39 R18 R38 R19 R37 R20 R36 R21 R35 R22 R34 R23 R33 R32 R32 R23 R33 R22 R34 R21 R35 R20 R36 R19 R37 R18 R38 R17 R39 R16 R40 R15 R41 R14 R42 R13 R43 R12 R44 R11 R45 R10 R46 R9 R47 R8 R48 R7 R49 R6 R50 R5 R51 R4 R52 R3 R53 R2 R54 R1 R55 R0 R56
0
0
0
0
Page 0
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
Scrolling Pointer
0
1
0
0
Page 4
0
1
0
1
Page 5
0
1
1
0
Page 6
Y-CARRIAGE
0 1 1 1
Page 7
00 1 X address
0
Page 8
COL Output
Normal Direction Reverse Direction
C C OO L L 0 1 C C O O L L 101 100
C O L 2 C O L 99
C O L 3 C O L 98
C O L 4 C O L 97
C O L 5 C O L 96
C O L 6 C O L 95
C O L 95 C O L 6
C O L 96 C O L 5
C O L 97 C O L 4
C O L 98 C O L 3
C C OO L L 99 100 C C O O L L 2 1
C O L 101 C O L 0
lr0275
23/79
Circuit description
STE2004S
Figure 23. Memory rows vs. row drivers mapping ICON_MODE=1, Y-Carriage=7, scrolling pointer>07h and MUX 49
Y Address D3 D2 D1 D0 D a t a D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 5FH 60H 61H 62H 63H 64H 65H ROW Output Normal Reverse direction direction R0 R55 R1 R54 R2 R53 R3 R52 R4 R51 R5 R50 R6 R49 R7 R48 R8 R47 R9 R46 R10 R45 R11 R44 R12 R43 R13 R42 R14 R41 R15 R40 R16 R39 R17 R38 R18 R37 R19 R36 R20 R35 R21 R34 R22 R33 R23 R32 R23 R32 R22 R33 R21 R34 R20 R35 R19 R36 R18 R37 R17 R38 R16 R39 R15 R40 R14 R41 R13 R42 R12 R43 R11 R44 R10 R45 R9 R46 R8 R47 R7 R48 R6 R49 R5 R50 R4 R51 R3 R52 R2 R53 R1 R54 R0 R55 R56 R56
0
0
0
0
Page 0
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
Scrolling Pointer
0
1
0
0
Page 4
0
1
0
1
Page 5
0
1
1
0
Page 6
Y-CARRIAGE
0 1 1 1
Page 7
00 1 X address
0
Page 8
COL Output
Normal Direction Reverse Direction
C C OO L L 0 1 C C O O L L 101 100
C O L 2 C O L 99
C O L 3 C O L 98
C O L 4 C O L 97
C O L 5 C O L 96
C O L 6 C O L 95
C O L 95 C O L 6
C O L 96 C O L 5
C O L 97 C O L 4
C O L 98 C O L 3
C C OO L L 99 100 C C O O L L 2 1
C O L 101 C O L 0
lr0276
24/79
STE2004S
Circuit description Figure 24. Memory rows vs. row drivers mapping ICON_MODE=1, Y-carriage=8, Scrolling pointer<10h and MUX 49
Y Address D3 D2 D1 D0 D a t a D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 5FH 60H 61H 62H 63H 64H 65H ROW Output Normal Reverse direction direction R0 R55 R1 R54 R2 R53 R3 R52 R4 R51 R5 R50 R6 R49 R7 R48 R8 R47 R9 R46 R10 R45 R11 R44 R12 R43 R13 R42 R14 R41 R15 R40 R16 R39 R17 R38 R18 R37 R19 R36 R20 R35 R21 R34 R22 R33 R23 R32 R23 R32 R22 R33 R21 R34 R20 R35 R19 R36 R18 R37 R17 R38 R16 R39 R15 R40 R14 R41 R13 R42 R12 R43 R11 R44 R10 R45 R9 R46 R8 R47 R7 R48 R6 R49 R5 R50 R4 R51 R3 R52 R2 R53 R1 R54 R0 R55 R56 R56
0
0
0
0
Page 0
Scrolling Pointer
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
0
1
0
0
Page 4
0
1
0
1
Page 5
0
1
1
0
Page 6
0
1
1
1
Page 7
Y-CARRIAGE
00 1 X address 0
Page 8
COL Output
Normal Direction Reverse Direction
C C OO L L 0 1 C C O O L L 101 100
C O L 2 C O L 99
C O L 3 C O L 98
C O L 4 C O L 97
C O L 5 C O L 96
C O L 6 C O L 95
C O L 95 C O L 6
C O L 96 C O L 5
C O L 97 C O L 4
C O L 98 C O L 3
C C OO L L 99 100 C C O O L L 2 1
C O L 101 C O L 0
LR0273
25/79
Circuit description
STE2004S
Figure 25. Memory rows vs. row drivers mapping ICON_MODE=0, Y-carriage=8, Scrolling pointer<10h and MUX 49
Y Address D3 D2 D1 D0 D a t a D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 5FH 60H 61H 62H 63H 64H 65H ROW Output Normal Reverse direction direction R0 R56 R1 R55 R2 R54 R3 R53 R4 R52 R5 R51 R6 R50 R7 R49 R8 R48 R9 R47 R10 R46 R11 R45 R12 R44 R13 R43 R14 R42 R15 R41 R16 R40 R17 R39 R18 R38 R19 R37 R20 R36 R21 R35 R22 R34 R23 R33 R32 R32 R23 R33 R22 R34 R21 R35 R20 R36 R19 R37 R18 R38 R17 R39 R16 R40 R15 R41 R14 R42 R13 R43 R12 R44 R11 R45 R10 R46 R9 R47 R8 R48 R7 R49 R6 R50 R5 R51 R4 R52 R3 R53 R2 R54 R1 R55 R0 R56
0
0
0
0
Page 0
Scrolling Pointer
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
0
1
0
0
Page 4
0
1
0
1
Page 5
0
1
1
0
Page 6
0
1
1
1
Page 7
Y-CARRIAGE
00 1 X address 0
Page 8
COL Output
Normal Direction Reverse Direction
C C OO L L 0 1 C C O O L L 101 100
C O L 2 C O L 99
C O L 3 C O L 98
C O L 4 C O L 97
C O L 5 C O L 96
C O L 6 C O L 95
C O L 95 C O L 6
C O L 96 C O L 5
C O L 97 C O L 4
C O L 98 C O L 3
C C OO L L 99 100 C C O O L L 2 1
C O L 101 C O L 0
LR0274
26/79
STE2004S
Circuit description Figure 26. Memory rows vs. row drivers mapping ICON_MODE=1, Y-carriage<=4 and MUX33
Y Address D3 D2 D1 D0 D a t a D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 5FH 60H 61H 62H 63H 64H 65H ROW Output Normal Reverse direction direction R0 R47 R1 R46 R2 R45 R3 R44 R4 R43 R5 R42 R6 R41 R7 R40 R8 R39 R9 R38 R10 R37 R11 R36 R12 R35 R13 R34 R14 R33 R15 R32 R15 R32 R14 R33 R13 R34 R12 R35 R11 R36 R10 R37 R9 R38 R8 R39 R7 R40 R6 R41 R5 R42 R4 R43 R3 R44 R2 R45 R1 R46 R0 R47 R48 R48
0
0
0
0
Page 0
0
0
0
1
Page 1
0
0
1
0
Page 2
Scrolling Pointer
0
0
1
1
Page 3
Y-CARRIAGE
0 1 0 0
Page 4
0
1
0
1
Page 5
0
1
1
0
Page 6
0
1
1
1
Page 7
00 1 X address
0
Page 8
COL Output
Normal Direction Reverse Direction
C C OO L L 0 1 C C O O L L 101 100
C O L 2 C O L 99
C O L 3 C O L 98
C O L 4 C O L 97
C O L 5 C O L 96
C O L 6 C O L 95
C O L 95 C O L 6
C O L 96 C O L 5
C O L 97 C O L 4
C O L 98 C O L 3
C C OO L L 99 100 C C O O L L 2 1
C O L 101 C O L 0
LR0272
27/79
Circuit description
STE2004S
Figure 27. Memory rows vs. row drivers mapping ICON_MODE=0, Y-carriage<=4 and MUX 33
Y Address D3 D2 D1 D0 D a t a D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 5FH 60H 61H 62H 63H 64H 65H ROW Output Normal Reverse direction direction R0 R48 R1 R47 R2 R46 R3 R45 R4 R44 R5 R43 R6 R42 R7 R41 R8 R40 R9 R39 R10 R38 R11 R37 R12 R36 R13 R35 R14 R34 R15 R33 R32 R32 R15 R33 R14 R34 R13 R35 R12 R36 R11 R37 R10 R38 R9 R39 R8 R40 R7 R41 R6 R42 R5 R43 R4 R44 R3 R45 R2 R46 R1 R47 R0 R48
0
0
0
0
Page 0
0
0
0
1
Page 1
0
0
1
0
Page 2
Scrolling Pointer
0
0
1
1
Page 3
Y-CARRIAGE
0 1 0 0
Page 4
0
1
0
1
Page 5
0
1
1
0
Page 6
0
1
1
1
Page 7
00 1 X address
0
Page 8
COL Output
Normal Direction Reverse Direction
C C OO L L 0 1 C C O O L L 101 100
C O L 2 C O L 99
C O L 3 C O L 98
C O L 4 C O L 97
C O L 5 C O L 96
C O L 6 C O L 95
C O L 95 C O L 6
C O L 96 C O L 5
C O L 97 C O L 4
C O L 98 C O L 3
C C OO L L 99 100 C C O O L L 2 1
C O L 101 C O L 0
LR0272
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STE2004S
Circuit description Figure 28. Row drivers vs. LCD panel interconnection in MUX65 mode
ICON
MUX 65
COLUMN DRIVERS
R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31
ROW DRIVERS
STE2004S
ROW DRIVERS
LR0109
Figure 29. Row drivers vs. LCD panel interconnection in MUX49 mode
ICON
MUX 49
COLUMN DRIVERS
R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31
ROW DRIVERS
STE2004S
ROW DRIVERS
LR0108
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Circuit description Figure 30. Row drivers vs. LCD panel interconnection in MUX33 mode
STE2004S
ICON
MUX 33
COLUMN DRIVERS
R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31
ROW DRIVERS
ROW DRIVERS
STE2004S
LR0107
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STE2004S
Bus interfaces
4
Bus interfaces
To provide the widest flexibility and ease of use the STE2004S features six different methods for interfacing the host controller. To select the desired interface the SEL1, SEL2 and SEL3 pads need to be connected to a logic LOW (connect to GND) or a logic HIGH (connect to VDD). All the I/O pins of the unused interfaces must be connected to GND. All interfaces work while the STE2004S is in power down. Table 7. Bus interfaces
SEL3 0 0 0 0 1 1 SEL2 0 0 1 1 0 0 SEL1 0 1 0 1 0 1 Interface I2C SPI 4 lines 8 bit SPI 3 lines 8 bit Serial 3 lines 9 bit Parallel 8080-series Parallel 68000-series Note Read and write; fast and high speed mode Read and write Read and write Read and write Read and write Read and write
4.1
I2C Interface
The I2C interface is a fully complying I2C bus specification, selectable to work in both Fast (400kHz Clock) and High Speed Mode (3.4MHz). This bus is intended for communication between different LCs. It consists of two lines: one bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via an active or passive pull-up. The following protocol has been defined: Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high are interpreted as control signals.
Accordingly, the following bus conditions have been defined: BUS not busy: Both data and clock lines remain High. Start Data Transfer: A change in the state of the data line, from High to Low, while the clock is High, define the START condition. Stop Data Transfer: A Change in the state of the data line, from low to High, while the clock signal is High, defines the STOP condition. Data Valid: The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the High period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and the stop conditions is not
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Bus interfaces
STE2004S
limited. The information is transmitted byte-wide and each receiver acknowledges with the ninth bit. By definition, a device that gives out a message is called "transmitter", the receiving device that gets the signals is called "receiver". The device that controls the message is called "master". The devices that are controlled by the master are called "slaves" Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA_IN line during the acknowledge clock pulse. Of course, setup and hold time must be taken into account. A master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case, the transmitter must leave the data line High to enable the master to generate the STOP condition. Connecting SDA_IN and SDA_OUT together the SDA line become the standard data line. Having the acknowledge output (SDAOUT) separated from the serial data line is advantageous in Chip-On-Glass (COG) applications. In COG applications where the track resistance from the SDAOUT pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is possible that during the acknowledge cycle the STE2004S will not be able to create a valid logic 0 level. By splitting the SDA input from the output the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDACK pad to the system SDA line to guarantee a valid LOW level. To be compliant with the I2C-bus Hs-mode specification the STE2004S is able to detect the special sequence "S00001xxx". After this sequence no acknowledge pulse is generated. Since no internal modification are applied to work in Hs-mode, the device is able to work in Hs-mode without detecting the master code. Figure 31. Bit transfer and start,stop conditions definition
DATA LINE STABLE DATA VALID CLOCK
DATA
START CONDITION
CHANGE OF DATA ALLOWED
STOP CONDITION
LR0069
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STE2004S Figure 32. Acknowledgment on the I2C-bus
Bus interfaces
START SCLK FROM MASTER
CLOCK PULSE FOR ACKNOWLEDGEMENT 1 2 8 9
DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER
MSB
LSB
LR0070
4.1.1
Communication protocol
The STE2004S is an I2C slave. The access to the device is bi-directional as data write and status read are allowed. The STE2004S has four device addresses. All have the first 5 bits (01111) in common. The two least significant bit of the slave address are set by connecting the SA0 and SA1 inputs to a logic 0 or logic 1. To start the communication between the bus master and the slave LCD driver, the master must initiate a START condition. Following this, the master sends an 8-bit byte, on the SDA bus line (most significant bit first). This consists of the 7-bit device select code, and the 1-bit read/write designator (R/W). All slaves with the corresponding address acknowledge in parallel, while the rest ignore the I2C-bus transfer.
Writing mode
When the R/W bit is set to logic 0, the STE2004S is set to be a receiver. After the slaves acknowledge, one or more command word follows to define the status of the device. A command word is composed of three bytes. The first is a control byte which defines the Co and D/C values, the second and third are data bytes. The Co bit is the command MSB and defines whether this command is followed by two data bytes and and another command word, or if a stream of data follows (Co = 1 Command word, Co = 0 Stream of data). The D/C bit defines whether the data byte is a command or RAM data (D/C = 1 RAM Data, D/C = 0 Command). If Co =1 and D/C = 0, the incoming data byte is decoded as a command, and if Co =1 and D/C =1, the following data byte is stored in the data RAM at the location specified by the data pointer. Every byte of a command word must be acknowledged by all addressed units. After the last control byte, if D/C is set to a logic 1, the incoming data bytes are stored inside the STE2004S display RAM starting at the address specified by the data pointer. The data pointer is automatically updated after every byte written and in the end points to the last RAM location written. Every byte must be acknowledged by all addressed units.
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Bus interfaces
STE2004S
Reading mode
If the R/W bit is set to logic 1 the chip outputs data immediately after the slave address. If the D/C bit during the last write access is set to a logic 0, the byte read is the status byte. Figure 33. Communication protocol
WRITE MODE DRIVER ACK DRIVER ACK DRIVER ACK DRIVER ACK DRIVER ACK
SS S 0 1 1 1 1 A A 0 A 1 DC Control Byte A 10 R/W Co SLAVE ADDRESS READ MODE DRIVER ACK SS S01111AA1A 10 R/W
DATA Byte
A 0 DC Control Byte A
DATA Byte
AP
Co COMMAND WORD
LAST CONTROL BYTE
N> 0 BYTE MSB. . ....LSB
MASTER ACK SSR 01111AA / 1 0W DRIVER SLAVE ADDRESS
P
HHH CD 000 A E [1] [0] oC
CONTROL BYTE
LR0008
4.2
Serial interfaces
STE2004S can feature three different serial synchronized interfaces with the host controller. It is possible to select a 3-lines SPI, a 4-lines SPI or 3-line 9 bits serial interface.
4.2.1
4-lines SPI interface
The STE2004S 4-lines serial interface is a bidirectional link between the display driver and the application supervisor. It consists of four lines: one/two for data signals (SDIN, SOUT), one for clock signals (SCLK), one for the peripheral enable (CS) and one for mode selection (SD/C). The serial interface is active only if the CS line is set to a logic 0. When CS line is high the serial peripheral power consumption is zero. While CS pin is high the serial interface is kept in reset. The STE2004S is always a slave on the bus and receives the communication clock on the SCLK pin from the master. Information is exchanged byte-wide. During data transfer, the data line is sampled on the positive SCLK edge. SD/C line status indicates whether the byte is a command (SD/C =0) or a data (SD/C =1); SD/C line is read on the eighth SCLK clock pulse during every byte transfer. If CS stays low after the last bit of a command/data byte, the serial interface expects the MSB of the next byte at the next SCLK positive edge. A reset pulse on RES pin interrupts the transmission. No data is written into the data RAM and all the internal registers are cleared. If CS is low after the positive edge of RES, the serial interface is ready to receive data. Throughout SDOUT, the driver I2C slave address or the status byte can be read. The command sequence to read the I2C slave address or the status byte is shown in Figure 34., Figure 35.,
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STE2004S
Bus interfaces
Figure 36.. SDOUT is in high impedance in steady state and during data write. It is possible to short circuit SDOUT and SDIN and read the I2C address or status byte without any additional lines.
Figure 34. 4-lines serial bus protocol - one byte transmission
CS
D/C
SCLK
SDIN
MSB
LSB
LR0071
Figure 35. 4-lines serial bus protocol - several byte transmission
CS
D/C
SCLK
SDIN
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
LR0072
Figure 36. 4-lines serial bus protocol - I2C address or status byte read
CS SCLK
SDIN
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
D/C High-Z SDOUT High-Z DB7 DB6 High-Z
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
ID Number DB5 DB4 DB3 DB2 DB1 DB0 High-Z
STATUS BYTE
Command Write
DATA Read
LR00076
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Bus interfaces Figure 37. 4-lines SPI reading sequence
READING SEQUENCE
STE2004S
Write a "0 0 0000" Instruction
SDOUT Buffer becomes active (Low Impedence)
Source 8 pulses on SCLK and 1 Read the ID Number or the Status Byte On SDOUT
SDOUT Buffer Configured in High Impedence
END OF READING SEQUENCE
note: 1) these data are not read by the display Diver 2) SDIN and SDOUT can be short circuited if the processor can configure serial output buffers in high impedence during data read.
LR0078
4.2.2
3-lines SPI interface
The STE2004S 3-lines serial interface is a bidirectional link between the display driver and the application supervisor. It consists of three lines: one/two for data signals (SDIN,SDOUT), one for clock signals (SCLK) and one for peripheral enable (CS). If the R/W bit is set to logic 0 the STE2004S is set to be a receiver. One or more command words follow to define the status of the device. A command word is composed by two bytes. The first is a control byte which defines Co, D/C, R/W H[1;0] and HE values, the second is a data byte (Figure 38.). The Co bit is the command MSB and defines whether the command is followed by one data byte and an other command word, or if it is followed by a stream of commands, or a steam of DDRAM data (Co = 1 Command word, Co = 0 Stream of data). The D/C bit defines whether the data byte is a command or DDRAM data (D/C = 1 RAM Data, D/C = 0 Command). The H[1;0] bits define the instruction Set Page if HE bit =1. If HE bit is set to 0, H[1;0] values are neglected and it is possible to update the instruction set page number using only the related instruction in the instruction set. If Co =1 and D/C = 0, the incoming data byte is decoded as a command, and if Co =1 and D/C =1, the following data byte is stored in the data RAM at the location specified by the data pointer. After the last control byte, if D/C is set to a logic 1, the incoming data bytes are stored inside the STE2004S display data RAM starting at the address specified by the data pointer. The data pointer is automatically updated after every byte written and in the end points to the last RAM location written.
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STE2004S
Bus interfaces Throughout SDOUT can be read the driver I2C slave address or the status byte. The command sequence that allows to read I2C slave address or the status byte is shown in Figure 39. and Figure 40.. If the R bit is set to logic 0 and D/C=0, the I2C slave address is read. If the R bit is set to logic 1 and D/C=0, the the I2C slave address is read. SDOUT is in high impedance in steady state and during data write. It is possible to short circuit SDOUT and SDIN and read the I2C address or status byte without any additional line. Figure 38. 3-lines serial interface protocol in writing mode
WRITE MODE R HHH CD /00 E [1] [0] o CW CONTROL BYTE
1
Control Byte
DATA Byte
0
Control Byte
DATA Byte
Co
COMMAND WORD
Co LAST CONTROL BYTE
N> 0 BYTE MSB. . ....LSB
Control Byte 00 DATA Byte DATA Byte TRANSFERRED ONLY COMMANDS DATA Byte = Command if D/C=0
LAST CONTROL BYTE Control Byte 01
N> 0 BYTE MSB. . ....LSB
DATA Byte = DDRAM Data if D/C=1
DATA Byte
DATA Byte
TRANSFERRED ONLY DDRAM DATA
LAST CONTROL BYTE
N> 0 BYTE MSB. . ....LSB
LR0002
Figure 39. 3-lines SPI interface protocol in reading mode
CS SCLK
Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care
SDIN
DB7
Co=1
DB6
DB5
DB4
DB3
DB2
DB1
DB0
D/C=0 R/W=1 "Command" "Read"
High-Z
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
High-Z
SDOUT High-Z DB7 DB6
ID-Number DB5 DB4 DB3 DB2 DB1 DB0 High-Z
STATUS BYTE
Command Write
DATA Read
LR0077
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Bus interfaces Figure 40. 3-lines SPI reading sequence
READING SEQUENCE
STE2004S
Set Co bit =1, D/C Bit =0 R/W Bit =1
SDOUT Buffer become active (Low Impedence)
Source 8 pulses on SCLK and 1 Read the ID-Number or the Status Byte On SDOUT
SDOUT Buffer Configured in High Impedence
END OF READING SEQUENCE
note: 1) these data are not read by the display Diver 2) SDIN and SDOUT can be short circuited if the processor can configure serial output buffers in high impedence during data read.
LR0079
4.2.3
3-lines 9 bits serial interface
The STE2004S 3-lines serial interface is a bidirectional link between the display driver and the application supervisor. It consists of three lines: one/two for data signals (SDIN, SDOUT), one for clock signals (SCLK) and one for peripheral enable (CS). The serial interface is active only if the CS line is set to a logic 0. When CS line is high the serial peripheral power consumption is zero. While CS pin is high the serial interface is kept in reset. The STE2004S is always a slave on the bus and receives the communication clock on the SCLK pin from the master. Information is exchanged word-wide. The word is composed of 9 bits. The first bit is named SD/C and indicates whether the following byte is a command (SD/C =0) or data byte (SD/C =1). During data transfer, the data line is sampled on the positive SCLK edge. If CS stays low after the last bit of a command/data byte, the serial interface expects the SD/C bit of the next word at the next SCLK positive edge. A reset pulse on RES pin interrupts the transmission. No data is written into the data RAM and all the internal registers are cleared. If CS is low after the positive edge of RES, the serial interface is ready to receive data. Throughout SDOUT, only the driver I2C slave address or the status byte can be read. The command sequence that the I2C slave address or status byte to be read is shown in Figure 43. and Figure 44.. SDOUT is in high impedance in steady state and during data write.
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STE2004S
Bus interfaces It is possible to short circuit SDOUT and SDIN, and read the I2C address or status byte without any additional line. Figure 41. 3-lines serial bus protocol - one byte transmission
CS
SCLK
SDIN
SD/C
MSB
LSB
LR0073
Figure 42. 3-lines serial bus protocol - several byte transmission
CS
SCLK
SDIN
D/C
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
D/C
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
D/C
DB7
DB6
LR0074
Figure 43. 3-lines serial interface protocol in Reading Mode
CS SCLK
Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care
SDIN
SD/C
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
High-Z SDOUT High-Z
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
High-Z
ID-Number DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 High-Z
STATUS BYTE
Command Write
DATA Read
LR0075
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Bus interfaces Figure 44. 3-lines serial reading sequence
READING SEQUENCE
STE2004S
Write a "0 0 0000" Instruction
SDOUT Buffer becomes active (Low Impedence)
Source 9 pulses on SCLK and 1 Read the ID Number or the Status Byte On SDOUT
SDOUT Buffer Configured in High Impedence
END OF READING SEQUENCE
note: 1) these data are not read by the display Diver 2) SDIN and SDOUT can be short circuited if the processor can configure serial output buffers in high impedence during data read.
LR0080
4.3
Parallel interface
The STE2004S selectable parallel interfaces are 68000-series and 8080-series. They are both an 8-bits bi-directional link between the display driver and the application supervisor. Both parallel interfaces can be read the I2C driver slave address or the status byte.
4.3.1
68000-series parallel interface
If CS is low after the positive edge of RES, the 68000 parallel interface is ready to receive or transmit data. While CS pin is high the 68000 parallel interface is kept in reset.
Write mode
If R/W line is set to 0, data is latched on the E falling edge.
Read mode
When R/W line is set to 1, data is output on the D0-D7 bus on the E rising edge. The data bus is set in high impedance mode when E is set to logic 0. The I2C address or status byte is output on D0-D7 bus, according to R bit value.
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STE2004S
Bus interfaces Figure 45. 68000-series parallel interface protocol - one byte transmission
CS
R/W
D/C
E
D0 to D7
LR0004
Figure 46. 68000-series parallel interface bus protocol - several bytes transmission
CS
R/W
D/C
E
D0 to D7
LR0081
Figure 47. 68000-series parallel interface protocol in reading mode
CS
D/C
R/W
E
D0 to D7
LR0082
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Bus interfaces
STE2004S
Figure 48. 68000-series parallel interface protocol in reading mode (several bytes)
CS
D/C
R/W
E
D0 to D7 Note 1) Data Bus is configured in high impedence mode after evry RD rising edge 2) Always the same data is output on D0-D7
LR0046
4.3.2
8080-series parallel interface
If CS is low after the positive edge of RES, the 8080 parallel interface is ready to receive or transmit data. While CS pin is high the 8080 parallel interface is kept in reset.
Write mode
Data are latched on WR rising edge.
Read mode
Data is output on the D0-D7 bus on the RD rising edge. The data bus is set in high impedance mode when RD is set to logic 1. The I2C address or status byte is output on D0-D7 bus, accordingly to R bit value. Figure 49. 8080-series parallel bus protocol - one byte transmission
CS
D/C
RD
WR
D0 to D7
LR0083
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STE2004S
Bus interfaces Figure 50. 8080-series parallel bus protocol - several bytes transmission
CS
D/C
RD
WR
D0 to D7
LR0084
Figure 51. 8080-series parallel interface protocol in reading mode
CS
D/C
RD
WR
D0 to D7
LR0085
Figure 52. 8080-series parallel interface protocol in reading mode (several bytes)
CS
D/C
RD
WR
D0 to D7
LR0045
Note 1) Data Bus is configured in high impedence mode after every RD rising edge 2) Always the same data is output on D0-D7
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Instruction set
STE2004S
5
Instruction set
Two different instructions formats are provided: With D/C set to LOW : commands are sent to the control circuitry. With D/C set to HIGH : the data RAM is addressed.
Two different instruction sets are embedded: the STE2001-like instruction set and the extended instruction set. To select the STE2001-like instruction set, the EXT pad must be connected to a logic LOW (connect to GND). To select the extended instruction set, the EXT pad must be connected to a logic HIGH (connect to VDD1). The instruction syntax is summarized in Table 8. (basic-set) and Table 9. (extended set). Table 8. STE2001/2-like instruction set
Instruction H=0 or H=1 Read I2C address or status byte (with 3-lines serial and 4-lines SPI only) D/C R/W B7 B6 B5 B4 B3 B2 B1 B0 Description
Read command
0
0
0
0
0
0
0
0
0
0
Function set Status byte ID code Write data H=0 Memory blank Scroll VLCD range setting Display control Set CP factor Set RAM Y Set RAM X
0 0 0 1
0 1 1 0
0 PD 0 D7
0 BSY 0 D6
1 0 1 D5
MX D 1 D4
MY E 1 D3
PD MX 1 D2
V MY ID1 D1
Power down H[0] management; entry mode; DO ID0 D0 Writes data to RAM (I2C interface only)
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 1
0 0 0 0 0 1 X6
0 0 0 0 0 0 X5
0 0 0 0 1 0 X4
0 0 0 1 0 Y3 X3
0 0 1 D S2 Y2 X2
0 1 0 0 S1 Y1 X1
1 DIR
Star ts memory blank procedure Scrolls by one row up or down
PRS[ VLDC programming 0] range selection E S0 Y0 X0 Select display configuration Charge pump multiplication factor Set horizontal (Y) RAM address Set vertical (X) RAM address
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STE2004S Table 8. STE2001/2-like instruction set
Instruction H=1 Checker board Duty TC select Data order Bias ratios Reserved Set VOP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 OP6 0 0 0 0 0 X OP5 0 0 0 0 1 X OP4 0 0 0 1 0 X OP3 0 0 1 DO BS2 X OP2 0 1 TC1 0 BS1 X OP1 1 D/C R/W B7 B6 B5 B4 B3 B2 B1 B0
Instruction set
Description
Star ts checker board procedure
MUX Selects duty factor TC0 0 BS0 Set desired bias ratios X OP0 Not to be used VOP register write instruction Set temperature coefficient for VLDC
Table 9. Extended instruction set
Instruction D/C R/W B7 B6 B5 B4 B3 B2 B1 B0 Description
H independent instructions Read I2C address or status byte (with 3-lines serial and 4-lines SPI only)
Read command
0
0
0
0
0
0
0
0
0
0
0 Status byte ID code Write data 0 0 1
0 1 1 0
0 PD 0 D7
0 BSY 0 D6
1 0 1 D5
MX D 1 D4
MY E 1 D3
PD MX 1 D2
H[1] MY ID1 D1
Page selector, power H[0] down management; entry mode DO ID0 D0 Writes data to RAM
H=[0;0] RAM commands Memory blank Scroll VLCD range setting Display control Set CP factor Set RAM Y Set RAM X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X6 0 0 0 0 0 0 X5 0 0 0 0 1 0 X4 0 0 0 1 0 Y3 X3 0 0 1 D S2 Y2 X2 0 1 1 DIR Star ts memory blank procedure Scrolls by one row up or down
PRS[ PRS[ VLDC programming 1] 0] range selection 0 S1 Y1 X1 E S0 Y0 X0 Select display configuration Charge pump multiplication factor Set horizontal (Y) RAM address Set vertical (X) RAM address
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Instruction set Table 9. Extended instruction set
Instruction H=[0;1] Checker board 0 0 TC select Data order Bias ratios Read mode, Set VOP H=[1;0] Driver control Display control 0 0 0 0 Par tial mode 0 0 0 H=[1;1] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 T2 0 1 X T1 1 X X T0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 FR1 M[1] 1 PE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 OP6 0 0 0 0 0 0 OP5 0 0 0 0 1 0 OP4 0 0 0 1 0 R OP3 0 0 1 DO BS2 0 OP2 0 1 TC1 0 BS1 0 OP1 1 V TC0 0 D/C R/W B7 B6 B5 B4 B3 B2 B1 B0
STE2004S
Description
Star ts checker board procedure Ver tical addressing mode Set temperature coefficient for VLDC MSB position
BS0 Set desired bias ratios 0 OP0 VOP register write instruction
Software reset Par tial enable
FR0 Frame rate control M[0] MUX ratio
PDC2 PDC1 PDC0 Par tial display config 1st Sector start address 2nd Sector start address
PDY5 PDY4 PDY3 PDY2 PDY1 PDY0
PDY6 PDY5 PDY4 PDY3 PDY2 PDY1 PDY0
Scrolling pointer reset Not used Not used Set temperature coefficient for VLDC
NW3 NW2 NW1 NW0 N-Line inversion YC-3 YC-2 YC-1 YC-0 Y carriage return
XC-6 XC-5 XC-4 XC-3 XC-2 XC-1 XC-0 X carriage return
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STE2004S Table 10. Explanations of Table 8 and Table 9 symbols
Bit DIR H[0] PD V MX MY DO PE MUX R 0 Scroll by one down Select page 0 Device fully working Horizontal addressing Normal X axis addressing Image is displayed not vertically mirrored MSB on TOP Par tial Display disabled MUX 65 mode Read ID-Number / I2C address Scroll by one up Select page 1 Device in power down Vertical addressing X axis address is mirrored. Image is displayed vertically mirrored MSB on BOTTOM Par tial Display enabled MUX 33 mode Read status byte 1
Instruction set
Reset state
0 1 0 0 0 0 0 0 0
Table 11. Page selection
H[1] 0 0 1 1 H[0] 0 1 0 1 Page 0 Page 1 Page 2 Page 3 Page 0 Description Reset state
Table 12. Display mode
D 0 0 1 1 E 0 1 0 1 Description Display blank Qll display segments on Normal mode Inverse video mode E=0 D=0 Reset state
Table 13. Frame rate control
FR[1] 0 0 1 1 FR[0] 0 1 0 1 Description 65Hz 70Hz 75Hz 80Hz 75Hz Reset state
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Instruction set Table 14. Vlcd range selection
PRS[1] 0 0 1 1 PRS[0] 0 1 0 1 2.94 6.78 10.62 10.62 Description
STE2004S
Reset state
Table 15. Multiplexing ratio
M[1] 0 0 1 1 M[0] 0 1 0 1 49 65 33 Not Allowed 01 Description Reset state
Table 16. Temperature coefficient (T0, T1, T2)
T2 0 0 0 0 1 1 1 1 T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 Description VLCD temperature coefficient 0 VLCD temperature coefficient 1 VLCD temperature coefficient 2 VLCD temperature coefficient 3 VLCD temperature coefficient 4 VLCD temperature coefficient 5 VLCD temperature coefficient 6 VLCD temperature coefficient 7 000 Reset state
Table 17. Temperature coefficient (TC0, TC1)
TC1 0 0 0 1 TC0 0 1 1 1 Description VLCD temperature coefficient 0 VLCD temperature coefficient 2 VLCD temperature coefficient 3 VLCD temperature coefficient 6 00 Reset state
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STE2004S Table 18. Charge pump multiplication factor
CP2 0 0 0 0 1 1 1 1 CP1 0 0 1 1 0 0 1 1 CP0 0 1 0 1 0 1 0 1 Description Multiplication factor X2 Multiplication factor X3 Multiplication factor X4 Multiplication factor X5 Not used Not used Not used Automatic
Instruction set
Reset state
000
Table 19. Bias ratio
BS2 0 0 0 0 1 1 1 1 BS1 0 0 1 1 0 0 1 1 BS0 0 1 0 1 0 1 0 1 Description Bias ratio equal to 7 Bias ratio equal to 6 Bias ratio equal to 5 Bias ratio equal to 4 Bias ratio equal to 3 Bias ratio equal to 2 Bias ratio equal to 1 Bias ratio equal to 0 000 Reset state
Table 20. Y Carriage return register
Y-C[3] 0 0 0 0 0 . 0 0 1 Y-C[2] 0 0 0 0 1 . 1 1 0 Y-C[1] 0 0 1 1 0 . 1 1 0 Y-C[0] 0 1 0 1 0 . 0 1 0 Y-CARRIAGE =6 Y-CARRIAGE =7 Y-CARRIAGE =8 Description Y-CARRIAGE =0 Y-CARRIAGE =1 Y-CARRIAGE =2 Y-CARRIAGE =3 Y-CARRIAGE =4 1000 Reset state
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Instruction set Table 21. Partial display configuration
PD2 0 0 0 0 1 1 1 1 PD1 0 0 1 1 0 0 1 1 PD0 0 1 0 1 0 1 0 1 Section 1 0 8 8 0 16 8 16 16 Section 2 8 + Icon row 0 + Icon row 8 + Icon row 16 + Icon row 0 + Icon row 16 + Icon row 8 + Icon row 16 + Icon row
STE2004S
Reset state
000
Table 22. N-Line inversion
NW3 0 0 0 0 : 1 1 NW2 0 0 0 0 : 1 1 NW1 0 0 1 1 : 1 1 NW0 0 1 0 1 : 0 1 Description 0-Line inversion (Frame inversion) 2-Line inversion 3-Line inversion 4-Line inversion : 15-Line inversion 16-Line inversion 0000 Reset state
5.1
Reset (RES)
At power-on, all internal registers are configured with the default value. The RAM content is not defined. A reset pulse on the RES pad (active low) re-initializes the internal registers content see Table 10. All on-going communication with the host controller is interrupted if a reset pulse is applied. After the power-on, the software reset instruction can be used to reload the reset configuration into the internal registers. The default configuration is:
Horizontal addressing (V = 0) Normal instruction set (H[1:0] = 0) Normal display (MX = MY = 0) Display blank (E = D = 0) Address counter X[6: 0] = 0 and Y[4: 0] = 0 Temperature coefficient (TC[1: 0] = 0) Bias system (BS[2: 0] = 0) Multiplexing ratio (M[1:0]=0 - MUX 65) Frame rate (FR[1:0]="75Hz") Power down (PD = 1) Dual partial display disabled (PE=0) VOP=0 Y-CARRIAGE=8 X-CARRIAGE=101
A memory blank instruction can be used to clear the DDRAM content.
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STE2004S
Instruction set
5.2
Power down (PD = 1)
At power down, all LCD outputs are kept at VSS (display off). Bias generator and VLCD generator are off (VLCDOUT output is discharged to VSS, and then VLCDOUT can be disconnected). The internal oscillator is in off state. An external clock can be provided. The RAM contents is not cleared.
5.3
Memory blanking procedure
This instruction fills the memory with "blank" patterns, in order to delete patterns randomly generated in memory when starting up the device. It substitutes (102X8) single "write" instructions. The procedure can only be programmed if: PD bit = 0 No instruction can be programmed for a period equivalent to 102X8 internal write cycles (102X8X1/fclock). The start of the memory blanking procedure is between one and two fclock cycles from the last active edge (E falling edge for the parallel interface, last SCLK rising edge for the serial and SPI interfaces, last SCL rising edge for the I2C interface).
5.4
Checker board procedure
This instruction fills the memory with "checker-board" pattern, allowing developers to create a complex module test configuration using one instruction. It can only be programmed if: PD bit = 0 No instruction can be programmed for a period equivalent to 102X8 internal write cycles (102X8X1/fclock). The start of checker-board procedure is between one and two fclock cycles from the last active edge (E falling edge for the parallel interface, last SCLK rising edge for the serial and SPI interfaces, last SCL rising edge for the I2C interface).
5.5
Scrolling function
The STE2004S can scroll the graphics display in units of raster-rows. The scrolling function changes the correspondence between the rows of the logical memory map and the output row drivers. The scroll function does not affect the data ram contentm it is only related to the visualization process. The information output on the drivers is related to the row reading sequence (the 1st row read is output on R0, the 2nd on R1 and so on). Scrolling means reading the matrix starting from a row that is sequentially increased or decreased. After every scrolling command the offset between the memory address and the memory scanning pointer is increased or decreased by one. The offset range changes in accordance with MUX Rate. After 64th/65th scrolling commands in MUX 65 mode, or after the 48th/49th scrolling commands in MUX 49 mode, or after 32nd/33rd scrolling command in MUX 33 mode, the offset between the memory address and the memory scanning pointer is again zero (Cyclic Scrolling). A Reset Scrolling Pointer instruction can be executed to force the offset between the memory address and the memory scanning pointer to zero. If ICON MODE =1, the Icon Row is not scrolled. If ICON MODE=0 the last row is like a general purpose row and it is scrolled as other lines.
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Instruction set
STE2004S
If the DIR bit is set to a logic 0, the offset register is increased by one and the raster is scrolled from top down. If the DIR bit is set to a logic 1, the offset register is decreased by one and the raster is scrolled from bottom-up. Table 23. Scrolling function
MUX Rate MUX 33 MUX 33 MUX 49 MUX 49 MUX 65 MUX 65 Icon mode 1 0 1 0 1 0 Description Icon row not scrooled 33 line graphic matrix Icon row not scrooled 49 line graphic matrix Icon row not scrooled 65 line graphic matrix Icon row driver with MY=0 R48 R48 R56 R56 R64 R64
5.6
Dual partial display
If the PE bit is set to a logic one the dual partial display mode is enabled. There are eight partial display modes available. The offset of the two partial display zones is row by row programmable. The icon row is accessed last in each partial display frame. Two sets of register for the HV-generator parameters are provided (PRS[1:0], Vop[6:0], BS[2:0], CP[2:0]), allowing normal mode and partial display mode to be switched using one instruction. The HV generator is automatically reconfigured using the parameters related to the enabled mode. The parameters of the two sets of registers with the same function are located in the same position of the instruction set. The registers related to the normal mode are accessible when normal mode (PE=0) is selected, the others are accessible when the partial display mode is enabled (PE=1). To setup the PRS[1:0], Vop[6:0], BS[2:0], CP[2:0] values, follow the instruction flow proposed in Figure 54. To setup partial display sectors start qddress and partial display mode no particular instruction flow has to be followed. Figure 53. Dual partial display enabling instruction flow
ENABLE DUAL PARTIAL DISPLAY
SET 1st Sector Start Address SET 2nd Sector Start Address
OPTIONAL1
SET PE=1
END OF ENABLING DUAL PARTIAL DISPLAY
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STE2004S Figure 54. Dual partial display mode configuration or duty change
SETUP PARTIAL DISPLAY CONFIGURATION
Instruction set
SET Driver in Power Down(PD=1)
SET Driver in Partial Display Mode (PE=1)
SET PRS[1:0], Vop[6:0], BS[2:0], CP[2:0] for Partial Display Operation
SET Partial Display Configuration (PDC[2:0]) SET 1st Sector Start Address SET 2nd Sector Start Address
OPTIONAL
SET Driver in Normal Mode (PE=0)
END OF PARTIAL DISPLAY CONFIG.
Table 24. Partial display configurations
PDC2 0 0 0 0 1 1 1 1 PDC1 0 0 1 1 0 0 1 1 PDC0 0 1 0 1 0 1 0 1 Section 1 0 8 8 0 16 8 16 16 Section2 8 + Icon Row 0 + Icon Row 8 + Icon Row 16 + Icon Row 0 + Icon Row 16 + Icon Row 8 + Icon Row 16 + Icon Row 000 Reset state
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ID-number
STE2004S
6
ID-number
The STE2004S lets you program a driver identification number (ID-Number), so more than one LCD module with different configuration parameters can be managed on one platform. There are four programmable device ID-numbers: 00111100, 00111101, 0011110 and 0011111. All have the first 6 bits (001111) in common. The two least significant bits can be used to connect the SA0 and SA1 inputs to a VSS or VDD1. The driver ID-number can be read through all communication interfaces. The way to read the ID-number changes according the interface selected. The readout protocol for each interface is described in Chapter 4. Figure 55. I2C interface interconnection in master/ slave mode
STE2004S
RES SCL SDAOUT SDAIN
STE2004S
RES SCL SDAOUT SDAIN
LR0214
NOTE: MASTER and SLAVE I2C AADDRESS MUST BE DIFFERENT RES SCL SDA
Figure 56. I3-lines SPI and 3-lines serial interfaces interconnection in master slave mode
STE2004S
RES CS SCLK SDIN SDOUT RES
STE2004S
CS SCLK SDIN SDOUT
LR0215
RES MASTER SCLK CS
SD
SLAVE CS
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STE2004S Figure 57. 4-lines SPI interface interconnection in master slave mode
ID-number
STE2004S
RES CS D/C SCLK SDIN SDOUT RES
STE2004S
D/C CS SCLK SDIN SDOUT
LR0216
RES
MASTER D/C CS
SCLK
SD
SLAVE CS
Figure 58. 8080-series and 68000-series interface interconnection in master slave mode
STE2004S
RES CS D/C RW-RD E-WR D7-D0 RES 8 LINES
STE2004S
D/C CS RW-RD E-WR D7-D0
LR0217
8 LINES
RES
MASTER D/C CS
RW-RD E-WR
D7-D0
SLAVE CS
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ID-number Figure 59. Host processor interconnection with I2C interface
STE2004S
VSS TEST_MODE VSSAUX D0 D1 D2 D3 D4 D5 D6 D7 SCLK -SCL SDOUT SDIN-SDAIN SDAOUT VSSAUX E - WR R/W - RD D/C CS RES VDD2 VDD1 ICON SEL1 SEL2 SEL3 EXT_SET M/S SA0 SA1 VSSAUX TEST VREF VSENSE_SLAVE OSC_IN FR_IN VDD1_AUX ANALOG VDD DIGITAL VDD VDD1 / VSSAUX VSSAUX
P
STE2004S
VDD1 / VSSAUX VDD1 VDD1 / VSSAUX VDD1 / VSSAUX
LR0110
Figure 60. Host processor interconnection with 4-line SPI interface
VSS TEST_MODE VSSAUX D0 D1 D2 D3 D4 D5 D6 D7
P
STE2004S
SCLK-SCL SDOUT SDIN-SDAIN SDAOUT VSSAUX E - WR R/W - RD D/C CS RES VDD2 VDD1 ICON SEL1 SEL2 SEL3 EXT_SET M/S SA0 SA1 VSSAUX TEST VREF VSENSE_SLAVE OSC_IN FR_IN VDD1_AUX ANALOG VDD DIGITAL VDD VDD1 / VSSAUX VDD1 VSSAUX VDD1 / VSSAUX VDD1 VDD1 / VSSAUX VDD1 / VSSAUX
LR0111
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STE2004S Figure 61. Host processor interconnection with 3-line SPI interface
ID-number
VSS TEST_MODE VSSAUX D0 D1 D2 D3 D4 D5 D6 D7
P
STE2004S
SCLK-SCL SDOUT SDIN-SDAIN SDAOUT VSSAUX E - WR R/W - RD D/C CS RES VDD2 VDD1 ICON SEL1 SEL2 SEL3 EXT_SET M/S SA0 SA1 VSSAUX TEST VREF VSENSE_SLAVE OSC_IN FR_IN VDD1_AUX ANALOG VDD DIGITAL VDD VDD1 / VSSAUX VSSAUX VDD1 VSSAUX VDD1 / VSSAUX VDD1 VDD1 / VSSAUX VDD1 / VSSAUX
LR0112
Figure 62. Host processor interconnection with 3-line serial interface
VSS TEST_MODE VSSAUX D0 D1 D2 D3 D4 D5 D6 D7
P
STE2004S
SCLK-SCL SDOUT SDIN-SDAIN SDAOUT VSSAUX E - WR R/W - RD D/C CS RES VDD2 VDD1 ICON SEL1 SEL2 SEL3 EXT_SET M/S SA0 SA1 VSSAUX TEST VREF VSENSE_SLAVE OSC_IN FR_IN VDD1_AUX ANALOG VDD DIGITAL VDD VDD1 / VSSAUX VDD1 VDD1 VSSAUX VDD1 / VSSAUX VDD1 VDD1 / VSSAUX VDD1 / VSSAUX
LR0113
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ID-number
STE2004S Figure 63. Host processor interconnection with 8080-series parallel interface
VSS TEST_MODE VSSAUX D0 D1 D2 D3 D4 D5 D6 D7
P
STE2004S
SCLK-SCL SDOUT SDIN-SDAIN SDAOUT VSSAUX E - WR R/W - RD D/C CS RES VDD2 VDD1 ICON SEL1 SEL2 SEL3 EXT_SET M/S SA0 SA1 VSSAUX TEST VREF VSENSE_SLAVE OSC_IN FR_IN VDD1_AUX ANALOG VDD DIGITAL VDD VDD1 / VSSAUX VSSAUX VSSAUX VDD1 VDD1 / VSSAUX VDD1 VDD1 / VSSAUX VDD1 / VSSAUX
LR0114
Figure 64. Host processor interconnection with 6800
VSS TEST_MODE VSSAUX D0 D1 D2 D3 D4 D5 D6 D7
P
STE2004S
SCLK-SCL SDOUT SDIN-SDAIN SDAOUT VSSAUX E - WR R/W - RD D/C CS RES VDD2 VDD1 ICON SEL1 SEL2 SEL3 EXT_SET M/S SA0 SA1 VSSAUX TEST VREF VSENSE_SLAVE OSC_IN FR_IN VDD1_AUX ANALOG VDD DIGITAL VDD VDD1 / VSSAUX VDD1 VSSAUX VDD1 VDD1 / VSSAUX VDD1 VDD1 / VSSAUX VDD1 / VSSAUX
LR0115
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STE2004S
ID-number Figure 65. Application schematic using the internal LCD voltage generator and two separate supplies
I/O VDD2 VDD1 1F VSS 1F VLCDSENSE 33 VDD2 VDD1 1F VSS 102 65 x 102 DISPLAY
32
VLCD
Figure 66. Application schematic using the internal LCD voltage generator and a single supply
I/O VDD 1F VSS 1F VLCDSENSE 33 VSS 102
VDD2 VDD1
32
65 x 102 DISPLAY
VLCD
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ID-number Figure 67. Power-ON timing diagram
STE2004S
Tvdd
Tw(res)
Tlogic(res)
VDD2
VDD1
RES
CS SCLK SDIN D/C E
R/W
D0 - D7 HOST
D0 - D7 DRIVER
Hi-Z
SCL- SDAIN
SDOUT SDA OUT
Hi-Z
OSCIN, FR_IN (HOST)
OSC OUT, FR_OUT (DRIVER)
RESET POWER ON BOOSTER Acceptance INTERNAL OFF RESET Time
LR0208
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STE2004S Figure 68. Power-OFF timing diagram
ID-number
TVDD
VDD2
VDD1
RES
CLK-SCL SDIN-SDAIN D/C E CS R/W
D0 - D7 HOST
D0 - D7 DRIVER
Hi-Z
SDOUT SDA-OUT
Hi-Z
OSCIN (HOST)
OSC OUT FR_OUT (DRIVER) FR_IN
RESET TABLE LOADED
LR0207
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ID-number Figure 69. Initialization with built-in booster
STE2004S
SETUP NORMAL DISPLAY MODE CONFIGURATION
SET Driver in Power Down(PD=1)
SET Driver in Normal Display Mode (PE=0)
SET Operative Voltage for Normal Display Operation ( Vop[6:0] - PRS[1;0])
SET Bias Raio for Normal Display Operation (BS[2:0])
SET Temperature Compensation for Normal Display Operation (T[2:0] or TC[1:0])
SET Multiplexing Rate M[1:0)
SET Charge Pump for Normal Display Operation (CP[1:0])
Switch "ON" Booster and Display Control Logic (PD=0)
END OF NORMAL DISPLAY MODE CONFIG.
LR0218
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STE2004S Figure 70. Data RAM to display mapping
DISPLAY DATA RAM
bank 0
ID-number
GLASS TOP VIEW
bank 1
DISPLAY DATA RAM = "1" DISPLAY DATA RAM = "0"
bank 2
LCD
bank 3
bank 7
bank 8
ICOR ROW
D00IN1155
Table 25. Test pin configuration
Test Pin TEST_VREF TEST_MODE Pin Configuration OPEN GND
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Electrical characteristics
STE2004S
7
7.1
Symbol VDD1 VDD2 VLCD ISS Vi Iin Iout Ptot Po Tj Tstg
Electrical characteristics
Absolute maximum ratings
Parameter Supply voltage range Supply voltage range LCD supply voltage range Supply current Input voltage (all input pads) DC input current DC output current Total power dissipation (Tj = 85C) Power dissipation per output Operating junction temperature(1) Storage temperature Value - 0.5 to + 5 - 0.5 to + 7 - 0.5 to + 15 - 50 to +50 -0.5 to VDD1 + 0.5 - 10 to + 10 - 10 to + 10 300 30 -25 to + 85 - 65 to 150 Unit V V V mA V mA mA mW mW C C
Table 26. Absolute maximum ratings
1. Device behavior and characterization are measured over this temperature range during internal qualification of the product. During production testing, however, device performance is measured at a fixed ambient temperature - typically 25C.
7.2
DC operation
VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =25C; unless otherwise specified.
Table 27. DC operation
Symbol Supply voltages VDD1 VDD2 Supply voltage(1) LCD voltage internally generated LCD voltage supplied externally Internally generated(2) VDD1 = 2.8V; VLCD = 10V; fsclk = 0; Parallel Port (3) (5) VDD2 = 2.8V; VLCD = 10V; fsclk = 1Mhz; OSC_IN=GND(3) 1.7 3.6 VDD2 Supply voltage LCD supply voltage VLCD LCD supply voltage Supply current I(VDD1) Supply current write mode 1.75 4.5 4.5 15 20 4.5 14.5 14.5 40 V V V V V A Parameter Test condition Min. Typ. Max. Unit
100
200
A
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STE2004S Table 27. DC operation (continued)
Symbol Parameter Test condition with VOP = 0 and PRS = [0:0] with external VLCD(4) Min.
Electrical characteristics
Typ.
Max. 5
Unit A
I(VDD2)
Voltage generator supply VDD2 = 2.8V; current VLCD = 10V; fsclk=0; no display load; 5x charge pump(5)(3) (6) VDD2 = 2.8V; VLCD = 10V; 5x charge pump; fsclk = 0; no display load(5) (3) (6) Power down mode with internal or external VLCD(7) External LCD supply voltage current VDD =2.8V; VLCD =10V; no display load; fsclk = 0;(3)
60
150
A
80
190
A
I(VDD1,2)
Total supply current
3
15
A
I(VLDCIN)
25
A
Logic outputs V0H VOL High logic level output voltage Low logic level output voltage IOH=-500A IOL=+500A 0.8VDD1 VSS VDD1 0.2VDD1 V V
Logic inputs VIL VIH Iin Logic low voltage level Logic high voltage level Input current Vin = VSS1 or VDD1 VSS 0.7 VDD1 -1 0.3 VDD1 VDD2 1 V V A
Logic inputs/outputs VIL VIH Logic low voltage level Logic high voltage level VSS 0.7 VDD1 0.3 VDD1 VDD1 + 0.5 V V
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Electrical characteristics Table 27. DC operation (continued)
Symbol Parameter Test condition Min. Typ. Max.
STE2004S
Unit
Column and row driver Rrow Rcol Vcol Vrow ROW output resistance Column output resistance Column bias voltage accuracy Row bias voltage accuracy No load -50 -50 3K 5K 5K 10K +5 0 +50 kohm kohm mV mV
LCD supply voltage LCD supply voltage accuracy; internally generated VDD = 2.8V; VLCD = 10V; fsclk=0; no display load(5)(3) (6) (8) VOP=69h, PRS=2Hex(9)
VLCD
-2
+2
%
TC0 TC1 TC2 TC3 Temperature coefficient TC4 TC5 TC6 TC7
1. VDD1<=VDD2
-0.0· 10-3 -0.35 · -0.7 · -1.05· 10-3
1/C 1/C 1/C 1/C 1/C 1/C 1/C 1/C
10-3 10-3
-1.4 · 10-3 -1.75· -2.1 · -2.3· 10-3 10-3 10-3
2. The maximum possible VLCD voltage that can be generated is dependent on voltage, temperature and (display) load. 3. When fsclk = 0 there is no interface clock. 4. If external VLCD, the display load current is not transmitted to IDD 5. Internal clock 6. Tolerance depends on the temperature; (typically zero at Tamb = 25C), maximum tolerance values are measured at the temperature range limit. 7. Power-down mode. During power-down all static currents are switched-off. 8. For TC0 to TC7 9. Data byte writing mode
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STE2004S
Electrical characteristics
7.3
AC operation
VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =25C; unless otherwise specified.
Table 28. AC operation
Symbol Parameter Test condition Min. Typ. Max. Unit
Internal oscillator (Figure 71) FOSC FEXT FFRAME Tw(RES) TLOGIC
(RES)
Internal oscillator frequency External oscillator frequency Frame frequency RES LOW pulse width Reset pulse rejection Internal logic reset time VDD1 vs. VDD2 Delay
VDD = 2.8V
61 20
72
83 100
kHz kHz Hz s
fosc or fext = 72 kHz(1) 5
75
1 5 0
s s s
TVDD I2C
bus interface (Figure
72)(2) (3)
Fast mode High speed mode; Cb=100pF (max);(4) VDD1=2 High speed mode; Cb=400pF (max)(4); VDD1=2 Fast Mode (4);VDD1=1.7V DC DC 400 3.4 kHz MHz
FSCL
SCL clock frequency
DC
1.7 400
MHz KHz ns ns ns ns ns ns ns
TSU;STA THD;STA TLOW THIGH TSU;DAT THD;DAT Tr;CL
Set-up time (repeated) START condition Hold time (repeated) START condition Low period of SCLH clock High period of SCLH clock Data set-up time Data hold time
Cb = 100pF(5) (6) Cb = 100pF(5) (6) Cb = 100pF(5) (6) Cb = 100pF(5) (6) Cb = 100pF(5) (6) Cb = 100pF(5) (6) 100pF(5) (6)
160 160 160 160 60 10 10
Rise time of SCLH signal Cb =
Tr;CL1
Rise time of SCLH signal after a repeated START Cb = 100pF(5) (6) condition and aftyer an acknowledge bit Fall time of SCLH signal Cb = 100pF(5) (6)
10
ns
Tf;CL
10
ns
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Electrical characteristics Table 28. AC operation
Symbol Tr;DA Tf;DA Tr;DA Tf;DA TSU;STO Cb Parameter Test condition
(5) (6)
STE2004S
Min. 10 10 20 20 160 100
Typ.
Max.
Unit ns
Rise time of SCLH signal Cb = 100pF Fall time of SDAH signal
Cb = 100pF(5) (6)
(5) (6) (5) (6)
80
ns ns
Rise time of SDAH signal Cb = 400pF Fall time of SDAH signal Setup time for STOP condition Capacitive load for SDAH and SCLH Capacitive load for SDAH +SDA line and SCLH +SCL line Cb = 400pF
160
ns ns
Cb = 100pF(5) (6)
400
pF
Cb
400
pF
Parallel interface (Figure 73, Figure 74) TCYC TCLW TCHW TCLR TCHR TEWHW TEWLW TEWHR TEWLR TSU(A) TH(A) TSU1 TH1 TSU2 TH2 System cycle time Control low pulse width (WR) Control high pulse width (WR) Control low pulse width (RD) Control high pulse width (RD) Enable high pulse width (Write) Enable low pulse width (Write) Enable high pulse width (Read) Enable low pulse width (Read) Address set-up time Address hold time Data set-up time Data hold time Read access time Output disable time 0 VDD1 = 1.7V; read and write 125 20 75 40 55 60 60 60 60 10 10 30 30 40 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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STE2004S Table 28. AC operation
Symbol Parameter Test condition Min.
Electrical characteristics
Typ.
Max.
Unit
Serial interface (Figure 75) FSCLK TCYC TPWH1 TPWL1 TS2 TH2 TPWH2 TS3 TH3 TS4 TH4 TS5 TH5 TH6 Clock frequency Clock cycle SCLK SCLK pulse width HIGH SCLK pulse width LOW CS setup time CS hold time CS minimum high time SD/C setup time SD/C hold time SDIN setup time SDIN hold time SDOUT access time SDOUT disable time vs. SCLK SDOUT disable time vs. CS 960 0 0 VDD1 = 1.7V VDD1 = 1.7V VDD1 = 1.7V VDD1 = 1.7V; 8 125 60 60 40 50 50 30 30 30 40 30 20 20 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns
fo sc 1. F ---f r a m e = ----2. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated 3. Trise and Tfall (30%-70%) -10ns 4. CVLCD is the filtering capacitor on VLCD
5. All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to VIL and VIH with an input voltage swing of VSS to VDD 6. Cb is the capacitive load for each bus line.
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Electrical characteristics Figure 71. Reset timing diagram
Tw(res) Tlogic(res)
STE2004S
VDD2
VDD1
RES
INPUTS
I/O (HOST)
I/O (DRIVER) INTERFACE OUTPUT OSCIN FR_IN (HOST) OSC OUT FR_OUT (DRIVER)
Hi-Z
Hi-Z
RESET TABLE LOADED
LR0209
Figure 72. I2C-bus timings
Sr tfDA trDA Sr P
SDAH tHD;DAT tSU;STA SCLH tfCL trCL tHIGH tLOW
= MCS current source pull-up
tSU;DAT
tHD;STA
trCL1
(1)
trCL1
(1)
tLOW tHIGH
LR0093
= Rp resistor pull-up
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STE2004S Figure 73. 68000-series parallel interface timing
D/C R/W
Electrical characteristics
tSU(A)
CS
tH(A)
tCYC tEWHR, tEWHW
E
tEWLR, tEWLW tSU1
D0 to D7 (Write)
tH1
tSU2
D0 to D7 (Read)
tH2
Figure 74. 8080-series parallel interface timing
D/C
tSU(A)
CS
tH (A)
tCYC tCLR , tCLW
WR, RD
tCHR , tCHW tSU1
D0 to D7 (Write)
tH1
tSU2
D0 to D7 (Read)
tH2
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Pad coordinates Figure 75. Serial interface timing
tS2 CS tS3 D/C tCYC tPWL1 SCLK tS4 SDIN tS5 SOUT
LR0096
STE2004S
tH2
tPWH2
tH3
tWH1 tS2
tH4
tH5
tH6
8
Pad coordinates
See Table 29: Pad coordinates and Table 30: Alignment marks coordinates.
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STE2004S Table 29. Pad coordinates
No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Pad placements Name X R5 R4 R3 R2 R1 R0 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 -2632.5 -2587.5 -2542.5 -2497.5 -2452.5 -2407.5 -2362.5 -2317.5 -2272.5 -2227.5 -2182.5 -2137.5 -2092.5 -2047.5 -2002.5 -1957.5 -1912.5 -1867.5 -1822.5 -1777.5 -1732.5 -1687.5 -1642.5 -1597.5 -1552.5 -1507.5 -1462.5 -1417.5 -1372.5 -1327.5 -1282.5 -1237.5 -1192.5 Y -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 No
Pad coordinates
Pad placements Name X -1147.5 -1102.5 -1057.5 -1012.5 -967.5 -922.5 -877.5 -832.5 -787.5 -742.5 -697.5 -652.5 -607.5 -562.5 -517.5 -472.5 -427.5 -382.5 -337.5 -292.5 -247.5 -202.5 -157.5 -112.5 112.5 157.5 202.5 247.5 292.5 337.5 382.5 427.5 472.5 Y -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8
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Pad coordinates Table 29. Pad coordinates
No 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Pad placements Name X C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 517.5 562.5 607.5 652.5 697.5 742.5 787.5 832.5 877.5 922.5 967.5 1012.5 1057.5 1102.5 1147.5 1192.5 1237.5 1282.5 1327.5 1372.5 1417.5 1462.5 1507.5 1552.5 1597.5 1642.5 1687.5 1732.5 1777.5 1822.5 1867.5 1912.5 1957.5 Y -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 C93 C94 C95 C96 C97 C98 C99 C100 C101 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 No
STE2004S
Pad placements Name X 2002.5 2047.5 2092.5 2137.5 2182.5 2227.5 2272.5 2317.5 2362.5 2407.5 2452.5 2497.5 2542.5 2587.5 2632.5 2773.8 2773.8 2773.8 2773.8 2773.8 2773.8 2773.8 2773.8 2773.8 2773.8 2773.8 2773.8 2773.8 2773.8 2773.8 2773.8 2773.8 2773.8 Y -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -532.8 -472.5 -427.5 -382.5 -337.5 -292.5 -247.5 -202.5 -157.5 -112.5 -67.5 -22.5 2 2 .5 6 7 .5 112.5 157.5 202.5 247.5 292.5
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STE2004S Table 29. Pad coordinates
No 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 Pad placements Name X R56 R57 R58 R59 R60 R61 R62 R63 R64/ICON VDD1 AUX FR IN OSC IN Vsns_Slave TEST_VREF VSSAUX SA1 SA0 M/S EXT_SET SEL3 SEL2 SEL1 ICON VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 2773.8 2773.8 2773.8 2773.8 2632.5 2587.5 2542.5 2497.5 2452.5 2227.5 2182.5 2137.5 2092.5 1777.5 1732.5 1687.5 1642.5 1597.5 1552.5 1507.5 1462.5 1417.5 1372.5 1327.5 1282.5 1237.5 1192.5 1147.5 1102.5 1057.5 1012.5 967.5 922.5 Y 337.5 382.5 427.5 472.5 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 _RES -CS D/C RW-RD E-WR VSSAUX SDA_OUT SDIN_SDAIN SDOUT SCLK_SCL D7 D6 D5 D4 D3 D2 D1 D0 VSSAUX TEST_MODE VSS VSS VSS VSS VSS VSS VSS No
Pad coordinates
Pad placements Name X 877.5 832.5 787.5 742.5 697.5 652.5 337.5 247.5 157.5 67.5 -22.5 -67.5 -157.5 -202.5 -247.5 -337.5 -382.5 -427.5 -472.5 -517.5 -562.5 -607.5 -652.5 -697.5 -742.5 -1102.5 -1147.5 -1192.5 -1237.5 -1282.5 -1327.5 -1372.5 -1417.5 Y 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8
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Pad coordinates Table 29. Pad coordinates
No 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 Pad placements Name X VSS VSS VSS VSS VSS VLCD_SNS VLCD VLCD VLCD VLCD VLCD OSC_OUT FR_OUT R31 R30 R29 R28 R27 R26 R25 R24 -1462.5 -1507.5 -1552.5 -1597.5 -1642.5 -1867.5 -1912.5 -1957.5 -2002.5 -2047.5 -2092.5 -2227.5 -2272.5 -2497.5 -2542.5 -2587.5 -2632.5 -2773.8 -2773.8 -2773.8 -2773.8 Y 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 532.8 472.5 427.5 382.5 337.5 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 R23 R22 R21 R20 R19 R18 R17 R16 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 No
STE2004S
Pad placements Name X -2773.8 -2773.8 -2773.8 -2773.8 -2773.8 -2773.8 -2773.8 -2773.8 -2773.8 -2773.8 -2773.8 -2773.8 -2773.8 -2773.8 -2773.8 -2773.8 -2773.8 -2773.8 Y 292.5 247.5 202.5 157.5 112.5 67.5 22.5 -22.5 -67.5 -112.5 -157.5 -202.5 -247.5 -292.5 -337.5 -382.5 -427.5 -472.5
1. I2C bus AC characteristics are tested by correlation
Table 30. Alignment marks coordinates
Marks mark1 mark2 mark3 mark4 X -2780.55 2780.55 -2160.0 484.89 Y -539.55 -539.55 539.55 539.55
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STE2004S Figure 76. Alignment marks dimensions
Pad coordinates
35 m 85 m
Table 31. Bumps
Dimensions Bumps size Pad size Pad pitch Spacing between bumps 28mX97mX17.5m 35m X 104m 45m 17m
Table 32. Die mechanical dimensions
Die Size (X x Y) Wafers thickness 5.815mm x 1.333mm 500m
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Ordering information
STE2004S
9
Ordering information
Table 33. Ordering information
Part numbers STE2004S DIE2 Type Bumped dice on waffle pack
10
Revision history
Table 34. Document revision history
Date 24-Jan-2006 Revision 1 Initial release. Junction temperature range in Table 26: Absolute maximum ratings set to: -25 to + 85 and added a footnote. Globally set Tamb = 25C Moved Table 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20 from Chapter 6: ID-number to Chapter 5: Instruction set where Table 8 and Table 9 are referenced. Ordering information moved from cover page to Chapter 9. Added Chapter 1: Block diagram and corrected the document title. Changes
12-Dec-2006
2
31-Jan-2007
3
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STE2004S
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