Datasheets | Application Specific for Mobile Systems | Converters for Mobile Systems | Audio Codec Interfaces

Dual low power asynchronous stereo audio Codec with integrated power amplifiers

Datasheet

Format: (939 kb)

Last Updated: 26/04/2007

Pages: 86

Untitled Document

Generic Part Number

Orderable Part Number

Status

STw5098	STW5098/E01	Preview
	STW5098T	Active
	STW5098BBLR/LF	Active
	STW5098BBLT/LF	Active
	STW5098	Active

Related Data Briefs

Dual low power asynchronous stereo audio codec with integrated power amplifiers

Related Programming Manuals

Low level drivers for STw5098 audio codec

Related User Manuals

STw5098 evaluation board

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IMPORTANT NOTICE
Dear customer, As from August 2nd 2008, the wireless operations of STMicroelectronics have moved to a new company, ST-NXP Wireless. As a result, the following changes are applicable to the attached document.

Company name - STMicroelectronics NV is replaced with ST-NXP Wireless. Copyright - the copyright notice at the bottom of the last page " STMicroelectronics 200x - All rights reserved", shall now read: " ST-NXP Wireless 200x - All rights reserved". Web site - http://www.st.com is replaced with http://www.stnwireless.com Contact information - the list of sales offices is found at http://www.stnwireless.com under Contacts.

If you have any questions related to the document, please contact our nearest sales office. Thank you for your cooperation and understanding. ST-NXP Wireless

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STw5098
Dual low power asynchronous stereo audio Codec with integrated power amplifiers
Features

Dual 20 bit audio resolution, 8kHz to 96kHz independent rate ADC and DAC Dual I2S or PCM digital interfaces for dual master Sustain complex voice and audio flow with or without mixing I2C/SPI compatible control I/F Asynchronous sampling ADC and DAC: they do not require oversampled clock and information on the audio data sampling frequency (fs). Jitter tolerant fs Wide master clock range: from 4MHz to 32MHz Stereo headphones drivers, handsfree loudspeaker driver, line out drivers Mixable analog line inputs Voice filters: 8/16kHz with voice channel filters Automatic gain control for microphone and linein inputs Frequency programmable clock outputs Multibit modulators with data weighted averaging ADC and DAC DSP functions for bass-treble-volume control, mute, mono/stereo selection, voice channel filters, de-emphasis filter and dynamic compression 93 dB dynamic range ADC, 0.001% THD with full scale output @ 2.7V 95 dB dynamic range DAC, 0.02% THD performance @ 2.7V over 16 load
LFBGA 6x6x1.4 (112 pins) VFBGA 5x5x1 (112 pins)

STw5098

Description
STw5098 is a dual low power asynchronous stereo audio CODEC device with headphones amplifiers for high quality audio listening and recording. Two I2S/PCM digital interfaces are available, one per master for example Bluetooth and Application Processor, enabling concurrent audio and voice flow between Network and user. The STw5098 control registers are accessible through a selectable I2C-bus compatible or SPI compatible interface.

Appl ication s

Digital cellular telephones with application processor such as mp3 or gaming and Bluetooth concurrent application

April 2007

Rev 1

1/85
www.st.com
1

Contents

STw5098

Contents
1 2 3 4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 P inout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4. 1 4.2 4. 3 4. 4 4. 5 4. 6 4.7 4. 8 4.9 4. 10 4. 11 4. 12 4. 13 4.14 4. 15 4.16 4.17 4.18 Naming convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Device programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Clock generators and master mode function . . . . . . . . . . . . . . . . . . . . . . 20 Audio digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Analog output drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Analog mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 AD paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DA paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Analog-only operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Automatic Gain Control (AGC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Interrupt request: IRQ pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Headset plug-in and push-button detection . . . . . . . . . . . . . . . . . . . . . . . 26 Microphone biasing circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5

Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5. 1 5.2 5. 3 5.4 5. 5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Supply and power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DSP control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Analog functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2/85

STw5098

Contents

5.6 5.7 5. 8 5.9 5. 10

Digital audio interfaces master mode and clock generators . . . . . . . . . . . 41 Digital audio interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Digital filters, software reset and master clock control . . . . . . . . . . . . . . . 45 Interrupt control and control interface SPI out mode . . . . . . . . . . . . . . . . 46 AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6

Control interface and master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.1 6.2 6. 3 Control interface I2C mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Control interface SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Master clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7 8 9

Audio interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Operative ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9. 1 9.2 9. 3 9. 4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Operative supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Typical power dissipation by entity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

10

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10. 1 10.2 10. 3 10.4 10.5 10.6 10.7 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 AMCK with sinusoid input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Analog interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Headset plug-in and push-button detector . . . . . . . . . . . . . . . . . . . . . . . . 64 Microphone bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Power supply rejection ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 LS and EAR gain limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

11

Analog input/output operative ranges . . . . . . . . . . . . . . . . . . . . . . . . . 66
11. 1 11.2 11. 3 11. 4 Analog levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Microphone input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Line output levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Power output levels HP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3/85

Contents

STw5098

11.5

Power output levels LS and EAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

12 13 14 15 16 17 18

Stereo audio ADC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Stereo audio DAC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 AD to DA mixing (sidetone) specifications . . . . . . . . . . . . . . . . . . . . . . 71 Stereo analog-only path specifications . . . . . . . . . . . . . . . . . . . . . . . . 72 ADC (TX) & DAC (RX) specifications with voice filters selected . . . . . 73 Typical performance plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
18. 1 18. 2 LFBGA 6x6x1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 VFBGA 5x5x1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

19 20 21

Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

4/85

STw5098

List of tables

List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. STw5098 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Control register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 CR0 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 CR1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CR2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CR3 and CR4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CR5 and CR6 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 CR7 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 CR8 and CR9 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 CR10 and CR11 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 CR12 and CR13 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 CR14 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 CR15 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 CR16 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 CR17 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 CR18 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 CR19 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 CR21-20 and CR24-23 description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 CR22 and CR25 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 CR26 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 CR27 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 CR28 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 CR29 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 CR30 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 CR31 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 CR32 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 CR33 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 CR 34 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 CR 35 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Control interface timing with I²C format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Control interface signal timing with SPI format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 AMCK timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Audio interface signal timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Operative supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Typical power dissipation, no master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Typical power dissipation with master clock AMCK = 13 MHz . . . . . . . . . . . . . . . . . . . . . . 61 Digital interfaces specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 AMCK with sinusoid input specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Analog interface specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Headset plug-in and push-button detector specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Microphone bias specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Power supply rejection ratio specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 LS and EAR gain limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Reference full scale analog levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Microphone input levels, absolute levels at pins connected to preamplifiers . . . . . . . . . . . 66 Microphone input levels, absolute levels at pins connected to the line-in amplifiers . . . . . 66

5/85

List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60.

STw5098

Absolute levels at OLP/OLN, ORP/ORN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Absolute levels at HPL - HPR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Absolute levels at 1EARP-1EARN and 2LSP - 2LSN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Stereo audio ADC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Stereo audio DAC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 AD to DA mixing (sidetone) specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Stereo analog-only path specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 ADC (TX) & DAC (RX) specifications with voice filters selected. . . . . . . . . . . . . . . . . . . . . 73 Dimensions of LFBGA 6x6x1.4 112 4R11x11. 0.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Dimensions of VFBGA 5x5x1.0 112 balls 0.4 mm pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6/85

STw5098

List of figures

List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 STw5098 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power up block diagram: example shown for one entity . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Plug-in and push-button detection application note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Control interface I2C format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Control interface: I2C format timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Control interface SPI format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Control interface: SPI format timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Audio interfaces formats: delayed, left and right justified . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Audio interfaces formats: DSP, SPI and PCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Audio interface timings: master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Audio interface timing: slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 A.C. testing input-output waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Bass treble control, de-emphasis filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Dynamic compressor transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 ADC audio path measured filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 ADC in band audio path measured filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 DAC digital audio filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 DAC in band digital audio filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 ADC 96 kHz audio path measured filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ADC 96 kHz audio in-band measured filter response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ADC voice TX path measured filter response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ADC voice TX path measured in-band filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 DAC voice (RX) digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 DAC voice (RX) in-band digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ADC path FFT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 ADC S/N versus input-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 DAC path FFT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 DAC S/N versus input-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Analog path FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Analog path S/N versus input-level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 LFBGA 6x6x1.4 112 4R11x11 0.5 drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 VFBGA 5x5x1.0 112 0.4 drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 STw5098 application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

7/85

Overview

STw5098

1

Overview

Dual 20 bit audio resolution, 8kHz to 96kHz independent rate ADC and DAC Dual I2S/PCM digital interfaces for dual master Sustain complex voice and audio flow with or without mixing Two I2C/SPI compatible independent control interfaces Asynchronous sampling ADC and DAC that do not require oversampled clock and information on the audio data sampling frequency (fs). Jitter tolerant fs Wide master clock range from 4MHz to 32MHz Two stereo headphones drivers, hand free loudspeaker driver, line out drivers Mixable analog line inputs Voice filters: 8/16kHz with voice channel filters Automatic gain control for microphone and line-in inputs Four programmable master/slave serial audio data interfaces: I2S, SPI, PCM compatible and other formats Frequency programmable clock outputs Multibit modulators with data weighted averaging ADC and DAC Four DSP functions for bass-treble-volume control, mute, mono/stereo selection, voice channel filters, de-emphasis filter and dynamic compression 93 dB dynamic range ADC, 0.001% THD with full scale with full scale output @ 2.7V 95 dB dynamic range DAC, 0.02% THD performance @ 2.7V over 16 load

Analog inputs

Selectable stereo differential or single-ended microphone amplifier inputs with 51dB range programmable gain 2 microphone biasing output Microphone plug-in and push-button detection input Selectable stereo differential or single-ended line inputs with 38dB range programmable gain

Analog output drivers

2 Stereo headphones outputs. driving capability: 40mW (0.1% THD) over 16 with 40dB range programmable gain Common mode voltage headphones driver (phantom ground) 1 Balanced loudspeaker output with driving capability up to 500mW (VCCLS>3.5V; 1% THD) over 8 with 30dB range programmable gain 1 Balanced earphone output with driving capability up to 125mW Transient suppression filter during power up and power down Balanced/unbalanced stereo line outputs with 1 k driving capability

8/85

STw5098

Pinout

2
Figure 1.

Pinout
Pin assignment

1

2

3

4

5

6

7

8

9

10

11

GND

1SCLK

1AD_OCK

2SDA/SDIN

1DA_OCK

1AD_CK

2AS/CSB

2AD_DATA

2AD_SYNC

1DA_SYNC

1DA_DATA

A
2HDET 2SCLK 2AD_OCK 1CMOD 2DA_OCK 2DA_CK AMCK VCC 2DA_SYNC 2DA_DATA GND

B
VCCA 1HDET VCCA 2CMOD 1SDA/SDIN 2AD_CK

1AD_DATA

1AD_SYNC

2IRQ

2MBIAS

1MBIAS

C
2AUX1L 1AUX1L 1MICLN VCC VCCIO 1DA_CK 1AS/CSB 1IRQ VCCA 1AUX1R 2AUX1R

D
2AUX3L 1AUX3L 1MICLP 2MICLN 2CAPLINEIN 1MICRN 2AUX3R 2MICRN

E
2CAPMIC 1CAPMIC GNDA 2MICLP 1CAPLINEIN 1MICRP 1AUX3R 2MICRP

F
1AUX2LN 2AUX2LN 1LINEINL 2LINEINL GNDA 1AUX2RP 1AUX2RN 2AUX2RN

G
1AUX2LP 2AUX2LP 2OLN GNDCM 1EARPS 1EARP VCCP 1HPR 2ORN 2LINEINR 2AUX2RP

H
1OLN 1OLP 2OLP 2HPL 1VCMHP 1CAPEAR 1EARN VCCLS 2ORP 1ORN 1LINEINR

J
GNDCM VCCP 1HPL 2VCMHPS VCCLS
GNDP

GNDP

1EARNS

VCCLS

1ORP

GNDP

K
VCCP GNDP 1VCMHPS 2VCMHP 2LSPS 2LSP 2CAPLS 2LSN 2LSNS VCCP 2HPR

L

9/85

Pinout

STw5098

Table 1.
Position A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7

STw5098 pin description
Type P DI DO DIOD DO DIO DI DO DIO DIO DI AI DI DO DI DO DIO DI AI P DIO DI P P Pin name GND 1SCLK 1AD_OCK 2SDA/SDIN 1DA_OCK 1AD_CK 2AS/CSB 2AD_DATA 2AD_SYNC 1DA_SYNC 1DA_DATA 2HDET 2SCLK 2AD_OCK 1CMOD 2DA_OCK 2DA_CK AMCK Description Ground pin for the digital section Control interface serial clock input Oversampled clock out from AD clock generator Control interface serial data input-output in I2C mode (SDA), control interface serial data input in SPI mode (SDIN). Oversampled clock out from DA clock generator Serial data clock for stereo A/D converter Control interface address select in I2C mode (AS). Interface enable signal in SPI mode (CSB). Serial data out for stereo A/D converter Frame sync for stereo A/D converter Frame sync for stereo D/A converter Serial data In for stereo D/A converter Headset detection input (microphone plug-in and push-button detection) Control interface serial clock input Oversampled clock out from AD clock generator Control interface type selector I2C-bus mode or SPI mode Oversampled clock out from DA clock generator Serial data clock for stereo D/A converter Master clock input. Accepted range 4 MHz to 32 MHz. AMCK is a digital square wave AMCK is an analog sinewave (Section 10.2 on page 62) Power supply pin for the digital section. Operating range: from 1.71 V to 2.7 V Frame sync for stereo D/A converter Serial data in for stereo D/A converter Ground pin for the digital section Power supply pin for the analog section. Standard operating range: from 2.7V to 3.3V Low voltage (LV) range: from 2.4V to 2.7V Headset detection input (microphone plug-in and push-button detection) Power supply pin for the analog section. Standard operating range: from 2.7V to 3.3V Low voltage (LV) range: from 2.4V to 2.7V Control interface type selector I2C-bus mode or SPI mode.

B8 B9 B10 B11 C1

VCC 2DA_SYNC 2DA_DATA GND VCCA

C2

AI

1HDET

C3 C4

P DI

VCCA 2CMOD

10/85

STw5098 Table 1.
Position C5 C6 C7 C8 C9 C10 C11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 E1 E2 E3 E4 E8 E9 E10 E11 F1 F2 F3 F4

Pinout STw5098 pin description
Type DIOD DIO DO DIO DO AO AO AI AI AI P P DIO DI DO P AI AI AI AI AI AI AI AI AI AI AI AI P AI Pin name 1SDA/SDIN 2AD_CK 1AD_DATA 1AD_SYNC 2IRQ 2MBIAS 1MBIAS 2AUX1L 1AUX1L 1MICLN VCC VCCIO 1DA_CK 1AS/CSB 1IRQ VCCA 1AUX1R 2AUX1R 2AUX3L 1AUX3L 1MICLP 2MICLN 2CAPLINEIN 1MICRN 2AUX3R 2MICRN 2CAPMIC 1CAPMIC GNDA 2MICLP Description Control interface serial data input-output in I2C mode (SDA). Control interface serial data input in SPI mode (SDIN). Serial data clock for stereo A/D converter Serial data out for stereo A/D converter Frame sync for stereo A/D converter Programmable interrupt output. Active low signal. Microphone biasing pin. Fixed voltage reference Microphone biasing pin. Fixed voltage reference Left and right channel single ended pins for microphone or line input Left and right channel single ended pins for microphone or line input Left and right channel differential pins for microphone input Power supply pin for the digital section. Operating range: from 1.71V to 2.7V Power supply pin for the digital I / O buffers. Operating ranges: from 1.2V to 1.8V and from 1.71V to VCC Serial data clock for stereo D/A converter Control interface address select in I2C mode (AS) Interface enable signal in SPI mode (CSB) Programmable interrupt output. Active low signal. Power supply pin for the analog section. Standard operating range: from 2.7V to 3.3V Low voltage (LV) range: from 2.4V to 2.7V Left and right channel single ended pins for microphone or line input Left and right channel single ended pins for microphone or line input Left and right channel single ended pins for microphone or line input Left and right channel single ended pins for microphone or line input Left and right channel differential pins for microphone input Left and right channel differential pins for microphone input A capacitor must be connected between CAPLINEIN and ground Left and right channel differential pins for microphone input Left and right channel single ended pins for microphone or line input Left and right channel differential pins for microphone input A capacitor must be connected between CAPMIC and ground. A capacitor must be connected between CAPMIC and ground Ground pin for the analog section Left and right channel differential pins for microphone input

11/85

Pinout Table 1.
Position F8 F9 F10 F11 G1 G2 G3 G4 G8 G9 G10 G11 H1 H2 H3 AI AI AI AI AI AI AI AI P AI AI AI AI AI AO

STw5098 STw5098 pin description
Type Pin name 1CAPLINEIN 1MICRP 1AUX3R 2MICRP 1AUX2LN 2AUX2LN 1LINEINL 2LINEINL GNDA 1AUX2RP 1AUX2RN 2AUX2RN 1AUX2LP 2AUX2LP 2OLN Description A capacitor must be connected between CAPLINEIN and ground Left and right channel differential pins for microphone input Left and right channel single ended pins for microphone or line input Left and right channel differential pins for microphone input Left and right channel differential pins for microphone or line input Left and right channel differential pins for microphone or line input Left and right channel single ended pins for line input Left and right channel single ended pins for line input Ground pin for the analog section Left and right channel differential pins for microphone or line input. Left and right channel differential pins for microphone or line input Left and right channel differential pins for microphone or line input Left and right channel differential pins for microphone or line input Left and right channel differential pins for microphone or line input Audio differential line out amplifier for left and right channels. This outputs can drive up to 1k resistive load. Can be used as single ended output. Ground pin for analog reference. GNDCM can be connected to GNDA EARPS, EARNS (sense) pins must be connected on the application board to EARP, EARN pins respectively. The connection must be as close as possible to the pins. Analog differential loudspeaker amplifier output for left channel or right channel or the sum of both. This output can drive 50nF (with series resistor) or directly an earpiece transductor from 8 to 32. . Can deliver from 500mW to 125mW. Power supply pin for the left and right output drivers (headphones and line-out). Operating range: from VCCA to 3.3V Audio single ended headphones amplifier outputs for left and right channels. The outputs can drive 50nF (with series resistor) or directly an earpiece transductor of 16 . Audio differential line out amplifier for left and right channels. This outputs can drive up to 1k resistive load. Can be used as single ended output. Left and right channel single ended pins for line input Left and right channel differential pins for microphone or line input Audio differential line out amplifier for left and right channels. This outputs can drive up to 1k resistive load. Can be used as single ended output.

H4

P

GNDCM

H5

AO

1EARPS

H6

AO

1EARP

H7

P

VCCP

H8

AO

1HPR

H9 H10 H11 J1

AO AI AI AO

2ORN 2LINEINR 2AUX2RP 1OLN

12/85

STw5098 Table 1.
Position J2 AO

Pinout STw5098 pin description
Type Pin name 1OLP Description Audio differential line out amplifier for left and right channels. This outputs can drive up to 1k resistive load. Can be used as single ended output. Audio differential line out amplifier for left and right channels. This outputs can drive up to 1k resistive load. Can be used as single ended output. Audio single ended headphones amplifier outputs for left and right channels. The outputs can drive 50nF (with series resistor) or directly an earpiece transductor of 16 . Common mode voltage headphones output. The negative pins of headphones left and right speakers can be connected to this pin to avoid decoupling capacitors. A capacitor can be connected between this node and ground Analog differential loudspeaker amplifier output for Left channel or Right channel or the sum of both. This output can drive 50nF (with series resistor) or directly an earpiece transductor from 8 to 32 ; . It can deliver from 500mW to 125mW. Power supply pin for the mono differential output driver. Operating range: from VCCA to 5.5V Audio differential line out amplifier for left and right channels. This outputs can drive up to 1k resistive load. Can be used as single ended output. Audio differential line out amplifier for left and right channels. This outputs can drive up to 1k resistive load. Can be used as single ended output. Left and right channel single ended pins for line input Ground pin for analog reference. GNDCM can be connected to GNDA Power supply pins for the left and right output drivers (headphones and line-out). Operating range: from VCCA to 3.3V Audio single ended headphones amplifier outputs for left and right channels. The outputs can drive 50nF (with series resistor) or directly an earpiece transductor of 16 . VCMHPS (sense) pin must be connected on the application board to VCMHP pin. The connection must be as close as possible to the pins. Power supply pin for the mono differential output driver. Operating range: from VCCA to 5.5V Ground pin for the left, right and mono-differential output drivers. GNDP and GNDA must be connected together. Ground pin for the left, right and mono-differential output drivers. GNDP and GNDA must be connected together.

J3

AO

2OLP

J4

AO

2HPL

J5 J6

AO AI

1VCMHP 1CAPEAR

J7

AO

1EARN

J8

P

VCCLS

J9

AO

2ORP

J10 J11 K1

AO AI P

1ORN 1LINEINR GNDCM

K2

P

VCCP

K3

AO

1HPL

K4

AO

2VCMHPS

K5 K6 K7

P P P

VCCLS GNDP GNDP

13/85

Pinout Table 1.
Position K8 AO

STw5098 STw5098 pin description
Type Pin name 1EARNS Description EARPS, EARNS (sense) pins must be connected on the application board to EARP, EARN pins respectively. The connection must be as close as possible to the pins. Power supply pins for the mono differential output driver. Operating range: from VCCA to 5.5V Audio differential line out amplifier for left and right channels. This outputs can drive up to 1k resistive load. Can be used as single ended output. Ground pin for the left, right and mono-differential output drivers. GNDP and GNDA must be connected together. Power supply pin for the left and right output drivers (headphones and line-out). Operating range: from VCCA to 3.3V Ground pin for the left, right and mono-differential output drivers. GNDP and GNDA must be connected together. VCMHPS (sense) pin must be connected on the application board to VCMHP pin. The connection must be as close as possible to the pins. Common mode voltage headphones output. The negative pins of headphones left and right speakers can be connected to this pin to avoid decoupling capacitors. LSPS, LSNS (sense) pins must be connected on the application board to LSP, LSN pins respectively. The connection must be as close as possible to the pins. Analog differential loudspeaker amplifier output for Left channel or Right channel or the sum of both. This output can drive 50nF (with series resistor) or directly an earpiece transductor of 8 ; It can . deliver up to 500mW. A capacitor can be connected between this node and ground Analog differential loudspeaker amplifier output for Left channel or Right channel or the sum of both. This output can drive 50nF (with series resistor) or directly an earpiece transductor of 8 Can deliver . up to 500mW. LSPS, LSNS (sense) pins must be connected on the application board to LSP, LSN pins respectively. The connection must be as close as possible to the pins. Power supply pin for the left and right output drivers (headphones and line-out). Operating range: from VCCA to 3.3V Audio single ended headphones amplifier outputs for left and right channels. The outputs can drive 50nF (with series resistor) or directly an earpiece transductor of 16 .

K9

P

VCCLS

K10

AO

1ORP

K11

P

GNDP

L1

P

VCCP

L2

P

GNDP

L3

AO

1VCMHPS

L4

AO

2VCMHP

L5

AO

2LSPS

L6

AO

2LSP

L7

AI

2CAPLS

L8

AO

2LSN

L9

AO

2LSNS

L10

P

VCCP

L11

AO

2HPR

14/85

STw5098

Pinout

Type definitions
AI AO AIO DI DO DIO DIOD P Analog input Analog output Analog input output Digital input Digital output Digital input output Digital input output open drain Power supply or ground

15/85

3

ADLIN1

ADMIC1

MIXLIN1

MIXMIC1

16/85
GNDA VCCIO VCC GND VCCA 1IRQ 2IRQ 1HDET 2HDET 1SDA/SDIN 1SCLK 1AS/CSB 2AS/CSB 2CMOD 1CMOD 2SCLK 2SDA/SDIN 2MICLP LINSEL2 2MICLN Stereo Diff. 2MICRP 2MICRN 2AUX1L 2AUX1R 2AUX2PL AGC (from DSP) MICSEL2 Stereo Diff. MICLG2 MICRG2 0÷39 dB Step 1.5 MIC L-R PreAmps Stereo Sing.E. 2AUX2NL 2AUX2PR 2AUX2NR 2AUX3L 2AUX3R 2LINEINR Stereo Sing.E. 2LINEINL Comm. Mode 2CAPMIC 2CAPLINEIN IRQ Gen Control I/F LINLG2 LINRG2 -20:+18 dB Step 2 LIN L-R Amps Stereo Sing.E. Headset Detection AGC (from DSP) Stereo Path Power-On Reset Registers R Control Logic Stereo Path L LINEIN AUX1 AUX2 AUX3 MUTE MICLA2 MICRA2 -12÷0 dB Step 1.5
ADLIN2

Figure 2.

VCCP

VCCLS

GNDP

GNDCM

1MICLP

1MICLN

LINSEL1

AGC (from DSP)

1MICRP

Stereo Diff.

Block diagram

1MICRN

LINLG1 LINRG1 -20:+18 dB Step 2

1AUX1L

1AUX1R

Stereo Sing.E.

LINEIN AUX1 AUX2 AUX3 MUTE

LIN L-R Amps

L

R

1AUX2PL

1AUX2NL

1AUX2PR

Stereo Diff.

MICSEL1

AGC (from DSP)

AUX2NR

MICLG1 MICRG1 0÷39 dB Step 1.5 L R

1AUX3L

1AUX3R

Stereo Sing.E.

MICLA1 MICRA1 -12÷0 dB Step 1.5

MIC L-R PreAmps

L

1LINEINR

1LINEINL

Stereo Sing.E.

MIC AUX1 AUX2 AUX3 MUTE

R

MIC AUX1 AUX2 AUX3 MUTE

1CAPMIC

1CAPLINEIN

Comm. Mode

STw5098
ADMIC2

Block diagram

STw5098 block diagram

1MBIAS

Mic. Bias

2.1V Reference

2.1V Reference

Mic. Bias

2MBIAS

LOG: -18:0 dB Step 3 Oscillator

LOG: -18:0 dB Step 3 Left LineOut MICLO2 Bandgap Right LineOut CurrentBias 2ORP 2ORN 2OLP 2OLN

1OLP

1OLN

Left LineOut

MICLO1

1ORP

1ORN

Right LineOut

MIXLIN2

MIXMIC2

1HPL

Left Driver

-40:0 dB Step 2 Transient Suppr. Filter

R

L

L

R

-40:0 dB Step 2 Transient Suppr. Filter

Left Driver HPLG2 Voltage Reference
CM Driv er

2HPL

HPLG1

1VCMHP

CM Driv er

Voltage Reference

2VCMHP 2VCMHPS -40:0 dB Step 2 Transient Suppr. Filter Right Driver HPRG2 2LSPS 2LSP Mono Driver 2CAPLS 2LSN 2LSNS 2HPR

1VCMHPS

1HPR

Right Driver

-40:0 dB Step 2 Transient Suppr. Filter

HPRG1

1EARPS

1EARP ADC ADC

1CAPEAR

Mono Driver

1EARN

LSG1 -24:6 dB Step 2 Transient Suppr. Filter

LSSEL1 L (L+R)/2 R

Stereo ADC

Stereo ADC

LSSEL2 L (L+R)/2 R

LSG2 -24:6 dB Step 2 Transient Suppr. Filter

1EARNS

1AD_DATA Digital AD-PLL AD_SYNC1 AD_SYNC2 Digital AD-PLL

AD Sample Rate Converter

AD Sample Rate Converter

2AD_DATA

1AD_CK MIXDAC1 ADCHSW

Audio AD-I/F

DSP1

DSP2
MIXDAC2 ADCHSW ADMONO

Audio AD-I/F

2AD_CK 2AD_SYNC

1AD_SYNC

ADMONO

1AD_OCK

CK Gen/ Master Mode
Analog Filter

AGC (Mic&Lin)

Analog Filter

A DC Filter Digital Audio/Voice G a in

A DC Filter Audio/Voice Digital Gain

AGC (Mic&Lin)

CK Gen/ Master Mode

2AD_OCK

MCK1 DAC

AMCK

PLL

DA to AD Mix in g G a in

Stereo DAC

Stereo DAC

MCK2 DAC DA to AD Mixing G a in
(A udio Only)

PLL

(A udio Only)

AD to DA M ixing G a in (s idetone)

AD to DA M ixing G a in (s idetone)

AMCK Modulator

Bass Treble

Bass Treble Modulator DA C Filter Digital Audio/Voice Gain
(A udio only)

AMCK

(A udio only)

1DA_OCK DA C Filter Dig it a l Gain Audio/Voice

2DA_OCK Dyn.Comp. CK Gen/ Master Mode

CK Gen/ Master Mode

Dyn.Comp.

DACHSW Digital DA-PLL DA_SYNC1

1DA_SYNC

DAMONO

DA Sample Rate Converter

DA_SYNC2

Digital DA-PLL

DACHSW DAMONO Audio DA-I/F 2DA_SYNC 2DA_CK 2DA_DATA

DA Sample Rate Converter

1DA_CK

Audio DA-I/F

1DA_DATA

STw5098

STw5098

Functional description

4
4.1

Functional description
Naming convention
The STw5098 is composed of two identical entities, with their respective set of control registers. Regarding the pin labelling, a pin name preceded by 1 refers to entity 1 and a pin name preceded by 2 refers to entity 2 (ie.g. 1SCLK, 2SCLK). In the following sections, no distinction is made between the two entities when it is not relevant. Consequently, the 1 and 2 prefixes for entities 1 and 2 respectively are omitted. The same naming convention applies to the control registers (CRxxx).

4.2

Power supply
STw5098 can have different supply voltages for different blocks, to optimize performance, power consumption and connectivity. See Section 9.2 on page 59 for voltage definition. The correct sequence to apply supply voltage is to set first (and unset last) the digital I/O supply (VCCIO). The other supply voltages can be set in any order and can be disconnected individually, if needed. Disconnection does not cause any harm to the device and no extra current is pulled from any supply during this operation. Moreover if a voltage conflict is detected, like VCCA < VCC (not allowed), simply all blocks connected to VCCA are set to power down and no extra current is pulled from supply. When VCCIO is set and VCC (digital supply) is not set, all the digital output pins are in high impedance state, while the digital inputs are disconnected to avoid power consumption for any input voltage value between GND and VCCIO. Before VCC is disconnected the device has to be reset (SWRES bit in CR30). When the analog supply (VCCA) is set and VCC is not set, all the analog inputs are in high impedance state. The two sets of control registers are powered by VCC pins (digital supply) so if these pins are disconnected all the information stored in control registers is lost. When the digital supply voltage is set, a power-on-reset (POR) circuit sets all the registers content to the default value and then generates IRQ signals writing 1 in bits PORMSK end POREV in CR31 and CR32 respectively for both entities. All supplies must be on during operation.

17/85

Functional description

STw5098

4.3

Device programming
STw5098 can be programmed by writing Control Registers with SPI or I2C compatible control interface (both slave). The interface is always active, there is no need to have the master clock running to program the device registers. The control interfaces of each entity can be operated independently either in SPI or I2C modes. The choice between the two interfaces for each entity is done via their input pins 1CMOD and 2CMOD (CMOD): 1. CMOD connected to GND: I2C compatible mode selected The device address is selected with AS pin:
chip address 00110101(35hex) for reading, 00110100 (34hex) for writing chip address 00110111(37hex) for reading, 00110110 (36hex) for writing

AS/CSB connected to GND: AS/CSB connected to VCCIO:

When this mode is selected control registers are accessed through pins: SCLK (clock) SDA (serial data out/in, open drain) 2. CMOD connected to VCCIO: SPI compatible mode selected When this mode is selected control registers are accessed through: AS/CSB (chip select, active low) SCLK (clock) SDIN (serial data in) AD_OCK or DA_OCK or IRQ (serial data out, if selected)

Device Programming: I2C. The I2C Control Interface timing is shown in Section 6.1 on page 50. The interface has an internal counter that keeps the current address of the control register to be read or written. At each write access of the interface the address counter is loaded with the data of the register address field. The value in the address counter is increased after each data byte read or write. It is possible to access the interface in 2 modes: single-byte mode in which the address and data of a single register are specified, and multi-byte mode in which the address of the first register to be written or read is specified and all the following bytes exchanged are the data of successive registers starting from the one specified (in multi-byte mode the internal address counter restart from register 0 after the last register 36). Using the multi-byte mode it is possible to write or read all the registers with a single access to the device on the I2C bus. This applies to both entities of the device. Device Programming: SPI. The SPI Control Interface timing is shown in section Section 6.2 on page 51. Bits SPIOSEL (SPI Output Select) in CR33 control the out pin selection for serial data out (none, AD_OCK, DA_OCK or IRQ), while bit SPIOHIZ=1 in CR33 selects the high impedance state of serial data out pin when idle. The first bit sent on SDIN, after AS/CSB falling edge, sets the interface for writing (SDIN=1) or reading (SDIN=0), then a 7-bit Control Register address follows. If the interface is set for writing then the last 8 bits on SDIN are written in the control register. If the interface is set for reading then after the 7 bit address STw5098 sends out 8 bits data on the pin selected with bits SPIOSEL in CR33, while bits present at SDIN pin are ignored. If SPIOSEL=00 (no out pin selected) the reading access on SPI interface can still be useful to clear the IRQ event bits in CR32.

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STw5098

Functional description

4.4

Power up
STw5098 internal blocks can individually be switched on and off according to the user needs. A general power-up bit is present at bit 7 of CR0. The output drivers should always be powered up after the general power up. See the following drawing to select the needed block for the desired function. A fast-settling function is activated to quickly charge external capacitors when the device is switched on (CAPLS, CAPLINEIN and CAPMIC). Figure 3. Power up block diagram: example shown for one entity
ENANA ENMICL ENHSD MBIAS POWERUP

ENMICR

ENADCL

STw5098

ENLINL

ENADCR

ENADCKGEN

ENLINR ADMAST ENADOCK

ENLOL

AUDIO I/F

DAMAST ENDAOCK ENHPL ENMIXL

ENLS ENMIXL

ENDA CL

ENDACKGEN

ENHPR

ENDACR

ENPLL

ENLOR ENOSC=0

ENAMCK

ENOSC=1 ENHPVCM

ENOSC

4.5

Master clock
Master clock is applied to both entities. The master clock pin (AMCK) accepts any frequency from 4 MHz to 32 MHz. The 4-32 MHz range is divided in sub-ranges that have to be programmed in bits CKRANGE in CR30. The jitter and spectral properties of this clock have a direct impact on the DAC and ADC performance because it is used to directly or by integer division drive the continuous-time to sampled-time interfaces.

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Functional description

STw5098

Note that AMCK clock does not need to have any relation to any other digital or analog input or output. AMCK can be either a square wave or a sinewave, bit AMCKSIN in CR30 selects the proper input mode. When a sinewave is used as input, AMCK pin must be decoupled with a capacitor. Specification for sinusoid input can be found in Section 10.2 on page 62. The AMCK clock is not needed when only analog functions are used. For this purpose an internal oscillator with no external components can be used to operate the device (see Section 4.14 on page 25).

4.6

Data rates
STw5098 supports any data rate in 2 ranges: 8 kHz to 48 kHz and 88 kHz to 96 kHz. The range is selected with bits DA96K and AD96K in CR29 for AD and DA paths respectively.

Note:

When AD96K=1 it is required to have DA96K=1.
The rates are fully independent in A/D and D/A paths. Moreover the rates do not have to be specified to the device and they can change on the fly, within one range, while data is flowing. The 2 audio data interfaces (for A/D and D/A) can independently operate in master or slave modes.

4.7

Clock generators and master mode function
STw5098 provides 4 internal clock generators that can drive, if needed, the audio interfaces (master mode), and/or two independent master clocks. The AMCK clock input frequency is internally raised via a PLL on each entity to obtain a clock (MCK) in the range 32 MHz to 48 MHz. The ratio MCK/AMCK is defined in CR30 (see MCKCOEFF in Section 4.7 on page 20). MCK is used to obtain, by fractional division, the oversampled clock (OCK), word clock (SYNC) and bit clock (CK), that will therefore have edges aligned with MCK (the OCK period can have jitter of 1 MCK period). The frequency of OCK, SYNC and CK is set with DAOCKF in CR21/20 for DA interface, and ADOCKF in CR24/23 for AD interface. The ratio between OCK and SYNC clocks is selected with bit DAOCK512 in CR22 for DA interface and bit ADOCK512 in CR25 for AD interface. The ratio between CK and SYNC clocks depends on the selected interface format (see Audio digital interfaces paragraph below). Note that SPI format can only be slave. The ADOCK and DAOCK output clocks are activated by bits ENADOCK and ENDAOCK respectively, while master mode generation is activated with two bits: first ADMAST (DAMAST) sets ADSYNC and ADCK (DASYNC and DACK) pins as outputs, then ADMASTGEN (DAMASTGEN) generates the SYNC and CK clocks. The logical value at SYNC and CK pins before data generation depends on the interface selected format. See description of CR20 to CR25 for further details.

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STw5098

Functional description

4.8

Audio digital interfaces
Four separate audio data interfaces are provided for AD and DA paths to have maximum flexibility in communicating with other devices. The 4 interfaces can have different rates and can work in different formats and modes (i.e an AD interface can be 8 kHz PCM slave while a DA is 44.1 kHz I2S master). The pins used by the interfaces are: AD_SYNC, AD_CK and AD_DATA for AD paths word clock, bit clock and data, respectively, and DA_SYNC, DA_CK and DA_DATA for DA paths word clock, bit clock and data, respectively. Data is exchanged with MSB first and left channel data first in all formats. Data word-length is selected with bits DAWL in CR26 and ADWL in CR27. AD_DATA pin, outside the selected time slot, is in the impedance condition selected by bit ADHIZ in CR28 in all data formats except right aligned format. In the following paragraphs SYNC, CK and DATA will be used when the distinction between AD and DA is not relevant. When Master Mode is selected (bits DAMAST and ADMAST in CR22 and CR25 respectively) the SYNC and CK clocks are generated internally. In addition, an oversampled clock can be generated for each interface (AD_OCK and DA_OCK). The clock is available in Slave Mode also, if needed. The AD and DA interfaces can also be used as a single bidirectional interface when they are configured with the same format (Delayed, DSP, etc.) and AD_SYNC is connected to DA_SYNC and DA_CK to AD_CK. Master Mode is still available selecting ADMAST or DAMAST (not both). The interfaces features are controlled with control registers CR26, CR27 and CR28. Suppor ted operating formats:

Delayed format (I2S compatible) (DAFORM or ADFORM =000): the Audio Interface is I2S compatible (Figure 9 on page 54). The number of CK periods within one SYNC period is not relevant, as long as enough CK periods are used to transfer the data and the maximum frequency limit specified for bit clock is not exceeded. CK can be either a continuous clock or a sequence of bursts. In master mode there are 32 CK periods per SYNC period (that means 16 CK periods per channel) when the word length is 16 bit, while there are 64 CK periods per SYNC period (or 32 CK periods per channel) when word length is 18bit or higher. Bits ADSYNCP, DASYNCP and ADCKP, DACKP affect the interface format inverting the polarity of SYNC and CK pins respectively. Left aligned format (DAFORM or ADFORM =001): this format is equivalent to delayed format without the 1 bit clock delay at the beginning of each frame (Figure 9 on page 54). Right aligned format (DAFORM or ADFORM =010): this format is equivalent to delayed format, except that the audio data is right aligned and that the number of CK periods is fixed to 64 for each SYNC period (Figure 9 on page 54). DSP format (DAFORM or ADFORM =011) in this format the audio interface starting from a frame sync pulse on SYNC receives (DA) or sends (AD) the left and right data one after the other (Figure 10 on page 55). The number of CK periods within one SYNC period is not relevant, as long as enough CK periods are used to transfer the data and the maximum frequency limit specified for bit clock is not exceeded. CK can be either a continuous clock or a sequence of bursts. In Master Mode there are 32 CK periods per SYNC period when the word length is 16 bit, while there are 64 CK periods per SYNC period when word length is 18bit or higher. Bit CKP (ADCKP and DACKP)

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Functional description

STw5098

affects the interface format inverting the polarity of CK pin. Bit SYNCP (ADSYNCP and DASYNCP) switches between delayed (SYNCP=0) and non delayed (SYNCP=1) formats. DSP format is suited to interface with a multi-channel serial port.

SPI format (DAFORM or ADFORM =100) in this format left and right data is received with separate data burst. Every burst is identified with a low level on SYNC signal (Figure 10 on page 55). There is no timing difference between the left and right data burst: the two channels are identified by the startup order: the first burst after AD path or DA path power-up identifies the left channel data, the second one is the Right channel data, then left and right data repeat one after the other. CK must have 16 periods per channel in case of 16 bit data word and 32 periods per channel in case of 18 bit to 32 bit data word. The SPI interface can be configured as a single-channel (mono) interface with bit SPIM (ADSPIM and DASPIM). The mono interface always exchanges the left channel sample. SPI-format can only be slave: if Master Mode is selected the CK and SYNC pins are set to 0. Bit CKP (ADCKP and DACKP) affects the interface format inverting the polarity of CK pin. PCM format (DAFORM or ADFORM =111): this format is monophonic, as it can only receive (DA) and transmit (AD) single channel data (Figure 10 on page 55). It is mainly used when voice filters are selected. If audio filters are used then the same sample is sent from DA-PCM interface to both channel of DA path, and the left channel sample from AD path is sent to AD-PCM interface. If in the AD path the right channel has to be sent to the PCM interface then the following must be set: ADRTOL=1 (CR27) and ENADCR=0 (CR1). In Master Mode the number of CK periods per SYNC period is between 16 and 512 (see DAPCMF in CR22 and ADPCMF in CR25 Section 4.7 on page 20 for details). Bit CKP (ADCKP and DACKP) affects the interface format inverting the polarity of CK pin. Bit SYNCP (ADSYNCP and DASYNCP) switches between delayed (SYNCP=0) and non delayed (SYNCP=1) formats.

4.9

Analog inputs
Each entity of the STw5098 has a stereo Microphone preamplifier and a stereo Line In amplifier, with inputs selectable among 5: MIC (for Microphone preamplifiers only), LINEIN (for Line In amplifiers only) and 3 different AUX inputs (for Microphone and Line In amplifiers). The AUX inputs can be used simultaneously for Line In amplifiers and Microphone preamplifiers. The following description is for one entity, it is similar for the other entity.

Microphone preamplifier: it has a very low noise input, specifically designed for low amplitude signals. For this reason the preamplifier has a high input gain (up to 39 dB) keeping a constant 50 k input impedance for the whole gain range. However it can also be used as line in preamplifier because it can accept a high dynamic input signal (up to 4 Vpp). There are two separate gain and attenuation stages in order to improve the S/N ratio when the preamplifier output range is below full scale (volume control).The gain and attenuation controls are separate for left and right channel (CR3 and CR4 respectively). The Preamplifier input is selected with bits MICSEL in CR18, and it is disconnected when MICMUTE=1. If a single ended input is selected then the preamplifier uses the selected pin as the positive input and connects the negative input (for both left and right channels) to CAPMIC pin, which has to be connected through a capacitor to a low noise ground (typically the same reference ground of the input).

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STw5098

Functional description Each stereo Microphone preamplifier is powered up with bits ENMICL and ENMICR in CR1.

Line In amplifier: each line in amplifier is designed for high level input signal. The input gain is in the range -20 dB up to 18 dB. The Line In amplifier input is selected with bits LINSEL in CR18, and it is disconnected when LINMUTE=1. If a single ended input is selected then the amplifier uses the selected pin as the positive input and connects the negative input (for both left and right channels) to CAPLINEIN pin, which has to be connected through a capacitor to a low noise ground (typically the same reference ground of the input). The stereo Line In amplifier is powered up with bits ENLINL and ENLINR in CR1.

4.10

Analog output drivers
Each entity of the STw5098 provides 3 different analog signal outputs and 1 common mode reference output. The description here below is for one entity. VCCP and VCCL are common for both entities.

Line out drivers: it is a stereo differential output, it can be used as single-ended output just by using the positive or negative pin. It can drive 1 k resistive load. The load can be connected between the positive and negative pins or between one pin and ground through a decoupling capacitor. The output gain is regulated with LOG bits in CR7, in the range 0 to -18 dB, simultaneously for left and right channels. When used as a single ended output the effective gain is 6 dB lower. It is muted with bit MUTELO in CR19. The input signal of this stereo output can come from the analog mixer or directly from MIC preamplifiers. The output Common Mode Voltage level is controlled with bits VCML in CR19. The supply voltage of line out drivers is VCCP . The line out drivers are powered up with bits ENLOL and ENLOR in CR1. The output pins are in high impedance state with a 180k pull-down resistor when the line out drivers are powered down. Headphones drivers: it is a stereo single ended output. It can drive 16 ohm resistive load and deliver up to 40 mW. The output gain is regulated with HPLG and HPRG bits in CR8 and CR9 respectively, with a range of -40 to 6 dB. It is muted with bit MUTEHP in CR19. The input signal of this stereo output comes from the analog mixer.The output common mode voltage is controlled with bits VCML in CR19. The supply voltage of headphones drivers is VCCP . The headphones drivers are powered up with bits ENHPL and ENHPR in CR2.The output pins are in high impedance state when the headphones drivers are powered down. Common mode voltage driver: it is a single ended output with output voltage value selectable with bits VCML in CR19, from 1.2 V to 1.65 V in steps of 150 mV. The output voltage should be set to the value closest to VCCP/2 to optimize output drivers performance. The common mode voltage driver is designed to be connected to the common pin of stereo headphones, so that decoupling capacitors are not needed at HPL and HPR outputs. The supply voltage of the common mode voltage driver is V CCP . The common mode voltage driver is powered up with bit ENHPVCM in CR2.The output pin is in high impedance state when the common mode voltage driver is powered down.

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Functional description

STw5098

Loudspeaker driver (one entity only): it is a monophonic differential output. It can drive 8 resistive load and deliver up to 500 mW to the load. The output gain is regulated with LSG bits in CR7, in the range -24 to +6 dB. The input signal of the loudspeaker driver comes from the analog mixers: bits LSSEL in CR29 select left channel, right channel, (L+R)/2 (mono) or mute. The output common mode voltage is obtained with an internal voltage divider from VCCLS and it is connected to CAPLS pin. The supply voltage of the loudspeaker driver is VCCLS. The loudspeaker driver is powered up with bit ENLS in CR2.The output pin is in high impedance state when the loudspeaker driver is powered down.

Note:

1

Together with the LS driver, only a second power output is allowed among: Ear (1EARP - 1EARN) Headphones 1 (1HPL and 1HPR) Headphones 2 (2HPL and 2HPR) Earphone driver (one entity only): it is a monophonic differential output. It can drive 32 resistive load and deliver up to 125 mW to the load. The output gain is regulated with EARG bits in CR7, in the range -24 to +6 dB. The input signal of the loudspeaker driver comes from the analog mixers: bits EARSEL in CR29 select left channel, right channel, (L+R)/2 (mono) or mute. The output Common Mode Voltage is obtained with an internal voltage divider from VCCLS and it is connected to CAPEAR pin. The supply voltage of the loudspeaker driver is VCCLS. The loudspeaker driver is powered up with bit ENEAR in CR2.The output pin is in high impedance state when the loudspeaker driver is powered down. Note on direct connection of VCCLS to the battery: The voltage of batteries of handheld devices during charging is usually below 5.5 V, making VCCLS supply pin suitable for a direct connection to the battery. In this case if STw5098 is delivering the maximum power to the load and the ambient temperature is above 70 C then the simultaneous charging of the battery can overheat the device. A basic protection scheme is implemented in STw5098 (activated with bit LSLIM in CR19): it limits the maximum gain of the loudspeaker to -6 dB when VCCLS is above 4.2 V, and it removes the limit for VCCLS below 4.0 V. The loudspeaker gain is left unchanged if it is set below -6 dB with bits LSG. This event (VCCLS > 4.2 V) can generate, if enabled (bit VLSMSK in CR31), an IRQ signal.

Note:

4.11

Analog mixers
STw5098 can send to the output drivers the sum of stereo audio signals from 3 different sources of each entity: DA path (bit MIXDAC in CR17), Microphone Preamplifiers (bit MIXMIC in CR17) and Line In Amplifiers (bit MIXLIN in CR17). The analog mixers do not have a gain control on the inputs, therefore the user should reduce the levels of the input signals within the analog signal range. The stereo analog mixers are powered up with bits ENMIXL and ENMIXR in CR2.

4.12

AD paths
In each entity the AD path converts audio signals from Microphone Preamplifiers (selected with bit ADMIC in CR17) and Line In Amplifiers (bit ADLIN in CR17) inputs to digital domain. If both inputs are selected then the sum of the two is converted. After AD conversion the audio data is resampled with a sample rate converter and then processed with the internal DSP. Two different filters are selectable in the DSP (bit ADVOICE in CR29): stereo Audio

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STw5098

Functional description Filter, with DC offset removal and FIR image filtering; and a standard mono voice-channel filter (uses left channel input and feeds both channel output). The AD path includes a digital gain control (ADCLG, ADCRG in CR12 and CR13 respectively) in the range -57 to +8 dB. The maximum gain from Mic Preamplifier to AD interface is then 47 dB. When Audio filter is selected in both AD and DA paths then DA audio data can be summed to AD data and sent to the AD Audio Interface (see DA2ADG in CR15). Left and right channels can be independently switched on and off to save power, if needed (bits ENADCL and ENADCR in CR1)

4.13

DA paths
In each entity the DA path converts digital data from the digital audio interface to analog domain and feeds it to the analog mixer. Incoming audio data is processed with a DSP where different filters are selectable (bit DAVOICE in CR29): Audio filter, stereo, with FIR image filtering, bass and treble controls (bits BASS and TREBLE in CR14), de-emphasis filter; and a standard voice channel filter, mono (uses left channel input and feeds both channel output). A dynamic compression function is available for both audio and voice filters (bit DYNC in CR14). The DA path includes a digital gain control (DACLG, DACRG in CR10 and CR11 respectively) in the range -65 to 0 dB. AD to DA mixing (sidetone) can be enabled: see CR16 for details. Left and right channel can be independently switched on and off to save power, if needed (bits ENDACL and ENDACR in CR1).

4.14

Analog-only operations
Each entity from the STw5098 can operate without AMCK master clock if analog-only functions are used. It is possible to mix Microphone and Line In preamplifiers signals and listen through headphones, loudspeaker or send them to line-out. The analog-only operation is enabled with bit ENOSC in CR0. When ENOSC=1 the AD and DA paths cannot be used. In Analog Mode, each of the two entities can handle two different stereo audio signals, so it can be used as a front end for an external voice codec that does not include microphone preamplifiers and power drivers: mic signal is sent through Microphone preamplifiers directly to line out drivers (Transmit path), while Receive signal is sent through Line In amplifiers to the selected power drivers.

4.15

Automatic Gain Control (AGC)
STw5098 provides a digital Automatic Gain Control in AD path for each entity. The circuit can control the input gain at MIC preamplifier, Line In amplifier or both (bits ENAGCMIC and ENAGCLIN in CR35). When one input is selected, the center gain value used for the input is fixed with bits MICLG, MICRG, LINLG and LINRG in CR3 to CR6 (like in normal operation), then the AGC circuit adds to all the gains a value in the range -10.5 dB to +10.5 dB (or, extended with bit AGCRANGE in CR35, -21 dB to 21 dB), in order to obtain an average level at the digital interface output in the range -6 dB to -30 dB (selected with bits AGCLEV in CR35). The AGC added gain acts directly in the input gain, to avoid input saturation and improve S/N ratio, so it cannot exceed the input gain range. When MIC and Line-In inputs are selected simultaneously the control is performed on the sum of the two, preserving the balance fixed with input gains. Different values for Attack and Decay constants can be selected, depending on the kind of signal the AGC has to control (i.e. voice, music). The

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Functional description

STw5098

Attack and Decay time constants are related to the AD data rate (see bits AGCATT and AGCDEL in CR34).

4.16

Interrupt request: IRQ pins
On each entity of the STw5098, the interrupt request feature can signal to a control device the occurrence of particular events on each entity. Two control registers are used to choose the behavior of IRQ pin: the first is a Status/Event Register (CR32), where bits can represent the status of an internal function (i.e. a voltage is above or below a threshold) or an event (i.e. a voltage changed crossing a threshold); the second is a Mask Register (CR31) where if a bit in the mask is set to 1 then the corresponding bit in the Status/Event Register can affect IRQ pin status. On each entity, the IRQ pin is always active low. At VCC power up an interrupt request is generated by the Power-On-Reset circuit that sets to 1 bits PORMSK in CR31 and POREV in CR32. After this event the PORMSK bit should be cleared by the user and bit IRQCMOS in CR33 should be set according to the application (open drain or CMOS). When an IRQ event occurs and SPI control interface is selected with no serial output pin it is still possible to identify the event (and relative status) that generated the interrupt request. This can be done by setting the IRQ mask/enable bits (in CR31) one at the time (with successive writings) and reading the IRQ pin status. A simple example of this is the headset plug-in detection: at first we set bit HSDETMSK=1 in CR31 (with all the other bits set to 0). If there is an interrupt request then we set HSDETMSK=0 and HSDETEN=1, so we can read the HSDET status at IRQ pin. Then we read CR32 to clear its content (even if no data is sent out).

4.17

Headset plug-in and push-button detection
Each entity of the STw5098 can detect the plug-in of a microphone connector and the press/release event of a call/answer push-button. An application example can be found below, while specifications can be found in Section 10.4 on page 64. Figure 4. Plug-in and push-button detection application note

HDET 200nF VCCA 3k 1.5k Call/Answer Button 10F 200nF CAPMIC AUX1L AUX1R

ST w5095

From driver Generic Connector

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STw5098

Functional description

4.18

Microphone biasing circuits
The Microphone Biasing Circuits can drive mono or stereo microphones and can switch them off when not needed in order to save the current used by the microphone biasing network on each entity. Two bits control the behavior of the microphone bias circuit: MBIAS in CR17 enables the circuit (fixed voltage at MBIAS pin), while bit MBIASPD in CR17 affects the behavior of MBIAS pin when the function is not enabled. In particular when MBIASPD=1 the MBIAS pin is pulled down, otherwise it is left in tristate mode. The specification for the microphone biasing circuits can be found in Section 10.6 on page 64.

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Control registers

STw5098

5
5.1
Table 2.
CR# (hex) CR0 (00h) CR1 (01h) CR2 (02h) CR3 (03h) CR4 (04h) CR5 (05h) CR6 (06h) CR7 (07h) CR8 (08h) CR9 (09h) CR10 (0Ah) CR11 (0Bh) CR12 (0Ch) CR13 (0Dh) CR14 (0Eh) CR15 (0Fh) CR16 (10h) CR17 (11h)

Control registers
Summary
Control register summary
Description Supply & power control #1 Power control #2 Power control #3 Mic gain left Mic gain right Line in gain left Line in gain right LO gain & LS gain HPL gain HPR gain DAC digital gain left DAC digital gain right ADC digital gain left ADC digital gain right Bass/treble/deemphasis DA to AD mixing gain AD to DA mix/sidetone gain Mixer switches & mic bias
X

D7
POWER UP

D6

D5

D4

D3

D2

D1

D0

Def.
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1001 0000 1001 0000 0011 0000 0011 0000 0011 0000 0000 0000 0000 0000 1000 0000 1000 0000 0000 0000 0000

ENANA

ENAMCK

ENOSC

ENPL L

ENHSD

A24V

D12V

ENADCL

ENADCR

ENDACL

ENDACR

ENMICL

ENMICR

ENLINL

ENLINR

ENLOL

E NL OR

ENHPL

E NHPR

ENHPVC M

1ENEAR 2ENLS

ENMIXL

ENMIXR

MICLA(2:0)

MICLG(4:0)

MICRA(2:0)

MICRG(4:0)

X

X

LINLG(4:0)

X

X

X

LINRG(4:0)

X

LOG(2:0)

1EARG(3:0) 2LSG(3:0)

X

X

X

HPLG(4:0)

X

X

X

HPRG(4:0)

X

X

DACLG(5:0)

X

X

DACRG(5:0)

X

X

ADCLG(5:0)

X

X

ADCRG(5:0)

DYNC

TREBLE(2:0)

BASS(3:0)

X

X

X

DA2ADG(4:0)

X

X

AD2DAG(5:0)

0000 0000

MBIAS

M BIASPD

ADMIC

ADLIN

MIXMIC

MIXLIN

MIXDAC

MICLO

0000 0000

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STw5098 Table 2.
CR# (hex) CR18 (12h) CR19 (13h) CR20 (14h) CR21 (15h) CR22 (16h) CR23 (17h) CR24 (18h) CR25 (19h) CR26 (1Ah) CR27 (1Bh) CR28 (1Ch) CR29 (1Dh) CR30 (1Eh) CR31 (1Fh) CR32 (20h) CR33 (21h) CR34 (22h) CR35 (23h) CR36 (24h)

Control registers Control register summary
Description D7 D6 D5 D4 D3 D2 D1 D0 Def.
0010 0100 0101 1000 0000 0000 0000 0000 DAO CK512 0000 0000 0000 0000 0000 0000 ADO CK512 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

Input switches Drivers control DAOCK frequency LSB DAOCK frequency MSB DA clock generator control ADOCK frequency LSB ADOCK frequency MSB AD Clock generator control DAC data IF control ADC data IF control DAC&ADC data IF control Digital filters control Soft reset & AMCK range Interrupt mask Interrupt status Misc. control AGC attack/decay coeff. AGC control RESERVED

X

IN2VCM

LINMUTE

LINSEL(1:0)

MICMUTE

MICSEL(1:0)

VCML(1:0)

X

MUTELO

MUTEHP

1EARLIM 2LSLIM

1EARSEL(1:0) 2LSSEL(1:0)

DAOCKF(7:0)

DAOCKF(15:8)

X

X

DAMAST

DA MASTGEN

END AOCK

DAPCMF(1:0)

ADOCKF(7:0)

ADOCKF(15:8)

X

X

ADMAST

AD MASTGEN

ENA DOCK

ADPCMF(1:0)

X

DAFORM(2:0)

DASPIM

DAWL(2:0)

ADRTOL

ADFORM2:0)

ADSPIM

ADWL(2:0)

AMC KINV

DACKP

DASYNCP

DAMONO

ADCKP

AD SYNCP

ADMONO

ADHIZ

X

DAVOICE

DA96K

RXNH

ADVOICE

AD96K

ADNH

TXNH

SWRES

X

X

X

AMCKSIN

CKRANGE(2:0)

VLSHEN

PUSH BEN

HSDETEN

VLSHMSK

PUSH BMSK

HSDET M SK

OVFMSK

PORMSK

VLSH

PUSHB

HS D E T

VLSHEV

PUSHBEV HSDETEV

OVFEV

POREV

X

X

SPIOHIZ

SPIOSEL(1:0)

IRQCMOS

OVFDA

OVFAD

AGCATT(3:0)

AGCDEC(3:0)

0000 0000

X

ENA GCLIN

ENAG CMIC

AGC RANGE

AGCLEV(3:0)

0000 0000 0000 0000

X

X

X

X

X

X

X

X

Note: X reserved, write zero

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Control registers Caution:

STw5098

In the following Section 5: Control registers, reference to each entity is omitted. Each entity of the STw5098 has the same register set.

5.2
CR# (hex) CR0 (00h) CR1 (01h) CR2 (02h)

Supply and power control
Description Supply & power control #1 Power control #2 Power control #3 D7
POWER UP

D6

D5

D4

D3

D2

D1

D0

Def.
0000 0000 0000 0000 0000 0000

ENANA

E N A M CK

ENOSC

ENPLL

E NHSD

A24V

D12V

ENADCL

ENADCR

ENDACL

ENDACR

ENMICL

ENMICR

ENLINL

ENLINR

ENLOL

ENLOR

ENHPL

E NHPR

ENH PVCM

ENLS

ENMIXL

ENMIXR

Table 3.
Bits 7 6 5

CR0 description
Na m e Val. 1 0 1 0 1 0 1 CR0 description All the enabled analog and digital blocks are in power up All the device is in power down The analog blocks can be enabled All the analog blocks are in power down AMCK clock input pin is enabled AMCK clock input pin is disabled The Internal oscillator is enabled. The analog blocks use oscillator clock The internal oscillator is in power down The PLL is enabled The PLL is in power down The headset plug-in detector is enabled The headset plug-in detector is disabled Analog supply pins voltage range is 2.4V
POWERUP ENANA ENAMCK

4

ENOSC 0 1 0 1 0 1 0 1 0

0

3 2 1 0

ENPLL ENHSD A24V D12V

0 0 0 0

30/85

STw5098 Table 4.
Bits 7 6 5 4 3 2 1 0

Control registers CR1 description
Na m e Value 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 CR1 description The left channel A/D converter is enabled The left channel A/D converter is in power down The right channel A/D converter is enabled The right channel A/D converter is in power down The left channel D/A converter is enabled The left channel D/A converter is in power down The right channel D/A converter is enabled The right channel D/A converter is in power down The left channel microphone preamplifier is enabled The left channel microphone preamplifier is in power down The right channel microphone preamplifier is enabled The right channel microphone preamplifier is in power down The left channel line-in preamplifier is enabled The left channel line-in preamplifier is in power down The right channel line-in preamplifier is enabled The right channel line-in preamplifier is in power down Def. 0 0 0 0 0 0 0 0

ENADCL ENADCR ENDACL ENDACR ENMICL ENMICR ENLINL ENLINR

Table 5.
Bit # 7 6 5 4 3

CR2 description
Name Value 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 CR2 Description The left channel line out driver is enabled The left channel line out driver is in power down (default) The right channel line out driver is enabled The right channel line out driver is in power down (default) The left channel headphones driver is enabled The left channel headphones driver is in power down (default) The right channel headphones driver is enabled The right channel headphones driver is in power down (default) The headphones reference voltage generator is enabled The headphones reference voltage generator is in power down (def) The 32 earphone amplifier is enabled The 32 earphone amplifier is in power down (default) The 8 loudspeaker amplifier is enabled The 8 loudspeaker amplifier is in power down (default) The left channel analog output mixer is enabled The left channel analog output mixer is in power down (default) The right channel analog output mixer is enabled The right channel analog output mixer is in power down (default) Def. 0 0 0 0 0 0 0 0 0

ENLOL ENLOR ENHPL ENHPR ENHPVCM 1ENEAR

2 2ENLS 1 0 ENMIXL ENMIXR

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Control registers

STw5098

5.3
CR# (hex) CR3 (03h) CR4 (04h) CR5 (05h) CR6 (06h) CR7 (07h) CR8 (08h) CR9 (09h) CR10 (0Ah) CR11 (0Bh) CR12 (0Ch) CR13 (0Dh)

Gains
Description Mic gain left Mic gain right Line in gain left Line in gain right LO gain & LS gain HPL gain HPR gain DAC digital gain left DAC digital gain right ADC digital gain left ADC digital gain right
X

D7

D6

D5

D4

D3

D2

D1

D0

Def.
0000 0000 0000 0000 0000 1001 0000 1001 0000 0011 0000 0011 0000 0011 0000 0000 0000 0000 0000 1000 0000 1000

MICLA(2:0)

MICLG(4:0)

MICRA(2:0)

MICRG(4:0)

X

X

LINLG(4:0)

X

X

X

LINRG(4:0)

X

LOG(2:0)

LSG(3:0)

X

X

X

HPLG(4:0)

X

X

X

HPRG(4:0)

X

X

DACLG(5:0)

X

X

DACRG(5:0)

X

X

ADCLG(5:0)

X

X

ADCRG(5:0)

Table 6.
Bits

CR3 and CR4 description
Name CR3 Name CR4 Value CR3 and CR4 description Left (CR3) and right (CR4) channels microphone attenuation 0.0 dB gain (default) -1.5 dB gain -3.0 dB gain ...step 1.5 dB -9.0 dB gain -12.0 dB gain Left (CR3) and right (CR4) channels microphone gain 0.0 dB gain (default) 1.5 dB gain 3.0 dB gain ...step 1.5 dB 39.0 dB gain Def.

7-5

MICLA(2:0) MICRA(2:0)

000 001 010 ... 110 111 0 0 0 00001 00010 ... 11010

000

4-0

MICLG(4:0) MICRG(4:0)

0 0 0

32/85

STw5098 Table 7.
Bits

Control registers CR5 and CR6 description

Name CR5 Name CR6

Value

CR5 and CR6 description Left (CR5) and right (CR6) channels line in gain 18.0 dB gain 16.0 dB gain 14.0 dB gain ...step 2.0 dB 0.0 dB gain (default) ...step 2.0 dB -20.0 dB gain

Def.

4-0

LINLG(4:0) LINRG(4:0)

0 0 0 00001 00010 ... 01001 ... 10011

01001

Table 8.
Bits

CR7 description
Na m e Value CR7 description Left and right channel line out drivers gain Gain to differential output Equivalent single-ended gain 18.0 dB gain (default) -24.0 dB gain (default) -15.0 dB gain -21.0 dB gain -12.0 dB gain -18.0 dB gain ...step 3 dB ...step 3 dB 00 dB gain -6.0 dB gain 32 earphone gain/ 8 loudspeaker gain 6.0 dB gain 4.0 dB gain 2.0 dB gain 0.0 dB gain (default) ...step 2.0 dB -24.0 dB gain Def.

6-4

LOG(2:0)

000 001 010 ... 110 0000 0001 0010 0011 ... 1111

000

1EARG(3:0)

3-0 2LSG(3:0)

0011

Table 9.
Bits

CR8 and CR9 description Name CR8 Name CR9 Value CR8 and CR9 description Left (CR8) and right (CR9) channels headphones driver gain 0.0 dB gain -2.0 dB gain -4.0 dB gain -6.0 dB gain (default) ...step 2.0 dB -40.0 dB gain Def.

4-0

HPLG(4:0) HPRG(4:0)

0 0 0 00001 00010 00011 ... 10100

00011

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Control registers Table 10.
Bits

STw5098

CR10 and CR11 description
Value CR10 and CR11 description Left (CR10) and right (CR11) channels DAC digital gain 0.0 dB gain (default) -1.0 dB gain -2.0 dB gain -3.0 dB gain -4.0 dB gain -5.0 dB gain -6.0 dB gain -7.0 dB gain -8.0 dB gain -9.0 dB gain -10.0 dB gain -11.0 dB gain -12.0 dB gain -13.0 dB gain -14.0 dB gain -15.0 dB gain -16.0 dB gain -17.0 dB gain -18.0 dB gain -20.0 dB gain -22.0 dB gain -24.0 dB gain -26.0 dB gain -28.0 dB gain -30.0 dB gain -32.0 dB gain -34.0 dB gain -36.0 dB gain -38.0 dB gain -41.0 dB gain -44.0 dB gain -47.0 dB gain -50.0 dB gain -53.0 dB gain -56.0 dB gain -59.0 dB gain -65.0 dB gain - dB gain Def.

Name CR10 Name CR11

5-0

DACLG(5:0) DACRG(5:0)

0 0 00 0 0 01 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 10 0 0 100001 100010 100011 100100 100101

0 0 00

34/85

STw5098 Table 11.
Bits

Control registers CR12 and CR13 description
Value CR12 and CR13 description Left (CR12) and right (CR13) channels ADC digital gain 8.0 dB gain 7.0 dB gain 6.0 dB gain 5.0 dB gain 4.0 dB gain 3.0 dB gain 2.0 dB gain 1.0 dB gain 0.0 dB gain (default) -1.0 dB gain -2.0 dB gain -3.0 dB gain -4.0 dB gain -5.0 dB gain -6.0 dB gain -7.0 dB gain -8.0 dB gain -9.0 dB gain -10.0 dB gain -11.0 dB gain -12.0 dB gain -14.0 dB gain -16.0 dB gain -18.0 dB gain -20.0 dB gain -22.0 dB gain -24.0 dB gain -26.0 dB gain -28.0 dB gain -30.0 dB gain -33.0 dB gain -36.0 dB gain -39.0 dB gain -42.0 dB gain -45.0 dB gain -48.0 dB gain -51.0 dB gain -57.0 dB gain - dB gain Def.

Name CR12 Name CR13

5-0

ADCLG(5:0) ACDRG(5:0)

0 0 00 0 0 01 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 10 0 0 100001 100010 100011 100100 100101 100110

001000

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Control registers

STw5098

5.4
CR# (hex) CR14 (0Eh) CR15 (0Fh) CR16 (10h)

DSP control
Description Bass/treble/deemphasis DA to AD mixing gain AD to DA mix/sidetone gain D7 D6 D5 D4 D3 D2 D1 D0 Def.
0000 0000 0000 0000

DYNC

TREBLE(2:0)

BASS(3:0)

X

X

X

DA2ADG(4:0)

X

X

AD2DAG(5:0)

0000 0000

Table 12.
Bits 7

CR14 description
Na m e Value 1 0 011 010 001 000 111 110 101 100 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 CR14 description Audio dynamic compression in D/A path is enabled Audio dynamic compression in D/A path is disabled Treble control in D/A path +6.0 dB treble gain +4.0 dB treble gain +2.0 dB treble gain 0.0 dB treble gain -2.0 dB treble gain -4.0 dB treble gain -6.0 dB treble gain De-emphasis filter enabled Bass control in D/A path +12.5 dB bass gain +10.0 dB bass gain +7.5 dB bass gain +5.0 dB bass gain +2.5 dB bass gain 0.0 dB bass gain -2.5 dB bass gain -5.0 dB bass gain -7.5 dB bass gain -10.0 dB bass gain -12.5 dB bass gain Def. 0

DYNC

6-4

TREBLE(2:0)

000

3-0

BASS(3:0)

0000

36/85

STw5098 Table 13.
Bits

Control registers CR15 description
Na m e Value CR15 description DA to AD mixing (Audio filter in D/A and A/D path selected) DA to AD mixing disabled (default) +2.0 dB gain 0.0 dB gain -2.0 dB gain -4.0 dB gain -6.0 dB gain -8.0 dB gain -10.0 dB gain -12.0 dB gain -14.0 dB gain -16.0 dB gain -18.0 dB gain -20.0 dB gain -22.0 dB gain -24.0 dB gain -26.0 dB gain -28.0 dB gain -30.0 dB gain -32.0 dB gain -34.0 dB gain -36.0 dB gain -38.0 dB gain -40.0 dB gain Def.

4-0

DA2ADG(4:0)*

0 0 0 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110

0 0 0

* When Voice filter in D/A or A/D path is selected this function is disabled Note: D/A to A/D mixing is performed at AD data rate, so if A/D and D/A rates are different then asynchronous sampling artifacts may occur.

37/85

Control registers Table 14.
Bits

STw5098

CR16 description
Na m e Value CR16 description AD to DA mixing (sidetone) AD to DA mixing disabled (default) -1.0 dB gain -2.0 dB gain -3.0 dB gain -4.0 dB gain -5.0 dB gain -6.0 dB gain -7.0 dB gain -8.0 dB gain -9.0 dB gain -10.0 dB gain -11.0 dB gain -12.0 dB gain -13.0 dB gain -14.0 dB gain -15.0 dB gain -16.0 dB gain -17.0 dB gain -18.0 dB gain -19.0 dB gain -20.0 dB gain -21.0 dB gain -22.0 dB gain -23.0 dB gain -24.0 dB gain -25.0 dB gain -26.0 dB gain -27.0 dB gain -28.0 dB gain -29.0 dB gain -30.0 dB gain -31.0 dB gain -32.0 dB gain -33.0 dB gain -34.0 dB gain -35.0 dB gain -36.0 dB gain -37.0 dB gain -38.0 dB gain -39.0 dB gain -40.0 dB gain -41.0 dB gain -42.0 dB gain Def.

5-0

AD2DAG(5:0)

0 0 00 0 0 01 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 10 0 0 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010

0 0 00

38/85

STw5098

Control registers

5.5
CR# (hex) CR17 (11h) CR18 (12h) CR19 (13h)

Analog functions
Description Mixer switches & Mic Bias Input switches Drivers control D7 D6 D5 D4 D3 D2 D1 D0 Def.
0000 0000 0010 0100 0101 1000

MBIAS

MBIASPD

ADMIC

ADLIN

MIXMIC

MIXLIN

MIXDAC

MICLO

X

IN2VCM

LINMUTE

LINSEL(1:0)

MICMUTE

MICSEL(1:0)

VCML(1:0)

X

MUTELO

MUTEHP

LSLIM

LSSEL(1:0)

Table 15.
Bits 7

CR17 description
Na m e Value 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 CR17 description Microphone Bias enabled (2.1V typ at MBIAS pin) Microphone Bias disabled MBIAS pin is pulled down when microphone bias is disabled MBIAS pin is in high impedance state when microphone Bias is disabled Microphone preamplifiers are connected to AD path Microphone preamplifiers are not connected to AD path Line in preamplifiers are connected to AD path Line in preamplifiers are not connected to AD path Microphone preamplifiers are connected to mixers Microphone preamplifiers are not connected to mixers Line in preamplifiers are connected to mixers Line in preamplifiers are not connected to mixers Stereo DAC path is connected to mixers Stereo DAC path is not connected to mixers Microphone preamplifiers are connected to line out drivers Mixers are connected to line out drivers Def. 0

MBIAS

6

MBIASPD

0

5 4 3 2 1 0

ADMIC ADLIN MIXMIC MIXLIN MIXDAC MICLO

0 0 0 0 0 0

Table 16.
Bits 6 5

CR18 description
Na m e Value 1 0 1 0 00 01 10 11 CR18 description Unused analog input pins are biased to common mode voltage Unused analog input pins are in high impedance state Line in preamplifiers are muted Line in preamplifiers are not muted Input pins connected to line in preamplifiers (if LINMUTE=0) LINEIN (LINEINL, LINEINR) AUX1 (AUX1L, AUX1R) AUX2 (AUX2LP-AUX2LN, AUX2RP-AUX2RN) AUX3 (AUX3L, AUX3R) Def. 0 1

IN2VCM LINMUTE

4-3

LINSEL(1:0)

00

39/85

Control registers Table 16.
Bits 2

STw5098

CR18 description
Na m e Value 1 0 00 01 10 11 CR18 description Microphone preamplifiers are muted Microphone preamplifiers are not muted Input pins connected to microphone preamplifiers (if MICMUTE=0) MIC (MICLP-MICLN, MICRP-MICRN) AUX1 (AUX1L, AUX1R) AUX2 (AUX2LP-AUX2LN, AUX2RP-AUX2RN) AUX3 (AUX3L, AUX3R) Def. 1

MICMUTE

1-0

MICSEL(1:0)

00

Table 17.
Bits

CR19 description
Name Value CR19 Description Common mode voltage level for line out and headphones drivers 1.20 V 1.35 V (default) 1.50 V 1.65 V Line out drivers are muted Line out drivers are not muted Headphones drivers (HP) are muted Headphones drivers (HP) are not muted EAR/LS driver gain is limited when VCCLS is above 4.2V typ EAR/LS driver (LS) gain is not limited Mute Right Left Mono driver Loudspeaker driver (LS) is muted Right channel mixer only connected to loudspeaker driver Left channel mixer only connected to loudspeaker driver (Left + Right)/2 channel mixers connected to loudspeaker Def.

7-6

VCML(1:0)

00 01 10 11 1 0 1 0 1 0 00 01 10 11

01

4 3

MUTELO MUTEHP 1EARLIM

1 1

2 2LSLIM 1EARSEL(1:0) 1-0 2LSSEL(1:0)

0

00

40/85

STw5098

Control registers

5.6
CR# (hex) CR20 (14h) CR21 (15h) CR22 (16h) CR23 (17h) CR24 (18h) CR25 (19h)

Digital audio interfaces master mode and clock generators
Description DAOCK frequency LSB DAOCK frequency MSB DA clock generator control ADOCK frequency LSB ADOCK frequency MSB AD clock generator control
X X ADMAST X X DAMAST

D7

D6

D5

D4

D3

D2

D1

D0

Def.
0000 0000 0000 0000

DAOCKF(7:0)

DAOCKF(15:8)

DA MASTGEN

END O CK

DAO CK512

DAPCMF(1:0)

0000 0000 0000 0000 0000 0000

ADOCKF(7:0)

ADOCKF(15:8)

AD MASTGEN

ENA DO CK

ADO CK512

ADPCMF(1:0)

0000 0000

Table 18.
Bits

CR21-20 and CR24-23 description
Value CR21-20 and CR24-23 Description The following formulas can be used to obtain the value of K for the desired FS or OCK respectively in the clock generator
K(FS) = round2
25

Name CR21-20 Name CR24-23

Def.

FS -------------------------------------------------------------- A M C K M C K C O E F F OC K ----------------------------------------------------------------------------------- A M C K M C K C O E F F O S R

15-0

DAOCKF(15:0) ADOCKF(15:0)

K(OCK) = roun d2

25

K

0000h

FS: Data rate (DA_SYNC or AD_SYNC frequency in master mode) OCK: Oversampled clock frequency (DA_OCK or AD_OCK) AMCK: Input master clock frequency MCKCOEFF: See CR30 for definition OSR: See bit 2 in CR22 and CR25

Note: CR21-20 and CR24-23 are meaningful in master mode only.

Table 19.
Bits

CR22 and CR25 description
Value 1 0 1 0 1 0 CR22 and CR25 description DA (AD) Audio interface is in master mode (low impedance output) DA (AD) Audio interface is in slave mode (high impedance input) DA (AD) Master generator is enabled DA (AD) Master generator is disabled DA_OCK (AD_OCK) output clock is enabled DA_OCK (AD_OCK) output clock is disabled Def.

Name CR22 (Name CR25) DAMAST (ADMAST) DAMASTGEN (ADMASTGEN) ENDAOCK (ENADOCK)

5 4 3

0 0 0

41/85

Control registers Table 19.
Bits

STw5098

CR22 and CR25 description
Value CR22 and CR25 description Definition of DA_OSR (AD_OSR) DA_OCK/DA_SYNC (AD_OCK/AD_SYNC) ratio in master mode is 512 da_ock/da_sync (ad_ock/ad_sync) ratio in master mode is 256 DA_CK/DA_SYNC (AD_CK/AD_SYNC) Ratio in PCM master mode - 16 when CR26 DAWL=000 (CR27 ADWL=000) - 32 when CR26 DAWL000 (CR27 ADWL000) - 64 - 128 - 256 when CR22 DAOCK512=0 (CR25 ADOCK512=0) - 512 when CR22 DAOCK512=1 (CR25 ADOCK512=1) Def.

Name CR22 (Name CR25)

2

DAOCK512 (ADOCK512)

1 0 00 00 01 10 11 11

0

1-0

DAPCMF(1:0) (ADPCMF(1:0))

00

42/85

STw5098

Control registers

5.7
CR# (hex) CR26 (1Ah) CR27 (1Bh) CR28 (1Ch)

Digital audio interfaces
Description DAC data IF control ADC data IF control DAC&ADC data IF control D7 D6 D5 D4 D3 D2 D1 D0 Def.
0000 0000 0000 0000 0000 0000

X

DAFORM(2:0)

DASPIM

DAWL(2:0)

ADRTOL

ADFORM2:0)

ADSPIM

ADWL(2:0)

AMCKINV

DACKP

DASYNCP

DAMONO

ADCKP

AD SYNCP

ADMONO

ADHIZ

Table 20.
Bits

CR26 description
Name Value CR26 Description DA audio interface format selection Delayed format (I2S compatible) Left aligned format Right aligned format DSP format SPI format PCM format (uses left channel) DA interface in SPI mode receives one word for both channels DA interface in SPI mode receives two words (alternated, left channel first) DA interface word length 16 bit 18 bit 20 bit 24 bit 32 bit Def.

6-4

DAFORM(2:0)

000 001 010 011 100 111 1 0

000

3

DASPIM

0

2-0

DAWL(2:0)

000 001 010 011 100

000

Table 21.
Bits 7

CR27 description
Na m e Value 1 0 000 001 010 011 100 111 CR27 description AD right channel sent to PCM I/F (must set ENADCR=0 in CR1) Normal operation AD audio interface format selection Delayed format (I2S compatible) Left aligned format Right aligned format DSP format SPI format PCM format (sends out left channel) Def. 0

ADRTOL

6-4

ADFORM(2:0)

000

43/85

Control registers Table 21.
Bits 3

STw5098

CR27 description (continued)
Na m e Value 1 0 000 001 010 011 100 CR27 description AD interface in SPI mode sends one channel (left) AD interface in SPI mode sends two channels (alternated, left first) AD interface word length 16 bit 18 bit 20 bit 24 bit 32 bit Def. 0

ADSPIM

2-0

ADWL(2:0)

000

Table 22.
Bits 7 6

CR28 description
Na m e Value 1 0 1 0 1 0 AMCK is inverted AMCK is not inverted DA Bit clock pin (DA_CK) polarity is inverted DA Bit clock pin (DA_CK) polarity is not inverted DSP and PCM formats in DA interface Non delayed format Delayed format 0 1 0 1 Delayed, left-aligned, right-aligned and SPI formats in DA interface DA sync pin (DA_SYNC) polarity is inverted DA sync pin (DA_SYNC) polarity is not inverted Mono mode: (L+R)/2 from Audio Interface is used on both DAC channels Stereo mode AD Bit clock pin (AD_CK) polarity is inverted AD Bit clock pin (AD_CK) polarity is not inverted DSP and PCM formats in AD interface Non delayed format Delayed format 0 1 0 1 Delayed, left-aligned, right-aligned and SPI formats in AD interface DA sync pin (DA_SYNC) polarity is inverted DA sync pin (DA_SYNC) polarity is not inverted Mono mode: (L+R)/2 from ADC is sent to both channels in the Audio interface Stereo mode AD data pin (AD_DATA) is in high impedance state when no data is available AD data pin (AD_DATA) is forced to 0 when no data is available 0 0 CR28 description Def. 0 0

AMCKINV DACKP

5

DASYNCP

4

DAMONO 0 1 0 1 0

3

ADCKP

0

2

ADSYNCP

1

ADMONO 0 1

0

ADHIZ 0

0

44/85

STw5098

Control registers

5.8
CR# (hex) CR29 (1Dh) CR30 (1Eh)

Digital filters, software reset and master clock control
Description Digital filters control Soft reset & AMCK range D7 D6 D5 D4 D3 D2 D1 D0 Def.
0000 0000 0000 0000

X

DAVOICE

DA96K

RXNH

ADVOICE

AD96K

ADNH

T X NH

SWRES

X

X

X

AMCKSIN

CKRANGE(2:0)

Table 23.
Bits 6 5 4 3 2 1 0

CR29 description
Na m e Value 1 0 1 0 1 0 1 0 1 0 1 0 1 0 CR29 description DA path voice RX filter is enabled (single channel, left used) DA path voice filters are enabled DA path data rate is in the range 88 kHz to 96 kHz DA path data rate is in the range 8 kHz to 48 kHz DA path high pass voice RX filter is disabled DA path high pass voice RX filter is enabled (300Hz @ 8kHz rate) AD path voice TX filter is enabled (single channel, left used) AD path audio filters are enabled AD path data rate is in the range 88 kHz to 96 kHz AD path data rate is in the range 8 kHz to 48 kHz AD path audio DC filter is disabled AD path audio DC filter is enabled AD path high pass voice TX filter is disabled AD path high pass voice TX filter is enabled (300Hz @ 8kHz rate) Def. 0 0 0 0 0 0 0

DAVOICE DA96K RXNH ADVOICE AD96K ADNH TXNH

Table 24.
Bits 7 3

CR30 description
Na m e Value 1 0 1 0 000 001 010 011 100 101 CR30 description Software reset: All registers content is reset to the default value Control Register content is left unchanged Signal at AMCK pin is a sinusoid Signal at AMCK pin is a square wave AMCK range 4.0 MHz to 6.0 MHz 6.0 MHz to 8.0 MHz 8.0 MHz to 12.0 MHz 12.0 MHz to 16.0 MHz 16.0 MHz to 24.0 MHz 24.0 MHz to 32.0 MHz MCKCOEFF 8.0 6.0 4.0 3 .0 2 .0 1 .5 Def. 0 0

SWRES AMCKSIN

2-0

CKRANGE(2:0)

000

45/85

Control registers

STw5098

5.9
CR# (hex) CR31 (1Fh) CR32 (20h) CR33 (21h)

Interrupt control and control interface SPI out mode
Description Interrupt mask Interrupt status Misc. control D7 D6
PUSH BEN

D5

D4

D3
PUSH BMSK

D2
HSDET MSK

D1

D0

Def.
0000 0000 0000 0000 0000 0000

VLSHEN

HSDETEN VLSHMSK

OVFMSK

PORMSK

VLSH

PUSHB

HS D E T

VLSHEV

PUSHBEV HSDETEV

OVFEV

POREV

x

X

SPIOHIZ

SPIOSEL(1:0)

IRQCMOS

OVFDA

OVFAD

Table 25.
Bits 7 6 5 4 3 2 1 0

CR31 description
Name Value 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 CR31description VLSH status can be seen at IRQ output VLSH status is masked PUSHB status can be seen at IRQ output PUSHB status is masked HSDET status can be seen at IRQ output HSDET status is masked VLSH event can be seen at IRQ output VLSH event is masked PUSHB event can be seen at IRQ output PUSHB event is masked HSDET event can be seen at IRQ output HSDET event is masked OVF event can be seen at IRQ output OVF event is masked POR event can be seen at IRQ output POR event is masked Def. 0 0 0 0 0 0 0 0

VLSHEN PUSHBEN HSDETEN VLSHMSK PUSHBMSK HSDETMSK OVFMSK PORMSK

Note:

Value at IRQ pin is:
I R Q = (1 or Z) w h e n (CR31 & CR32) = 00 hex 0 w h e n (CR31 & CR32) 00 hex

Table 26.
Bits

CR32 description
Name Read only 1 0 1 0 1 0 VCCLS is above 4.2 V VCCLS is below 4.0 V Headset Button is pressed Headset Button is released Headset Connector is inserted Headset Connector is not inserted CR32 description Def.

7 6 5

VLSH* PUSHB* HSDET*

0 0 0

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STw5098 Table 26.
Bits

Control registers CR32 description (continued)
Name Read only 1 0 1 0 1 0 1 0 1 0 CR32 description VLSH bit has changed VLSH bit has not changed Headset Button Status has changed Headset Button Status has not changed Headset Connector Status has changed Headset Connector Status has not changed An Audio Data overflow has occurred in DSP No Audio Data overflow has occurred in DSP Device was reset by power-on-reset Device was not reset by power-on-reset Def.

4 3 2 1 0

VLSHEV PUSHBEV HSDETEV OVFEV POREV

0 0 0 0 0

Note: content of bits 4 to 0 in CR32 is cleared after reading, while it is left unchanged if accessed for writing. *Bits 7 to 5 represent the status when the Control register is read, not when the event occurred.

Table 27.
Bits

CR33 description
Na m e Val. 1 CR33 description SPI control interface out pin is set to high impedance state when inactive SPI control interface out pin is set to zero when inactive Out pin selection for SPI control interface No output. Control registers cannot be read in SPI mode SPI output sent to IRQ pin SPI output sent to DA_OCK pin SPI output sent to AD_OCK pin IRQ interrupt request pin is set to CMOS (active low) IRQ interrupt request pin is set to pull down An overflow (saturation) occurred in DA path No overflow occurred in DA channel An overflow (saturation) occurred in AD path No overflow occurred in AD channel Def.

5

SPIOHIZ 0 00 01 10 11 1 0 1 0 1 0

0

4-3

SPIOSEL(1:0)

00

2 1 0

IRQCMOS OVFDA OVFAD

0 0 0

Note: content of bits 1 to 0 in CR33 is cleared after reading, while it is left unchanged if accessed for writing.

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Control registers

STw5098

5.10
CR# (hex) CR34 (22h) CR35 (23h)

AGC
Description AGC attack/decay coeff. AGC control
X

D7

D6

D5

D4

D3

D2

D1

D0

Def. 0000 0000 0000 0000

AGCATT(3:0)

AGCDEC(3:0)

ENAG CLIN

ENAG CMIC

AGC RANGE

AGCLEV(3:0)

Table 28.
Bits

CR 34 description
Na m e Value CR 34 description AGC attack time constant; FS=AD data rate 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 Audio filter in AD path 4096 / FS 2048 / FS 1365 / FS 1024 / FS 683 / FS 512 / FS 341 / FS 256 / FS 171 / FS 128 / FS 85 / FS 64 / FS 43 / FS 32 / FS Voice filter in AD path 8192 / FS 4096 / FS 2731 / FS 2048 / FS 1365 / FS 1024 / FS 683 / FS 512 / FS 341 / FS 256 / FS 171 / FS 128 / FS 85 / FS 64 / FS Def.

7-4

AGCATT(3:0)

0000

AGC decay time constant; FS=AD data rate 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Audio filter in AD path 65536 / FS 32768 / FS 21845 / FS 16384 / FS 10923 / FS 8192 / FS 5461 / FS 4096 / FS 2731 / FS 2048 / FS 1365 / FS 1024 / FS 683 / FS 512 / FS 341 / FS 256 / FS Voice filter in AD path 131072 / FS 65536 / FS 43691 / FS 32768 / FS 21845 / FS 16384 / FS 10923 / FS 8192 / FS 5461 / FS 4096 / FS 2731 / FS 2048 / FS 1365 / FS 1024 / FS 683 / FS 512 / FS

3-0

AGCDEC(3:0)

0000

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STw5098 Table 29.
Bits 6 5 4

Control registers CR 35 description
Na m e Value 1 0 1 0 1 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 CR35 description AGC control on AD path acts on Line In Gain AGC control on AD path does not act on Line In Gain AGC control on AD path acts on Mic Gain AGC control on AD path does not act on Mic Gain AGC action range is -21.0 dB to +21.0 dB AGC action range is -10.5 dB to +10.5 dB AGC requested output level -30.0 dB gain -30.0 dB gain -27.0 dB gain -24.0 dB gain -21.0 dB gain -18.0 dB gain -15.0 dB gain -12.0 dB gain -9.0 dB gain -6.0 dB gain Def. 0 0 0

ENAGCLIN ENAGCMIC AGCRANGE

3-0

AGCLEV(3:0)

0000

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Control interface and master clock

STw5098

6

Control interface and master clock
Unless specified, the following description applies to both entities.

6.1
Figure 5.
WRITE SINGLE BYTE

Control interface I2C mode
Control interface I2C format
A CK ACK ACK

DEVICE ADDRESS REG n ADDRESS 0 0 0 1 1 0 1 AS START

REG n DATA IN STOP

WRITE MULTI BYTE

ACK ACK ACK ACK ACK DEVICE ADDRESS REG n ADDRESS REG n DATA IN REG n+m DATA IN 0 0 1 1 0 1 AS 0 START m+1 data bytes STOP

CURRENT ADDR READ SINGLE BYTE CURRENT ADDR READ MULTI BYTE

ACK NO ACK DEVICE ADDRESS urrent REG DATA OUT C 0 0 1 1 0 1 AS1 START STOP ACK ACK ACK NO ACK DEVICE ADDRESS urrent REG DATA OUT C Curr REG+m DATA OUT 1 0 0 1 1 0 1 AS m+1 data bytes START STOP

RANDOM ADDR READ SINGLE BYTE RANDOM ADDR READ MULTI BYTE

ACK ACK ACK NO ACK DEVICE ADDRESS REG n ADDRESS DEVICE ADDRESS REG n DATA OUT 0 0 0 1 1 0 1 AS 1 0 0 1 1 0 1 AS START START STOP ACK ACK A CK ACK ACK NO ACK DEVICE ADDRESS REG n ADDRESS DEVICE ADDRESS REG n DATA OUT REG n+m DATA OUT 0 0 1 1 0 1 AS 0 1 0 0 1 1 0 1 AS START START m+1 data bytes STOP

Note:
Figure 6.

CMOD pin tied to GND
Control interface: I2C format timing

SDA

tBUF

tHD (STA)

tLOW

tHD (DAT)

tHIGH

tSU (DAT)

tSU (STA)

tHD (STA)

tSU (STO)

SCLK

tR P S P = STOP S = START Sr = START repeated

tF Sr P

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STw5098 Table 30.
Symbol fSCL tHIGH tLOW tR tF tHD:STA tSU:STA tHD:DAT tSU:DAT tSU:STO tBUF

Control interface and master clock Control interface timing with I²C format
Parameter Clock frequency Clock pulse width high Clock pulse width low SDA and SCLK rise time SDA and SCLK fall time Star t condition hold time Star t condition setup time Data input hold time Data input setup time Stop condition setup time Bus free time 600 600 0 250 600 1300 600 1300 1000 300 Test conditions Min. Typ. Max. 400 Unit kHz ns ns ns ns ns ns ns ns ns ns

6.2

Control interface SPI mode
Figure 7.
CSB SCLK

Control interface SPI format(a)

SDIN

W/R A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

8 bit Address

8 bit Data

SDO SPIOHIZ=1

D7

D6

D5

D4

D3

D2

D1

D0

8 bit Data

a. CMOD pin tied to VCCIO; SDO pin position selected with bits SPIOSEL in CR33.

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Control interface and master clock Figure 8. Control interface: SPI format timing
tHICS CSB tSCSF tPSCK tLSCK SCLK 0 tSDI tHDI 8 tHSCK 15 tHCS

STw5098

tSCSR

SDIN

W/R tDDO F SPIOHIZ=1 SPIOHIZ=0

D7 tDDO

D0 tDDOL

SDO

D7

D0

Table 31.
Symbol tHICS tSCSR tSCSF tHCS tSDI tHDI tDDOF tDDO tDDOL tPSCK tHSCK tLSCK

Control interface signal timing with SPI format
Parameter CSB pulse width high Setup time CSB rising edge to SCLK rising edge Setup time CSB falling edge to SCLK rising edge Hold time CSB rising edge from SCLK rising edge Setup time SDIN to SCLK rising edge Hold time SDIN from SCLK rising edge SDO first Delay time from SCLK falling edge SDO Delay time from SCLK falling edge SDO Delay time from CSB rising edge Period of SCK SCK pulse width high SCK pulse width low Measured from VIH to VIH Measured from VIL to VIL 100 40 40 Test conditions Min. 80 20 20 20 20 20 30 20 30 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns

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STw5098

Control interface and master clock

6.3
Table 32.
Symbol tCKDC

Master clock timing
AMCK timing
Parameter AMCK duty cycle AMCK range 4 MHz-8 MHz 8 MHz-32 MHz Min. 45 40 Typ. Max. 55 60 Unit % %

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Audio interfaces

STw5098

7

Audio interfaces
Information included in the following section is valid for both entities.

Figure 9.

Audio interfaces formats: delayed, left and right justified

I2S format (delayed) with default polarity settings, ADHIZ=0
DA_SYNC/ AD_SYNC DA_CK/ AD_CK 1 AD_CK/DA_CK DA_DATA 1 2 n-1 n MSB n-bit word Left data LSB 1 2 n-1 n MSB n-bit word Left data LSB
1 AD_CK/DA_CK

1 2 n-1 n MSB n-bit word Right data LSB 1 2 n-1 n MSB n-bit word Right data LSB

AD_DATA

Left justified format with default polarity settings, ADHIZ=0
DA_SYNC/ AD_SYNC DA_CK/ AD_CK DA_DATA 1 2 n-1 n MSB n-bit word Left data LSB 1 2 n-1 n MSB n-bit word Left data LSB 1 2 n-1 n MSB n-bit word Right data LSB 1 2 n-1 n MSB n-bit word Right data LSB

AD_DATA

Right justified format with default polarity settings
32 AD_CK/DA_CK DA_SYNC/ AD_SYNC DA_CK/ AD_CK DA_DATA 1 2 n-1 n MSB n-bit word Left data LSB
1 2 n-1 n MSB n-bit word Left data LSB

32 AD_CK/DA_CK

1 2 n-1 n MSB n-bit word Right data LSB 1 2 n-1 n MSB n-bit word Right data LSB

AD_DATA

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STw5098 Figure 10. Audio interfaces formats: DSP, SPI and PCM
DSP format delayed and non-delayed (default AD_CK/DA_CK polarity, ADHIZ=0)

Audio interfaces

DA_SYNC/ AD_SYNC DA_CK/ A D_ CK DA_DATA

{

SYNCP=0 SYNCP=1

1 2 n-1 n 1 2 n-1 n MSB n-bit word Left data LSB MSB n-bit word Right data LSB 1 2 n-1 n 1 2 n-1 n MSB n-bit word Left data LSB MSB n-bit word Right data LSB

AD_DATA

SPI format (slave only) (default AD_CK/DA_CK polarity, ADHIZ=1 - Stereo or Mono)
DA_SYNC/ AD_SYNC DA_CK/ A D_ CK DA_DATA
1 M SB x 1 M SB 2 3 n-1 n n-bit word Left/Mono data LSB 2 3 n-1 n n-bit word Left/Mono data LSB High impedance x 1 2 3 MSB n-bit word Right/Mono data 1 2 3 MSB n-bit word Right/Mono data

AD_DATA

PCM format (default AD_CK/DA_CK polarity, ADHIZ=1)

DA_SYNC/ AD_SYNC

{

SYNCP=0 SYNCP=1

DA_CK/ A D_ CK DA_DATA
1 M SB 1 M SB 2 3 n-1 n LSB n-bit word Mono data 3 n-1 n LSB n-bit word Mono data High impedance 1 M SB 1 M SB

AD_DATA

2

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Audio interfaces Figure 11. Audio interface timings: master mode
DA_SYNC/ AD_SYNC t DS Y

STw5098

DA_CK/ AD_CK

{

CKP=0

CKP=1 tSDDA tHDDA

DA_DATA tDAD AD_DATA PCM format only ADHIZ=1 ADHIZ=0 tDAD AD_DATA All other formats ADHIZ=1 ADHIZ=0 ADHIZ =1 ADHIZ =0 tDAD tDADZ ADHIZ =1 ADHIZ=0

Figure 12. Audio interface timing: slave mode
DA_SYNC/ AD_SYNC tHSY tSSY

DA_CK/ AD_CK

{

CKP=0 tHCK CKP=1 tSDDA tHDDA tPCK tLCK

DA_DATA tDADST ADHIZ=1 ADHIZ=0 tDAD ADHIZ=1 ADHIZ=0 tDAD ADHIZ =1 ADHIZ =0 tDAD tDADZ ADHIZ =1 ADHIZ =0

AD_DATA PCM format

AD_DATA All other formats

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STw5098 Table 33.
Symbol

Audio interfaces Audio interface signal timings
Parameter Test conditions Min. Typ. Max. Unit

tDSY

Delay of AD_SYNC/DA_SYNC Master Mode edge from AD_CK/DA_CK active edge Setup time DA_DATA to DA_CK active edge Hold time DA_DATA from DA_CK active edge Delay of AD_DATA edge from AD_CK active edge Delay of the first AD_DATA AD_SYNC active edge comes edge from AD_SYNC after AD_CK active edge active edge Delay of AD_DATA high impedance from AD_SYNC inactive edge Setup time AD_SYNC/DA_SYNC to AD_CK/DA_CK active edge PCM format 10 10 10

10

ns

tSDDA tHDDA tDAD

ns ns 30 ns

tDADST

30

ns

tDADZ

50

ns

tSSY

Sla