VIPer53EDIP - E VIPer53ESP - E
OFF-line Primary Switch
Features
Switching frequency up to 300kHz Current mode control with adjustable limitation Soft start and shut-down control Automatic burst mode in standby condition ("Blue Angel" compliant ) Undervoltage lockout with Hysteresis Integrated start-up current source Over-temperature protection Overload and short-circuit control Overvoltage protection In compliance with the 2002/95/EC European Directive Typical applications cover offline power supplies with a secondary power capability ranging up to 30W in wide range input voltage, or 50W in single European voltage range and DIP-8 package and 40W in wide range input voltage, or 65W in single European voltage range and PowerSO-10 package, with the following benefits: Overload and short-circuit events controlled by feedback monitoring and delayed device reset; Efficient standby mode by enhanced pulse skipping. Integrated start-up current source is disabled during normal operation to reduce the input power.
DRAI N
PowerSO-10
DIP-8
Description
The VIPer53E combines an enhanced current mode PWM controller with a high voltage MDMesh Power MOSFET in the same package.
Block diagram
OS C ON/ OFF OS CI LLAT OR
PW M LA TCH OV ERTEM P . DET ECTOR R1 S FF Q R2 R3 R4 R5 B LA NK ING TIME S E LE CTION 1V
UV LO COM P A RA TOR V DD 8. 4/ 11. 5V 8V 150/ 400ns BL ANKI NG
PW M COMP A RA TOR
0. 5V
HC O MP
CURRE NT A M P LIFIE R
S TA NDB Y COMP A RA TOR
0. 5V
Vc c
125k 4V OV E RLOA D COM P A RA TOR
IC OMP
4. 4V
OV E RV OLTA GE COM P A RA TOR 4. 5V 18V
TO V L
COM P
S OURCE
January 2006
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Contents
VIPer53EDIP - E / VIPer53ESP - E
Contents
1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 1.2 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin connections and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Rectangular U-I Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Secondary Feedback Configuration Example . . . . . . . . . . . . . . . . . . . . 9 Current Mode Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 High Voltage Start-up Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Short-Circuit and Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . 15 Regulation Loop Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Special Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Software Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Operation pictures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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Electrical data
1
1.1
Electrical data
Maximum rating
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 1.
Symbol VDS ID VDD VOSC ICOMP ITOVL VESD TJ TC TSTG
Absolute maximum rating
Parameter Continuous Drain Source Voltage (TJ= 25 ... 125C) (1) Continuous Drain Current Supply Voltage OSC Input Voltage Range COMP and TOVL Input Current Range (1) Electrostatic Discharge: Machine Model (R = 0; C = 200pF) Charged Device Model Junction Operating Temperature Case Operating Temperature Storage Temperature Value -0.3 ... 620 Internally limited 0 ... 19 0 ... V DD -2 ... 2 Unit V A V V mA
200 1.5 Internally limited -40 to 150 -55 to 150
V kV C C C
1. In order to improve the ruggedness of the device versus eventual drain overvoltages, a resistance of 1k should be inserted in series with the TOVL pin.\
1.2
Thermal data
Table 2.
Symbol RthJC RthJA
Thermal data
Parameter Thermal Resistance Junction-case Thermal Resistance Ambient-case Ma x Max PowerSO-10 (1) 2 60 DIP-8 (2) 20 80 Unit C/W C/W
1. When mounted on a standard single-sided FR4 board with 50mm˛ of Cu (at least 35 mm thick) connected to the DRAIN pin. 2. When mounted on a standard single-sided FR4 board with 50mm˛ of Cu (at least 35 mm thick) connected to the device tab.
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Electrical characteristics
VIPer53EDIP - E / VIPer53ESP - E
2
Electrical characteristics
TJ = 25C, VDD = 13V, unless otherwise specified Table 3.
S y mb o l BVDSS IDSS
Power section
Parameter Drain-Source Voltage Off State Drain Current Test conditions ID = 1mA; VCOMP = 0V VDS = 500V; VCOMP = 0V; Tj = 125C Min. 620 150 Typ. Max. Unit V A
RDS(on)
ID = 1A; VCOMP = 4.5V; VTOVL = 0V Static Drain-Source TJ = 25C On State Resistance TJ = 100C Fall Time Rise Time Drain Capacitance Effective Output Capacitance ID = 0.2A; VIN = 300V (1) ID = 1A; VIN = 300V (1) VDS = 25V 200V < V DSon < 400V (2)
0.9
1 1.7
ns ns pF pF
tfv trv Coss CEon
100 50 170 60
1. On clamped inductive load 2. This parameter can be used to compute the energy dissipated at turn on Eton according to the initial drain to source voltage VDSon and the following formula:
VD S o n 1 2 E t o n = -- C E o n 300 ---------------2 300
1.5
Table 4.
Symbol FOSC1
Oscillator Section
Parameter Oscillator Frequency Initial Accuracy Test Conditions RT = 8k; CT = 2.2nF Figure 15 on page 23 RT = 8k; CT = 2.2nF Min. 95 Typ. 100 Max. 105 Unit kHz
FOSC2
Oscillator Frequency Total Variation
Figure 17 on page 24 VDD = V DDon ... VDDovp; TJ = 0 ... 100C
93
100
107
kHz
VOSChi VOSClo
Oscillator Peak Voltage Oscillator Valley Voltage
9 4
V V
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VIPer53EDIP - E / VIPer53ESP - E
Electrical characteristics
Table 5.
S y mb o l VDSstart IDDch1 IDDch2 IDDchoff IDD0 IDD1 VDDoff VDDon VDDhyst VDDovp
Supply Section
Parameter Drain Voltage Starting Threshold Startup Charging Current Test Conditions VDD = 5V; IDD = 0mA VDD = 0 ... 5V; VDS = 100V Figure 9 on page 22 M in. Typ. 34 -12 -2 0 M ax. Unit 50 V mA mA mA
Startup Charging Current VDD = 10V; VDS = 100VFigure 9. Startup Charging Current VDD = 5V; V DS = 100VFigure 11. in Thermal Shutdown TJ > TSD - THYST Operating Supply Current Fsw = 0kHz; V COMP = 0V Not Switching Operating Supply Current Fsw=100kHz Switching VDD Undervoltage Shutdown Threshold VDD Startup Threshold VDD Threshold Hysteresis VDD Overvoltage Shutdown Threshold Figure 9 on page 22 Figure 9. Figure 9. Figure 9. 7.5 10. 2 2.6 17
8 9 8.4 11.5 3.1 18
11
mA mA
9.3 12.8
V V V
19
V
Table 6.
Symbol HCOMP
Pwm Comparator Section
Parameter VCOMP / IDPEAK Test Conditions VCOMP = 1 ... 4 V Figure 14. dID/dt = 0 dID/dt = 0 Figure 14. ICOMP = 0mA; VTOVL = 0V Figure 14. dID/dt = 0 VCOMP = VCOMPovl ; VTOVL = 0V dID/dt = 0 ID = 1A Figure 10 on page 22 VCOMP < VCOMPBLFigure 10. VCOMP > VCOMPBLFigure 10. VCOMP < VCOMPBL 300 100 450 Min. Typ. Ma x . Unit
1. 7
2 0.5
2. 3
V/ A V
VCOMPos VCOMP Offset IDlim Peak Drain Current Limitation Drain Current Capability Current Sense Delay to Turn-Off VCOMP Blanking Time Change Threshold Blanking Time Blanking Time Minimum On Time
1. 7
2
2. 3
A
IDmax td VCOMPbl tb1 tb2 tONmin1
1. 6
1. 9 250 1 400 150 600
2. 3
A ns V
500 200 750
ns ns ns
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Electrical characteristics Table 6.
Symbol tONmin2 VCOMPoff VCOMPhi ICOMP
VIPer53EDIP - E / VIPer53ESP - E
Pwm Comparator Section
Parameter Minimum On Time VCOMP Shutdown Threshold VCOMP High Level Test Conditions VCOMP > VCOMPBL Figure 13 on page 23 ICOMP=0m A (1) Min. 250 Typ. 350 0. 5 4. 5 0. 6 Ma x . 450 Unit ns V V mA
COM P Pull Up Current VCOMP= 2.5V
1. In order to ensure a correct stability of the internal current source, a 10nF capacitor (minimum value 8nF) should always be present on the COMP pin.
Table 7.
Symbol VCOMPovl
Overload Protection Section
Parameter VCOMP Overload Threshold VCOMPhi to VCOMPovl Voltage Difference VTOVL Overload Threshold Overload Delay Test Conditions ITOVL = 0mA Figure 7 on page 20
(1)
Min.
Typ. 4.35
Ma x .
Uni t V
VDIFFovl
VDD = VDDoff ... VDDreg; ITOVL= 0mA Figure 7.
(1)
50
150
250
mV
VOVLth tOVL
Figure 7. COVL = 100nF Figure 7.
4 8
V ms
1. VCOMPovl is always lower than VCOMPhi
Table 8.
S y mb o l TSD THYST
Over temperature Protection Section
Parameter Thermal Shutdown Temperature Thermal Shutdown Hysteresis Test Conditions Figure 11 on page 22 Figure 11 on page 22 Min. 140 Typ. 160 40 Ma x . Uni t C C
Table 9.
Typical Output Power Capability
Type European (195 - 265Vac) 50W 65W US / Wide range (85 - 265Vac) 30W 40W
VIPer53EDIP-E VIPer53ESP-E
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Pin connections and function
3
Pin connections and function
Figure 1. Pin connection (top view)
8 T O VL
CO MP 1
DRAIN NC 1 2 3 4 5 10 9 8 7 6 SOU RC E NC NC OSC COMP
OSC 2
7
VD D
NC NC
SOURCE 3
6
NC
V DD TO V L
SOURCE 4
5
DRAIN
DIP-8 Figure 2. Current and voltage conventions
I DD
PowerSO-10
ID
VDD IOSC OSC 15 V
DRAIN
V DS V DD ITOVL VOS C ICOMP VT OVL VCOMP T OV L C O MP SOURCE
Table 10.
Pin Name
Pin function
Pin Function Power supply of the control circuits. Also provides the charging current of the external capacitor during start-up. The functions of this pin are managed by four threshold voltages: - VDDon: Voltage value at which the device starts switching (Typically 11.5 V). - VDDoff: Voltage value at which the device stops switching (Typically 8.4 V). - VDDovp: Triggering voltage of the overvoltage protection (Trimmed to 18 V). Power MOSFET source and circuit ground reference. Power MOSFET drain. Also used by the internal high voltage current source during the start-up phase, to charge the external VDD capacitor. Allows the setting of the dynamic characteristic of the converter through an external passive network. The useful voltage range extends from 0.5V to 4.5V. The Power MOSFET is always off below 0.5V, and the overload protection is triggered if the voltage exceeds 4.35V. This action is delayed by the timing capacitor connected to the TOVL pin. Allows the connection of an external capacitor for delaying the overload protection, which is triggered by a voltage on the COMP pin higher than 4.4V. Allows the setting of the switching frequency through an external Rt-Ct network. DocRev1 7/31
VDD
SO URCE DRAI N
CO MP
TOVL OS C
Rectangular U-I Output characteristics
VIPer53EDIP - E / VIPer53ESP - E
4
Rectangular U-I Output characteristics
Figure 3. Off Line Power Supply With Optocoupler Feedback
F1
A C IN
C1
D1 T1
R1
C2
R2 C3
T2
D2
L1 D4 R4 D3 C8 C9 DC OUT
R3
V DD
DRA IN
C10
OSC
CONTROL R8 COMP TOV L SOURCE U2
C4
C5
C12 10nF
R5
R9 1k
C7
C6
C11 R7
U3
R6
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VIPer53EDIP - E / VIPer53ESP - E
Secondary Feedback Configuration Example
5
Secondary Feedback Configuration Example
The secondary feedback is implemented through an optocoupler driven by a programmable zener diode (TL431 type) as shown in Figure 3 on page 8 The optocoupler is connected in parallel with the compensation network on the COMP pin which delivers a constant biasing current of 0.6mA to the optotransistor. This current does not depend on the compensation voltage, and so it does not depend on the output load either. Consequently, the gain of the optocoupler ensures a constant biasing of the TL431 device (U3), which is responsible for secondary regulation. If the optocoupler gain is sufficiently low, no additional components are required to a minimum current biasing of U3. Additionally, the low biasing current protects the optocoupler from premature failure. The constant current biasing can be used to simplify the secondary circuit: instead of a TL431, a simple zener and resistance network in series with the optocoupler diode can insure a good secondary regulation. Current flowing in this branch remains constant just as it does by using a TL431, so typical load regulation of 1% can be achieved from zero to full output current with this simple configuration. Since the dynamic characteristics of the converter are set on the secondary side through components associated to U3, the compensation network has only a role of gain stabilization for the optocoupler, and its value can be freely chosen. R5 can be set to a fixed value of 2.2k, offering the possibility of using C7 as a soft start capacitor: When starting up the converter, the VIPer53E device delivers a constant current of 0.6mA on the COMP pin, creating a constant voltage of 1.3V in R5 and a rising slope across C7. This voltage shape, together with the operating range of 0.5V to 4.5V provides a soft startup of the converter. The rising speed of the output voltage can be set through the value of C7. The C4 and C6 values must be adjusted accordingly in order to ensure a correct startup.
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Current Mode Topology
VIPer53EDIP - E / VIPer53ESP - E
6
Current Mode Topology
The VIPer53E implements the conventional current mode control method for regulating the output voltage. This kind of feedback includes two nested regulation loops: The inner loop controls the peak primary current cycle by cycle. When the Power MOSFET output transistor is on, the inductor current (primary side of the transformer) is monitored with a SenseFET technique and converted into a voltage. When VS reaches VCOMP, the power switch is turned off. This structure is completely integrated as shown on the Block Diagram of Figure on page 1, with the current amplifier, the PWM comparator, the blanking time function and the PWM latch. The following formula gives the peak current in the Power MOSFET according to the compensation voltage:
VCO MP VCO MP os I D p e a k = ------------------------------------------------HC O M P
The outer loop defines the level at which the inner loop regulates peak current in the power switch. For this purpose, VCOMP is driven by the feedback network (TL431 through an optocoupler in secondary feedback configuration, see Figure 3 on page 8) and is sets accordingly the peak drain current for each switching cycle. As the inner loop regulates the peak primary current in the primary side of the transformer, all input voltage changes are compensated for before impacting the output voltage. This results in an improved line regulation, instantaneous correction to line changes, and better stability for the voltage regulation loop. Current mode topology also provides a good converter start-up control. The compensation voltage can be controlled to increase slowly during the start-up phase, so the peak primary current will follow this soft voltage slope to provide a smooth output voltage rise, without any overshoot. The simpler voltage mode structure which only controls the duty cycle, leads generally to high current at start-up with the risk of transformer saturation. An integrated blanking filter inhibits the PWM comparator output for a short time after the integrated Power MOSFET is switched on. This function prevents anomalous or premature termination of the switching pulse in the case of current spikes caused by primary side transformer capacitance or secondary side rectifier reverse recovery time when working in continuous mode.
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VIPer53EDIP - E / VIPer53ESP - E
Standby Mode
7
Standby Mode
The device offers a special feature to address the low load condition. The corresponding function described hereafter consists of reducing the switching frequency by going into burst mode, with the following benefits: It reduces the switching losses, thus providing low consumption on the mains lines. The device is compliant with "Blue Angel" and other similar standards, requiring less than 0.5 W of input power when in standby. It allows the regulation of the output voltage, even if the load corresponds to a duty cycle that the device is not able to generate because of the internal blanking time, and associated minimum turn on. For this purpose, a comparator monitores the COMP pin voltage, and maintains the PWM latch and the Power MOSFET in the Off state as long as VCOMP remains below 0.5V (See Block Diagram on page 2). If the output load requires a duty cycle below the one defined by the minimum turn on of the device, the VCOMP net decreases its voltage until it reaches this 0.5V threshold (VCOMPoff). The Power MOSFET can be completely Off for some cycles, and resumes normal operation as soon as VCOMP is higher than 0.5V. The output voltage is regulated in burst mode. The corresponding ripple is not higher than the nominal one at full load. In addition, the minimum turn on time which defines the frontier between normal operation and burst mode changes according to VCOMP value. Below 1.0V (VCOMPbl), the blanking time increases to 400ns, whereas for higher voltages, it is 150ns Figure 10 on page 22 The minimum turn on times resulting from these values are respectively 600 ns and 350 ns, when taking into account internal propagation time. This brutal change induces an hysteresis between normal operation and burst mode as shown on Figure 10 on page 22 When the output power decreases, the system reaches point 2 where VCOMP equals VCOMPbl. The minimum turn-on time passes immediately from 350ns to 600ns, exceeding the effective turn-on time that should be needed at this output power level. Therefore the regulation loop will quickly drive VCOMP to VCOMPoff (Point 3) in order to pass into burst mode and to control the output voltage. The corresponding hysteresis can be seen on the switching frequency which passes from FSWnom which is the normal switching frequency set by the components connected to the OSC pin and to FSWstby. Note: This frequency is actually an equivalent number of switching pulses per second, rather than a fixed switching frequency since the device is working in burst mode. As long as the power remains below PRST the output of the regulation loop remains stuck at VCOMPsd and the converter works in burst mode. Its "density" increases (i.e. the number of missing cycles decreases) as the power approaches P RST and finally resumes normal operation at point 1. The hysteresis cannot be seen on the switching frequency, but it can be seen in the sudden surge of the COMP pin voltage from point 3 to point 1 at that power level. The power points value PRST and PSTBY are defined by the following formulas:
2 1 1 2 P R S T = -- · F S W n o m · ( t b 1 + t d ) · V I N · -----Lp 2
1 2 P S T B Y = -- · F S W n o m · I p ( V C O M P b l ) · L p 2
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Standby Mode
VIPer53EDIP - E / VIPer53ESP - E
Where Ip(VCOMPbl2) is the peak Power MOSFET current corresponding to a compensation voltage of VCOMPbl (1V). Note: The power point PSTBY where the converter is going into burst mode does not depend on the input voltage. The standby frequency FSWstby is given by:
PS T BY P S W s t b y = ---------------- · F S W n o m PR S T
The ratio between the nominal and standby switching frequencies can be as high as 4, depending on the Lp value and input voltage. Figure 4. .Standby Mode Implementation
ton
3 600ns Minimum turn on 350ns 1 2
VCOMP
VCOMPsd VCOMPoff VCOMPbl
PIN
PRST 3 PSTBY 2 1
FSW
FSWstby FSWnom
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VIPer53EDIP - E / VIPer53ESP - E
High Voltage Start-up Current Source
8
High Voltage Start-up Current Source
An integrated high voltage current source provides a bias current from the DRAIN pin during the start-up phase. This current is partially absorbed by internal control circuits in standby mode with reduced consumption, and also supplies the external capacitor connected to the VDD pin. As soon as the voltage on this pin reaches the high voltage threshold VDDon of the UVLO logic, the device turns into active mode and starts switching. The start-up current generator is switched off, and the converter should normally provide the needed current on the VDD pin through the auxiliary winding of the transformer, as shown on Figure 3 on page 8. The external capacitor CVDD on the VDD pin must be sized according to the time needed by the converter to start-up, when the device starts switching. This time tss depends on many parameters, including transformer design, output capacitors, soft start feature, and compensation network implemented on the COMP pin and possible secondary feedback circuit. The following formula can be used for defining the minimum capacitor needed:
ID D1 t s s C V D D > -----------------------VD D h y s t
Figure 9 on page 22 shows a typical start-up event. V DD starts from 0V with a charging current IDDch1 at about 9 mA. When about VDDoff is reached, the charging current is reduced down to IDDch2 which is about 0.6mA. This lower current leads to a slope change on the VDD rise. Device starts switching for VDD equal to VDDon, and the auxiliary winding delivers some energy to VDD capacitor after the start-up time tss. The charging current change at VDDoff allows a fast complete start-up time tSDU, and maintains a low restart duty cycle. This is especially useful for short circuits and overloads conditions, as described in the following section.
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High Voltage Start-up Current Source Figure 5. Start-up Waveforms
VIPer53EDIP - E / VIPer53ESP - E
ID D
IDD 1
t
IDD ch2
IDD ch1
VDD
VDDreg VDDs t VD Dsd tSU
tSS
t
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Short-Circuit and Overload Protection
9
Short-Circuit and Overload Protection
A VCOMPovl threshold of about 4.4V has been implemented on the COMP pin. When VCOMP goes above this level, the capacitor connected on the TOVL pin begins to charge. When reaching typically VOVLth (4V), the internal MOSFET driver is disabled and the device stops switching. This state is latched because of to the regulation loop which maintains the COMP pin voltage above the V COMPovl threshold. Since the VDD pin does not receive any more energy from the auxiliary winding, its voltage drops down until it reaches VDDoff and the device is reset, recharging the VDD capacitor for a new restart cycle. Note: If VCOMP drops below the VCOMPovl threshold for any reason during the VDD drop, the device resumes switching immediately. The device enters an endless restart sequence if the overload or short circuit condition is maintained. The restart duty cycle DRST is defined as the time ratio for which the device tries to restart, thus delivering its full power capability to the output. In order to keep the whole converter in a safe state during this event, DRST must be kept as low as possible, without compromising the real start-up of the converter. A typical value of about 10% is generally sufficient. For this purpose, both VDD and TOVL capacitors can be used to satisfy the following conditions:
C O V L > 12.5 10
6
tss
CO VL I D D c h 2 4 1 C V D D > 8 10 ------------- 1 -----------------------------------DRST VD D h ys t
Refer to the previous start-up section for the definition of tss, and CVDD must also be checked against the limit given in this section. The maximum value of the two calculus will be adopted. All this behavior can be observed on Figure 2 on page 7. In Figure 7 on page 20 the value of the drain current Id for VCOMP = VCOMPovl is shown. The corresponding parameter IDmax is the drain current to take into account for design purposes. Since IDmax represents the maximum value for which the overload protection is not triggered, it defines the power capability of the power supply.
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Regulation Loop Stability
VIPer53EDIP - E / VIPer53ESP - E
10
Regulation Loop Stability
The complete converter open loop transfer function can be built from both power cell and the feedback network transfer functions. A theoretical example can be seen in Figure 11 on page 22 for a discontinuous mode flyback loaded by a simple resistor. A typical schematic corresponding to this situation can be seen on Figure 3 on page 8. The transfer function of the power cell is represented as G(s) in .Figure 11 on page 22 It exhibits a pole which depends on the output load and on the output capacitor value. As the load of a converter may change, two curves are shown for two different values of output resistance value, RL1 and R L2. A zero at higher frequency values then appears, due to the output capacitor ESR. Note: The overall transfer function does not depend on the input voltage because of the current mode control. A typical regulation loop is shown on Figure 3 on page 8 and has a fixed behavior represented by F(s) on Figure 11 on page 22. A double zero due to the R 1-C1 network on the COMP pin and to the integrator built around the TL431 and R2-C2 is set at the same value as the maximum load RL2 pole. The total transfer function is shown as F(s). G(s) at the bottom of Figure 11 on page 22. For maximum load (plain line), the load pole begins exactly where the zeros of the COMP pin and the TL431 stop, and this results in a first order decreasing slope until it reaches the zero of the output capacitor ESR. The point where the complete transfer function has a unity gain is known as the regulation bandwidth and has a double interest: The higher it is, the faster the reaction will be to an eventual load change, and the smaller the output voltage change will be. The phase shift in the complete system at this point has to be less than 135 to ensure good stability. Generally, a first-order slope gives 90 of phase shift, and a second-order gives 180. In Figure 3 on page 8, the unity gain is reached in a first order slope, so the stability is ensured. The dynamic load regulation is improved by increasing the regulation bandwidth, but some limitations have to be respected: 1. As the transfer function above zero due the ESR capacitor is not reliable (the ESR itself is not well specified, and other parasitic effects may take place), the bandwidth should always be lower than the minimum of FC and ESR zero As the highest bandwidth is obtained with the highest output power (plain line with RL2 load in Figure 3, the above criteria will be checked for this condition and allows the value of R4 if R1 is set to a fixed value (e.g., (2.2k).
2.
As the highest bandwidth is obtained with the highest output power (Plain line with RL2 load in Figure 3), the above criteria will be checked for this condition and allows to define the value of R 4, if R1 is set fixed (2.2k, for instance). The following formula can be derived:
R 4 = P G R MA X O 1 -------------------- ------------------------------------------------------P F R C O U T 2 BW 2 L 2 OUT 2 V OUT = ---------------O UT2 RL 2
with:
P
and:
P
MAX
2 1 = -- L I F 2 P L I M SW
Go is the current transfer ratio of the optocoupler.
16/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E
Regulation Loop Stability
The lowest load gives another condition for stability: The frequency FBW1 must not encounter the third order slope generated by the load pole, the R1-C1 network on the COMP pin and the R2-C2 network at the level of the TL431 on secondary side. This condition can be met by adjusting both C1 and C2 values:
R C P L 1 OUT OU T1 C > ---------------------------------- -------------------1 GO PM A X 2 6 .3 -------- R 1 R4 POU T 1 R L 1 CO U T C > ---------------------------------------------- -------------------2 G P O MA X 6 .3 -------- R R 1 2 R 4
2 VOU T = -----------------R L1
with:
PO U T 1
The above formula gives a minimum value for C1. It can be then increased to provide a natural soft start function as this capacitor is charged by the current ICOMP at start-up.
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17/31
Special Recommendations
VIPer53EDIP - E / VIPer53ESP - E
11
Special Recommendations
10nF capacitor (minimum value: 8nF) should always be connected to the COMP pin to ensure correct stability of the internal current source Figure 12 on page 22. In order to improve the ruggedness of the device versus eventual drain overvoltages, a resistance of 1k should be inserted in series with the TOVL pin, as shown on Figure 12 on page 22
Note:
This resistance does not impact the overload delay, as its value is negligible prior to the internal pull-up resistance (about 125k).
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VIPer53EDIP - E / VIPer53ESP - E
Software Implementation
12
Software Implementation
All the above considerations and some others are included included in ST design software which provides all of the needed components around the VIPer device for specified output configurations, and is available on www.st.com.
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Operation pictures
VIPer53EDIP - E / VIPer53ESP - E
13
Operation pictures
Figure 6.
ID
C <
Rise and Fall time
t
VD D D RAIN
VDS
OSC 300V C ONTRO L
90% tfv trv
COMP
TOVL
SOU RCE
10%
t
Figure 7.
Overloaded Event
VDD
Normal operation Abnormal operation
V D D on VDDoff
VCOMP
VDIF Fovl
VTOVL
VOVLth tOVL
V DS
Not switching
Switching
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VIPer53EDIP - E / VIPer53ESP - E Figure 8. Complete Converter Transfer Function
P MAX ---------------- - - -P OU T1 P MA X --------------- - - - -PO UT2 1 -------------------------------- --- -- --R C L1 OUT 1 -------------------------------- -- --- -- R C L2 O UT
Operation pictures
3. 2
3. 2
1
1 --------------------------------------- - - - - - - - - - -2 ESR C OUT
FS
1 ---------------------------------------------------- --- -- --- -- -- -2R C COMP COMP G R 1 -----OR 4
FC
1
F S. GS
F B W2 1 FB W1
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Operation pictures
VIPer53EDIP - E / VIPer53ESP - E
Figure 9.
IDD
I DD 0
Start-up VDD current
Figure 10. Blanking Time
tb
tb1
VD Dhys t
VD Doff ID Dc h2
V D Do n
VDD
tb2
VDS = 100 V FSW = 0 kHz
ID Dc h1
VCOMPbl VCOMPhi
VCOMP
Figure 11. Thermal Shutdown
Tj
TSD
TSD-THYST
Figure 12. Overvoltage Event
VDD
VDDovp
VDD
V DDon
VCOMP
Abnormal operation
Automatic startup
VCO MP
VDS
Not switching
Switching
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VIPer53EDIP - E / VIPer53ESP - E Figure 13. Shutdown Action
VOSC
VOSChi
Operation pictures Figure 14. Comp Pin Gain and Offset
VOSClo
IDpeak
t
VCOMP
IDlim IDmax Slope = 1 / HCOMP
VCOMPoff
t ID
VCOMP
VCOMPos VCOMPovl VCOMPhi
t
Figure 15. Oscillator Schematic
Vcc
VDD
Rt
OSC
PWM section 320
Ct
SOURCE
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Operation pictures
VIPer53EDIP - E / VIPer53ESP - E
The switching frequency settings shown on the graphic here below is valid within the following boundaries: Rt > 2k FSW = 300kHz Figure 16. Oscillator Settings
F requency (kHz)
300
2 .2 n F
4 .7 n F
1nF
10 0
10nF
22nF
10 1 10 100
RT (K )
Figure 17. Typical Frequency Variation vs. Junction Temperature
No rm alise d Frequency
1.04
1.02
1
0.98
0.96
-20
0
20
40
60
80
100
120
Tem perature (C)
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VIPer53EDIP - E / VIPer53ESP - E Figure 18. Typical Current Limitation vs. Junction Temperature
Operation pictures
N o rm a lis ed IDlim
1.04
1.02
1
0.98
0.96
-20
0
20
40
60
80
100
120
Te m p e ra tu re (C)
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Mechanical Data
VIPer53EDIP - E / VIPer53ESP - E
14
Mechanical Data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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Mechanical Data
Table 11.
DIP8 Mechanical Data
Dimensions Databook (mm) Ref. Nom. A A1 A2 b b2 c D E E1 e eA eB L 2.92 3.30 Gr. 470 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 3.30 0.46 1.52 0.25 9.27 7.87 6.35 2.54 7.62 10.92 3.81 4.95 0.56 1.78 0.36 10.16 8.26 7.11 Mi n Ma x 5.33
Package Weight
Figure 19. Package Dimensions
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Mechanical Data Table 12. PowerSO-10 Mechanical Data
Dimensions
VIPer53EDIP - E / VIPer53ESP - E
Databook (mm) Ref. Nom. A A1 B c D D1 E E1 E2 E3 E4 e F H h L q 0 1.20 1.70 8 1.25 13.80 0.50 1.80 3.35 0.00 0.40 0.35 9.40 7.40 9.30 7.20 7.20 6.10 5.90 1.27 1.35 14.40 Mi n Ma x 3.65 0.10 0.60 0.55 9.60 7.60 9.50 7.40 7.60 6.35 6.10
Figure 20. Package Dimensions
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VIPer53EDIP - E / VIPer53ESP - E
Order codes
15
Order codes
Table 13. Order codes
Package PowerSO-10 PowerSO-10 DIP-8 Shipment Tape and reel Tube Tube
Part Number VIPer53ESPTR - E VIPer53ESP - E VIPer53EDIP - E
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Revision history
VIPer53EDIP - E / VIPer53ESP - E
16
Revision history
Table 14.
Date 12-Jan-2006
Document revision history
Revision 1 Initial release. Changes
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Revision history
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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