STLC3085
Integrated Pots interface for home access gateway and WLL
Preliminary Data
Features
Monochip SLIC optimized for WLL & VoIP applications Implement all key features of Borsht function Single supply (4.5V to 12V) Built in DC/DC converter controller Soft battery reversal with programmable transition time On-hook transmission Programmable off-hook detector threshold Integrated ringing Integrated ring trip Parallel control interface (3.3V logic level) Programmable constant current feed Surface mount package Integrated thermal protection Dual gain value option Automatic recognition flyback and buckboost configuration BCDIIIS 90V technology -40C to +85C operating range The battery level is properly adjusted depending on the operating mode. A useful characteristic for these applications is the integrated ringing generator. The control interface is parallel with open drain output and 3.3V logic levels. Constant current feed can be set from 20mA to 25mA. Off-hook detection threshold is programmable from 5mA to 9mA. The device, which is developed in BCDIIIS technology (90V process), operates in the extended temperature range and integrates a thermal protection that sets the device in power down when Tj exceeds 140C.
TQFP44
Description
The STLC3085 is a SLIC device specifically designed for WLL (Wireless Local Loop), and ISDN Terminal Adaptors and VoIP applications. One distinctive characteristic of this device is its ability to operate with a single supply voltage (from +4.5V to +12V) and to self generate the negative battery by means of an on-chip DC/DC conver ter controller that drives an external MOS switch.
February 2007
Rev 3
1/28
www.st.com
28
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
STLC3085
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1. 1 1.2 1. 3 1. 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2. 1 2. 2 2. 3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3. 1 3.2 DC/DC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 Power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 High impedance feeding (HI-Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Layout recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 External components list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
Applications diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Appendix A STLC3085 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Appendix B STLC3085 over voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Appendix C Typical state diagram for STLC3085 operation. . . . . . . . . . . . . . . . 25 5 6 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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STLC3085
Block diagram and pin description
1
1.1
Block diagram and pin description
Block diagram
Figure 1. Block diagram
D0 D1 D2 DET
INPUT LOGIC AND DECODER
OUTPUT LOGIC
BGND
Status and functions
TIP TX RX ZAC1 ZAC RS ZB
LINE
OUTPUT
SUPERVISION AC PROC
DRIVER
STAGE
RING
CREV
DC PROC
CSVR
CLK RSENSE GATE VF
DC/DC CONV.
REFERENCE
Vcc Vss
Agnd
CVCC VPOS
VOLT.
REG.
VBAT
Vbat
CAC
ILTF RD IREF RLIM RTH
AGND
1.2
Pin connection
Figure 2. Pin connection
VBAT1 BGND 35 CREV VBAT N.C. CSVR 34 33 32 31 30 29 28 27 26 25 24 23 12 RES 13 RX 14 ZAC1 15 ZAC 16 RS 17 ZB 18 CAC 19 TX 20 CZ 21 VF 22 N.C. ILTF RD RTH IREF RLIM AGND CVCC VPOS RSENSE GATE CLK RING 37 N.C. N.C. N.C. 38 TIP
44 D0 D1 D2 PD GAIN SET N.C. DET RES RES RES RES 1 2 3 4 5 6 7 8 9 10 11
43
42
41
40
39
36
D00TL488
3/28
Block diagram and pin description
STLC3085
1.3
Table 1.
N 1 2 3 4 5 6,22,38, 39,40,42 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Pin description
Pin description
Pin D0 D1 D2 PD Gain SET NC DET Control Interface: input bit 0. Control Interface: input bit 1. Control interface: input bit 2. Power Down input. Normally connected to CVCC (or to logic level high). Control gain interface:0 Level Rxgain = 0dBTxgain = -6dB Txgain = -12dB 1 Level Rxgain = +6dB Not connected. Logic interface output of the supervision detector (active low). Function
RESERVED Connected to GND RESERVED Connected to GND RESERVED Connected to GND RESERVED Left open. RESERVED Connected to GND RX ZAC1 ZAC RS ZB CAC TX CZ VF 4 wire input port (RX input); 300K input impedance. This signal is referred to AGND. If connected to single supply CODEC output it must be DC decoupled with proper capacitor. RX buffer output (the AC impedance is connected from this node to ZAC). AC impedance synthesis. Protection resistors image (the image resistor is connected from this node to ZAC). Balance Network for 2 to 4 wire conversion (the balance impedance ZB is connected from this node to AGND. ZA impedance is connected from this node to ZAC1). AC feedback input, AC/DC split capacitor (CAC). 4 wire output port (TX output). The signal is referred to AGND. If connected to single supply CODEC input it must be DC decoupled with proper capacitor. Fly-Back compensation Feedback input for DC/DC converter controller. Power Switch Controller Clock (typ. 125KHz). This pin can also be connected to CVCC or AGND. When the CLK pin is connected to CVCC an internal auto-oscillation is internally generated and it is used instead of the external clock. When the CLK pin is connected to AGND, the GATE output is disabled. Driver for external Power MOS transistor (P-channel in Buck-boost configuration, Nchannel in Fly-back configuration). Voltage input for current sensing. RSENSE resistor should be connected close to this pin and VPOS pin (Buck-boost) or GND (Fly-back). The PCB layout should minimize the extra resistance introduced by the copper tracks.
23
CLK
24
GATE
25
RSENSE
4/28
STLC3085 Table 1.
N 26 27 28 29 30 31 32 33 34 35 36 37 41 43 44
Block diagram and pin description Pin description (continued)
Pin VPOS CVCC AGND RLIM IREF RTH RD ILTF CSVR BGND VBAT RING TIP CREV VBAT1 Positive supply input. Internal positive voltage supply filter. Analog Ground, must be shorted with BGND. Constant current feed programming pin (via RLIM). RLIM should be connected close to this pin and AGND pin to avoid noise injection. Internal bias current setting pin. RREF should be connected close to this pin and AGND pin to avoid noise injection. Off-hook threshold programming pin (via RTH). RTH should be connected close to this pin and AGND pin to avoid noise injection. DC feedback and ring trip input. RD should be connected close to this pin and AGND pin to avoid noise injection. Transversal line current image output. Batter y supply filter capacitor. Batter y Ground, must be shorted with AGND. Regulated battery voltage self generated by the device via DC/DC converter. Must be shorted to VBAT1. 2 wire port; RING wire (Ib is the current sunk into this pin). 2 wire port; TIP wire (Ia is the current sourced from this pin). Reverse polarity transition time control. A proper capacitor connected between this pin and AGND is setting the reverse polarity transition time. This is the same transition time used to shape the "trapezoidal ringing" during ringing injection. Frame connection. Must be shorted to VBAT. Function
1.4
Table 2.
Symbol Rth j-amb
Thermal data
Thermal data
Parameter Thermal Resistance Junction to Ambient Typ. Value 60 Unit C/W
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Electrical specification
STLC3085
2
2.1
Electrical specification
Absolute maximum ratings
Table 3.
Symbol Vpos A/BGND Vdig Tj Vbtot ESD RATING
Absolute maximum ratings
Parameter Positive Supply Voltage AGND to BGND Pin D0, D1, D2, DET Max. junction Temperature Vbtot=|Vpos|+|Vbat|. (Total voltage applied to the device supply pins). Human Body Model Charged Device Model Value -0.4 to +13 -1 to +1 -0.4 to 5.5 150 85 1750 500 Unit V V V C V V V
2.2
Operating range
Table 4.
Symbol Vpos A/BGND Vdig Top Vbat
(1)
Operating range
Parameter Positive Supply Voltage AGND to BGND Pin D0, D1, D2, DET, PD Ambient Operating Temperature Range Self Generated Battery Voltage Value 4.5 to +12 -100 to +100 -0.25 to 5.25 -40 to +85 -64 max. Unit V mV V C V
1. Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2. RF1 and RF2 shall be selected in order to fulfil the a.m limits (see Table 10)
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STLC3085
Electrical specification
2.3
Electrical characteristics
Test conditions: Vpos = 6.0V, AGND = BGND, Normal Polarity, Tamb = 25C. External components as listed in the "Typical values" column of EXTERNAL COMPONENTS tables (Table 10 and Table 11).
Note:
Testing of all parameter is performed at 25C. Characterization as well as design rules used allow correlation of tested performances at other temperatures. All parameters listed here are met in the operating range of -40C to +85C.
Electrical characteristics
Parameter Test Condition Min. Typ. Max. Unit
Table 5.
Symbol
DC characteristics Il = 0, HI-Z (High impedance feeding) Tamb = 0 to 85C Il = 0, HI-Z (High impedance feeding) Tamb = -40 to 85C Il = 0, ACTIVE Tamb = 0 to 85C Il = 0, ACTIVE Tamb = -40 to 85C ACTIVE mode ACTIVE mode. Rel. to programmed value 20mA to 25mA HI-Z (High Impedance feeding)
Vlohi
Line voltage
40
46
V
Vlohi
Line voltage
38
44
V
Vloa Vloa Ilim
Line voltage Line voltage Lim. current programming range Lim. current accuracy Feeding resistance
31 29 20
38 35 25
V V mA
Ilima Rfeed HI
-10 2.4
10 3.6
% k
AC characteristics Long. to transv. (see Appendix A) Transv. to long. (see Appendix A) Transv. to long. (see Appendix A) 2W return loss Rp = 50 1% tol., , ACTIVE N. P., RL = 600 (1) f = 300 to 3400Hz Rp = 50 1% tol., , ACTIVE N. P., RL = 600 (1) f = 300 to 3400Hz Rp = 50 1% tol., , ACTIVE N. P., RL = 600 (1) f = 1kHz 300 to 3400Hz, ACTIVE N. P., RL = 600 (1) 300 to 3400Hz, 20Log|VRX/VTX|, ACTIVE N. P., RL = 600 (1)
L/T
50
58
dB
T/L
40
45
dB
T/L
48
53
dB
2WRL
22
26
dB
THL
Trans-hybrid loss
30
dB
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Electrical specification Table 5.
Symbol Ovl TXoff G24 G42
STLC3085
Electrical characteristics (continued)
Parameter 2W overload level TX output offset Transmit gain abs. Receive gain abs. Test Condition at line terminals on ref. imped. ACTIVE N. P., RL = 600 (1) ACTIVE N. P., RL = 600 (1) 0dBm @ 1020Hz, ACTIVE N. P., RL = 600 (1) 0dBm @ 1020Hz, ACTIVE N. P., RL = 600 (1) rel. 1020Hz; 0dBm, 300 to 3400Hz, ACTIVE N. P., RL = 600 (1) rel. 1020Hz; 0dBm, 300 to 3400Hz, ACTIVE N. P., RL = 600 (1) Min. 3.2 -250 -6.4 -0.4 250 -5.6 0.4 Typ. Max. Unit dBm mV dB dB
G24f
TX gain variation vs. freq.
-0.12
0.12
dB
G24f
RX gain variation vs. freq.
-0.12
0.12
dB
V2Wp
psophometric filtered Idle channel noise at line ACTIVE N. P., RL = 600 (1) 0dB gainset Tamb = 0 to +85C psophometric filtered Idle channel noise at line ACTIVE N. P., RL = 600 (1) 0dB gainset Tamb = -40 to +85C psophometric filtered Idle channel noise at line ACTIVE N. P., RL = 600 (1) 0dB gainset Tamb = 0 to +85C psophometric filtered Idle channel noise at line ACTIVE N. P., RL = 600 (1) 0dB gainset Tamb = -40 to +85C Total Harmonic Distortion CLK operating range ACTIVE N. P., RL = 600 (1) -10%
-73
-6 8
dBmp
V2Wp
-68
dBmp
V4Wp
-75
-7 0
dBmp
V4Wp
-75
dBmp
Thd CLKfreq Ring
-44 125 10%
dB kHz
Vr ing
Line voltage
RING D2 toggling @ fr = 25Hz Load = 2REN; Crest Factor = 1.25 1REN = 1800 + 1.0F Tamb = 0 to +85C RING D2 toggling @ fr = 25Hz Load = 2REN; Crest Factor = 1.25 1REN = 1800 + 1.0F Tamb = -40 to +85C
41
45
Vrms
Vr ing
Line voltage
40
44
Vrms
8/28
STLC3085 Table 5.
Symbol Detectors IOFFTHA ROFTHA IONTHA RONTHA IOFFTHI ROFFTHI IONTHI RONTHI Ir t Ir ta Tr td Td Rlr t
(2)
Electrical specification Electrical characteristics (continued)
Parameter Test Condition Min. Typ. Max. Unit
Off/hook current threshold Off/hook loop resistance threshold On/hook current threshold On/hook loop resistance threshold Off/hook current threshold Off/hook loop resistance threshold On/hook current threshold On/hook loop resistance threshold Ring Trip detector threshold range Ring Trip detector threshold accuracy Ring trip detection time Dialling distortion Loop resistance Tj for th. alarm activation
ACT. mode, RTH = 32.4k 1% (Prog. ITH = 9mA) ACT. mode, RTH = 32.4k 1% (Prog. ITH = 9mA) ACT. mode, RTH = 32.4k 1% (Prog. ITH = 9mA) ACT. mode, RTH = 32.4k 1% (Prog. ITH = 9mA) Hi Z mode, RTH = 32.4k 1% (Prog. ITH = 9mA) Hi Z mode, RTH = 32.4k 1% (Prog. ITH = 9mA) Hi Z mode, RTH = 32.4k 1% (Prog. ITH = 9mA) Hi Z mode, RTH = 32.4k 1% (Prog. ITH = 9mA) RING RING RING ACTIVE
10.5 3.4 6 8 10.5 800 6 8 20 -15 TBD -1 1 500 160 50 15
mA k mA k mA mA k mA % ms ms C
ThAl
DIgital Interface Inputs: D0, D1, D2, PD, CLK Outputs: DET Vih Vil Iih Iil Vol In put high voltage Input low voltage Input high current Input low current Output low voltage Iol = 1mA -10 -10 2 0 .8 10 10 0.45 V V A A V
9/28
Electrical specification Table 5.
Symbol
STLC3085
Electrical characteristics (continued)
Parameter Test Condition Min. Typ. Max. Unit
PSRR and power consumption PSERRC Power supply rejection Vpos to 2W port Vpos supply current @ II = 0 Peak current limiting accuracy Vripple = 100mVrms 50 to 4000Hz HI-Z On-Hook ACTIVE On-Hook, RING (line open) RING Off-Hook RSENSE = 130m -20% 26 36 13 50 55 770 25 80 90 +20% dB mA mA mA mApk
Ivpos
Ipk (3)
1. RL: Line Resistance 2. Rlrt = Maximum loop resistance (including telephone) for correct ring trip detection. 3. Buck Boost configuration.
10/28
STLC3085
Functional description
3
Functional description
The STLC3085 is a device specifically developed for WLL VoIP and ISDN-TA applications. It is based on a SLIC core, on purpose optimized for these applications, with the addition of a DC/DC converter controller to fulfil the WLL and ISDN-TA design requirements. The SLIC performs the standard feeding, signalling and transmitting functions. It can be set in three different operating modes via the D0, D1, D2 pins of the control logic interface (0 to 3.3V logic levels). The loop status is carried out on the DET pin (active low). The DET pin is an open drain output to allow easy interfacing with both 3.3V and 5V logic levels. The four possible SLIC's operating modes are:
Power down High-impedance feeding (HI-Z) Active Ringing
Table 6 shows the settings of the different SLIC operating modes.
Table 6.
PD 0 1 1 1
SLIC operating modes
D0 0 0 0 0 D1 0 0 1 1 D2 X X 0 1 Power down High impedance feeding (HI-Z) Active normal polarity Active reverse polarity Not used Not used Operating mode
1
1
0
0/1
Ring (D2 bit toggles @ fring)
3.1
DC/DC converter
The DC/DC converter controller drives an external power MOS transistor N-Ch plus transformer (Flyback configuration) or P-Ch plus inductor (BuckBoost configuration), in order to generate the negative battery voltage required for the device operation. The DC/DC converter controller is synchronized with an external CLK (125 kHz typ.) or with an internal clock generated when the pin CLK is connected to CVCC. One Rsense in series to PGND supply (FlyBack) or to Vpos supply (BuckBoost) allows to fix the maximum allowed input peak current. This feature is implemented in order to avoid an overload on Vpos supply in case of line transient (ex. ring trip detection). The 130m typical value guarantees an average current consumption from Vpos < 600mA for BuckBoost configuration and < 1.25A for Fly- Back configuration.
11/28
Functional description
STLC3085
The 220 m typical value guarantees an average current consumption from Vpos < 800mA for Fly-Back configuration. The self generated battery voltage is set to a predefined value in on-hook state. This value can be adjusted via one external resistor (RF1) and it is typically -46V. When RING mode is selected this value is increased to -64V typ. Once the line goes in off-hook condition, the DC/DC converter automatically adjusts the generated battery voltage in order to feed the line with a fixed DC current (programmable via RLIM) optimizing the power dissipation.
3.2
3.2.1
Operating modes
Power down
When this mode is selected the SLIC is switched off and the TIP and RING pins are in high impedance. Also the line detectors are disabled therefore the off-hook condition cannot be detected. This mode can be selected in emergency condition when it is necessary to cut any current delivered to the line. This mode is also forced by STLC3085 in case of thermal overload (Tj > 140C). In this case the device goes back to the previous status as soon as the junction temperature decreases under the hysteresis threshold. No AC transmission is possible.
3.2.2
High impedance feeding (HI-Z)
This operating mode is normally selected when the telephone is on-hook in order to monitor the line status keeping the power consumption at the minimum. The output voltage in on-hook condition is equal to the self generated battery voltage (-46V typ). When off-hook occurs the DET becomes active (low logic level). The off-hook threshold value in HI-Z mode is the same as the programmed value in ACTIVE mode. The DC characteristic in HI-Z mode is equal to the self generated battery with 2x(1600+Rp) in series (see Figure 3), where Rp is the external protection resistance. No AC transmission is possible. Figure 3. DC Characteristic in HI-Z mode.
IL Vbat 2x(R1+Rp)
Slope: 2x(R1+Rp) (R1=1500ohm)
VL Vbat (-46V)
12/28
STLC3085
Functional description
3.2.3
Active
DC characteristics & supervision
When this mode is selected the STLC3085 provides both DC feeding and AC transmission. The STLC3085 feeds the line with a constant current fixed by RLIM (20mA to 25mA range). The on-hook voltage is typically 38V allowing on-hook transmission; the self generated Vbat is -46V typ. If the loop resistance is very high and the line current cannot reach the programmed constant current feed value, the STLC3085 behaves like a 38V voltage source with a series impedance equal to the protection resistors 2xRp (typ. 2x50). Figure 4 shows the typical DC characteristic in ACTIVE mode. The line status (on/off hook) is monitored by the SLIC'S supervision circuit. The off-hook threshold can be programmed via the external resistor RTH in the range from 5mA to 9mA. Independently on the programmed constant current value, the TIP and RING buffers have a current source capability limited to 65mA typ. Figure 4. DC characteristic in ACTIVE mode
IL Ilim (20 to 25mA)
2Rp
10V
VL
Vbat (-46V)
Moreover the power available at Vbat is controlled by the DC/DC converter that limits the peak current drawn from the Vpos supply. The maximum allowed current peak is set by RSENSE resistor.
AC characteristics
The SLIC provides the standard SLIC transmission functions. Once in active mode the SLIC can operate with two different Tx, Rx gains properly set by the Gain set control bit (see Table 7). Table 7. Gain set in active mode
4 to 2 wire gain 0dB +6dB 2 to 4 wire gain -6dB -12dB Impedance synthesis scale factor x 50 x 25
Gain set 0 1
13/28
Functional description
STLC3085
Input impedance synthesis: can be real or complex and is set by a scaled (x50 or x25) external ZAC impedance. Transmit and receive: The AC signal present on the 2W port (TIP/RING) is transferred to the TX output with a -6dB or -12dB gain and from the RX input to the 2W port with a 0dB or +6dB gain. 2 to 4 wire conversion: The balance impedance can be real or complex, the proper cancellation is obtained by means of two external impedance ZA and ZB.
Once in Active mode (D1=1) the SLIC can operate in different states setting properly D0 and D2 control bits (see also Table 8). Table 8.
D0 0 0
SLIC states in ACTIVE mode
D1 1 1 D2 0 1 Active normal polarity Active reverse polarity Operating mode
Polarity reversal
The D2 bit controls the line polarity, the transition between the two polarities is performed in a "soft" way. This means that the TIP and RING wires exchange their polarities following a ramp transition (see Figure 5). The transition time is controlled by an external capacitor CREV. This capacitor also sets the shape of the ringing trapezoidal waveform. When the control pins set battery reversal the line polarity is reversed with a proper transition time set via an external capacitor (CREV). Figure 5. TIP/RING typical transition from direct to reverse polarity
GND T IP
4V typ.
38 V typ ON-HOOK
dV/dT set by CREV RING
3.2.4
Ringing
When this mode is selected the STLC3085 self generates an higher negative battery (-64V typ.) in order to allow a balanced ringing signal of typically 59Vpeak. In this condition both the DC and AC feedback loops are disabled and the SLIC line drivers operate as voltage buffers. The ring waveform is obtained toggling the D2 control bit at the desired ring frequency. This bit in fact controls the line polarity (0=direct; 1= reverse). As in the ACTIVE mode the line voltage transition is performed with a ramp transition, creating a trapezoidal balanced ring waveform (see Figure 6). The shaping is defined by the CREV external capacitor.
14/28
STLC3085 Figure 6. TIP/RING typical ringing waveform
GND TIP
2.5V typ.
Functional description
59V typ.
dV/dT set by CREV RING VBAT
2.5V typ.
Selecting the proper capacitor value permits to obtain different crest factor values. The following table shows the crest factor values obtained with a 20Hz and 25Hz ring frequency and with 1REN. These value are valid either with European or USA specifications. Table 9. Crest factors
CREV 22nF 27nF 33nF
1. Distortion already less than 10%.
CREST factor @20Hz 1.2 1.25 1.33
CREST factor @25Hz 1.26 1.32 Not significant (1)
The ring trip detection is performed by sensing the variation of the AC line impedance from on-hook (relatively high) to off-hook (low). This particular ring trip method allows to operate without DC offset superimposed on the ring signal. Therefore, the maximum possible ring level on the load is obtained, starting from a given negative battery. It should be noted that such a method is optimized for operation on short loop applications and may not operate properly in the presence of long loop applications (> 500). Once ring trip is detected, the DET output is activated (logic level low), at this point the card controller or a simple logic circuit should stop the D2 toggling in order to effectively disconnect the ring signal and then set the STLC3085 in the proper operating mode (normally ACTIVE).
Ring level in presence of more telephone in parallel
As already mentioned above the maximum current that can be drawn from the Vpos supply is controlled and limited via the external RSENSE. This also limits the power available at the self generated negative battery. If for any reason the ringer load is too low the self generated battery drops in order to keep the power consumption to the fixed limt. Consequently the ring voltage level is reduced. In the typical Buck Boost configuration with RSENSE = 130m the peak current from Vpos is limited to about 770mA, which corresponds to an average current of 600mA max. In this condition the STLC3085 can drive up to 2REN with a ring frequency fr=25Hz (1REN = 1800 + 1.0F, European standard). In Fly-Back configuration the value of RSENSE = 220m matches both European and USA standards.
15/28
Functional description
STLC3085
3.2.5
Layout recommendation
A properly designed PCB layout is a basic issue to guarantee a correct behavior and good noise performances. Par ticular care must be taken on the ground connection and in this case the star configuration allows surely to avoid possible problems (see Application Diagram Figure 7 and Figure 8). The ground of the power supply (Vpos) has to be connected to the center of the star named SYSTEM-GND in this document. This point should show the lowest possible resistance, that means it should be a ground plane. In particular to avoid noise problems the layout should prevent any coupling between the DC/DC converter components and analog pins that are referred to AGND (ex: RD, IREF, RTH, RLIM, VF). As a first recommendation the components CV, L, T1, D1, CVPOS, RSENSE should be kept as close as possible to each other and isolated from the other components. Additional improvements can be obtained:
by decoupling the center of the star from the analog ground of STLC3085 using small chokes, by adding a capacitor in the range of 100nF between Vpos and AGND in order to filter the switch frequency on Vpos.
3.2.6
External components list
In order to properly define the external components value the following system parameters have to be defined:
the AC input impedance shown by the SLIC at the line terminals "Zs" to which the return loss measurement is referred. It can be real (typ. 600) or complex. the AC balance impedance, it is the equivalent impedance of the line "Zl" used for evaluation of the trans-hybrid loss performances (2/4 wire conversion). It is usually a complex impedance. the value of the two protection resistors Rp in series with the line termination the slope of the ringing waveform "VTR/T " the value of the constant current limit current "Ilim" the value of the off-hook current threshold "ITH" the value of the ring trip rectified average threshold current "IRTH" the value of the required self generated negative battery "VBATR" in ring mode (max value is 64V). This value can be obtained from the desired ring peak level + 5V. the value of the maximum current peak drawn from Vpos "IPK".
Table 10.
Name RRX RREF CSVR
External components for buckboost configuration
Function Rx input bias resistor Bias setting current Negative battery filter RREF = 1.3/Ibias Ibias = 50A CSVR = 1/(2 fp 1.8M) fp = 50Hz Formula Typ. value 100k 5% 26k 1% 1.5nF 10% 100V
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STLC3085 Table 10.
Name RD CAC RP RLIM RTH CREV RDD CVCC
Functional description External components for buckboost configuration
Function Formula RD = 100/IRTH 2K < RD < 5K Typ. value 4.12k 1% @ IRTH = 24mA 22F 20% 15V @ RD = 4.12k Rp > 30 RLIM = 1300/Ilim 32.5k < RLIM < 65k 50 1% 52.3k 1% @ Ilim = 25mA 32.4k 1% @ITH = 9mA 22nF 10% 10V @ 12V/ms 100k 100nF 20% 10V 100F
Ring trip threshold setting resistor AC/DC split capacitance Line protection resistor Current limiting programming
Off-hook threshold programming RTH = 290/ITH (ACTIVE mode) 27k < RTH < 52k Reverse polarity transition time programming Pull up resistors Internally supply filter capacitor CREV = ((1/3750) · T/VTR)
Positive supply filter capacitor CVpos(1) with low impedance for switch mode power supply CV(2) CVB CRD
(3 )
Battery supply filter capacitor with low impedance for switch mode power supply High frequency noise filter High frequency noise filter DC/DC converter switch P ch. MOS transistor RDS(ON) .2,VDS = -100V 1 Total gate charge=20nC max. with VGS=4.5V and VDS=1V ID>500mA Vr > 100V, tRR 50ns RSENSE = 100mV/IPK 250K
100F 20% 100V 470nF 20% 100V 100nF 10% 15V Possible choices: IRF9510 or IRF9520 or IRF9120 or equivalent SMBYW01-200 or equivalent 130m @IPK = 770mA 270k 1% @ VBATR = -64V 9.1k 1% DC resistance 0.1 L=100H SUMIDA CDRH125 or equivalent
Q1
D1 RSENSE RF1 RF2 L(4)
DC/DC converter series diode DC/DC converter peak current limiting Negative battery programming level Negative battery programming level DC/DC converter inductor
1. CVpos should be defined depending on the power supply current capability and maximum allowable ripple. 2. For low ripple application use 2x47 F in parallel. 3. Can be saved if proper PCB layout avoid noise coupling on RD pin (high impedance input). 4. For high efficiency in HI-Z mode coil resistance @125kHz must be < 3.
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Functional description Table 11.
Name RRX RREF CSVR RD CAC RP RLIM RTH CREV RDD CVCC
STLC3085
External components for flyback configuration
Function Rx input bias resistor Bias setting current Negative Battery Filter Ring Trip threshold setting resistor AC/DC split capacitance Line protection resistor Current limiting programming Rp > 30 RLIM = 1300/Ilim 52.3k < RLIM < 65k RREF = 1.3/Ibias; Ibias = 50A CSVR = 1/(2 fp 1.8M) fp = 50Hz RD = 100/IRTH 2K < RD < 5K Formula Typ. value 100k 5% 26k 1% 1.5nF 10% 100V 4.12k 1% @ IRTH = 24mA 22F 20% 15V @ RD = 4.12k 50 1% 52.3k 1% @ Ilim = 25mA 32.4k 1% @ITH = 9mA 22nF 10% 10V @ 12V/ms 100k 100nF 20% 10V 100F
Off-hook threshold programming RTH = 290/ITH (ACTIVE mode) 27k < RTH < 52k Reverse polarity transition time programming Pull up resistors Internally supply filter capacitor CREV = ((1/3750) · T/VTR)
Positive supply filter capacitor CVpos(1) with low impedance for switch mode power supply CV(2) CVB CRD
(3 )
Battery supply filter capacitor with low impedance for switch mode power supply High frequency noise filter High frequency noise filter Fly-Back compensation capacitor Sense Filter capacitor Sense Filter resistor DC/DC converter peak current limiting DC/DC converter switch N-channel MOS transistor RSENSE = 375mV/IPK RDS(ON) .05 VDSS = 30V 0 , VDG=30V, ID = 6.5A Low threshold drive Vr > 350V, tRR 80ns Fly-Back transformer 4W, Turns Ratio 1:16 fro Vpos range from 4.5V to 8.5V
100F 20% 100V 470nF 20% 100V 100nF 10% 15V 2.2nF, 20% 120pF, 20% 1k 220m @IPK = 1.7A STN4NF03L or equivalent SMBYTW01-400 or equivalent Tyco COEV MAGNETICS MGPWG-00007 or Coilcraft FA2469-AL
CZ CSF RSF RSENSE
Q1
D1
DC/DC converter series diode
T1
DC/DC Converter transformer
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STLC3085 Table 11.
Name
Functional description External components for flyback configuration (continued)
Function Formula Fly-Back transformer 4W, Turns Ratio 1:8 fro Vpos range from 8.5V to 12V 250K
T1
DC/DC Converter transformer Negative battery programming level Negative battery programming level
RF1 RF2
Table 12.
Name
Gain set for flyback and buckboost configurations
Function Formula Typ. value
@Gain Set = 0
RS ZAC ZA(1) ZB(5) Protection resistance image Two wire AC impedance SLIC impedance balancing network Line impedance balancing network RS = 50 (2Rp) ZAC = 50 (Zs - 2Rp) ZA = 50 Zs ZB = 50 Zl fo = 250kHz CCOMP = 1/(2 fo 100 (RP)) CH = CCOMP 5k @ Rp = 50 25k 1% @ Zs = 600 30k 1% @ Zs = 600 30k 1% @ Zl = 600
CCOMP AC feedback loop compensation CH Trans-Hybrid Loss frequency compensation
120pF 10% 10V @ Rp = 50 120pF 10% 10V
@Gain Set = 1
RS ZAC ZA(5) ZB(5) Protection resistance image Two wire AC impedance SLIC impedance balancing network Line impedance balancing network RS = 25 (2Rp) ZAC = 25 (Zs - 2Rp) ZA = 25 Zs ZB = 25 Zl fo = 250kHz CCOMP = 2/(2 fo 100 (RP)) CH = CCOMP 2.55k @ Rp = 50 12.5k 1% @ Zs = 600 15k 1% @ Zs = 600 15k 1% @ ZI = 600 220pF 10% 10VL @ Rp = 50 220pF 10% 10V
CCOMP AC feedback loop compensation CH Trans-Hybrid Loss frequency compensation
1. In case Zs = Zl, ZA and ZB can be replaced by two resistors of same value: RA = RB = |Zs|.
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Applications diagram
STLC3085
4
Applications diagram
Figure 7. Application diagram with N-channel
RX RRX T1 RS RX RS ZAC CCO M P ZAC ZA ZB CH VDD RD D GAIN SET ZB VF CZ CZ RF2 VBAT CVB RF1 CV ZAC1 TX AGND BGND CVCC VPOS GATE R SF RSENSE CSF RSENSE D1 Q1 N - ch TX CVCC VPOS CVPOS
STLC3085
CONTROL INTERFACE DET D0 D1 D2 PD DET D0 D1 D2 PD 8R E S 9R E S 10 R E S 12RES 11RE S CAC ILTF RD
CLK RP TIP RP RING CS VR CREV
CLK TIP R I NG
CRE V RTH R L IM IREF RREF RLIM
CS VR
RTH
RD AGND BGND SYSTEM GND SUGGESTED GROUND LAY-OUT CAC
CRD
D 04TL 62 6
PG ND
Figure 8.
Application diagram with P-channel
VPOS CVPOS
CVCC RX RRX TX
RSENSE
RS
RX RS ZAC
TX
AGND BGND
CVCC
VPOS RSENSE GATE D1 VBAT CVB RF1 CV RF2 L Q1 P-ch
CCOMP ZAC ZA
ZAC1
ZB CH VDD RDD ZB
VF
CLK GAIN SET
CLK RP TIP RP RING
STLC3085
CONTROL INTERFACE DET D0 D1 D2 PD DET D0 D1 D2 PD 8RES 9RES 10RES 12RES 11RES CAC ILTF RD
TIP RING
CSVR CREV CREV RTH RLIM IREF RREF RLIM RTH CSVR
RD AGND BGND SYSTEM GND SUGGESTED GROUND LAY-OUT CAC
CRD
D01TL494A
PGND
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STLC3085
STLC3085 test circuits
Appendix A
STLC3085 test circuits
Referring to the application diagram shown in Figure 11 and using as external components the typical values specified in Table 10, the proper configuration for each measurement is detailed below. All measurements requiring DC current termination should be performed using "Wandel & Goltermann DC Loop Holding Circuit GH-1" or equivalent. Figure 9. 2W Return loss - 2WRL = 20Log(|Zref + Zs|/|Zref-Zs|) = 20Log(E/2Vs)
W&G GH1 Zref TIP 600ohm Vs 1Kohm E
100mA DC max Zin = 100K 200 to 6kHz
TX
100F
STLC3085 application circuit
1Kohm
100F RING RX
Figure 10. THL Trans Hybrid Loss - THL = 20Log|Vrx/Vtx|
W&G GH1 TIP 100F
100mA DC max Zin = 100K 200 to 6kHz
TX Vtx
600ohm
STLC30885 STLC 3 0 5 app cai i n applicattoon c rcui ciircuitt
100F RING RX Vrx
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STLC3085 test circuits Figure 11. G24 Transmit Gain - G24 = 20Log|2Vtx/E|
W&G GH1 TIP 100F
100mA DC max Zin = 100K 200 to 6kHz
STLC3085
TX V tx
600ohm
STLC3085 application circuit
E
100F RING RX
Figure 12. G42 Receive Gain - G42 = 20Log|VI/Vrx|
W&G GH1 TIP 100F Vl 600ohm
100mA DC max Zin = 100K 200 to 6kHz
TX
STLC3085 application circuit
100F RING RX Vrx
Figure 13. PSRRC Power supply rejection Vpos to 2W port - PSSRC = 20Log|Vn/Vl|
W&G GH1 TIP 100F Vl 600ohm
100mA DC max Zin = 100K 200 to 6kHz
TX
STLC3085 application circuit
100F RING VPOS RX
~
Vn
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STLC3085
STLC3085 test circuits Figure 14. L/T Longitudinal to Transversal Conversion - L/T = 20Log|Vcm/Vl|
W &G GH1 300ohm 100F TIP 100F
100mA DC max
TX
Impedance matching better than 0.1%
Vcm
Vl
Zin = 100K 200 to 6kHz
STLC3085 application circuit
100F RING RX
300ohm
100F
Figure 15. T/L Transversal to Longitudinal Conversion - T/L = 20Log|Vrx/Vcm|
W&G GH1 TIP 100F
100mA DC max Impedance matching better than 0.1% Zin = 100K 200 to 6kHz
300ohm
100F
TX
STLC3085 application circuit
600ohm
Vcm
100F RING RX Vrx
300ohm
100F
Figure 16. V2Wp and W4Wp: Idle channel psophometric noise at line and TX. V2Wp = 20Log|Vl/0.774l|; V4Wp = 20Log|Vtx/0.774l|
W&G GH1 TIP 100F
100mA DC max Zin = 100K 200 to 6kHz
TX V tx psophometric filtered
600ohm Vl psophometric filtered
STLC3085 application circuit
100F RING RX
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STLC3085 over voltage protection
STLC3085
Appendix B
STLC3085 over voltage protection
Figure 17. Simplified configuration for indoor over voltage protection
BGND
STPR120A
STLC3085N
TIP SM6T39A 2x RING RP1 RP1 RP2 RP2 TIP RING
VBAT STPR120A
RP1 = 30ohm: RP2 =Fuse or PTC > 20ohm
Figure 18. Standard over voltage protection configuration for K20 compliance
BGND
STLC3085N
T IP 2x SM6T39A RP1
LCP1521S
RP2
TIP
RING
RP1
RP2
RING
VBAT
RP1 = 30ohm: RP2 =Fuse or PTC > 20ohm
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STLC3085
Typical state diagram for STLC3085 operation
Appendix C
Typical state diagram for STLC3085 operation
Figure 19. Typical state diagram for STLC3085 operation
Normally used for On Hook Transmission PD=0, D0=D1=0 Active On Hook Ring Pause D0=0, D1=1, D2=0
Tj>Tth
Power Down
Ring Burst
Ring Burst D0=1, D1=0, D2=0/1 PD=1, D0=D1=0 On Hook Detection for T>Tref HI-Z Feeding Active Off Hook Off Hook Detection D0=0, D1=1, D2=0 Ring Trip Detection Ringing
On Hook Condition
Off Hook Detection
Note: all state transitions are under the microprocessor control.
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Package mechanical data
STLC3085
5
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 20. TQFP44 (10x10x1.4mm) mechanical data & package dimensions
mm DIM. MIN. A A1 A2 B C D D1 D3 E E1 E3 e L L1 k 0.45 11.80 9.80 0.05 1.35 0.30 0.09 11.80 9.80 12.00 10.00 8.00 12.00 10.00 8.00 0.80 0.60 1.00 0.75 0.018 12.20 10.20 0.464 0.386 1.40 0.37 TYP. MAX. 1.60 0.15 1.45 0.45 0.20 12.20 10.20 0.002 0.053 0.012 0.004 0.464 0.386 0.472 0.394 0.315 0.472 0.394 0.315 0.031 0.024 0.039 0.030 0.480 0.401 0.055 0.015 MIN. TYP. MAX. 0.063 0.006 0.057 0.018 0.008 0.480 0.401 inch
OUTLINE AND MECHANICAL DATA
TQFP44 (10 x 10 x 1.4mm)
0 (min.), 3.5(typ.), 7(max.)
D D1 A A2 A1
33 34 23 22
0.10mm .004 Seating Plane
E1
B
44 1 11
12
E
B C L K
e
TQFP4410
0076922 D
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STLC3085
Ordering information
6
Ordering information
Table 13. Order codes
Temp range, C -40 to 85 Package TQFP44 Packing Tube
Part number E-STLC3085 (1)(*)
1. ECOPACK (see Section 5)
7
Revision history
Table 14.
Date 15-Feb-2006
Document revision history
Revision 1 Initial release. Split table 10 into Table 10, Table 11 and Table 12. Added RRX in Table 10 and Table 11. Added `Coilcraft FA2470-AL' as typical value for T1 in Table 11 Added RRX resistor in Figure 7 and Figure 8. Replaced ii with II for Ivpos description in Table 5 Changes
17-Jan-2007
2
07-Feb-2007
3
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STLC3085
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