M41T93
Serial SPI bus RTC with battery switchover
Features
Ultra-low battery supply current of 365 nA Factor y calibrated accuracy 5 ppm guaranteed after 2 reflows (SOX18) Much better accuracies achievable using built-in programmable analog and digital calibration circuits 2.0 V to 5.5 V clock operating voltage Counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century Automatic switchover and reset output circuitry (fixed reference) M41T93S: VCC = 3.0 V to 5.5 V (2.85 V VRST 3.00 V) M41T93R: VCC = 2.7 V to 5.5 V (2.55 V VRST 2.70 V) M41T93Z: VCC = 2.38 V to 5.50 V (2.25 V VRST 2.38 V) Compatible with SPI bus serial interface (supports SPI mode 0 [CPOL = 0, CPHA = 0]) Programmable alarm with interrupt function (valid even during battery back-up mode) Optional 2nd programmable alarm available Square wave output (defaults to 32 kHz on power-up) RESET (RST) output Watchdog timer Programmable 8-bit counter/timer 7 bytes of battery-backed user SRAM Battery low flag Power-down time stamp (HT bit) Low operating current of 80 A Oscillator stop detection Battery or SuperCapTM backup Operating temperature of 40C to +85C
18 1
QFN16, 4 mm x 4 mm (QA)
SOX18 (MY, 18-pin, 300 mil SOIC with embedded crystal)
Package options include: a 16-lead QFN or an 18-lead embedded crystal SOIC RoHS compliance: lead-free components are compliant with the RoHS directive
August 2008
Rev 4
1/51
www.st.com 1
Contents
M41T93
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 SPI signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1.1 1.1.2 1.1.3 1.1.4 Serial data output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Serial data input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Serial clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chip enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 2.2 2.3 2.4 SPI bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Read and write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data retention and battery switchover (VSO = VRST) . . . . . . . . . . . . . . . . 15 Power-on reset (trec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 3.2 3.3 3.4 Power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Clock/control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Real-time clock accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.1 3.4.2 Digital calibration (periodic counter correction) . . . . . . . . . . . . . . . . . . . 20 Analog calibration (programmable load capacitance) . . . . . . . . . . . . . . 22
3.5 3.6 3.7 3.8
Setting the alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Optional second programmable alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8-bit (countdown) timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.8.1 3.8.2 3.8.3 3.8.4 3.8.5 TI/TP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 TF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 TIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 TD1/0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.9 3.10 3.11
Square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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M41T93
Contents
3.12 3.13 3.14 3.15 3.16
Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Oscillator fail detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Oscillator fail interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 OTP bit operation (SOX18 package only) . . . . . . . . . . . . . . . . . . . . . . . . 35
4 5 6 7 8 9
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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List of tables
M41T93
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Signal name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Clock/control register map (32 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Digital calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Analog calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Timer control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Interrupt operation (bit TI/TP = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Timer source clock frequency selection (244.1 s to 4.25 hrs). . . . . . . . . . . . . . . . . . . . . . 31 Timer countdown value register bits (addr 11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Century bits examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Initial power-on default values (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Initial power-up default values (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 QFN16 16-lead, quad, flat package, no lead, 4 x 4 mm body, mech. data . . . . . . . . . . . 45 SOX18 18-lead plastic SO, 300 mils, embedded crystal, pkg. mech. data . . . . . . . . . . . 47 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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M41T93
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 QFN16 (QA) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SOX18 (MY) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data and clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Internal load capacitance adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Clock accuracy vs. on-chip load capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Clock divider chain and calibration circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Crystal isolation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Backup mode alarm waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Measurement AC I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 ICC2 vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Input timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Output timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 QFN16 16-lead, quad, flat package, no lead, 4 x 4 mm body size, outline . . . . . . . . . . . 44 QFN16 16-lead, quad, flat, no lead, 4 x 4 mm, recommended footprint . . . . . . . . . . . . . 46 32 kHz crystal + QFN16 vs. VSOJ20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 SOX18 18-lead plastic small outline, 300 mils, embedded crystal . . . . . . . . . . . . . . . . . 47
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Description
M41T93
1
Description
The M41T93 is a low-power serial SPI bus real-time clock with a built-in 32.768 kHz oscillator (external crystal-controlled for the QFN16 package, and embedded crystal for the SOX18 package). Eight bytes of the register map (see Table 3 on page 18) are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. An additional 17 bytes of the register map provide status/control of the two alarms, watchdog, 8-bit counter, and square wave functions. An additional seven bytes are made available as user SRAM. Addresses and data are transferred serially via a serial SPI bus-compatible interface. The built-in address register is incremented automatically after each WRITE or READ data byte. The M41T93 has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power failure occurs. The energy needed to sustain the clock operations can be supplied by a small lithium button battery when a power failure occurs. Functions available to the user include a non-volatile, time-of-day clock/calendar, alarm interrupt, watchdog timer, programmable 8-bit counter, and square wave outputs. The eight clock address locations contain the century, year, month, date, day, hour, minute, second, and tenths/hundredths of a second in 24-hour BCD format. Corrections for 28, 29 (leap year), 30, and 31 day months are made automatically. The M41T93 is supplied in either a QFN16 or an SOX18 (MY), 300mil SOIC which includes an embedded 32 kHz crystal. The SOX18 package requires only a user-supplied battery to provide non-volatile operation.
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M41T93 Figure 1. Logic diagram
VBAT VCC XI(1) XO(1) SDI SCL SDO E
Description
SQW(2) IRQ/OUT/FT(3) RST(3)
VSS
AI11818
1. For QFN16 package only 2. Defaults to 32 kHz on power-up 3. Open drain
Table 1.
Signal name
Description 32 kHz oscillator input 32 kHz oscillator output Interrupt /frequency test/output driver (open drain) 32 kHz programmable square wave output Power-on reset output (open drain) Chip enable Serial data address input Serial data address output Serial clock input Battery supply voltage (Tie VBAT to VSS if no battery is connected.) Do not use Supply voltage Ground
Symbol XI(1) XO
(1)
IRQ/FT/OUT SQW
(2)
RST E SDI SDO SCL VBAT DU(3) VCC VSS
1. For QFN16 package only
2. Defaults to 32 kHz on power-up 3. Do not use (must be tied to VCC)
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Description Figure 2. QFN16 (QA) connections
XO XI VCC E
M41T93
16 RST (1) 1 2
15
14
13 12 11 SDO IRQ/FT/OUT SCL SDI (1)
NC NC SQW (2)
M41T93 3 4 5
VBAT
10 9 6
VSS
7
NC
8
NC
AI11819
1. Open drain output 2. Defaults to 32 kHz on power-up
Figure 3.
SOX18 (MY) connections
NC NF(1) (1) NF NC (2) RST (3) DU (4) SQW VBAT VSS 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 NC NF(1) (1) NF VCC E SDO IRQ/FT/OUT(2) SCL SDI
AI11820
M41T93
1. NF pins must be tied to VSS. Pins 2 and 3, and 16 and 17 are internally shorted together. 2. Open drain output 3. Do not use (must be tied to VCC) 4. Defaults to 32kHz on power-up
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M41T93 Figure 4. Block diagram
REAL TIME CLOCK CALENDAR OSCILLATOR FAIL CIRCUIT ALARM1 ALARM2 WATCHDOG SPI INTERFACE FT OUT TIE SQWE SQW OFIE A1IE
Description
XI CRYSTAL 32kHz OSCILLATOR XO
E SDI SCL SDO WRITE PROTECT VCC < VRST
(1) IRQ/FT/OUT
FREQUENCY TEST OUTPUT DRIVER 8-BIT COUNTER SQUARE WAVE 8 BITS OF OTP USER SRAM (7 Bytes)
INTERNAL POWER VCC
VBAT COMPARE trec TIMER
VRST/VSO(2)
RST(1)
AI11821
1. Open drain output 2. VRST = VSO = 2.93 V (S), 2.63 V (R), and 2.32 V (Z)
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Description Figure 5. Hardware hookup
VCC
M41T93
M41T93 VCC XI XO VBAT VSS (1) IRQ/FT/OUT (1) RST SCL SDO SDI E SQW
MCU (ST6, ST7, ST9, ST10, Others) VCC INT Reset Input SCL SDI SDO CS 32kHz CLKIN
AI11822
(2)
SPI Interface with (CPOL = 0, CPHA = 0)
1. Open drain output 2. CPOL (clock polarity) and CPHA (clock phase) are bits that may be set in the SPI control register of the MCU.
Table 2.
Function table
E H L
AI04630
Mode Disable reset WRITE
SCL Input disabled
SDI Input disabled Data bit latch
SDO High Z High Z
READ
L
AI04631
X
Next data bit shift(1)
1. SDO remains at High Z until eight bits of data are ready to be shifted out during a READ.
Figure 6.
Data and clock timing
CPOL
CPHA
0
0
C
SDI
MSB
LSB
SDO
MSB
LSB
AI04632
Note:
Suppor ts SPI mode 0 (CPOL = 0, CPHA = 0) only.
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M41T93
Description
1.1
1.1.1
SPI signal description
Serial data output (SDO)
The output pin is used to transfer data serially out of the memory. Data is shifted out on the falling edge of the serial clock.
1.1.2
Serial data input (SDI)
The input pin is used to transfer data serially into the device. Instructions, addresses, and the data to be written, are each received this way. Input is latched on the rising edge of the serial clock.
1.1.3
Serial clock (SCL)
The serial clock provides the timing for the serial interface (as shown in Figure 19 on page 41 and Figure 20 on page 41). The W/R bit, addresses, or data are latched, from the input pin, on the rising edge of the clock input. The output data on the SDO pin changes state after the falling edge of the clock input. The M41T93 can be driven by a microcontroller with its SPI peripheral running in only mode 0: (CPOL, CPHA) = (0,0). For this mode, input data (SDI) is latched in by the low-to-high transition of clock SCL, and output data (SDO) is shifted out on the high-to-low transition of SCL (see Table 2 on page 10 and Figure 6 on page 10).
1.1.4
Chip enable (E)
When E is high, the memory device is deselected, and the SDO output pin is held in its high impedance state. After power-on, a high-to-low transition on E is required prior to the start of any operation.
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Operation
M41T93
2
Operation
The M41T93 clock operates as a slave device on the SPI serial bus. Each memory device is accessed by a simple serial interface that is SPI bus-compatible. The bus signals are SCL, SDI, and SDO (see Table 1 on page 7 and Figure 5 on page 10). The device is selected when the chip enable input (E) is held low. All instructions, addresses and data are shifted serially in and out of the chip. The most significant bit is presented first, with the data input (SDI) sampled on the first rising edge of the clock (SCL) after the chip enable (E) goes low. The 32 bytes contained in the device can then be accessed sequentially in the following order:
1 2 3 4 5 6 7 8 9 10
Tenths/hundredths of a second register Seconds register Minutes register Centur y/hours register Day register Date register Month register Year register Digital calibration register Watchdog register
11-15 Alarm1 registers 16 17 18 19 20
Flags register Timer value register Timer control register Analog calibration register Square wave register
21-25 Alarm2 registers 26-32 User RAM
The M41T93 clock continually monitors VCC for an out-of tolerance condition. Should VCC fall below VRST, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from a an out-of-tolerance system. The power input will also be switched from the VCC pin to the external battery when VCC falls below the battery back-up switchover voltage (VSO = VRST). At this time the clock registers will be maintained by the battery supply. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min) plus tREC (min). For more information on battery storage life refer to application note AN1012.
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M41T93
Operation
2.1
SPI bus characteristics
The serial peripheral interface (SPI) bus is intended for synchronous communication between different ICs. It consists of four signal lines: serial data input (SDI), serial data output (SDO), serial clock (SCL) and a chip enable (E). By definition a device that gives out a message is called "transmitter," the receiving device that gets the message is called "receiver." The device that controls the message is called "master." The devices that are controlled by the master are called "slaves." The E input is used to initiate and terminate a data transfer. The SCL input is used to synchronize data transfer between the master (micro) and the slave (M41T93) device. The SCL input, which is generated by the microcontroller, is active only during address and data transfer to any device on the SPI bus (see Figure 5 on page 10). The M41T93 can be driven by a microcontroller with its SPI peripheral running in only mode 0: (CPOL, CPHA) = (0,0). For this mode, input data (SDI) is latched in by the low-to-high transition of clock SCL, and output data (SDO) is shifted out on the high-to-low transition of SCL (see Table 2 and Figure 6 on page 10). There is one clock for each bit transferred. Address and data bits are transferred in groups of eight bits. Due to memory size the second most significant address bit is a "don't care" (address bit 6).
2.2
Read and write cycles
Address and data are shifted MSB first into the serial data input (SDI) and out of the serial data output (SDO). Any data transfer considers the first bit to define whether a READ or WRITE will occur. This is followed by seven bits defining the address to be read or written. Data is transferred out of the SDO for a READ operation and into the SDI for a WRITE operation. The address is always the second through the eighth bit written after the enable (E) pin goes low. If the first bit is a '1,' one or more WRITE cycles will occur. If the first bit is a '0,' one or more READ cycles will occur (see Figure 7 and Figure 8 on page 14). Data transfers can occur one byte at a time or in multiple byte burst mode, during which the address pointer will be automatically incremented. For a single byte transfer, one byte is read or written and then E is driven high. For a multiple byte transfer all that is required is that E continue to remain low. Under this condition, the address pointer will continue to increment as stated previously. Incrementing will continue until the device is deselected by taking E high. The address will wrap to 00h after incrementing to 3Fh. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). Although the clock continues to maintain the correct time, this will prevent updates of time and date during either a READ or WRITE of these address locations by the user. The update will resume either due to a deselect condition or when the pointer increments to an non-clock or RAM address (08h to 1Fh).
Note:
This is true both in READ and WRITE mode.
13/51
Operation Figure 7.
E 0 SCL W/R BIT 7 BIT ADDRESS 1 2 3 4 5 6 7 8 9 12 13 14 15 16 17 22
M41T93 Read mode sequence
SDI
7 MSB
6
5
4
3
2
1
0 DATA OUT (BYTE 1) 7 MSB 6 5 4 3 2 1 0 7 MSB
AI04635
DATA OUT (BYTE 2) 6 5 4 3 2 1 0
SDO
HIGH IMPEDANCE
Figure 8.
E
Write mode sequence
0 SCL
1
2
3
4
5
6
7
8
9
10
15
W/R BIT
7 BIT ADDR
DATA BYTE
SDI
7 MSB
6
5
4
3
2
1
0
7 MSB
6
5
4
3
2
1
0
7
SDO HIGH IMPEDANCE
AI04636
14/51
M41T93
Operation
2.3
Data retention and battery switchover (VSO = VRST)
Once VCC falls below the switchover voltage (VSO = VRST), the device automatically switches over to the battery and powers down into an ultra low current mode of operation to preserve battery life. If VBAT is less than, or greater than VRST, the device power is switched from VCC to VBAT when VCC drops below VRST (see Figure 18 on page 40). At this time the clock registers and user RAM will be maintained by the attached battery supply. When it is powered back up, the device switches back from battery to VCC at VSO + hysteresis. When VCC rises above VRST, it will recognize the inputs. For more information on battery storage life refer to application note AN1012.
2.4
Power-on reset (trec)
The M41T93 continuously monitors VCC. When VCC falls to the power fail detect trip point, the RST output pulls low (open drain) and remains low after power-up for trec (210ms typical) after VCC rises above VRST (max).
Note:
The trec period does not affect the RTC operation. Write protect only occurs when VCC is below VRST. When VCC rises above VRST, the RTC will be selectable immediately. Only the RST output is affected by the trec period. The RST pin is an open drain output and an appropriate pull-up resistor to VCC should be chosen to control the rise time.
15/51
Clock operation
M41T93
3
Clock operation
The M41T93 is driven by a quartz-controlled oscillator with a nominal frequency of 32.768 kHz. The accuracy of the real-time clock depends on the frequency of the quartz crystal that is used as the time-base for the RTC. The 8-byte clock register (see Table 3 on page 18) is used to both set the clock and to read the date and time from the clock, in binary coded decimal format. Tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers. Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. When reset to a '0' the oscillator restarts within one second (typical).
Note:
Upon initial power-up, the user should set the ST bit to a '1,' then immediately reset the ST bit to '0.' This provides an additional "kick-start" to the oscillator circuit. Bits D6 and D7 of clock register 03h (century/ hours register) contain the CENTURY bit 0 (CB0) and CENTURY bit 1 (CB1). Bits D0 through D2 of register 04h contain the day (day of week). Registers 05h, 06h, and 07h contain the date (day of month), month, and years. The ninth clock register is the digital calibration register, while the analog calibration register is found at address 12h (these are both described in the clock calibration section). Bit D7 of register 09h (watchdog register) contains the oscillator fail interrupt enable bit (OFIE). When the user sets this bit to '1,' any condition which sets the oscillator fail bit (OF) (see Oscillator fail detection on page 34) will also generate an interrupt output.
Note:
A WRITE to ANY location within the first eight bytes of the clock register (00h-07h), including the ST bit and CB0-CB1 bits will result in an update of the system clock and a reset of the divider chain. This could result in an inadvertent change of the current time. These non-clock related bits should be written prior to setting the clock, and remain unchanged until such time as a new clock time is also written. The eight clock registers may be read one byte at a time, or in a sequential block. Provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of data during the READ.
3.1
Power-down time-stamp
When a power failure occurs, the halt update bit (HT) will automatically be set to a "1". This will prevent the clock from updating the clock/control registers, and will allow the user to read the exact time of the power-down event. Resetting the HT bit to a "0" will allow the clock to update the clock/registers with the current time. For more information, see application note AN1572.
3.2
Clock/control register map
The M41T93 offers 32 internal registers which contain clock, calibration (digital and analog), alarm 1 and 2, watchdog, flags, timer, and square wave. The clock registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORTTM TIMEKEEPER cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. The internal divider (or clock) chain will be reset upon the
16/51
M41T93
Clock operation completion of a WRITE to any clock address (00h to 07h). The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume either due to a stop condition or when the pointer increments to a non-clock address. Clock and alarm registers store data in BCD format. Calibration, timer, watchdog, and square wave bits are written in a binary format.
17/51
Clock operation Table 3.
Addr D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h1Fh ST 0 CB1 0 0 0 OUT OFIE A1IE RPT14 RPT13 RPT12 RPT11 WDF TE ACS RS3 0 RPT24 RPT23 RPT22 RPT21 D6 D5 D4 D3 D2 D1 D0 0.1 seconds 0.01 seconds 10 seconds Seconds 10 minutes Minutes CB0 10 hours Hours (24-hour format) 0 0 0 0 Day of week 0 10 date Date: day of month 0 0 10M Month 10 Years Year FT DCS DC4 DC3 DC2 DC1 DC0 BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 SQWE ABE Al1 10M Alarm1month RPT15 AI1 10 date Alarm1 date HT AI1 10 hour Alarm1 hour Alarm1 10 minutes Alarm1 minutes Alarm1 10 seconds Alarm1 seconds BL TF OF 0 0 AF1 AF2(1) Timer countdown value TIE 0 0 0 TD1 TD0 TI/TP AC6 AC5 AC4 AC3 0 AC2 AC1 AC0 OTP
M41T93
Clock/control register map (32 bytes)
Function/range BCD format Seconds 00-99 Seconds 00-59 Minutes 00-59 Century/hours 0-3/00-23 Day 01-7 Date 01-31 Month 01-12 Year 00-99 Digital calibration Watchdog Al1 month 01-12 Al1 date 01-31 Al1 hour 00-23 Al1 min 00-59 Al1 sec 00-59 Flags Timer value Timer control Analog calibration SQW SRAM/Al2 month 01-12 SRAM/Al2 date 01-31 SRAM/Al2 hour 00-23 SRAM/Al2 min 00-59 SRAM/Al2 sec 00-59 SRAM
RS2 RS1 RS0 0 0 Al2 10M RPT25 AI2 10 date 0 AI2 10 hour Alarm2 10 minutes Alarm2 10 seconds
0 AL2E Alarm2 month Alarm2 month Alarm2 date Alarm2 minutes Alarm2 seconds
User SRAM (7 bytes)
1. AF2 will always read `0' if the AL2E bit is set to `0'.
0 = Must be set to zero ABE = Alarm in battery backup enable bit A1IE = Alarm1 interrupt enable bit AC0-AC6 = analog calibration bits ACS = analog calibration sign bit AF1, AF2 = Alarm flag AL2E = Alarm 2 enable bit BL = Battery low bit BMB0-BMB4 = Watchdog multiplier bits CB0, CB1 = Century bits DC0-DC4 = Digital calibration bits DCS = Digital calibration sign bit FT = Frequency test bit HT = Halt update bit OF = Oscillator fail bit OUT= Output level
OFIE = Oscillator fail interrupt enable OTP = OTP control bit RB0-RB2 = Watchdog resolution bits RPT11-RPT15 = Alarm 1 repeat mode bits RPT21-RPT25 = Alarm 2 repeat mode bits RS0-RS3 = SQW frequency SQWE = Square wave enable SRAM/ALM2 = SRAM/Alarm 2 bit ST = Stop bit TD0, TD1 = Timer frequency bits TE = Timer enable bit TF = Timer flag TI/TP = Timer interrupt or pulse TIE = Timer interrupt enable WDF = Watchdog flag
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M41T93
Clock operation
3.3
Real-time clock accuracy
The M41T93 is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The accuracy of the real-time clock is dependent upon the accuracy of the crystal, and the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Temperature also affects the crystal frequency, causing additional error (see Figure 10 on page 23). The M41T93 provides the option of clock correction through either manufacturing calibration or in-application calibration. The total possible compensation is typically 93 ppm to +156 ppm. The two compensation circuits that are available are: 1. An analog calibration register (12h) can be used to adjust internal (on-chip) load capacitors for oscillator capacitance trimming. The individual load capacitors CXI and CXO (see Figure 9), are selectable from a range of 18 pF to +9.75 pF in steps of 0.25pF. This translates to a calculated compensation of approximately 30 ppm (see Analog calibration (programmable load capacitance) on page 22). A digital calibration register (08h) can also be used to adjust the clock counter by adding or subtracting a pulse at the 512 Hz divider stage. This approach provides periodic compensation of approximately 63 ppm to +126 ppm (see Digital calibration (periodic counter correction) on page 20). Internal load capacitance adjustment
2.
Figure 9.
XI CXI Crystal Oscillator XO CXO
AI11804
19/51
Clock operation
M41T93
3.4
Clock calibration
The M41T93 oscillator is designed for use with a 12.5 pF crystal load capacitance. When the calibration circuit is properly employed, accuracy improves to better than 1 ppm at 25C. The M41T93 design provides the following two methods for clock error correction.
3.4.1
Digital calibration (periodic counter correction)
This method employs the use of periodic counter correction by adjusting the ratio of the 100 Hz divider stage to the 512 Hz divider stage. Under normal operation, the 100Hz divider stage outputs precisely 100 pulses for every 512 pulses of the 512 Hz input stage to provide the input frequency to the fraction of seconds clock register. By adjusting the number of 512 Hz input pulses used to generate 100 output pulses, the clock can be sped up or slowed down, as shown in Figure 12 on page 26. When a non-zero value is loaded into the five calibration bits (DC4 DC0) found in the digital calibration register (08h) and the sign bit is `1,' (indicating positive calibration), the 100 Hz stage outputs 100 pulses for every 511 input pulses instead of the normal 512. Since the 100 pulses are now being output in a shorter window, this has the effect of speeding up the clock by 1/512 seconds for each second the circuit is active. Similarly, when the sign bit is `0,' indicating negative calibration, the block outputs 100 pulses for every 513 input pulses. Since the 100 pulses are then being output in a longer window, this has the effect of slowing down the clock by 1/512 seconds for each second the circuit is active. The amount of calibration is controlled by using the value in the calibration register (N) to generate the adjustment in one second increments. This is done for the first N seconds once every eight minutes for positive calibration, and for N seconds once every sixteen minutes for negative calibration (see Table 4 on page 21). For example, if the calibration register is set to '100010,' then the adjustment will occur for two seconds in every minute. Similarly, if the calibration register is set to '000011,' then the adjustment will occur for 3 seconds in every alternating minute. The digital calibration bits (DC4 DC0) occupy the five lower order bits in the digital calibration register (08h). These bits can be set to represent any value between 0 and 31 in binary form. The sixth bit (DCS) is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within an 8-minute (positive) or 16-minute (negative) cycle. Therefore, each calibration step has an effect on clock accuracy of +4.068 or 2.034 ppm. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or 5.35 seconds per month, which corresponds to a total range of +5.5 or 2.75 minutes per month.
Note:
1
The modified pulses are not observable on the frequency test (FT) output, nor will the effect of the calibration be measurable real-time, due to the periodic nature of the error compensation. Positive digital calibration is performed on an eight minute cycle, therefore the value in the calibration register should not be modified more frequently than once every eight minutes for positive values of calibration. Negative digital calibration is performed on a sixteen minute cycle, therefore negative values in the calibration register should not be modified more frequently than once every sixteen minutes.
2
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M41T93 Table 4. Digital calibration values
Clock operation
Calibration value (binary) DC4 DC0 0 (0 0 0) 1 (00001) 2 (00010) 3 (00011) 4 (00100) 5 (00101) 6 (00110) 7 (00111) 8 (01000) 9 (01001) 10 (01010) 11 (01011) 12 (01100) 13 (01101) 14 (01110) 15 (01111) 16 (10000) 17 (10001) 18 (10010) 19 (10011) 20 (10100) 21 (10101) 22 (10110) 23 (10111) 24 (11000) 25 (11001) 26 (11010) 27 (11011) 28 (11100) 29 (11101) 30 (11110) 31 (11111) N
Calibration value rounded to the nearest ppm Negative calibration (DCS = 0) Positive calibration (DCS = 1) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 N/491520 (per minute) 0 4 8 12 16 20 24 28 33 37 41 45 49 53 57 61 65 69 73 77 81 85 90 94 98 102 106 110 114 118 122 126 N/245760 (per minute)
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Clock operation
M41T93
3.4.2
Analog calibration (programmable load capacitance)
A second method of calibration employs the use of programmable internal load capacitors to adjust (or trim) the oscillator frequency. By design, the oscillator is intended to be 0 ppm crystal accuracy at room temperature (25C, see Figure 10 on page 23). For a 12.5 pF crystal, the default loading on each side of the crystal will be 25 pF. For incrementing or decrementing the calibration value, capacitance will be added or removed in increments of 0.25 pF to each side of the crystal. Internally, CLOAD of the oscillator is changed via two digitally controlled capacitors, CXI and CXO, connected from the XI and XO pins to ground (see Figure 9 on page 19). The effective on-chip series load capacitance, CLOAD, ranges from 3.5 pF to 17.4 pF, with a nominal value of 12.5 pF (AC0-AC6 = `0'). The effective series load capacitance (CLOAD) is the combination of CXI and CXO: CL O A D = 1 / ( 1 / CX I + 1 / CX O ) Seven analog calibration bits, AC0 to AC6, are provided in order to adjust the on-chip load capacitance value for frequency compensation of the RTC. Each bit has a different weight for capacitance adjustment. An analog calibration sign (ACS) bit determines if capacitance is added (ACS bit = `0,' negative calibration) or removed (ACS bit = `1,' positive calibration). The majority of the calibration adjustment is positive (i.e. to increase the oscillator frequency by removing capacitance) due to the typical characteristic of quartz crystals to slow down due to changes in temperature, but negative calibration is also available. Since the analog calibration register adjustment is essentially "pulling" the frequency of the oscillator, the resulting frequency changes will not be linear with incremental capacitance changes. The equations which govern this mechanism indicate that smaller capacitor values of analog calibration adjustment will provide larger increments. Thus, the larger values of analog calibration adjustment will produce smaller incremental frequency changes. These values typically vary from 6-10 ppm/bit at the low end to <1 ppm/bit at the highest capacitance settings. The range provided by the analog calibration register adjustment with a typical surface mount crystal is approximately 30 ppm around the AC6-AC0 = 0 default setting because of this property (see Table 5 on page 23).
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M41T93 Figure 10. Crystal accuracy across temperature
Frequency (ppm) 20 0 20 40 60 80 100 120 140 160 40 30 20 10 0 10 20 30 40 50 60 70 F = K x (T T )2 O F K = 0.036 ppm/C 0.006 ppm/C TO = 25C 5C
2 2
Clock operation
80
Temperature C
AI07888
Table 5.
Analog calibration values
Analog calibration value D7 ACS () 0 pF 3 pF 5 pF 7 pF 9.75 pF(2)
(3)
D6
D5
D4 AC4 (4 pF) 0 0 1 1 0 0
D3 AC3 (2 pF) 0 1 0 1 0 1
D2 AC2 ( 1pF) 0 1 1 1 1 0
D1 AC1
D0 AC0
CXI, CXO CLOAD(1)
Addr
AC5 AC6 (16 pF) (8 pF) 0 0 0 0 0 1 0 0 0 0 1 0
(0.5 pF) (0.25 pF) 0 0 0 0 1 0 0 0 0 0 1 0 25 pF 28 pF 30 pF 18 pF 34.75 pF 7 pF 12.5 pF 14 pF 15 pF 9 pF 17.4 pF 3.5 pF
x 0 0 1 0 1
12h
18 pF
1. CLOAD = 1/(1/CXI + 1/CXO) 2. Maximum negative calibration value 3. Maximum positive calibration value
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Clock operation The on-chip capacitance can be calculated as follows: C L O A D = [ ( A C 6 A C 0 v a l ue, d e c i m a l) × 0.25 p F ] + 7 p F For example: CLOAD (12h = x0 0 000) = 12.5 pF CLOAD (12h =11001000) = 3.5 pF and CLOAD (12h = 00100111) = 17.4 pF
M41T93
The oscillator sees a minimum of 3.5 pF with no programmable load capacitance selected. Note: These are typical values, and the total load capacitance seen by the crystal will include approximately 1-2 pF of package and board capacitance in addition to the analog calibration register value. Any invalid value of analog calibration will result in the default capacitance of 25 pF. The combination of analog and digital trimming can give up to 93 to +156 ppm of the total adjustment. Figure 11 on page 25 represents a typical curve of clock ppm adjustment versus the Analog Calibration value. This curve may vary with different crystals, so it is good practice to evaluate the crystal to be used with an M41T93 device before establishing the adjustment values for the application in question.
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M41T93 Figure 11. Clock accuracy vs. on-chip load capacitors
Clock operation
100.0
XI XO Crystal Oscillator CXI CXO
80.0
PPM ADJUSTMENT
60.0 40.0
CLOAD =
20.0
FASTER DECREASING LOAD CAP.
CXI * CXO CXI + CXO
On-Chip
0.0
SLOWER
INCREASING LOAD CAP.
-20.0 OFFSET TO CXI, CXO (pF) NET EQUIV. LOAD CAP., C LOAD, (pF) Analog Calibr ation Value, AC, register 0x12 -18.0 -15.0 3.5 5.0 -10.0 7.5 0xA8 -5.0 10 0x94 0.0 12.5 0x00 5.0 15 0x14 9.75 17.4 0x27
0xC8 0xBC
ai13906
25/51
Clock operation
M41T93
Two methods are available for ascertaining how much calibration a given M41T93 may require:
The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses either or both of the calibration bytes. The second approach is better suited to a manufacturing environment, and involves the use of the IRQ/FT/OUT pin. The IRQ/FT/ OUT pin will toggle at 512 Hz when FT and OUT bits = '1' and ST = '0.' Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm oscillator frequency error, requiring either a 10 (xx001010) to be loaded into the digital calibration byte, or +6 pF (00011000) into the analog calibration byte for correction.
Note:
Setting or changing the digital calibration byte does not affect the frequency test, square wave, or watchdog timer frequency, but changing the analog calibration byte DOES affect all functions derived from the low current oscillator (see Figure 12).
Figure 12. Clock divider chain and calibration circuits
512Hz Output Frequency Test ÷2 CXI 32kHz Low Current Oscillator ÷8 CXO Digital Calibration Circuitry (divide by 511/512/513) 1Hz Signal Analog Calibration Circuitry Clock Registers ÷2 ÷2 ÷2 ÷2 Remainder of Divider Circuit Square Wave Watchdog Timer 8-Bit Timer
AI11806a
26/51
M41T93 Figure 13. Crystal isolation example
Crystal Local Grounding Plane (Layer 2)
Clock operation
XI XO
VSS
AI11814
Note:
The substrate pad should be tied to VSS.
3.5
Setting the alarm clock registers
Address locations 0Ah-0Eh (alarm 1) and 14h-18h (alarm 2) contain the alarm settings. Either alarm can be configured independently to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or second. Bits RPT15RPT11 and RPT25-RPT21 put the alarms in the repeat mode of operation. Table 6 on page 28 shows the possible bit configurations. Codes not listed in the table default to the once-per-second mode to quickly alert the user of an incorrect alarm setting. When the clock information matches the alarm clock settings based on the match criteria defined by RPT15RPT11 and/or RPT25-RPT21, AF1 (alarm 1 flag) or AF2 (alarm 2 flag) is set. If A1IE (alarm 1 interrupt enable) is set, the alarm condition activates the IRQ/FT/OUT output pin. To disable either of the alarms, write a '0' to the alarm date registers and to the RPTx5RPTx1 bits.
Note:
If the address pointer is allowed to increment to the flag register address, or the last address written is "Alarm Seconds," the address pointer will increment to the flag address, and an alarm condition will not cause the interrupt/flag to occur until the address pointer is moved to a different address. The IRQ output is cleared by a READ to the flags register (0Fh) as shown in Figure 14. A subsequent READ of the flags register is necessary to see that the value of the alarm flag has been reset to '0.'. The IRQ/FT/OUT pin can also be activated in the battery backup mode (see Figure 15 on page 28).
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Clock operation
M41T93
3.6
Optional second programmable alarm
When the alarm 2 enable (AL2E) bit (D1 of address 13h) is set to a logic `1,' registers 14h through 18h provide control for a second programmable alarm which operates in the same manner as the alarm function described above. The AL2E bit defaults on initial power-up to a logic `0' (alarm 2 disabled). In this mode, the five address bytes (14h-18h) function as additional user SRAM, for a total of 12 bytes of user SRAM. Figure 14. Alarm interrupt reset waveform
0Eh 0Fh 00h
ALARM FLAG BITS (AFx)
IRQ/FT/OUT
HIGH-Z
AI11823
Figure 15. Backup mode alarm waveform
VCC VPFD VSO trec AFx Bits in Flags Register
IRQ/FT/OUT HIGH-Z
AI11824
Note:
ABE and A1IE bits = 1. Table 6.
RPT5 1 1 1 1 1 0
Alarm repeat modes
RPT4 1 1 1 1 0 0 RPT3 1 1 1 0 0 0 RPT2 1 1 0 0 0 0 RPT1 1 0 0 0 0 0 Alarm setting Once per second Once per minute Once per hour Once per day Once per month Once per year
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M41T93
Clock operation
3.7
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (For example: writing 00001110 in the watchdog register = 3*1, or 3 seconds). If the processor does not reset the timer within the specified period, the M41T93 sets the WDF (watchdog flag) and generates a watchdog interrupt. The watchdog timer can be reset by having the microprocessor perform a WRITE of the watchdog register. The time-out period then starts over. Should the watchdog timer time-out, a value of 00h needs to be written to the watchdog register in order to clear the IRQ/FT/OUT pin. This will also disable the watchdog function until it is again programmed correctly. A READ of the flags register will reset the watchdog flag (bit D7; register 0Fh). The watchdog function is automatically disabled upon power-up and the watchdog register is cleared. If the watchdog function is set, the frequency test function is activated, and the SQWE bit is '0,' the watchdog function prevails and the frequency test function is denied.
3.8
8-bit (countdown) timer
The timer value register is an 8-bit binary countdown timer. It is enabled and disabled via the timer control register (11h) TE bit. Other timer properties such as the source clock, or interrupt generation are also selected in the timer control register (see Table 7). For accurate read back of the countdown value, the serial clock (SCL) must be operating at a frequency of at least twice the selected timer clock. The timer control register selects one of four source clock frequencies for the timer (4096, 64, 1, or 1/60 Hz), and enables/disables the timer. The timer counts down from a softwareloaded 8-bit binary value. At the end of every countdown, the timer sets the timer flag (TF) bit. The TF bit can only be cleared by software. When asserted, the timer flag (TF) can also be used to generate an interrupt (IRQ/FT/OUT) on the M41T93. The interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the condition of TF. The timer interrupt/timer pulse (TI/TP) bit is used to control this mode selection. When reading the timer, the current countdown value is returned. Table 7.
Addr 0Fh 10h 11h TE TI/TP
Timer control register map
D7 WDF D6 AF1 D5 AF2 D4 BL D3 TF D2 OF D1 0 D0 0 Function Flags Timer value 0 TD1 TD0 Timer control
Timer countdown value TIE 0 0
Note:
Bit positions labeled with `0' should always be written with logic '0.'
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Clock operation
M41T93
3.8.1
TI/TP
TI/TP = 0 IRQ/FT/OUT is active when TF is logic '1' (subject to the status of the timer interrupt enable bit (TIE).
TI/TP = 1 IRQ/FT/OUT pulses active according to Table 8 (subject to the status of the TIE bit).
Note:
If an alarm condition, watchdog time-out, oscillator failure, or OUT = 0 cause IRQ/FT/OUT to be asserted low, then IRQ/FT/OUT will remain asserted even if TI/TP is set to '1.' When in pulse mode (TI/TP = 1), clearing the TF bit will not stop the pulses on IRQ/FT/OUT. The output pulses will only stop if TE, TIE, or TI/TP are reset to '0.' Table 8. Interrupt operation (bit TI/TP = 1)
IRQ(1) period(s) Source clock (Hz) 4096 64 1 1/60 n(2) = 1 1/8192 1/128 1/64 1/64 n>1 1/4096 1/64 1/64 1/64
1. TF and IRQ/FT/OUT become active simultaneously. 2. n = loaded countdown timer value. The timer is stopped when n = 0.
3.8.2
TF
At the end of a timer countdown, TF is set to logic '1.' If both timer and alarm interrupts are required in the application, the source of the interrupt can be determined by reading the flag bits. The timer will auto-reload and continue to count down regardless of the state of TF bit (or TI/TP bit). The TF bit is cleared by reading the flags register.
3.8.3
TIE
In level mode (TI/TP = 0), when TF is asserted, the interrupt is asserted (if TIE = 1). To clear the interrupt, the TF bit or the TIE bit must be reset.
3.8.4
TE
TE = 0 When the timer register (10h) is set to `0,' the timer is disabled. TE = 1 The timer is enabled. TE is reset (disabled) on power-down. When re-enabled, the counter will begin from the same value as when it was disabled.
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M41T93
Clock operation
3.8.5
TD1/0
These are the timer source clock frequency selection bits (see Table 9). These bits determine the source clock for the countdown timer (see Table 10). When not in use, the TD1 and TD0 bits should be set to `11' (1/60 Hz) for power saving. Table 9. Timer source clock frequency selection (244.1 s to 4.25 hrs)
TD1 0 0 1 1 TD0 0 1 0 1 Timer source clock frequency (Hz) 4096 (244.1 s) 64 (15.6 ms) 1 (1 s) 1/60 (60 s)
Table 10.
Bit 7-0
Timer countdown value register bits (addr 11h)
Symbol Countdown period = n / source clock frequency Description This register holds the loaded countdown value `n.'
Note:
Writing to the timer register will not reset the TF bit or clear the interrupt.
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Clock operation
M41T93
3.9
Square wave output
The M41T93 offers the user a programmable square wave function which is output on the SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These frequencies are listed in Table 11. Once the selection of the SQW frequency has been completed, the SQW pin can be turned on and off under software control with the square wave enable bit (SQWE) located in register 0Ah.
Note:
If the SQWE bit is set to '1', and VCC falls below the switchover (VSO) voltage, the squarewave output will be disabled. Table 11. Square wave output frequency
Square wave bits RS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Square wave Frequency None 32.768 8.192 4.096 2.048 1.024 512 256 128 64 32 16 8 4 2 1 Units kHz kHz kHz kHz kHz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz
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M41T93
Clock operation
3.10
Battery low warning
The M41T93 automatically performs battery voltage monitoring upon power-up and at factory-programmed time intervals of approximately 24 hours. The battery low (BL) bit, bit D4 of flags register 0Fh, will be asserted if the battery voltage is found to be less than approximately 2.5 V. The BL bit will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to maintain data integrity. Clock data should be considered suspect and verified as correct. A fresh battery should be installed. If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCC is supplied. In order to insure data integrity during subsequent periods of battery backup mode, the battery should be replaced. The M41T93 only monitors the battery when a nominal VCC is applied to the device. Thus applications which require extensive durations in the battery backup mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique.
3.11
Century bits
These two bits will increment in a binary fashion at the turn of the century, and handle all leap years correctly. See Table 12 for additional explanation. Table 12. Century bits examples
CB1 0 1 0 1 Leap Year? Yes No No No Example(1) 2000 2100 2200 2300
CB0 0 0 1 1
1. Leap year occurs every four years (for years evenly divisible by four), except for years evenly divisible by 100. The only exceptions are those years evenly divisible by 400 (the year 2000 was a leap year, year 2100 is not).
3.12
Output driver pin
When the OFIE bit, A1IE bit, and watchdog register are not set to generate an interrupt, the IRQ/FT/OUT pin becomes an output driver that reflects the contents of D7 of register 08h. In other words, when D7 (OUT bit) is a '0,' then the IRQ/FT/OUT pin will be driven low.
Note:
The IRQ/FT/OUT pin is an open drain which requires an external pull-up resistor.
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Clock operation
M41T93
3.13
Oscillator fail detection
If the oscillator fail (OF) bit is internally set to a '1,' this indicates that the oscillator has either stopped, or was stopped for some period of time and can be used to judge the validity of the clock and date data. This bit will be set to '1' any time the oscillator stops. In the event the OF bit is found to be set to '1' at any time other than the initial power-up, the STOP bit (ST) should be written to a '1,' then immediately reset to '0.' This will restart the oscillator. The following conditions can cause the OF bit to be set:
The first time power is applied (defaults to a '1' on power-up).
Note:
If the OF bit cannot be written to '1' four seconds after the initial power-up, the STOP bit (ST) should be written to a '1,' then immediately reset to '0.'
The voltage present on VCC or battery is insufficient to support oscillation The ST Bit is set to '1.' External interference of the crystal
For the M41T93, if the oscillator fail interrupt enable bit (OFIE) is set to a '1,' the IRQ/FT/OUT pin will also be activated. The IRQ/FT/OUT output is cleared by resetting the OFIE or OF bit to '0' (NOT by reading the flag register). The OF bit will remain set to '1' until written to logic '0.' The oscillator must start and have run for at least 4 seconds before attempting to reset the OF bit to '0.' If the trigger event occurs during a power down condition, this bit will be set correctly.
3.14
Oscillator fail interrupt enable
If the oscillator fail interrupt bit (OFIE) is set to a '1,' the IRQ/FT/OUT pin will also be activated. The IRQ/FT/OUT output is cleared by resetting the OFIE or OF bit to '0' (not be reading the flags register).
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M41T93
Clock operation
3.15
Initial power-on defaults
Upon initial application of power to the device, the register bits will initially power-on in the state indicated in Table 13 and Table 14.
Table 13.
Condition(1) Initial power-up
Initial power-on default values (part 1)
ST 0 UC CB1 CB0 OUT FT 0 UC 0 UC 1 UC 0 0 DCS Digital Analog OFIE Watchdog(2) ACS calib. calib. 0 UC 0 UC 0 UC 0 UC 0 0 A1IE SQWE ABE 0 UC 1 UC 0 UC
Subsequent power-up(3)(4)
1. All other control bits power-up in an undetermined state 2. BMB0-BMB4, RB0, RB1 3. With battery backup 4. UC = Unchanged
Table 14.
Initial power-up
Initial power-up default values (part 2)
RPT11-15 0 UC HT 1 1 OF 1 UC TE 0 0 TI/TP 0 UC TIE 0 UC TD1 TD0 RS0 RS1-3 OTP RPT21-25 1 UC 1 UC 1 UC 0 UC 0 UC 0 UC AL2E 0 UC
Condition(1)
Subsequent power-up (2)(3)
1. All other control bits power-up in an undetermined state 2. With battery backup 3. UC = Unchanged
3.16
OTP bit operation (SOX18 package only)
When the OTP (one time programmable) bit is set to a '1,' the value in the internal OTP registers will be transferred to the analog calibration register (12h) and are "read only." The OTP value is programmed by the manufacturer, and will contain the calibration value necessary to achieve 5 ppm at room temperature after two SMT reflows. This clock accuracy can be guaranteed to drift no more than 3 ppm the first year, and 1 ppm for each following year due to crystal aging. If the OTP bit is set to '0,' the analog calibration register will become a WRITE/READ register and function like standard SRAM memory cells, allowing the user to implement any desired value of analog calibration. When the user sets the OTP bit, they need to wait for approximately 8 ms before the analog registers transfer the value from the OTP to the analog registers due to the OTP read operation.
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Maximum ratings
M41T93
4
Maximum ratings
Stressing the device above the rating listed in the "absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 15.
Symbol TSTG VCC TSLD(2) VIO IO PD
Absolute maximum ratings
Parameter Storage temperature (VCC off, oscillator off) Supply voltage QFN16 Lead solder temperature for 10 seconds SOX18 Input or output voltages Output current Power dissipation 245 0.2 to Vcc+0.3 20 1 C V mA W Value(1) 55 to 125 0.3 to 7.0 260 Unit C V C
1. Data based on characterization results, not tested in production. 2. Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds).
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M41T93
DC and AC parameters
5
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 16. Operating and AC measurement conditions
Parameter Supply voltage (VCC) Ambient operating temperature (TA) Load capacitance (CL, typical) Input rise and fall times Input pulse voltages Input and output timing ref. voltages M41T93 2.38 V to 5.5 V 40 to +85C 30 pF 50 ns 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC
Note:
Output Hi-Z is defined as the point where data is no longer driven. Figure 16. Measurement AC I/O waveform
0.8VCC
0.7VCC 0.3VCC
AI02568
0.2VCC
Table 17.
Capacitance
Parameter(1)(2) Input capacitance Output capacitance Min Max 7 10 Unit pF pF
Symbol CIN COUT
(3)
1. Effective capacitance measured with power supply at 3.6 V; sampled only, not 100% tested 2. At 25C, f = 1 MHz 3. Outputs deselected
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DC and AC parameters Table 18.
Sym
M41T93
DC characteristics
Parameter Test condition(1) 40 to 85C 40 to 85C 40 to 85C 0V VIN VCC 0V VOUT VCC fSCL = 2 MHz fSCL = 5 MHz fSCL = 10 MHz 5.5 V 3.0 V 0.3 0.7VCC RST, FT/RST VCC/VBAT = 3.0 V, IOL = 1.0 mA VCC = 3.0 V, IOL = 1.0 mA VCC = 3.0 V, IOL = 3.0 mA 2.4 5.5 1.8 25C; VCC = 0 V; OSC on; VBAT = 3 V; 32 kHz off 365 5.5 450 8 6.5 0.3VCC VCC+0.3 0.4 0.4 0.4 Min 3.00 2.70 2.38 Typ Max 5.50 5.50 5.50 1 1 0.5 1.0 2.0 10 Unit V V V A A mA mA mA A A V V V V V V V V nA
Operating voltage (S) VCC ILI ILO ICC1 Operating voltage (R) Operating voltage (Z) Input leakage current Output leakage current Supply current SCL = 0.1VCC/0.9VCC SDO = open
ICC2 VIL VIH
E = VCC; Supply current (standby) All inputs VCC 0.2 V; VSS + 0.2 V Input low voltage Input high voltage
VOL
Output low voltage
SQW, IRQ/FT/OUT SDO
VOH
Output high voltage Pull-up supply voltage (open drain)
VCC = 3.0 V, IOH = 1.0 mA (push-pull) IRQ/FT/OUT
VBAT IBAT
Backup supply voltage Batter y supply current
1. Valid for ambient operating temperature: TA = 40 to 85C; VCC = 2.38 V to 5.5 V (except where noted)
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M41T93 Figure 17. ICC2 vs. temperature
10.000
DC and AC parameters
9.000
8.000
7.000
Icc2 (A)
6.000
(3.0V) (5.0V)
5.000
4.000
3.000
2.000 -40
-20
0
20 Temperature (C)
40
60
80
ai 13909
Table 19.
Symbol fO RS CL
Crystal electrical characteristics
Parameter(1)(2) Resonant frequency Series resistance Load capacitance 12.5 Min Typ 32.768 65(3) Max Units kHz k pF
1. Externally supplied if using the QFN16 package. STMicroelectronics recommends the Citizen CFS-145 (1.5 x 5 mm) and the KDS DT-38 (3 x 8 mm) for thru-hole, or the KDS DMX-26S (3.2 x 8 mm) or Micro Crystal MS3V-T1R (1.5 x 5 mm) for surface-mount, tuning fork-type quartz crystals. For contact information, see Section 8: References on page 49. 2. Load capacitors are integrated within the M41T93. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account. 3. Guaranteed by design.
Table 20.
Symbol VSTA tSTA CXI, CXO(1)
Oscillator characteristics
Parameter(1)(2) Oscillator start voltage Oscillator start time Capacitor input, capacitor output IC-to-IC frequency variation(2)(3) 10 Conditions 4 s VCC = VSO 25 +10 Min 2.0 1 Typ Max Units V s pF ppm
1. With default analog calibration value ( = 0) 2. Reference value 3. TA = 25C, VCC = 5.0 V
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DC and AC parameters Figure 18. Power down/up mode AC waveforms
VCC VSO tPD SCL SDI DON'T CARE trec
M41T93
AI11839
Table 21.
Sym
Power down/up trip points DC characteristics
Parameter(1)(2) S Min 2.85 2.55 2.25 VRST 25 140 2.5 280 Typ 2.93 2.63 2.32 Max 3.0 2.7 2.38 Unit V V V V mV ms s
VRST
Reset threshold voltage
R Z
Battery backup switchover VSO Hysteresis Reset pulse width (VCC rising) trec VCC to reset delay, VCC = (VRST + 100 mV), falling to (VRST 100 mV; for VCC slew rate of 10 mV/s
1. All voltages referenced to VSS 2. Valid for ambient operating temperature: TA = 40 to 85C; VCC = 2.38 to 5.5 V (except where noted)
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M41T93 Figure 19. Input timing requirements
DC and AC parameters
tEHEL E tCHEL SCL tDVCH tCHDX SDI MSB IN tDLDH tDHDL tCLCH LSB IN tCHCL tELCH tCHEH tEHCH
SDO
HIGH IMPEDANCE
AI12295
Figure 20. Output timing requirements
E tCH SCL tCLQV tCLQX SDO
MSB OUT
tCL
tEHQZ
LSB OUT tQLQH tQHQL
SDI
ADDR. LSB IN AI04634
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DC and AC parameters Table 22.
Sym fSCL tELCH tEHCH tEHEL tCHEH tCHEL tCH(2) tCL
(2)
M41T93 AC characteristics
Parameter(1) SCL clock frequency E active setup time E not active setup time E deselect time E active hold time E not active hold time Clock high time Clock low time Clock rise time Clock fall time Data in setup time Data in hold time Output disable time Clock low to output valid Output hold time Output rise time Output fall time 0 50 50 20 30 100 60 0 40 40 VCC < 2.7 V Min D.C. 90 90 100 90 90 90 90 1 1 10 10 40 40 M ax 5 VCC 2.7 V Units Min D.C. 30 30 40 30 30 40 40 2 2 M ax 10 MHz ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns
tCLCH(3) tCHCL(3) tDVCH tCHDX tEHQZ
(3)
tCLQV tCLQX tQLQH(3) tQHQL
(3)
1. Valid for ambient operating temperature: TA = 40 to 85C; VCC = 2.38 to 5.5 V (except where noted) 2. tCH and tCL must never be lower than the shortest possible clock period, 1/fC(max) 3. Value guaranteed by characterization, not 100% tested in production
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M41T93
Package mechanical data
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com.
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Package mechanical data
M41T93
Figure 21. QFN16 16-lead, quad, flat package, no lead, 4 x 4 mm body size, outline
D
E
A3
A1
A
ddd C
b L
e K
1
(2) E2
2 3
Ch
K D2
QFN16-A2
1. Drawing is not to scale 2. Substrate pad should be tied to VSS
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M41T93 Table 23.
Sym Typ A A1 A3 b D D2 E E2 e K L ddd Ch N 0.90 0.02 0.20 0.30 4.00 4.00 0.65 0.20 0.40 Min 0.80 0.00 0.25 3.90 2.50 3.90 2.50 0.30 0.08 0.33 16 Max 1.00 0.05 0.35 4.10 2.80 4.10 2.80 0.50 Typ 0.035 0.001 0.008 0.010 0.118 0.067 0.118 0.067 0.020 0.008 0.016
Package mechanical data QFN16 16-lead, quad, flat package, no lead, 4 x 4 mm body, mech. data
mm inches Min 0.032 0.000 0.007 0.114 0.061 0.114 0.061 0.012 0.003 0.013 16 Max 0.039 0.002 0.012 0.122 0.071 0.122 0.071 0.020
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Package mechanical data
M41T93
Figure 22. QFN16 16-lead, quad, flat, no lead, 4 x 4 mm, recommended footprint
2.70 0.70 0.20 (2) 4.50 2.70
0.35 0.325 0.65
AI11815
1. Dimensions shown are in millimeters (mm) 2. Substrate pad should be tied to VSS
Figure 23. 32 kHz crystal + QFN16 vs. VSOJ20 mechanical data
6.0 0.2
3.2 VSOJ2 0
1.5
SMT CRYSTAL
7.0 0.3
15 XI 16 XO 14 13
1
3.9
2 3 4
ST QFN16
3.9
AI11816
Note:
Dimensions shown are in millimeters (mm).
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M41T93
Package mechanical data Figure 24. SOX18 18-lead plastic small outline, 300 mils, embedded crystal
D
9 1
h x 45
C E H
10
18
A2 B SO-J e A1
A ddd A1 L
Note:
Drawing is not to scale. Table 24.
Sym Typ A A1 A2 B C D ddd E e H L N 11.61 1.27 Min 2.44 0.15 2.29 0.41 0.20 11.56 7.57 10.16 0.51 0 18 Max 2.69 0.31 2.39 0.51 0.31 11.66 0.10 7.67 10.52 0.81 8 Typ 0.457 0.050 Min 0.096 0.006 0.090 0.016 0.008 0.455 0.298 0.400 0.020 0 18 Max 0.106 0.012 0.094 0.020 0.012 0.459 0.004 0.302 0.414 0.032 8
SOX18 18-lead plastic SO, 300 mils, embedded crystal, pkg. mech. data
mm inches
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Part numbering
M41T93
7
Table 25.
Example:
Part numbering
Ordering information
M41T 93 S QA 6 E
Device family M41T Device type 93 Operating voltage S = VCC = 3.00 to 5.5 V R = VCC = 2.70 to 5.5 V Z = VCC = 2.38 to 5.5 V Package QA = QFN16 (4 mm x 4 mm) MY(1) = SOX18 Temperature range 6 = 40C to +85C Shipping method E = ECOPACK package, tubes F = ECOPACK package, tape & reel
1. The SOX18 package includes an embedded 32,768 Hz crystal. Contact local ST sales office for availability.
For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you.
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M41T93
References
8
References
Below is a listing of the crystal component suppliers mentioned in this document.
KDS can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp. Citizen can be contacted at csd@citizen-america.com or http://www.citizencrystal.com. Micro Crystal can be contacted at sales@microcrystal.ch or http://www.microcrystal.com.
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Revision history
M41T93
9
Revision history
Table 26.
Date 07-Aug-2006
Document revision history
Revision 1 Initial release. Document status upgraded to full datasheet; updated Figure 11: Clock accuracy vs. on-chip load capacitors; Section 3.16; Section 3.4.1; Table 1, 15, and 18, Figure 3 and 23; added Figure 17: ICC2 vs. temperature. Micro Crystal information added (Table 19). Updated Features on cover page; minor formatting changes; modified footnote 1 in Table 19; added Section 8: References. Removed references to SPI bus mode 3 operation (updated cover page, Figure 5, 6, Section 1.1.3, Section 2.1); minor formatting changes. Changes
08-May-2007
2
22-Oct-2007
3
15-Aug-2008
4
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M41T93
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