PM6675A
High efficiency step-down controller with embedded 2A LDO regulator
Target Specification
Features switching
Switching section 4.5V to 36V input voltage range 0.6V, 1% voltage reference Selectable 1.5V fixed output voltage Adjustable 0.6V to 3.3V output voltage 1.237V 1% reference voltage available Very fast load transient response using constant-on-time control loop No RSENSE current sensing using low side MOSFETs' RDS(ON) Negative current limit Latched OVP and UVP Soft start internally fixed at 3ms Selectable pulse skipping at light load Selectable No-Audible (33KHz) pulse skip mode Ceramic output capacitors supported Output voltage ripple compensation Output soft-end LDO regulator section Adjustable 0.6V to 2.5V output voltage Selectable 1Apk or 2Apk current limit Dedicated power-good signal Ceramic output capacitors supported Output soft-end
VFQFPN-24 4x4
Description
The PM6675A device consists of a single high efficiency step-down controller and an independent Low Drop-Out (LDO) linear regulator. The Constant On-Time (COT) architecture assures fast transient response supporting both electrolytic and ceramic output capacitors. An embedded integrator control loop compensates the DC voltage error due to the output ripple. Selectable low-consumption mode allows the highest efficiency over a wide range of load conditions. The low-noise mode sets the minimum switching frequency to 33kHz for audio-sensitive applications. The LDO linear regulator can sink and source up to 2Apk. Two fixed current limit (1A- 2A) can be chosen. An active Soft-End is independently performed on both the switching and the linear regulators outputs when disabled.
Applications
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Industrial application on 24V Graphic cards Embedded computer systems
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Order codes
Part number PM6675A October 2006 Package VFQFPN-24 4x4 (Exposed Pad) Rev 1 Packaging Tube 1/15
www.st.com 15
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
Contents
PM6675A
Contents
1 2 Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 2.2 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 3.2 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 5 6 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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PM6675A
Typical application circuit
1
Figure 1.
Typical application circuit
Application circuit
R LP
+5V VIN
C IN3
C IN2
R1 C IN R2
3 NOSKIP
12 LILIM
6 AVCC
18 VCC
8 VOSC
22 B O O HGATE 21 T PHASE 20
VLDOIN
C IN4 LDO PG
C BOOT L
10 VSEL 23 LIN
4 LPG 24 LOUT
LGATE 17
PM6675A
CSNS PGND VSNS
19 16 9
VLDO VLDO
2 LFB 1 LGND
R LIM
5
15
14
13
7
11
C OUT 2 SMPS PG
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C OUT
VSMPS
SW EN
SGND
COMP
VREF
SPG
LEN
C INT
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Pin settings
PM6675A
2
2.1
Pin settings
Connections
Figure 2. Pin connection (through top view)
HGATE
BOOT
PHASE
LOUT
24 1 LGND LFB NOSKIP LPG SGND AVCC 6 7
CSNS 19 18 VCC LGATE
LIN
PM6675A
PGND SPG
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COMP
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VREF
LILIM
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PM6675A
Pin settings
2.2
Pin description
Table 1. Pin functions
N 1 2 3 4 Pin LGND LFB NOSKIP LPG Function LDO power ground. Connect to negative terminal of VTT output capacitor. LDO remote sensing. Connect as close as possible to the load via a low noise PCB trace. Pulse-Skip/No-Audible Pulse-Skip Modes selector. See Mode of Operation Selection section for details. LDO section Power-Good signal (open drain output). High when LDO output voltage is within 10% of nominal value. Ground Reference for analog circuitry, control logic and VTTREF buffer. Connect together with the thermal pad and VTTGND to a low impedance ground plane. See the Application Note for details. +5V supply for internal logic. Connect to +5V rail through a simple RC filtering network.
5
SGND
6
AVCC
7
VREF
High accuracy output voltage reference (1.237V) for multilevel pins setting. It can deliver up to 50uA. Connect a 100nF capacitor between VREF and SGND in order to enhance noise rejection. Frequency Selection. Connect to the central tap of a resistor divider to set the desired switching frequency. The pin cannot be left floating. See Device Description section for details. Switching section output remote sensing and discharge path during output Soft-End. Connect as close as possible to the load via a low noise PCB trace. Fixed output selector and feedback input for the switching controller. If VSEL pin voltage is higher than 4V, the fixed 1.5V output is selected. If VSEL pin voltage is lower than 4V, it is used as negative input of the error amplifier. See Mode of Operation Selection section for details. DC voltage error compensation pin for input the switching section. Refer to Mode of Operation Selection section for more details. Current limit selector for the LDO. Connect to SGND for 1A current limit or to +5V for 2A current limit.
8
VOSC
9
VSNS
10
VSEL
11 12
COMP LILIM
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SWEN LEN SPG PGND
Switching Controller Enable. When tied to ground, the switching output is turned off and a Soft-End is performed. Linear Regulator Enable. When tied to ground, the LDO output is turned off and a Soft-End is performed. Switching Section Power-Good signal (open drain output). High when the switching regulator output voltage is within 10% of nominal value. Power ground for the switching section. Low-side gate driver output. +5V low-side gate driver supply. Bypass with a 100nF capacitor to PGND.
14
15 16 17 18
LGATE VCC
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Pin settings Table 1. Pin functions (continued)
N Pin Function
PM6675A
19
CSNS
Current sense input for the switching section. This pin must be connected through a resistor to the drain of the synchronous rectifier (RDSon sensing) or to the source of the synchronous rectifier (RSENSE sensing) to set the current limit threshold. Switch node connection and return path for the high side gate driver. High-Side Gate Driver Output Bootstrap capacitor connection. Input for the supply voltage of the high-side gate driver. Linear Regulator Input. Bypass to LGND by a 10F ceramic capacitor for noise rejection enhancement. LDO linear regulator output. Bypass with a 20F (2x10F MLCC) filter capacitor.
20 21 22 23 24
PHASE HGATE BOOT LIN LOUT
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PM6675A
Electrical data
3
3.1
Electrical data
Maximum rating
Table 2. Absolute maximum ratings (1)
Symbol VAVCC VVCC AVCC to SGND VCC to SGND PGND, LGND to SGND HGATE and BOOT to PHASE HGATE and BOOT to PGND VPHASE PHASE to SGND LGATE to PGND CSNS, SPG, LEN, SWEN, LILIM, COMP, VSEL, VSNS, VOSC, VREF, NOSKIP to SGND LPG,VREF, LOUT, LFB to SGND LIN, LOUT, LPG, LIN to LGND PTOT Power dissipation @TA = 25C Parameter Value -0.3 to 6 -0.3 to 6 -0.3 to 0.3 -0.3 to 6 -0.3 to 44 -0.3 to 38 -0.3 to VVCC +0.3 V Unit
-0.3 to VAVCC + 0.3 -0.3 to VAVCC + 0.3
1. Free air operating conditions unless otherwise specified. Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
3.2
Thermal data
Table 3. Thermal data
Symbol RthJA
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Thermal resistance junction to ambient Storage temperature range Operating ambient temperature range Junction operating temperature range
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-0.3 to VAVCC + 0.3 2.3 W
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Parameter
Value 42 -40 to 150 -40 to 85 -25 to 125
Unit C/W C C C
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Electrical characteristics
PM6675A
4
Electrical characteristics
TA = 0C to 85C , VCC = AVCC = +5V, LIN = 1.5V and LOUT= 0.9V if not otherwise specified.
Table 4. Electrical characteristics
Symbol Supply section Parameter Test condition Min. Typ. Max. Unit
V IN VAVCC V VCC
IIN
Input voltage range IC supply voltage IC supply voltage Operating current (Switching + LDO) SWEN, LEN, VSEL and NOSKIP connected to AVCC, No load on LOUT output. SWEN, VSEL and NOSKIP connected to AVCC, LEN connected to SGND. SWEN and LEN tied to SGND.
4.5 4.5 4.5
36 5.5 5.5 2
V
ISW
Operating current (Switching)
ISHDN
Shutdown operating current AVCC Under Voltage Lockout upper threshold
UVLO
AVCC Under Voltage Lockout upper threshold UVLO hysteresis
ON-time (SMPS) tON On-time duration
OFF-time (SMPS) tOFFMIN
Minimum Off-Time
Voltage reference
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Voltage accuracy Load regulation Undervoltage Lockout Fault Threshold
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VSEL and NOSKIP high,
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A
4.1 3.9
4.2 V 4.0 mV
VOSC = 300mV VOSC = 500mV
650 390
750 450
850 ns 510
VVSNS = 2V
300
350
ns
4.5V< VIN < 25V -50A< IVREF < 50A
1.224 -4
1.237
1.249 4
V
mV 800
SMPS output SMPS fixed output voltage (1) VOUT Output voltage accuracy (1) VSEL connected to AVCC, NOSKIP tied to SGND, No Load -2 1.5 2 V %
1. Guaranteed by design. Not production tested.
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PM6675A Table 5. Electrical characteristics
Symbol Parameter Test condition
Electrical characteristics
Min.
Typ.
Max.
Unit
Current limit and zero crossing comparator ICSNS CSNS input bias current Comparator offset Positive current limit threshold Fixed negative current limit threshold VZC,OFFS Zero crossing comparatot offset High and low side gate drivers HGATE high state (pullup) HGATE driver on-resistance HGATE low state (pulldown) LGATE high state(pullup) LGATE driver on-resistance LGATE low state (pulldown) UVP/OVP protections and PGOOD signals OVP UVP Over voltage threshold Under voltage threshold SMPS upper threshold SMPS lower threshold PGOOD LDO upper threshold LDO lower threshold IPG,LEAK SPG and LPG leakeage current¹ VPG,LOW SPG and LPG low level voltage Soft start section (SMPS) Soft-star t ramp time (4 steps current limit) 1.8 1.4 2.7 2.1 2.0 3 VPGND - VCSNS 90 -5 -115 -130 -10 -100 -110 -5 100 110 5 -85 mV -90 0 A
SPG and LPG forced to 5.5V
Soft-star t initial current limit
Soft end section
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Soft-star t current limit step
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ILPG,SINK = ISPG,SINK = 4mA
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112 63 107 87 107 87
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115 70 110 90 110 90
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0.9 73 93
118
113 % 113 93 1 A mV
150
250
2 22.5 22.5
3 25 25
4 27.5 27.5
ms A
Switching section discharge resistance
25 25
LDO section discharge resistance
LDO section VLREF VDROP LDO reference voltage LDO drop-out voltage VLOUT = 0.9V, ILOUT =1A, -10% output drop 0.594 0.6 0.25 0.606 V
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Electrical characteristics Table 5. Electrical characteristics (continued)
Symbol Parameter LDO Internal high-side MOSFET RDS(on) LDO source current limit Test condition ILOUT = 1A, AVCC = 5V VLFB < 1.10* VLREF , LILIM = 5V VLFB < 1.10* VLREF, LILIM = 0V 0.90* VLREF < VLFB < 1.10* VLREF, LILIM = 5V ILDO,CL LDO sink current limit 0.90* VLREF < VLFB < 1.10* VLREF, LILIM = 0V VLFB > 1.10* VLREF, LILIM = 5V VLFB > 1.10* VLREF, LILIM = 0V LDO input bias current, On ILIN,BIAS LDO input bias current, Off LEN connected to AVCC, no load LEN = 0V, no load LEN connected to AVCC VLFB = 0.6V LEN = 0V, VLFB = 0.6V -1 2 1 -2.2 -1.2 -1.2 -0.6 Min. Typ. 0.2 2.1 1.1 -2.1 -1.1 -1.1 -0.55 1
PM6675A
Max. 0.23 2.2 1.2 -2
Unit
A -1 -1 -0 . 6 10
ILFB,BIAS LFB input bias current ILFB,LEAK LFB leakage current Power management section
Fixed mode VVTHVSEL VSEL pin thresholds Adjustable mode
Forced-PWM Mode VVTHNOS
KIP
NOSKIP pin thresholds
(1)
No-Audible Mode
VVTHLILIM LILIM pin thresholds (1) IIN,LEAK
Logic input leakage current (1)
IIN3,LEAK Multilevel input leakage current (1) VSEL and NOSKIP=5V IOSC,LEAK VOSC pin leakage current (1) Thermal shutdown VOSC=1V
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1. Guaranteed by design. Not production tested.
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Pulse-Skip Mode
2A LDO Current Limit 1A LDO Current Limit
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1 1 1 3.7
A
3.5 0.5
V
2.4 0.8 1 1 1 A
LEN, SWEN and LILIM=5V
Shutdown temperature (1)
150
C
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PM6675A
Block diagram
5
Figure 3.
Block diagram
Functional and block diagram
VREF VOSC
Vr = 0.6V 1.236V Bandgap Level shifter
BOOT
To n 1-shot To n min 1-shot
LFB LIN
_
HGATE PHASE
Anti Cross Conduction
LOUT LOUT
+ LDS LEN
LILIM
Toff min 1-shot
VCC LGATE PGND
0.6V
LGND
Vr +10% _ + + Vr -10% + SWEN VREF
Zero Crossing & Current Limit
LPG
SGND
UVP/OVP
AVCC
UVLO
LILIM
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SWEN
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LDS
VSNS
SDS
CONTROL LOGIC
Thermal Shutdown
adj
fix
LEN
SWEN
VSEL
Table 6. Legend
SWEN LEN LDS SDS LILIM Switching controller enable LDO regulator enable LDO output discharge enable Switching output discharge enable LDO regulator current limit
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Package mechanical data
PM6675A
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Table 7. VFQFPN-24 4mm x 4mm mechanical data
mm. Dim. Typ A A1 A2 D D1 E E1 0.00 0.65 4.00 3.75 4.00 3.75 Min. 0.80 0.05 Max. 1.00 0.05 0.80
P e N Nd Ne L b D2 0.42 0.50
24.00 6.00
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12 0.60
0.40
0.50 0.30 2.25 2.25
2.10 2.10
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PM6675A
Package mechanical data
Figure 4.
Package dimensions
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Revision history
PM6675A
7
Revision history
Table 8. Revision history
Date 11-Oct-2006 Revision 1 Initial release. Changes
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PM6675A
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