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High Voltage Converters
OFF-line primary switch
Datasheet
Format:
(355 kb)
or
(40 kb)
Last Updated: 21/12/2006
Pages: 36
Untitled Document
Generic Part Number
Orderable Part Number
Status
VIPER53-E
VIPER53SPTR-E
Active
VIPER53DIP-E
Active
VIPER53SP-E
Active
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VIPer53 - E
OFF-line primary switch
General features
Type DIP-8 PowerSO-10TM European (195 - 265Vac) 50W 65W US / Wide range (85 - 265 Vac) 30W 40W PowerSO-10 DIP-8
Features
Switching frequency up to 300kHz Current limitation Current mode control with adjustable limitation Soft start and shut-down control Automatic burst mode in standby condition ("Blue Angel" compliant ) Undervoltage lockout with Hysteresis HIgh voltage star-tup current source Overtemperature protection Overload and short-circuit control
Description
The VIPer53-E combines an enhanced current mode PWM controller with a high voltage MDMesh Power Mosfet in the same package. Typical applications cover offline power supplies with a secondary power capability ranging up to 30W in wide range input voltage, or 50W in single European voltage range and DIP-8 package, with the following benefits:
Overload and short circuit controlled by feedback monitoring and delayed device reset. Efficient standby mode by enhanced pulse skipping. Primary regulation or secondary loop failure protection through high gain error amplifier.
D R AIN
Block diagram
O SC O N/O FF O S C ILLAT O R
PW M LATC H O VER T EM P . D ET ECT O R R1 S FF Q R2 R3 R4 R 5 B LANK ING TIME S E LE C TIO N 1V
UVLO C O MP AR ATO R VD D 8.4/ 11.5V 0.5V 15V ERR O R AMP LIFIE R 4.35V S TAND BY C O MP AR ATO R 4V 150/400ns B LAN K IN G PW M C O MP AR ATO R 8V
0.5V
HCO M P C UR R E NT AMP LIFIE R
125k
O VE R LO AD C O MP AR ATO R O VE R VO LTAGE C O MP AR ATO R 4.5V
18V
T O VL
COM P
SO U R C E
November 2006
Rev 1
1/36
www.st.com 36
Contents
VIPer53 - E
Contents
1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 1.2 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin connections and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Operation pictures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Primary regulation configuration example . . . . . . . . . . . . . . . . . . . . . . 15 Secondary feedback configuration example . . . . . . . . . . . . . . . . . . . . 17 Current mode topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 High voltage Start-up current source . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Short-circuit and overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Transconductance error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Special recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Software implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2/36
VIPer53 - E
Electrical data
1
1.1
Electrical data
Maximum rating
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 1.
Symbol VDS ID VDD VOSC ICOMP ITOVL VESD TJ TC TSTG
Absolute maximum rating
Parameter Continuous drain source voltage (TJ= 25 ... 125C) (1) Continuous drain current Supply voltage OSC input voltage range COMP and TOVL input current range (1) Electrostatic discharge: Machine model (R = 0; C = 200pF) Charged device model Junction operating temperature Case operating temperature Storage temperature Value -0.3 ... 620 Internally limited 0 ... 19 0 ... VDD -2 ... 2 Unit V A V V mA
200 1.5 Internally limited -40 to 150 -55 to 150
V kV C C C
1. In order to improve the ruggedness of the device versus eventual drain overvoltages, a resistance of 1k should be inserted in series with the TOVL pin.\
1.2
Thermal data
Table 2.
Symbol RthJC RthJA
Thermal data
Parameter Thermal Resistance Junction-case Thermal Resistance Ambient-case Max Max PowerSO-10 (1) 2 60 DIP-8 (2) 20 80 Unit C/W C/W
1. When mounted on a standard single-sided FR4 board with 50mm˛ of Cu (at least 35 mm thick) connected to the DRAIN pin. 2. When mounted on a standard single-sided FR4 board with 50mm˛ of Cu (at least 35 mm thick) connected to the device tab.
3/36
Electrical characteristics
VIPer53 - E
2
Electrical characteristics
TJ = 25C, VDD = 13V, unless otherwise specified Table 3.
Symbol BVDSS I DSS
Power section
Parameter Test conditions Min. 620 150 Typ. Max. Unit V A
Drain-source voltage ID = 1mA; VCOMP = 0V Off state drain current Static drain-source On state resistance Fall time Rise time Drain capacitance Effective output capacitance VDS = 500V; VCOMP = 0V; TJ = 125C ID = 1A; VCOMP = 4.5V; VTOVL = 0V TJ = 25C TJ = 100C ID = 0.2A; VIN = 300V (1) ID = 1A; VIN = 300V (1) VDS = 25V 200V < VDSon < 400V (2)
RDS(on)
0.9
1 1.7
ns ns pF pF
tfv tr v Coss CEon
100 50 170 60
1. On clamped inductive load 2. This parameter can be used to compute the energy dissipated at turn on Eton according to the initial drain to source voltage VDSon and the following formula:
V D S o n 1.5 1 2 E t o n = -- C E o n 300 ---------------- 300 2
Table 4.
Symbol FOSC1
Oscillator section
Parameter Oscillator frequency initial accuracy Test conditions RT = 8k; CT = 2.2nF Figure 12 on page 12 RT = 8k; CT = 2.2nF Min. 95 Typ. 100 Max. 105 Unit kHz
FOSC2
Oscillator frequency total variation
Figure 16 on page 14 VDD = VDDon ... VDDovp; TJ = 0 ... 100C
93
100
107
kHz
VOSChi VOSClo
Oscillator peak voltage Oscillator valley voltage
9 4
V V
4/36
VIPer53 - E
Electrical characteristics
Table 5.
Symbol VDSstart IDDch1 IDDch2 IDDchoff IDD0 IDD1 VDDoff VDDon VDDhyst VDDovp
Supply section
Parameter Drain voltage starting threshold Star tup charging current Star tup charging current Star tup charging current in thermal shutdown Operating supply current not switching Operating supply current switching VDD undervoltage shutdown threshold VDD startup threshold VDD threshold hysteresis VDD Overvoltage shutdown threshold Test conditions VDD = 5V; IDD = 0mA VDD = 0 ... 5V; VDS = 100V Figure 5 on page 10 VDD = 10V; VDS = 100VFigure 5. VDD = 5V; VDS = 100VFigure 7. TJ > TSD - THYST Fsw = 0kHz; VCOMP = 0V Fsw = 100kHz Figure 5 on page 10 Figure 5. Figure 5. Figure 5. 7.5 10.2 2.6 17 0 Min. Typ. 34 -12 -2 Max. Unit 50 V mA mA mA
8 9 8.4 11.5 3.1 18
11
mA mA
9.3 12.8
V V V
19
V
Table 6.
Symbol VDDreg VDDreg
Error amplifier section
Parameter VDD regulation point VDD regulation point total variation Unity gain bandwidth Voltage gain DC transconductance Test conditions ICOMP = 0mA Figure 11. on page 11 ICOMP = 0mA; TJ = 0 ... 100C From Input = VDD to Output = VCOMP ICOMP = 0mA Figure 14 and 15 ICOMP = 0mA Figure 14 and 15 VCOMP = 2.5V Figure 11. ICOMP = -0.4mA; VDD = 16V ICOMP = 0.4mA; VDD=14V(1) VCOMP = 2.5V; VDD = 16V Figure 11. on page 11 VCOMP = 2.5V; VDD= 14V Figure 11. 40 1 Min. 14.5 Typ. 15 2 Max. Unit 15.5 V %
GBW AVOL Gm
700 45 1.4 0.2 4.5 -0.6 0.6 1.8
kHz dB mS V V mA mA
VCOMPlo Output low level VCOMPhi Output high level ICOMPlo ICOMPhi Output sinking current Output sourcing current
1. In order to insure a correct stability of the error amplifier, a capacitor of 10nF (minimum value: 8nF) should always be present on the COMP pin.
5/36
Electrical characteristics
VIPer53 - E
Table 7.
Symbol HCOMP
PWM comparator section
Parameter VCOMP / IDPEAK Test conditions VCOMP = 1 ... 4 V Figure 10. dID/dt = 0 dID/dt = 0 Figure 10. on page 11 ICOMP = 0mA; VTOVL = 0V Figure 10. dID/dt = 0 VCOMP = VCOMPovl; VTOVL = 0V dID/dt = 0 Min. Typ. Max. Unit
1.7
2 0.5
2.3
V/A V
VCOMPos VCOMP Offset IDlim Peak drain current limitation Drain current capability
1.7
2
2.3
A
IDmax td VCOMPbl tb1 tb2 tONmin1 tONmin2 VCOMPoff
1.6
1.9 250 1
2.3
A ns V
Current sense delay to ID = 1A Turn-Off VCOMP blanking time change threshold Blanking time Blanking time Minimum On time Minimum On time VCOMP Shutdown Threshold Figure 6 on page 10 VCOMP < VCOMPBLFigure 6. VCOMP > VCOMPBLFigure 6. VCOMP < VCOMPBL VCOMP > VCOMPBL Figure 9 on page 11 300 100 450 250
400 150 600 350 0.5
500 200 750 450
ns ns ns ns V
Table 8.
Symbol VCOMPovl
Overload protection section
Parameter VCOMP overload threshold VCOMPhi to VCOMPovl voltage difference VTOVL overload threshold Overload delay Test conditions ITOVL = 0mA (1) Figure 4 on page 9 VDD = VDDoff ... VDDreg; ITOVL= 0mA Figure 4.
(1)
Min.
Typ. 4.35
Max.
Unit V
VDIFFovl
50
150
250
mV
VOVLth tOVL
Figure 4. COVL = 100nF Figure 4.
4 8
V ms
1. VCOMPovl is always lower than VCOMPhi
Table 9.
Symbol TSD THYST
Over temperature Protection Section
Parameter Thermal shutdown temperature Thermal shutdown hysteresis Test Conditions Figure 7 on page 10 Figure 7 on page 10 Min. 140 Typ. 160 40 Max. Unit C C
6/36
VIPer53 - E
Pin connections and function
3
Pin connections and function
Figure 1. Pin connection (top view)
COMP 1
8
T OV L
O SC 2
7
VDD
SOURCE 3
6
NC
SOURCE 4
5
DRAIN
DIP-8
PowerSO-10
Figure 2.
Current and voltage conventions
IDD ID
V DD IOSC OSC 15 V
DRAIN
V DD ITOVL VOSC
TOVL
COM P
SOURCE
V DS
ICOMP VTOVL V COMP
7/36
Pin connections and function
VIPer53 - E
Table 10.
Pin Name
Pin function
Pin function Power supply of the control circuits. Also provides the charging current of the external capacitor during start-up. The functions of this pin are managed by four threshold voltages: - VDDon: Voltage value at which the device starts switching (Typically 11.5 V). - VDDoff: Voltage value at which the device stops switching (Typically 8.4 V). - VDDreg: Regulation voltage point when working in primary feedback (Trimmed to 15 V). - VDDovp: Triggering voltage of the overvoltage protection (Trimmed to 18 V). Power MOSFET source and circuit ground reference. Power MOSFET drain. Also used by the internal high voltage current source during the start-up phase to charge the external VDD capacitor. Input of the current mode structure, and output of the internal error amplifier. Allows the setting of thedynamic characteristic of the converter through an external passive network. The useful voltage range extends from 0.5V to 4.5V. The Power MOSFET is always off below 0.5V, and the overload protection is triggered if the voltage exceeds 4.35V. This action is delayed by the timing capacitor connected tothe TOVL pin. Allows the connection of an external capacitor for delaying the overload protection, which is triggered by a voltage on the COMP pin higher than 4.35V. Allows the setting of the switching frequency through an external Rt-Ct network.
VDD
SOURCE DRAIN
COMP
TOVL OSC
8/36
VIPer53 - E
Operation pictures
4
Operation pictures
Figure 3.
ID
C<
Rise and fall time
t VDS
90% tfv trv
T OVL COMP SOURCE OSC 15V VDD DRAIN
300V
10%
t
Figure 4.
Overloaded event
V DD
Normal operation Abnormal operation
VDDon VDDoff
VCOMP
VDIFFovl
V TOV L
VOVLth tOVL
V DS
Not switching
Switching
9/36
Operation pictures
VIPer53 - E
Figure 5.
IDD
IDD0
Start-up VDD current
Figure 6.
tb
tb1
Blanking time
VDDhyst
VDDoff IDDch2
VDDon
VD D
VDS = 100 V FSW = 0 kHz
IDDch1
tb2
VCOMPbl
VCOMPhi
Figure 7.
Tj
TS D
TSD-THYST
Thermal shutdown
Figure 8.
VDD
VDDovp
Overvoltage event
VDD
VDDon
VCOMP
Abnormal operation
Automatic startup
VCOMP
VD S
Not switching
Switching
10/36
VIPer53 - E Figure 9.
VOSC
VOSChi VOSClo
Operation pictures Shutdown action Figure 10. Comp pin gain and offset
IDpeak
t
VCOMP
IDlim IDmax Slope = 1 / HCOMP
VCOMPoff
t
ID
VCOMP
VCOMPos VCOMPovl VCOMPhi
t
Figure 11. Output characteristics
ICOMP
ICOMPhi Slope = Gm
0
V DDreg
VDD
ICOMPlo
11/36
Operation pictures Figure 12. Oscillator schematic
Vcc
VIPer53 - E
Rt
VDD
O SC
PW M section 320
Ct
SOURCE
The switching frequency settings shown on the graphic here below is valid within the following boundaries: Rt > 2k FSW = 300kHz Figure 13. Oscillator settings Frequency (kHz)
300
2 .2 n F
4 .7 n F
1nF
10 0
10nF
22n F
10 1 10 100
R T (K )
12/36
VIPer53 - E Figure 14. Error amplifier test cpfiguration
Vin VDD DRAIN
Operation pictures
O SC 15V
TOVL
COMP
SOURCE Vout
R
2.5 V
This configuration is for test purpose only. In order to insure a correct stability of the error amplifier, a capacitor of 10nF (minimum value: 8nF) should be always connected between COMP pin and ground. See figures Figure 18, 19 and 22. Figure 15. Error amplifier transfer function
G ain (dB)
60
O pe n
40
R = 10 k
20
R = 2.2 k
0
R = 470
-2 0
-4 0
-6 0
1
10
100
1k
10 k
10 0 k
1M
1 0M
F requency (Hz)
13/36
Operation pictures Figure 16. Typical frequency variation vs. junction temperature
VIPer53 - E
N o rm alised Frequency
1.04
1.02
1
0.98
0.96 -20 0 20 40 60 80 100 1 20
Tem perature (C)
Figure 17. Typical current limitation vs. junction temperature
N orm alised IDlim
1.04
1.02
1
0.98
0.96 -2 0 0 20 40 60 80 1 00 1 20
Tem perature (C)
14/36
VIPer53 - E
Primary regulation configuration example
5
Primary regulation configuration example
Figure 18. Off line power supply with auxiliary supply feedback
F1
A C IN
C1
D1 T1
R1
C2
R2 C3 T2 D2
L1 D4 R4 U1 V IP er73 R3 VDD DRA IN C10 D3 C8 C9 DC OUT
OS C 15V
C4
TOV L
COMP
S OURCE
R6 1k C5 C11 10nF C6
R5
C7
The schematic on Figure 18 delivers a fixed output voltage by using the internal error amplifier of the device in a primary feedback configuration. The primary auxiliary winding provides a voltage to the VDD pin, and is automatically regulated at 15V, due to the internal error amplifier connected to this pin. The secondary voltage has to be adjusted through the turn ratio of the transformer between auxiliary and secondary. The error amplifier of the VIPer53 is a transconductance type: its output is a current proportional to the difference of voltage between the VDD pin and the internally trimmed 15V reference (i.e., the error voltage). As the transconductance value is set at a relatively low value to control the overall loop gain and ensure stability, this current has to be integrated by a capacitor (C7 in Figure 18). When the steady state operation is reached, this capacitor blocks any DC current from the COMP pin and imposes a "nil" error voltage. Therefore, the VDD voltage is accurately regulated to 15V. This results in a good load regulation, which depends only on transformer coupling and output diodes impedance. The current mode structure takes care of all incoming voltage changes, thus providing at the same time an excellent line regulation.
15/36
Primary regulation configuration example
VIPer53 - E
The switching frequency can be set to any value through the choice of R3 and C5. This allows to optimize the efficiency of the converter by adopting the best compromise between switching losses, EMI (Lower with low switching frequencies) and transformer size (Smaller with high switching frequencies). For an output power of a few watts, typical switching frequencies between 20kHz and 40kHz because of the small size of the transformer. For higher power, 70kHz to 130kHz are generally chosen. The R5 compensation resistor value sets the dynamic behavior of the converter. It can be adjusted to provide the best compromise between stability and recovery time with fast load changes.
16/36
VIPer53 - E
Secondary feedback configuration example
6
Secondary feedback configuration example
Figure 19. Off line power supply with optocoupler feedback
F1
AC IN
C1
D1 T1
R1
C2
R2 C3 T2 D2
L1 D4 R4 U1 VIPe r73 R3 VD D D RAIN C 10 D3 C8 C9 D C OUT
OSC 15V R8 C4 TOVL C OMP SOU R CE U2
C5
R9 1k
C 11 1 0n F
R5
C6
C7
C12 R7 U3 R6
When a more accurate output voltage is needed, the way is to monitor it directly secondary side, and drive the PWM controller through an optocoupler as shown on Figure 17. The optocoupler is connected in parallel with the compensation network on the COMP pin. The design of the auxiliary winding that the VDD voltage is always lower than the internal 15V reference. The internal error amplifier will therefore be saturated in the high state, and because of its transconductance nature, will deliver a constant biasing current of 0.6mA to the optotransistor. This current does not depend on the compensation voltage, and so it does not depend on the output load either. Consequently, the gain of the optocoupler ensures consequently a constant biasing of the TL431 device (U3) which is in charge of secondary regulation. If the optocoupler gain is sufficiently low, no additional components are required to ensure a minimum current biasing of U3. Also, the low biasing current value avoid any ageing of the optocoupler. The constant current biasing can be used to simplify the secondary circuit: Instead of a TL431, a simple zener and resistance network in series with the optocoupler diode can insure a good secondary regulation. As the current flowing in this branch remains constant for the same reason as above, typical load regulation of 1% can be achieved from zero to full output current with this simple configuration.
17/36
Secondary feedback configuration example
VIPer53 - E
Since the dynamic characteristics of the converter are set on the secondary side through components associated to U3, the compensation network has only a role of gain stabilization for the optocoupler, and its value can be freely chosen. R5 can be set to a fixed value of 1k offering the possibility of using C7 as a soft start capacitor: When starting up , the converter, the VIPer53 device delivers a constant current of 0.6 mA on the COMP pin, creating a constant voltage of 0.6V in R5 and a rising slope across C7. This voltage shape, together with the operating range of 0.5V to 4.5V provides a soft start-up of the converter. The rising speed of the output voltage can be set through the value of C7. The C4 and C6 values must be adjusted accordingly in order to ensure a correct start-up.
18/36
VIPer53 - E
Current mode topology
7
Current mode topology
The VIPer53-E implements the conventional current mode control method for regulating the output voltage. This kind of feedback includes two nested regulation loops: The inner loop controls the peak primary current cycle by cycle. When the Power MOSFET output transistor is on, the inductor current (primary side of the transformer) is monitored with a SenseFET technique and converted into a voltage. When VS reaches VCOMP, the power switch is turned off. This structure is completely integrated as shown on the Block Diagram on page 1, with the current amplifier, the PWM comparator, the blanking time function and the PWM latch. The following formula gives the peak current in the Power MOSFET according to the compensation voltage: Equation 1
VC P VC O M P o I D p e a k = --------O-M---------------------------------s -----HC O M P
The outer loop defines the level at which the inner loop regulates peak current in the power switch. For this purpose, VCOMP is driven by the feedback network (TL431 through an optocoupler in secondary feedback configuration, see Figure 19 on page 17) and is sets accordingly the peak drain current for each switching cycle. As the inner loop regulates the peak primary current in the primary side of the transformer, all input voltage changes are compensated for before impacting the output voltage. This results in an improved line regulation, instantaneous correction to line changes, and better stability for the voltage regulation loop. Current mode topology also provides a good converter start-up control. The compensation voltage can be controlled to increase slowly during the start-up phase, so the peak primary current will follow this soft voltage slope to provide a smooth output voltage rise, without any overshoot. The simpler voltage mode structure which only controls the duty cycle, leads generally to high current at start-up with the risk of transformer saturation. An integrated blanking filter inhibits the PWM comparator output for a short time after the integrated Power MOSFET is switched on. This function prevents anomalous or premature termination of the switching pulse in the case of current spikes caused by primary side transformer capacitance or secondary side rectifier reverse recovery time when working in continuous mode.
19/36
Standby mode
VIPer53 - E
8
Standby mode
The device offers a special feature to address the low load condition. The corresponding function described hereafter consists of reducing the switching frequency by going into burst mode, with the following benefits: It reduces the switching losses, thus providing low consumption on the mains lines. The device is compliant with "Blue Angel" and other similar standards, requiring less than 0.5 W of input power when in standby. It allows the regulation of the output voltage, even if the load corresponds to a duty cycle that the device is not able to generate because of the internal blanking time, and associated minimum turn on. For this purpose, a comparator monitores the COMP pin voltage, and maintains the PWM latch and the Power MOSFET in the Off state as long as VCOMP remains below 0.5V (See Block Diagram on page 1). If the output load requires a duty cycle below the one defined by the minimum turn on of the device, the VCOMP net decreases its voltage until it reaches this 0.5V threshold (VCOMPoff). The Power MOSFET can be completely Off for some cycles, and resumes normal operation as soon as VCOMP is higher than 0.5V. The output voltage is regulated in burst mode. The corresponding ripple is not higher than the nominal one at full load. In addition, the minimum turn on time which defines the frontier between normal operation and burst mode changes according to VCOMP value. Below 1.0V (VCOMPbl), the blanking time increases to 400ns, whereas for higher voltages, it is 150ns Figure 6 on page 10 The minimum turn on times resulting from these values are respectively 600 ns and 350 ns, when taking into account internal propagation time. This brutal change induces an hysteresis between normal operation and burst mode as shown on Figure 20 on page 21. When the output power decreases, the system reaches point 2 where VCOMP equals VCOMPbl. The minimum turn-on time passes immediately from 350ns to 600ns, exceeding the effective turn-on time that should be needed at this output power level. Therefore the regulation loop will quickly drive VCOMP to VCOMPoff (Point 3) in order to pass into burst mode and to control the output voltage. The corresponding hysteresis can be seen on the switching frequency which passes from FSWnom which is the normal switching frequency set by the components connected to the OSC pin and to FSWstby. Note: This frequency is actually an equivalent number of switching pulses per second, rather than a fixed switching frequency since the device is working in burst mode. As long as the power remains below PRST the output of the regulation loop remains stuck at VCOMPsd and the converter works in burst mode. Its "density" increases (i.e. the number of missing cycles decreases) as the power approaches PRST and finally resumes normal operation at point 1. The hysteresis cannot be seen on the switching frequency, but it can be seen in the sudden surge of the COMP pin voltage from point 3 to point 1 at that power level. The power points value PRST and PSTBY are defined by the following formulas: Equation 2
2 1 1 2 P R S T = -- · F S W n o m · ( t b 1 + t d ) · V I N · -----Lp 2
20/36
VIPer53 - E Equation 3
1 2 P S T B Y = -- · F S W n o m · I p ( V C O M P b l ) · L p 2
Standby mode
Where Ip(VCOMPbl2) is the peak Power MOSFET current corresponding to a compensation voltage of VCOMPbl (1V). Note: The power point PSTBY where the converter is going into burst mode does not depend on the input voltage. The standby frequency FSWstby is given by: Equation 4
PS T B Y P S W s t b y = ---------------- · F S W n o m PR S T
The ratio between the nominal and standby switching frequencies can be as high as 4, depending on the Lp value and input voltage. Figure 20. Standby mode implementation
ton
600ns Minimum turn on 350ns 3 1 2
VCOMP
VCOMPsd VCOMPoff VCOMPbl
PIN
PRST 3 PSTBY FSWstby 2 1
FSW
FSWnom
21/36
High voltage Start-up current source
VIPer53 - E
9
High voltage Start-up current source
An integrated high voltage current source provides a bias current from the DRAIN pin during the start-up phase. This current is partially absorbed by internal control circuits in standby mode with reduced consumption, and also supplies the external capacitor connected to the VDD pin. As soon as the voltage on this pin reaches the high voltage threshold VDDon of the UVLO logic, the device turns into active mode and starts switching. The start-up current generator is switched off, and the converter should normally provide the needed current on the VDD pin through the auxiliary winding of the transformer, as shown on Figure 19 on page 17. The external capacitor CVDD on the VDD pin must be sized according to the time needed by the converter to start-up, when the device starts switching. This time tss depends on many parameters, including transformer design, output capacitors, soft start feature, and compensation network implemented on the COMP pin and possible secondary feedback circuit. The following formula can be used for defining the minimum capacitor needed: Equation 5
ID D 1 t s s C V D D > -------------------------VD D h y s t
Figure 21 on page 23 shows a typical start-up event. VDD starts from 0V with a charging current IDDch1 at about 9 mA. When about VDDoff is reached, the charging current is reduced down to IDDch2 which is about 0.6mA. This lower current leads to a slope change on the VDD rise. Device starts switching for VDD equal to VDDon, and the auxiliary winding delivers some energy to VDD capacitor after the start-up time tss. The charging current change at VDDoff allows a fast complete start-up time tSDU, and maintains a low restart duty cycle. This is especially useful for short circuits and overloads conditions, as described in the following section.
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VIPer53 - E Figure 21. Start-up waveforms
High voltage Start-up current source
ID D
IDD1
t
IDDch2
IDDch1
VDD
VDDreg VDDst VDDsd tSU
tSS
t
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Short-circuit and overload protection
VIPer53 - E
10
Short-circuit and overload protection
A VCOMPovl threshold of about 4.35V has been implemented on the COMP pin. When VCOMP goes above this level, the capacitor connected on the TOVL pin begins to charge. When reaching typically VOVLth (4V), the internal MOSFET driver is disabled and the device stops switching. This state is latched because of to the regulation loop which maintains the COMP pin voltage above the VCOMPovl threshold. Since the VDD pin does not receive any more energy from the auxiliary winding, its voltage drops down until it reaches VDDoff and the device is reset, recharging the VDD capacitor for a new restart cycle. Note: If VCOMP drops below the VCOMPovl threshold for any reason during the VDD drop, the device resumes switching immediately. The device enters an endless restart sequence if the overload or short circuit condition is maintained. The restart duty cycle DRST is defined as the time ratio for which the device tries to restart, thus delivering its full power capability to the output. In order to keep the whole converter in a safe state during this event, DRST must be kept as low as possible, without compromising the real start-up of the converter. A typical value of about 10% is generally sufficient. For this purpose, both VDD and TOVL capacitors can be used to satisfy the following conditions: Equation 6
C O V L > 12.5 10
6
tss
Equation 7
CO V L ID D c h 2 4 1 C V D D > 8 10 ------------- 1 -------------------------------------D VD D h y s t RST
Refer to the previous start-up section for the definition of tss, and CVDD must also be checked against the limit given in this section. The maximum value of the two calculus will be adopted. All this behavior can be observed on Figure 8 on page 10. In Figure 10 on page 11 the value of the drain current Id for VCOMP = VCOMPovl is shown. The corresponding parameter IDmax is the drain current to take into account for design purposes. Since IDmax represents the maximum value for which the overload protection is not triggered, it defines the power capability of the power supply.
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VIPer53 - E
Transconductance error amplifier
11
Transconductance error amplifier
The VIPer53-E includes a transconductance error amplifier. Transconductance Gm is the change in output current ICOMP versus change in input voltage VDD. Thus: Equation 8
I O M Gm = -----C---------P --- -V D D
The output impedance ZCOMP at the output of this amplifier (COMP pin) can be defined as: Equation 9
V C O M P VC O M P 1 Z C O M P = --------------------- = --------- --------------------I C O M P G m V D D
This last equation shows that the open loop gain AVOL can be related to Gm and ZCOMP: Equation 10
AV O L = G m ZC O M P
where Gm value for VIPer53 is typically 1.4mA/V. Gm is well defined by specification, but ZCOMP, and therefore AVOL, are subject to large tolerances. An impedance Z must be connected between the COMP pin and ground in order to accurately define the transfer function F of the error amplifier, the following equation, very similar to the one above: Equation 11
F(s ) = Gm Z( s)
The error amplifier frequency response is shown in .0 for different values of a simple resistance connected on the COMP pin. The unloaded transconductance error amplifier shows an internal ZCOMP of about 140K More complex impedances can be connected on . the COMP pin to achieve different compensation methods. A capacitor provides an integrator function, thus eliminating the DC static error, and a resistance in series leads to a flat gain at higher frequency, introducing a zero level and ensuring a correct phase margin. This configuration illustrated in Figure 22, for the schematic and Figure 23 on page 28 for the error amplifier transfer function for a typical set of values of CCOMP and RCOMP. Note that a 10nF capacitor (8nF, minimum value) should always be connected to the COMP pin to ensure a correct stability of the internal error amplifier. The complete converter open loop transfer function can be built from both power cell and error amplifier transfer functions. A theoretical example can be seen in Figure 24 for a discontinuous mode flyback loaded by a simple resistor, regulated from primary side (no
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Transconductance error amplifier
VIPer53 - E
optocoupler, the internal error amplifier is fully used for regulation). A typical schematic corresponding to this situation can be seen on Figure 18. The transfer function of the power cell is represented as G(s) in Figure 24 Iexhibits a pole which depends on the output load and on the output capacitor value. As the load of a converter may change, two curves are shown for two different values of output resistance value, RL1 and RL2. A zero at higher frequency values then appears, due to the output capacitor ESR. Note: The overall transfer function does not depend on the input voltage because of the current mode control. The error amplifier has a fixed behavior, similar to the one shown in Figure 23. Its bandwidth is to avoid injection of high frequency noise in the current mode section. A zero due to the RCOMP-CCOMP network is set at the same value as the maximum load RL2 pole. The total transfer function is shown as F(s). G(s) at the bottom of Figure 24. For maximum load (plain line), the load pole is exactly compensated by the zero of the error amplifier, and the result is a perfect first order decreasing until it reaches the zero of the output capacitor ESR. The error amplifier cut-off then definitely any further spurious noise or resonance from disturbing the regulation loop. The point where the complete transfer function has a unity gain is known as the regulation bandwidth and has: The higher it is, the faster the reaction will be to an eventual load change, and the smaller the output voltage change will be. The phase shift in the complete system at this point has to be less than 135 to ensure good stability. Generally, a first-order slope gives 90 of phase shift, and a second-order gives 180.
In Figure 24, the unity gain is reached in a first order slope, so the stability is ensured. The dynamic load regulation is improved by increasing the regulation bandwidth, but some limitations have to be respected: As the transfer function above the zero due the capacitor ESR is not reliable (The ESR itself is not well specified, and other parasitic effects may take place), the bandwidth should always be lower than the minimum of FC and ESR zero. As the highest bandwidth is obtained with the highest output power (Plain line with RL2 load in Figure 24), the above criteria will be checked for this condition and allows to define the value of RCOMP, as the error amplifier gain depends only on this value for this frequency range. The following formula can be derived: Equation 12
RC O M P =
2
PO U T 2 F B W 2 RL 2 CO U T ---------------- ----------------------------------------------------Gm PM A X 1 2 and: PM A X = -- L P I L I M F S W 2
OU With: PO U T 2 = ------------T --
V RL 2
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VIPer53 - E
Transconductance error amplifier The lowest load gives another condition for stability: The frequency FBW1 must not encounter the second order slope generated by the load pole and the integrator part of the error amplifier. This condition can be met by adjusting the CCOMP value: Equation 13
RL 1 CO U T C C O M P > ----------------------------------------------------- 2 6.3 G m R C O M P PO U T 1 -----------------PM A X
With:
2 VO U T P O U T 1 = --------------RL 1
The above formula gives a minimum value for CCOMP. It can be then increased to provide a natural soft start function as this capacitor is charged by the error amplifier current capacity ICOMPhi at start-up. Figure 22. Typical compensation network
VDD
DRAIN
OSC 15V
TOVL
COMP
SOURCE
Rcomp 10nF
Ccomp
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Transconductance error amplifier Figure 23. Typical transfer functions
Gain (dB)
60
R com p= 4.7k C com p= 47 0n F
VIPer53 - E
50 40 30 20 10 0 -1 0 1 10 10 0 1k 10k 10 0k 1M
Phase ()
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -1 00 1 10
Frequency (Hz)
R com p= 4.7k C com p= 47 0n F
1 00
1k
1 0k
100k
1M
Frequency (Hz)
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VIPer53 - E Figure 24. Complete converter transfer function
Transconductance error amplifier
G(S)
1 --------------------------------------------- R C L1 OUT
1 --------------------------------------------- R C L2 OUT
F
1
1 ----------------------------------------------------------2 ESR C OUT
F(S )
1 --------------------------------------------------------------------------2 R C COMP COMP
FC
F
1
F(S).G(S)
1
FBW2 FBW1
F
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Special recommendations
VIPer53 - E
12
Special recommendations
As steted in the error amplifier section, a capacitor of 10nF capacitor (minimum value: 8nF) should always be connected to the COMP pin to ensure correct stability of the internal error amplifier Figure 18, 19 and 22. In order to improve the ruggedness of the device versus eventual drain overvoltages, a resistance of 1k should be inserted in series with the TOVL pin, as shown on Figure 18, Figure 19 on page 17. Note that, this resistance does not impact the overload delay, as its value is negligible prior to the internal pull-up resistance (about 125k).
13
Software implementation
All the above considerations and some others are included included in ST design software which provides all of the needed components around the VIPer device for specified output configurations, and is available on www.st.com.
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VIPer53 - E
Package mechanical data
14
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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Package mechanical data
VIPer53 - E
Table 11.
DIP8 mechanical data
Dimensions Databook (mm) Ref. Nom. A A1 A2 b b2 c D E E1 e eA eB L 2.92 3.30 Gr. 470 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 3.30 0.46 1.52 0.25 9.27 7.87 6.35 2.54 7.62 10.92 3.81 4.95 0.56 1.78 0.36 10.16 8.26 7.11 Min Max 5.33
Package Weight
Figure 25. Package dimensions
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VIPer53 - E Table 12. PowerSO-10 mechanical data
Dimensions
Package mechanical data
Databook (mm) Ref. Nom. A A1 B c D D1 E E1 E2 E3 E4 e F H h L q 0 1.20 1.70 8 1.25 13.80 0.50 1.80 3.35 0.00 0.40 0.35 9.40 7.40 9.30 7.20 7.20 6.10 5.90 1.27 1.35 14.40 Min Max 3.65 0.10 0.60 0.55 9.60 7.60 9.50 7.40 7.60 6.35 6.10
Figure 26. Package dimensions
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Order codes
VIPer53 - E
15
Order codes
Table 13. Order codes
Package DIP-8 PowerSO-10 PowerSO-10 Shipment Tube Tube Tape and reel
Part Number VIPer53DIP-E VIPer53SP-E VIPer53SPTR - E
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VIPer53 - E
Revision history
16
Revision history
Table 14.
Date 13-Nov-2006
Revision history
Revision 1 Initial release. Changes
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VIPer53 - E
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