STA2416
Bluetooth technology baseband transceiver with integrated Flash memory
Features
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Bluetooth specification V1.1, V1.2 compliant Software compatible with STLC2416 2-layer class-4 PCB compatible Point-to-point, point-to-multi-point (up to 7 slaves) and scatternet capability Asynchronous connection-less (ACL) logical transport link Synchronous connection oriented (SCO) links: 2 simultaneous SCO channels Supports pitch-period error concealment (PPEC) Improves speech quality in the vicinity of interference Improves coexistence with WLAN Works at receiver, no Bluetooth implication Adaptive frequency hopping (AFH): hopping kernel, channel assessment as master and as slave Faster connection: interlaced scan for page and inquiry scan, first FHS without random backoff, RSSI used to limit range Extended SCO (eSCO) links Standard BlueRF bus interface QoS flush Clock support System clock input: 13 MHz (20 ppm if shared with Bluetooth RF chipset LPO clock input at 3.2 and 32 kHz or via the embedded 32 kHz crystal oscillator cell ARM7TDMI 32-bit CPU Memory Integrated 4-Mbit Flash
Order code STA2416 Package
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LFBGA120 (10x10x1.4 mm)
64-KByte on-chip RAM 4-KByte on-chip boot ROM Low power architecture with sleep mode Hardware support for packet types ACL: DM1, 3, 5 and DH1, 3, 5 SCO: HV1, 3 and DV eSCO: EV3, 5 Communication interfaces Synchronous serial interface, supporting up to 32-bit data Two enhanced 16550 UARTs with 128-byte FIFO depth 12 Mbit/s USB interface Fast master I2C bus interface Multi slot PCM interface 15 programmable GPIOs 2 external interrupts and various interrupt possibilities through other interfaces 32 kHz clock out Efficient support for WLAN coexistence Ciphering support for up to 128-bit key Receiver signal strength indication (RSSI) support for power-controlled links Separate control for external power amplifier (PA) for class-1 power support Software support: low level (up to HCI) stack or embedded stack with profiles Suppor t of UART and USB HCI transport layers.
Packaging Tube
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Table 1. Device summary
LFBGA120 (10x10x1.4mm)
February 2008
Rev 2
1/40
www.st.com 1
Contents
STA2416
Contents
1 2 Application features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin description and assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 3.2 3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 I/O specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.1 3.3.2 Specifications for 3.3-V I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Specifications for 1.8-V I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4
Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1 Baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1.1 4.1.2 Baseband 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Baseband 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2
Integrated Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2.1 Flash signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5
General specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 System clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.1 Slow clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Boot procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Master reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Interrupts/wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 V1.2 detailed functions - extended SCO . . . . . . . . . . . . . . . . . . . . . . . . . 23 V1.2 detailed functions - adaptive frequency hopping . . . . . . . . . . . . . . . 24 V1.2 detailed functions - faster connection . . . . . . . . . . . . . . . . . . . . . . . 24 V1.2 detailed functions - quality of service . . . . . . . . . . . . . . . . . . . . . . . . 25
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STA2416
Contents
5.10
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.10.1 5.10.2 5.10.3 5.10.4 Sniff or park . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Inquir y/page scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 No connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Active link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.11 5.12
Software initiated low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Bluetooth, WLAN coexisting in collocated scenario . . . . . . . . . . . . . . . . 26
5.12.1 5.12.2 5.12.3 5.12.4 5.12.5 Algorithm 1: packet traffic arbitration (PTA) . . . . . . . . . . . . . . . . . . . . . . 27 Algorithm 2: WLAN master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Algorithm 3: Bluetooth master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Algorithm 4: two-wire mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Algorithm 5: alternating wireless medium access (AWMA) . . . . . . . . . . 28
6
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1 6.2 UART interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Synchronous serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2.1 6.2.2 Feature description: Agilent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Feature description: 32-bit SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3 6.4 6.5 6.6 6.7 6.8
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 RF interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PCM voice interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Applications examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7
HCI-UART transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1 UART settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8 9 10 11
HCI-USB transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Class-1 power support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 38
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Contents
STA2416
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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STA2416
List of tables
List of tables
Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 LVTTL DC input specification (3V < VDDIO < 3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 LVTTL DC output specification (3V < VDDIO < 3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DC input specification (1.55V < VDD < 1.95V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DC output specification (1.55V < VDD < 1.95V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Typical power consumption (VDD = VDDF = VDDPLL = 1.8V, VDDIO = 3.3V) . . . . . . . . . . . . 18 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 WLAN hardware signal assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 List of supported baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PCM interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 GPIOs alternative functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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List of figures
STA2416
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Bluetooth technology applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin out (top view (PCB top side)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 eSCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AFH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Algorithm 1: PTA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Algorithm 2: WLAN master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Algorithm 3: Bluetooth master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Agilent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PCM (A-law, -law) standard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Linear mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PCM interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Bluetooth technology v1.2 application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Bluetooth technology v2.0 application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 UART transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 LFBGA120 (10x10x1.4mm) mechanical data and package dimensions . . . . . . . . . . . . . . 37
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STA2416
Application features
1
Application features
Typical applications in which the STA2416 can be used are:
" " " " " " "
serial or audio cable replacement (SPP or A2DP profile) por table computers, PDA handheld data transfer devices computer peripherals other devices that require wireless communication using Bluetooth technology software host for ST single chip STLC2500x audio applications include: wireless audio Bluetooth extensions for cradles and home-audio systems wireless speakers for, for example, TV, STB and LCDPDP displays indoor multi-room audio diffusion with remote speaker sets headsets and headphones wireless transmitters.
When used in Bluetooth applications the STA2416 can support two different partitionings.
" "
Bluetooth v1.2 (basic rate): STLC2150 + STA2416. A dedicated customer framework SDK (CFW) can be provided by STM to customers needing to develop their own code. Bluetooth v2.0 (enhanced data rate): STLC2500x + STA2416. In this case please refer to the CFWLite SDK. Bluetooth technology applications
GPIO UARTs JTAG
Figure 1.
BlueRF
SPI
STLC2150
13 MHz 13 MHz 12 pF 12 pF 22 pF XIN
STA2416
I2C PCM
STLC2150 + STA2416 par titioning for Bluetooth v1.2 solution
32 kHz RST 22 pF
GPIO UART1 JTAG
STLC2500x
REF_CLK_IN PCM
UART2 HCI link XIN
SPI
STA2416
I2C
STLC2500 + STA2416 par titioning for Bluetooth v2.0 solution
32 kHz RST Osc 13 MHz 22 pF 22 pF
Both CFW and CFWLite are provided by STM free of charge and include all the required software drivers to easily operate with the device I/O peripherals, a proprietary multi-tasking RTOS, all required Bluetooth lower layers to communicate with the RF/HCI front-end and a complete offering of APIs to access and control device functions. STM provides support for full Bluetooth stack integration as well as complete and pre-configured solutions for both audio and SPP applications. Contact your STM representative for more information.
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Description
STA2416
2
Description
The STA2416 from STMicroelectronics is a Bluetooth technology baseband controller with integrated 4-Mbit Flash memory. Together with a Bluetooth radio this product offers a compact and complete solution for short-range wireless connectivity. It incorporates all the lower layer functions of the Bluetooth protocol. The microcontroller allows the support of all data packets of Bluetooth transmission in addition to voice. The embedded controller can be used to run the Bluetooth protocol and application layers if required. The software is located in the integrated Flash memory.
2.1
Figure 2.
Block diagram
Block diagram
JTAG
5 VDD 100nF INTERRUPT CONTROLLER
PCM
4 2
PCM EXT._INT1/2
VDDIO 100nF
USB
2
USB
I2C VDDIO 100nF ARM7 TDMI 13 RADIO I/F BLUETOOTH CORE D M A APB BRIDGE SPI
2
I2C
4
SPI
RF BUS
TIMER
GPIO
15
GPIO(0..9)(11...15)
LPOCLKOUT (*) 22pF LPOCLKP Y2 32kHz 22pF LPOCLKN LPO
RAM
START DETECT
UART
8
UART2
BOOT ROM
UART FIFO
UART
2
UART1
SYSTEM CONTROL DATA(0..15) ADDR(0..19) EMI WRN RDN CSN(0) 1 1 20 18 16 16 DATA(0..15) ADDR(1..18) NW NG NE
2
NRESET SYS_CLK_REQ
VDD
VDDPLL
100nF
4Mbit FLASH
VDD 100nF
1 XIN BOOT
2 CSN(1..2)
1
5
16
1
1 NRP (**) NWP
D05AU1623
RDN/NG ADDR DATA(0..15) (0,2,17,18,19)
CSN(0)
NE
(*) If a low-power clock is available, it can be connected to the LPOCLKP pin in stead of using a crystal (**) For device testing only (should not be connected in the application.
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STA2416
Description
2.2
Pin description
Figure 3.
18
Pin out (top view (PCB top side))
17 16 15 14 13 12 11 10
USB _DN
9
8
7
6
5
V DD _IO
4
VDD
3
VSS
2
SPI _FRM
1
SPI _CLK
NRESET NRP
UART1 UART1 I2C _RXD _TXD _DAT
I2C P CM P CM _CLK _SYNC _A
UART2 UART2 UART2 UART2 _RXD _TXD _I1 _O2
A
XIN SYS_ CLK_REQ TCK VDD _IO VSS _IO P CM _CLK PCM _B US B _ DP UART2 UART2 UART2 UART2 _I2 _O1 _IO1 _IO2 VSS _IO RDN / NG SPI_TXD
B
N.C. INT2 INT1 SPI_RXD
C
VSS_IO NE CSN1
D
TDO TMS CS N0 CSN2
E
NTRST TDI A DDR0 VDD
F
BTXEN VDD_IO N.C. VSS
G
BRXEN ANT_SW NW P ADDR2
H
BPKTCTL BPAEN VPP VDD
J
BTXD BDCLK VDD_F VSS
K
BRCLK BMOSI VSS_F A DDR17
L
BRXD BMISO VDD_Q A DDR18
M
BSEN BNDEN N.C. A DDR19
N
GPIO12 LPO_ CLK_OUT GPIO11 GPIO14 N.C. DATA0
P
GPIO15 DATA3 VSS _IO V DD _IO DATA1
R
VSS GPIO13 _PLL GPIO3 GPIO1 BOOT VSS VDD DATA8 DATA7 DATA6 DATA5 DATA4 DATA2
T
VDD
GPIO9 V DD _PLL LPO_ LPO_ GPIO5 GPIO4 GPIO2 GPIO0 CLK_N CLK_P DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9
U
GPIO8 GPIO7 GPIO6 VSS
V
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Description
STA2416
2.3
Pin description and assignment
Table 2 shows the pin list of the STA2416. There are 91 functional pins of which 25 are used for device testing only (should not be connected in the application) and 24 supply pins. The column headed PU/PD shows the pads which implement an optional internal weak pull-up or pull-down to set the logical level of the pin if left unconnected. The pads are grouped according to two different power supply values, as shown in the column headed VDD:
" "
V1 for nominal 3.3 V (2.7 - 3.6 V range) V2 for nominal 1.8 V (1.55 - 1.95 V range) I for inputs O for outputs I/O for input/outputs O/T for 3-state outputs
Finally the column headed DIR describes the pin directions:
" " " "
Table 2.
Name
Pin list
Pin # Description DIR PU/ VDD PD PAD
(
Clock and test pins XIN NRESET NRP NWP SYS_CLK_REQ B18 A18 A17 H3 C18 System clock Reset Flash memory reset Flash memory write protect System clock request Low-power mode oscillator + (slow clock input) Low-power mode oscillator 32 MHz clock out External interrupt used also as external walk-up Second external interrupt Select external boot from EMI or internal from ROM I V1 I I I I/O V2 V2 V1 CMOS 1.8V CMOS, 3.3V TTL compatible, 2mA, 3-state, slew rate control CMOS, 3.3V TTL compatible, schmitt trigger
LPO_CLK_P LPO_CLK_N LPO_CLK_OUT INT1 INT2 BOOT
V9 V10 R18 C14 C15 T10
I V2 O O I I I
(1)
V1 CMOS, 3.3V TTL compatible, schmitt trigger
V1
(1) (1)
V2
CMOS 1.8V
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STA2416 Table 2.
Name SPI interface SPI_FRM SPI_CLK SPI_TXD SPI_RXD UART interface UAR T1_TXD UAR T1_RXD UAR T2_O1 UAR T2_O2 UAR T2_I1 UAR T2_I2 UAR T2_IO1 UAR T2_IO2 UAR T2_TXD UAR T2_RXD I2C interface I2C_DAT I2C_CLK USB interface USB_DN USB_DP A10 C9 USB - pin (Needs a series resistor of 27 5%) USB + pin (Needs a series resistor of 27 5%) I/O I/O
(1)
Description Pin list (continued)
Pin # Description DIR PU/ VDD PD PAD
A2 A1 B1 C1
Synchronous serial interface frame sync Synchronous serial interface clock Synchronous serial interface transmit data Synchronous serial interface receive data
I/O V1 I/O O/t I
(1)
CMOS, 3.3V TTL compatible, 2mA, 3-state, slew rate control, schmitt trigger CMOS, 3.3V TTL compatible, 2mA, slew rate control CMOS, 3.3V TTL compatible, schmitt trigger
V1 V1
A15 A16 C7 A6 A7 C8 C6 C5 A8 A9
UART1 transmit data UART1 receive data UART2 modem output UART2 modem output UART2 modem input UART2 modem input UART2 modem input/output UAR T2 modem input/output UAR T2 transmit data UAR T2 receive data
O/t I O O/t I I I/O I/O O/t I
(2) (2) (2) (2) (2) (2)
V1 V1 V1 V1 V1
CMOS, 3.3V TTL compatible, 2mA, slew rate control CMOS, 3.3V TTL compatible, schmitt trigger CMOS, 3.3V TTL compatible, 2mA, slew rate control CMOS, 3.3V TTL compatible, 2mA, slew rate control CMOS, 3.3V TTL compatible
V1 V1 V1 V1 V1 CMOS, 3.3V TTL compatible, 2mA, 3-state, slew rate control CMOS, 3.3V TTL compatible, 2mA, slew rate control CMOS, 3.3V TTL compatible
A14 A13
I2C data pin I2 C clock pin
I/O I/O
(3) (3)
V1 V1
CMOS, 3.3V TTL compatible, 2mA, 3-state, slew rate control
V1 V1
(1)
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Description Table 2.
Name GPIO interface GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 JTAG interface NTRST TCK TMS TDI TDO PCM interface PCM_A PCM_B PCM_SYNC PCM_CLK A11 C10 A12 C11 PCM data PCM data PCM 8 kHz sync PCM clock I/O I/O I/O I/O PD PD PD PD V1 V1 F18 D18 E16 F16 E18 JTAG pin JTAG pin JTAG pin JTAG pin JTAG pin (should be left open) I I I I O/T PD
(1)
STA2416 Pin list (continued)
Pin # Description DIR PU/ VDD PD PAD
V11 T11 V12 T12 V13 V14 V16 V17 V18 U18 T18 P18 T16 P16 R16
GPIO port 0 GPIO port 1 GPIO port 2 GPIO port 3 GPO port 4 GPO port 5 GPO port 6 GPO port 7 GPO port 8 GPO port 9 GPO port 11 GPO port 12 GPO port 13 GPO port 14 GPO port 15
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
PU PU PU PU PU PU V1 PU PU PU PU PU PU PU PU PU V1 V1 V1
CMOS, 3.3V TTL compatible, 4mA, 3-state, slew rate control CMOS, 3.3V TTL compatible, 4mA, 3-state, slew rate control, schmitt trigger CMOS, 3.3V TTL compatible, 4mA, 3-state, slew rate control
CMOS, 3.3V TTL compatible, 2mA, 3-state, slew rate control
V1 V1
CMOS, 3.3V TTL compatible CMOS, 3.3V TTL compatible, schmitt trigger CMOS, 3.3V TTL compatible CMOS, 3.3V TTL compatible, 2mA, slew rate control
PU V1 PU V1
CMOS, 3.3V TTL compatible, 2mA, 3-state, slew rate control CMOS, 3.3V TTL compatible, 2mA, 3-state, slew rate control, schmitt trigger
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STA2416 Table 2.
Name Radio interface BRCLK BRXD BMISO BNDEN BMOSI BDCLK BTXD BSEN BPAEN BRXEN BTXEN BPKTCTL ANT_SW Power supply VSS_PLL VDD_PLL VDD VDD VDD VDD VDD VDD_F VDD_Q VPP VDD_IO VDD_IO VDD_IO VDD_IO T15 V15 A4 F1 J1 U1 T8 K3 M3 J3 C13 A5 T13 G16 PLL ground 1.8V supply for PLL 1.8V digital supply 1.8V digital supply 1.8V digital supply 1.8V digital supply 1.8V digital supply 1.8V digital supply for Flash memory 1.8V I/O supply for Flash memory 12V fast program supply for Flash memory 3.3V I/O supply 3.3V I/O supply 3.3V I/O supply 3.3V I/O supply L18 M18 M16 N16 L16 K16 K18 N18 J16 H18 G18 J18 H16 Transmit clock Receive data RF serial interface input data RF serial interface control RF serial interface output data RF serial interface clock Transmit data Synthesizer on Open PLL Receive on Transmit on Packet on Antenna switch I I I O O O O O O O O O O V1 V1
(1) (1)
Description Pin list (continued)
Pin # Description DIR PU/ VDD PD PAD
V1 V1
CMOS, 3.3V TTL compatible, schmitt trigger CMOS, 3.3V TTL compatible
CMOS, 3.3V TTL compatible, 2mA, slew rate control
CMOS, 3.3V TTL compatible, 8mA, slew rate control
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Description Table 2.
Name VSS VSS VSS VSS VSS VSS_F VSS_IO VSS_IO VSS_IO VSS_IO
STA2416 Pin list (continued)
Pin # A3 G1 K1 V1 T9 L3 C12 C4 T14 D16 Description Digital ground Digital ground Digital ground Digital ground Digital ground Digital ground for Flash memory I/O ground I/O ground I/O ground I/O ground DIR PU/ VDD PD PAD
To be connected together on the PCB NE CSN0 D3 E3 Flash memory enable External chip select bank 0 I O
Test interface only (do NOT connect) RDN / NG CSN1 CSN2 ADDR0 ADDR2 ADDR17 ADDR18 ADDR19 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 C3 D1 E1 F3 H1 L1 M1 N1 P1 R1 T1 R3 T3 T4 T5 T6 T7 V2 V3 V4 External read External chip select bank 1 External chip select bank 2 External address bit 0 External address bit 2 External address bit 17 External address bit 18 External address bit 19 External data bit 0 External data bit 1 External data bit 2 External data bit 3 External data bit 4 External data bit 5 External data bit 6 External data bit 7 External data bit 8 External data bit 9 External data bit 10 External data bit 11 O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PD PD V2 PD PD PD PD PD PD PD PD PD PD CMOS 1.8V, 4mA, slew rate control
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STA2416 Table 2.
Name DATA12 DATA13 DATA14 DATA15 Not connected C16, G3, Not connected N3, P3
Description Pin list (continued)
Pin # V5 V6 V7 V8 Description External data bit 12 External data bit 13 External data bit 14 External data bit 15 DIR I/O I/O I/O I/O PU/ VDD PD PD PD V2 PD PD CMOS 1.8V, 4mA, slew rate control PAD
N.C.
1. Must be strapped to VSS_IO if not used 2. Must be strapped to VDD_IO if not used 3. Must have a 10 k pull-up
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Quick reference data
STA2416
3
3.1
Quick reference data
Absolute maximum ratings
Operation of the device beyond these maximum ratings is not guaranteed. Sustained exposure to these limits will adversely affect device reliability. Table 3.
Symbol VDD VDDF VPP VDDIO VDDQ VIN Tstg Tlead
Absolute maximum ratings
Conditions Supply voltage baseband core Supply voltage Flash Fast Program Voltage Supply voltage baseband I/O Supply voltage Flash I/O Input voltage on any digital pin (excluding Flash input pins) Storage temperature Lead temperature < 10s VSS - 0.5 VSS - 0.5 -5 5 Min VSS - 0.5 VSS - 0.5 VSS - 0.5 Ma x 2.5 2.5 13 4 2.5 VDDIO + 0.3 +150 +240 Unit V V V V V V C C
3.2
Operating ranges
Operating ranges define the limits for functional operation and parametric characteristics of the device. Operation outside these limits is not implied. Table 4.
Symbol VDD VDDF VDDIO VDDQ Tamb
Operating ranges
Conditions Supply voltage baseband core and EMI pads Supply voltage for Flash memory Supply voltage for digital I/O Supply voltage for Flash memory I/Os (VDDQ VDDF) Operating ambient temperature Min 1.55 1.55 2.7 1.55 -40 Typ 1.8 1.8 3.3 1.8 Max 1.95 1.95 3.6 1.95 +85 Unit V V V V C
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STA2416
Quick reference data
3.3
I/O specifications
The I/O voltage depends on the interface. The voltage is typically 1.8 V for the interface to the Flash memory and typically 3.3 V for all the other interfaces. These I/Os comply with the EIA/JEDEC standard JESD8-B.
3.3.1
Specifications for 3.3-V I/Os
Table 5.
Symbol Vil Vih Vhyst
LVTTL DC input specification (3V < VDDIO < 3.6V)
Parameter Low level input voltage High level input voltage Schmitt trigger hysteresis 2 0.4 Conditions Min Typ Max 0.8 Unit V V V
Table 6.
Symbol Vol Voh
LVTTL DC output specification (3V < VDDIO < 3.6V)
Parameter Low level output voltage High level output voltage Conditions Iol = X mA
(1)
Min
Typ
Max 0.15
Unit V V
Ioh =-X mA (1)
VDDIO - 0.15
1. X is the source/sink current under worst-case conditions according to the drive capability, see Table 2 on page 10 for the value of X.
3.3.2
Specifications for 1.8-V I/Os
Table 7.
Symbol Vil Vih Vhyst
DC input specification (1.55V < VDD < 1.95V)
Parameter Low level input voltage High level input voltage Schmitt trigger hysteresis 0.65 * VDD 0.2 0.3 0.5 Conditions Min Typ Max 0.35 * VDD Unit V V V
Table 8.
Symbol Vol Voh
DC output specification (1.55V < VDD < 1.95V)
Parameter Low level output voltage High level output voltage Conditions Iol = X mA
(1)
Min
Typ
Max 0.15
Unit V V
Ioh =-X mA (1)
VDD - 0.15
1. X is the source/sink current under worst-case conditions according to the drive capability, see Table 2 on page 10 for the value of X.
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Quick reference data
STA2416
3.4
Current consumption
Table 9. Typical power consumption (VDD = VDDF = VDDPLL = 1.8V, VDDIO = 3.3V)
Core STA2416 state Slave Standby (no low-power mode) Standby (low-power mode enabled) ACL connection (no transmission) ACL connection (data transmission) SCO connection (no codec connected) Inquiry and Page scan (low-power mode enabled) Low-power mode (32 kHz crystal) 5.10 0.94 7.60 7.90 8.70 127 20 M aster 5.10 0.94 6.99 7.20 7.90 n.a. 20 0.13 0.13 0.13 0.13 0.14 5 0 mA mA mA mA mA A A IO Unit
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STA2416
Functional description
4
4.1
Functional description
Baseband
"
WLAN coexistence. See also Section 5.12: Bluetooth, WLAN coexisting in collocated scenario.
4.1.1
Baseband 1.1 features
The baseband is based on Ericsson Technology Licensing Baseband Core (EBC) and it is compliant with the Bluetooth wireless technology specification 1.1:
" " " " " " " " " " "
point-to-multipoint (up to 7 slaves). asynchronous connection-less (ACL) link support giving data rates up to 721 kbit/s. synchronous connection oriented (SCO) link with support for 2 voice channels over the air interface. flexible voice format to host and over the air (CVSD, PCM 13/16 bits, A-law, -law). hardware support for packet types: DM1, 3, 5; DH1, 3, 5; HV1, 3; DV. Scatternet capabilities (master in one piconet and slave in the other one; slave in two piconets). All Scatternet v.1.1 errata supported. ciphering support up to 128 bits key. paging modes R0, R1, R2. channel quality driven data rate. full Bluetooth software stack available. low-level link controller.
4.1.2
Baseband 1.2 features
The baseband part is also compliant with the Bluetooth specification 1.2:
" "
extended SCO (eSCO) links: supports EV3 and EV5 packets. See also Section 5.6: V1.2 detailed functions - extended SCO on page 23. adaptive frequency hopping (AFH): hopping kernel, channel assessment as Master and as Slave. See also Section 5.7: V1.2 detailed functions - adaptive frequency hopping on page 24. faster connection: interlaced scan for page and inquiry scan, answer FHS at first reception, RSSI used to limit range. See also Section 5.8: V1.2 detailed functions faster connection on page 24. QoS flush. See also Section 5.9: V1.2 detailed functions - quality of service on page 25. synchronization: the local and the master BT clock are available via HCI commands for synchronization of parallel applications on different slaves. L2CAP flow and error control. LMP improvements. LMP SCO handling. parameter ranges update.
"
" " " " " "
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Functional description
STA2416
4.2
Integrated Flash memory
Features:
" " " "
4-Mbit size eight parameter blocks of 4 Kword (top configuration) seven main blocks of 32 Kword 120 ns access time.
See the datasheet for the standalone product M28R400CT for detailed information. Figure 4. Block addresses
M28R400CT Top Boot Block Addresses
3FFFF 4 KWords 3F000 Total of 8 4 KWord Blocks 38FFF 4 KWords 38000 37FFF 32 KWords 30000
Total of 7 32 KWord Blocks 0FFFF 32 KWords 08000 07FFF 32 KWords 0 0 0
4.2.1
Flash signals description
Write protect (NWP)
Write protect is an input that gives an additional hardware protection for each block. When pin NWP is 0.4 V the lock-down is enabled and the protection status of the Flash blocks cannot be changed. When NWP is (VDDQ - 0.4 V), the lock-down is disabled and the Flash memory blocks can be locked or unlocked.
Reset (NRP)
The reset input provides a hardware reset of the memory. When NRP is 0.4 V, the memory is in reset mode where the outputs are high impedance and the current consumption is minimized. After a reset all blocks are in the locked state. When NRP is (VDDQ - 0.4 V), the device is in normal operation. On exiting the reset mode the device enters the read array mode, but a negative transition of chip enable (CSN0, NE) or a change of the address is required to ensure valid data outputs.
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STA2416
Functional description
VDD_F supply voltage (VDDF)
VDD_F provides the power supply to the internal core of the Flash memory device. It is the main power supply for all operations (read, program and erase)
VDD_Q supply voltage (VDDQ)
Pin VDD_Q provides the power supply to the I/O pins and enables all outputs to be powered independently from VDD_F. Pin VDD_Q can be tied to VDD_F or can use separate supply.
VPP program supply voltage (VPP)
VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. The supply voltage VDDF and the program supply voltage VPP can be applied in any order. If pin VPP is kept within a low voltage range (0 V to 3.6 V) then pin VPP is seen as a control input. In this case a voltage lower than 1 V gives protection against program or block erase, while 1.65 V < Vpp < 3.6 V enables these functions. Pin VPP is sampled only at the beginning of a program or block erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If VPP is in the range 11.4 V to 12.6 V, then pin VPP acts as a power supply pin. In this condition VPP must be stable until the program/erase algorithm has terminated.
VSS_F Flash memory ground (VSSF)
VSSF, the voltage on pin VSS_F, is the reference for all voltage measurements.
Address inputs, data I/Os, control signals
The address inputs (ADDR0-ADDR17), data I/Os (DATA0-DATA15), chip enable (CSN0), output enable (RDN / NG) and write enable (NWP) are internally connected to and controlled by the Bluetooth technology baseband controller.
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General specification
S TA24 1 6
5
5.1
General specification
System clock
The STA2416 works with a single 13 MHz clock provided on pin XIN. For proper Bluetooth wireless operation this clock must have a tolerance of 20 ppm or better.
5.1.1
Slow clock
The slow clock is used by the baseband as reference clock during the low-power modes. The slow clock requires an accuracy of 250 ppm (overall). Several options are foreseen in order to adjust the STA2416 behavior according to the features of the radio used.
"
If the system clock is not provided at all times (power consumption saving) and no slow clock is provided by the system, a 32 kHz crystal must be used by the STA2416 (default mode). If the system clock is not provided at all times (power consumption saving) and the system provides a slow clock at 32 kHz or 3.2 kHz, this signal is simply connected to the STA2416 (LPO_CLK_P). If the system clock is provided at all times, the STA2416 generates from the reference clock an internal 32 kHz clock. This mode is not an optimized mode for power consumption.
"
"
5.2
Boot procedure
The boot code instructions are the first that ARM7TDMI executes after a hardware reset. All the internal device registers are set to their default value. There are two types of boot:
"
Flash memory boot When boot pin is set to `1' (connected to VDD), the STA2416 boots on its Flash. UART download boot from ROM When boot pin is set to `0' (connected to GND), the STA2416 boots on its internal ROM (needed to download the new firmware in the Flash memory). When booting on the internal ROM, the STA2416 will monitor the UART interface for approximately 1.4 second. If there is no request for code downloading during this period, the ROM jumps to Flash.
"
In order to reliably download code the STA2416 must run with a system clock of 13 MHz. At other frequencies the download may fail.
5.3
Clock detection
The STA2416 has an automatic slow-clock frequency detection (32kHz, 3.2kHz or none).
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STA2416
General specification
5.4
Master reset
When the device reset is held active (NRESET is low) then UART1_TXD and UART2_TXD are set to input state. When the NRESET returns high, the device starts to boot.
Note:
The device should be held in active reset for minimum 20 ms in order to guarantee a complete reset of the device.
5.5
Interrupts/wake-up
All GPIOs can be used both as external interrupt source and as wake-up source. In addition the chip can be woken-up by USB, UART1_RXD, UART2_RXD, INT1, INT2.
5.6
V1.2 detailed functions - extended SCO
User perspective - extended SCO
This function gives improved voice quality since it enables the possibility to retransmit lost or corrupted voice packets in both directions.
Technical perspective - extended SCO
eSCO incorporates CRC, negotiable data rate, negotiable retransmission window and multi-slot packets. Retransmission of lost or corrupted packets during the retransmission window guarantees on-time delivery. Figure 5. eSCO
SCO
SCO
SCO
S CO
ACL
ACL
S CO
SCO
eSCO retransmission window
t
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General specification
S TA24 1 6
5.7
V1.2 detailed functions - adaptive frequency hopping
User perspective - adaptive frequency hopping
In the Bluetooth specification 1.1 the Bluetooth wireless devices hop in the 2.4 GHz band over 79 channels. Since WLAN 802.11 has become popular, there are specification improvements in the 1.2-SIG spec for Bluetooth technology where the Bluetooth units can avoid the jammed bands and thereby provide an improved co-existence with WLAN.
Technical perspective - adaptive frequency hopping
Figure 6. AFH
f
AFH(79)
WLAN used frequency
t
f
AFH(19
WLAN used frequency
t
First the master and/or the slaves identify the jammed channels. The master decides on the channel distribution and informs the involved slaves. The master and the slaves, at a predefined instant, switch to the new channel distribution scheme. No longer are jammed channels re-inserted into the channel distribution scheme. AFH uses the same hop frequency for transmission as for reception
5.8
V1.2 detailed functions - faster connection
User perspective - faster connection
This feature gives the user about 65% faster connection on average when enabled compared to Bluetooth specification 1.1 connection procedure.
Technical perspective - faster connection
The faster Inquiry function is based on a removed/shortened random back off and also a new interlaced inquiry scan scheme. The faster page function is based on interlaced page scan.
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STA2416
General specification
5.9
V1.2 detailed functions - quality of service
User perspective - quality of service
Small changes to the BT1.1 spec regarding quality of service (QoS) makes a large difference by allowing all QoS parameters to be communicated over HCI to the link manager that enables efficient bandwidth management. Below is a short list of user perspectives.
"
Flush time-out: enables time-bounded traffic such as video streaming to become more robust when the channel degrades. It sets the maximum delay of an L2CAP frame. It does not enable multiple streams in one piconet, or heavy data transfer at the same time. Simple latency control: allows the host to set the poll interval. It provides enough support for HID devices mixed with other traffic in the piconet.
"
5.10
Low-power modes
To save power, two low-power modes are supported. Depending on the Bluetooth and the host activity, the STA2416 autonomously decides to use Sleep mode or Deep Sleep mode. Table 10. Low-power modes
Description The STA2416: accepts HCI commands from the host suppor ts page- and inquiry scans suppor ts Bluetooth links that are in Sniff, Hold or Park can transfer data over Bluetooth links the system clock is still active in part of the design The STA2416: does not accept HCI commands from the host keeps track of page- and inquiry scan activities switches between sleep and active mode when it is time to scan suppor ts Bluetooth links that are in Sniff, Hold or Park does not transfer data over Bluetooth links the system clock is not active in any part of the design
Low power mode
Sleep mode
Deep sleep mode(1)
1. Deep Sleep mode is not compatible with a USB transport layer
5.10.1
Sniff or park
The STA2416 is in active mode with a Bluetooth connection, once the connection is concluded the SNIFF or the PARK is programmed. Once one of these two states is entered the STA2416 goes in Sleep mode. After that, the host may decide to place the STA2416 in Deep Sleep mode by putting the UART link in low-power mode. The Deep Sleep mode allows smaller power consumption. When the STA2416 needs to send or receive a packet (for example, at TSNIFF or at the beacon instant) it will require the clock and it will go in active mode for the needed transmission/reception. Immediately afterwards it will go back to the Deep Sleep mode. If some HCI transmission is needed, the UART link will be reactivated, using one of the two ways explained in 7.5, and the STA2416 will move from the Deep Sleep mode to the Sleep mode.
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General specification
S TA24 1 6
5.10.2
Inquiry/page scan
When only inquiry scan or page scan is enabled, the STA2416 will go in Sleep mode or Deep Sleep mode outside the receiver activity. The selection between Sleep mode and Deep Sleep mode depend on the UART activity like in SNIFF or PARK.
5.10.3
No connection
If the host places the UART in low power and there is no activity, then the STA2416 can be placed in Deep Sleep mode.
5.10.4
Active link
When there is an active link (SCO or ACL), the STA2416 cannot go in Deep Sleep mode whatever the UART state is. But the STA2416 baseband is made such that whenever it is possible, depending on the scheduled activity (number of link, type of link, amount of data exchanged), it goes in Sleep mode.
5.11
Software initiated low-power mode
A wide set of wake-up mechanisms is supported.
5.12
Bluetooth, WLAN coexisting in collocated scenario
The coexistence interface uses four GPIO pins, when enabled. Bluetooth wireless and WLAN 802.11 b/g technologies occupy the same 2.4-GHz ISM band. STA2416 implements a set of mechanisms to avoid interference in a collocated scenario. The STA2416 supports five different algorithms in order to provide efficient and flexible simultaneous function between the two technologies in collocated scenarios.
" " " " "
Algorithm 1: PTA (packet traffic arbitration) based coexistence algorithm defined in accordance with the IEEE 802.15.2 recommended practice. Algorithm 2: the WLAN is the master and it indicates to the STA2416 when not to operate in case of simultaneous use of the air interface. Algorithm 3: the STA2416 is the master and it indicates to the WLAN chip when not to operate in case of simultaneous use of the air interface. Algorithm 4: two-wire mechanism. Algorithm 5: alternating wireless medium access (AWMA), defined in accordance with the WLAN 802.11 b/g technologies.
The algorithm is selected via HCI command. The default algorithm is algorithm 1.
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STA2416
General specification
5.12.1
Algorithm 1: packet traffic arbitration (PTA)
Algorithm 1 is based on a bus connection between the STA2416 and the WLAN chip. Figure 7. Algorithm 1: PTA
STA2416
D05AU1628
WLAN
By using this coexistence interface it's possible to dynamically allocate bandwidth to the two devices when simultaneous operations are required while the full bandwidth can be allocated to one of them in case the other one does not require activity. The algorithm involves a priority mechanism, which allows preserving the quality of certain types of link. A typical application would be to guarantee optimal quality to the Bluetooth voice communication while an intensive WLAN communication is ongoing. Several algorithms have been implemented in order to provide a maximum of flexibility and efficiency for the priority handling. Those algorithms can be activated via specific HCI commands. The combination of a time division multiplexing techniques to share the bandwidth in case of simultaneous operations and of the priority mechanism avoid the interference due to packet collision and it allows the maximization of the 2.4-GHz ISM bandwidth usage for both devices while preserving the quality of some critical types of link.
5.12.2
Algorithm 2: WLAN master
In case the STA2416 has to cooperate, in a collocated scenario, with a WLAN chip not supporting a PTA based algorithm, it's possible to put in place a simpler mechanism. The interface is reduced to 1 line. Figure 8. Algorithm 2: WLAN master
RF_NOT_ALLOWED
STA2416
D05AU1626
WLAN
When the WLAN has to operate, it alerts HIGH the RF_NOT_ALLOWED signal and the STA2416 will not operate while this signals stays HIGH. This mechanism permits to avoid packet collision in order to make an efficient use of the bandwidth but cannot provide guaranteed quality over the Bluetooth links.
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General specification
S TA24 1 6
5.12.3
Algorithm 3: Bluetooth master
This algorithm represents the symmetrical case of Section 5.12.2: Algorithm 2: WLAN master. Also in this case the interface is reduced to 1 line. Figure 9. Algorithm 3: Bluetooth master
RF_NOT_ALLOWED
STA2416
D05AU1627
WLAN
When the STA2416 has to operate it puts the RF_NOT_ALLOWED signal HIGH. The WLAN will not operate while this signals stays HIGH. This mechanism is used to avoid packet collision in order to make efficient use of the bandwidth. It provides high quality for all Bluetooth links but cannot provide guaranteed quality over the WLAN links.
5.12.4
Algorithm 4: two-wire mechanism
Based on algorithms 2 and 3, the host decides, on a case-by-case basis, whether WLAN or Bluetooth is master.
5.12.5
Algorithm 5: alternating wireless medium access (AWMA)
AWMA utilizes a portion of the WLAN beacon interval for Bluetooth operations. From a timing perspective, the medium assignment alternates between usage following WLAN procedures and usage following Bluetooth procedures. The timing synchronization between the WLAN and the STA2416 is done by the hardware signal MEDIUM_FREE.
Table 11.
WLAN WLAN 1 WLAN 2 WLAN 3 WLAN 4
WLAN hardware signal assignment
Scenario 1: PTA TX_ CONFIRM TX_ REQUEST STATUS OPTIONAL_ SIGNAL Scenario 2: WLAN master BT_RF_NOT_ ALLOWED Not used Not used Not used Scenario 3: BT master Not used Scenario 4: 2-wire BT_RF_NOT_ ALLOWED Scenario 5: AWMA MEDIUM_FREE Not used Not used Not used
WLAN_RF_ NOT_ WLAN_RF_ NOT_ ALLOWED ALLOWED Not used Not used Not used Not used
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STA2416
Interfaces
6
6.1
Interfaces
UART interface
The chip contains two enhanced (128 byte transmit FIFO and 128 byte receive FIFO, sleep mode, 127 Rx and 128 Tx interrupt thresholds) UARTs named UART1 and UART2 compatible with the standard M16550 UART. For UART1, only Rx and Tx signals are available (used for debug purposes). UART2 features:
"
standard HCI UART transport layer: all HCI commands as described in the Bluetooth specification 1.1 ST specific HCI command (check STA2416 Software Interface document for more information)
" " " "
RXD, TXD, CTS, RTS on permanent external pins 128-byte FIFOs, for transmit and for receive default configuration: 57.600 kbit/s specific HCI command to change to the baud rates given in Table 12 List of supported baud rates
57.600 kbit/s (default) 38.4 kbit/s 28.8 kbit/s 19.2 kbit/s 14.4 kbit/s 9600 bit/s 7200 bit/s 4800 bit/s 2400 bit/s 1800 bit/s 1200 bit/s 900 bit/s 600 bit/s 300 bit/s
Table 12.
921.6 kbit/s 460.8 kbit/s 230.4 kbit/s 153.6 kbit/s 115.2 kbit/s 76.8 kbit/s
6.2
Synchronous serial interface
The synchronous serial interface (SSI) (or the synchronous peripheral interface (SPI)) is a flexible module supporting full-duplex and half-duplex synchronous communications with external devices in master and slave mode. It enables a microcontroller unit to communicate with peripheral devices or allows inter-processor communications in a multiple-master environment. This Interface is compatible with the Motorola SPI standard, with the Texas Instruments Synchronous Serial Frame format and with National Semiconductor Microwire standard. Special extensions are implemented to support the Agilent SPI interface for optical mouse applications and the 32-bit data SPI for stereo codec applications. Some applications examples are given in Section 6.8 on page 33.
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Interfaces
STA2416
6.2.1
Feature description: Agilent mode
One application is a combination of a Bluetooth device with an Agilent optical mouse sensor to build a Bluetooth Mouse. The Agilent chip has an SPI interface with one bi-directional data port. When SPI_IO from ADNS_2030 is driving, SPI_RXD should be active, while SPI_TXD is set as a 3-state high impedance input. For a read operation, the Bluetooth SPI_TXD is put in high impedance state after the reception of the address. Note that this feature works independently of the SPI mode, supporting other combinations. In this case, the devices are connected as described in Figure 10. Figure 10. Agilent mode
STA2416
SPI_CLK SPI_FRM
Agilent ADNS-2030
SPI_CLK
SPI_TXD SPI_RXD SPI_IO
6.2.2
Feature description: 32-bit SPI
One application is a Bluetooth technology stereo headset. In this application, the audio samples are received from the emitter through the air using the Bluetooth baseband with ACL packets. The samples are decoded by the embedded ARM CPU (the samples were encode for compression in SBC codec) and then sent to a stereo codec though the SPI interface. To support this application, the data size is 32 bits. The 32-bit support is implemented for both transmit and receive.
6.3
I2C Interface
Used to access I2C peripherals. The interface is a fast master I2C. It has full control of the interface at all times. I2C slave function is not supported.
6.4
USB interface
The USB interface is compliant with the USB-2.0 full-speed specification. Maximum throughput on the USB interface is 12 Mbit/s. Figure 11 gives an overview of the main components needed for supporting the USB interface, as specified in the Bluetooth core specification. For clarity, the serial interface (including the UART transport layer) is also shown.
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STA2416 Figure 11. USB interface
HCI
Interfaces
USB TRANSPORT LAYER
UART TRANSPORT LAYER
USB DEVICE REGISTERS FIFOs
USB DRIVER
SERIAL DRIVER
UART DEVICE REGISTERS FIFOs
IRQ
RTOS
IRQ
STA2416 HW
The USB device registers and FIFOs are memory mapped. The USB driver will use these registers to access the USB interface. The equivalent exists for the HCI communication over UART. For transmission to the host, the USB and Serial Drivers interface with the hardware via a set of registers and FIFOs, while in the other direction, the hardware may trigger the drivers through a set of interrupts (identified by the RTOS, and directed to the appropriate driver routines).
6.5
JTAG interface
The JTAG interface is compliant with the JTAG IEEE Standard 1149.1. Its allows both the boundary scan of the digital pins and the debug of the ARM7TDMI application when connected with the standard ARM7 development tools.
6.6
RF interface
The STA2416 radio interface is compatible to BlueRF (unidirectional RxMode2 for data and unidirectional serial interface for control).
6.7
PCM voice interface
The voice interface is a direct PCM interface to connect to a standard codec (for example, STA529) including internal decimator and interpolator filters. The data can be linear PCM (13 to 16-bit), -law (8-bit) or A-law (8-bit). By default the codec interface is configured as master. The encoding on the air interface is programmable to be CVSD, A-law or -law. The PCM block is able to manage the PCM bus with up to three timeslots. In master mode, PCM clock and data can operate at 2 MHz or at 2.048 MHz to allow interfacing of standard codecs.
D05AU1625
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Interfaces The four signals of the PCM interface are:
" " " "
STA2416
PCM_CLK: PCM clock PCM_SYNC: PCM 8 kHz sync PCM_A: PCM data PCM_B: PCM data.
Directions of PCM_A and PCM_B are software configurable. Three additional PCM_SYNC signals can be provided via the GPIOs. See Chapter 9 on page 36 for more details. Figure 12. PCM (A-law, -law) standard mode
0 PCM_CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PCM_SYNC PCM_A B B
PCM_B
B 125s
B
D02TL558
Figure 13. Linear mode
0 PCM_CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PCM_SYNC PCM_A
PCM_B 125s
D02TL559
Table 13.
Symbol Fpcm_clk
PCM interface timing
Description Frequency of PCM_CLK (master) Min Typ 2048 8 200 200 200 100 100 100 150 Max Unit kHz kHz ns ns ns ns ns ns ns
Fpcm_sync Frequency of PCM_SYNC tWCH tWCL tWSH tSSC tSDC tHCD tDCD High period of PCM_CLK Low period of PCM_CLK High period of PCM_SYNC Setup time, PCM_SYNC high to PCM_CLK low Setup time, PCM_A/B input valid to PCM_CLK low Hold time, PCM_CLK low to PCM_A/B input invalid Delay time, PCM_CLK high to PCM_A/B output valid
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STA2416 Figure 14. PCM interface timing
tWCL PCM_CLK tWCH tSSC
Interfaces
PCM_SYNC tWSH
tSDC tHCD
MSB MSB-1 MSB-2 MSB-3 MSB-4
PCM_A/B in
tDCD PCM_B/A out
MSB MSB-1 MSB-2 MSB-3 MSB-4
D02TL557
6.8
Applications examples
Figure 15. Bluetooth technology v1.2 application example
Bluetooth 1.2
Bluetooth RF GPIOs UARTs JTAG
I2C clock I2C data
BlueRF
CMOS Bridge OUT / ADC IN
SPI_RX / PCM_OUT
STLC2150
13MHz
STA2416
SPI_TX / PCM_IN SPI_FRM / PCM_SINC SPI_CLK / PCM_CLK
STA529
13MHz
32KHz reset 13MHz
Figure 16. Bluetooth technology v2.0 application example
Bluetooth RF
GPIOs
UART1
JTAG
PCM I/F
SPI I/F
SAI I/F
CMOS Bridge OUT / ADC IN
STLC2500x
13MHz clk
HCI link (UART2)
STA2416
32KHz reset
I2C I/F
STA529
13MHz
oscillator
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HCI-UART transport layer
STA2416
7
HCI-UART transport layer
The UART transport layer has been specified by the Bluetooth SIG, and allows HCI-level communication between a host controller (STA2416) and a host (for example, PC), via a serial line. The objective of this HCI-UART transport layer is to make it possible to use the Bluetooth HCI over a serial interface between two UARTs on the same PCB. The HCI-UART transport layer assumes that the UART communication is free from line errors.
7.1
UART settings
The HCI-UART transport layer uses the following settings for RS232: Baud rate: Number of data bits: Parity bit: Stop bit: Flow control: Configurable (default baud rate: 57.600 kbit/s) 8 no parity 1 stop bit RTS/CTS
Flow-off response time: 3 ms Flow control with RTS/CTS is used to prevent temporary UART buffer overrun. It should not be used for flow control of HCI, since HCI has its own flow control mechanisms for HCI commands, HCI events and HCI data. If CTS is 1, then the host/host controller is allowed to send. If CTS is 0, then the host/host controller is not allowed to send. The flow-off response time defines the maximum time from setting RTS low until the byte flow actually stops. The signals should be connected in a null-modem fashion; that is, the local TXD should be connected to the remote RXD and the local RTS should be connected to the remote CTS and vice versa. Figure 17. UART transport layer
BLUETHOOTH HOST BLUETHOOTH HCI BLUETHOOTH HOST CONTROLLER
HCI UART TRANSPORT LAYER
D02TL556
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STA2416
HCI-USB transport layer
8
HCI-USB transport layer
The USB transport layer has been specified by the Bluetooth SIG, and allows HCI-level communication between a host controller (STA2416) and a host (for example, PC), via a USB interface. The USB transport layer is completely implemented in software. It accepts HCI messages from the HCI layer, prepares it for transmission over a USB bus, and sends it to the USB driver. It reassembles the HCI messages from USB data received from the USB driver, and sends these messages to the HCI layer. The transport layer does not interpret the contents (payload) of the HCI messages; it examines only the header.
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Class-1 power support
STA2416
9
Class-1 power support
The chip can control an external power amplifier (PA). Several signals are duplicated on GPIOs for this purpose in order to avoid digital/analogue noise loops in the radio. A software controlled register enables the alternative functions of GPIO[15:11, 9:6] to generate the signals for driving an external PA in a Bluetooth technology class-1 power application. Each bit enables a dedicated signal on a GPIO pin, as described in Table 14. Table 14. GPIOs alternative functions
Description No dedicated function WLAN 1 WLAN 2 WLAN 3 WLAN 4 Can be used for plug/unplug emulation in the case of USB connectivity Power Class 1 RX_ON Power Class 1 NOT_RXON Power Class 1 PA0 or PCM sync 1 Power Class 1 PA1 or PCM sync 2 Power Class 1 PA3 Power Class 1 PA4 Power Class 1 PA5 Power Class 1 PA6 Power Class 1 PA7
Involved GPIO GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15
The signal BRXEN is the same as the RX_ON (GPIO6) output pin. The signal NOT_RXON is the inverted signal, provided in order to save components on the application board. PA7 to PA0 are the power amplifier control lines. They are managed, on a connection basis, by the baseband core. The power level programmed for a certain Bluetooth technology connection is managed by the firmware, as specified in the Bluetooth SIG specification. The WLAN signals, as described in Section 5.12: Bluetooth, WLAN coexisting in collocated scenario on page 26, can be enabled on GIPIO pins The WXTRA PCM sync signals, as described in Section 6.7: PCM voice interface on page 31, can be flexibly configured on GPIO pins to connect multiple codecs.
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STA2416
Package information
10
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 18. LFBGA120 (10x10x1.4mm) mechanical data and package dimensions
DIM. A A1 A2 b D D1 D2 E E1 E2 eD eE FD FE mD mE n SE SD aaa bbb ddd eee fff MIN. 0.20 0.25 9.90 mm TYP. MAX. 1.40 MIN. 0.008 inch TYP. MAX. 0.055
OUTLINE AND MECHANICAL DATA
1 0.039 0.30 0.35 0.010 0.012 0.014 10.00 10.10 0.390 0.394 0.398 8.50 0.335 6.50 0.256 9.90 10.00 10.10 0.390 0.394 0.398 8.50 0.335 6.50 0.256 0.50 basic 0.020 basic 0.50 basic 0.020 basic 0.75 0.029 0.75 0.029 18 18 120 balls 0.25 basic 0.0098 basic 0.25 basic Tolerance 0.15 0.10 0.08 0.15 0.05 0.0098 basic 0.006 0.0039 0.0031 0.006 0.002
Body: 10 x 10 x 1.4mm
LFBGA120 Low Fine Ball Grid Array
7513355 A
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Trademarks and other acknowledgements
STA2416
11
Trademarks and other acknowledgements
Agilent is a trademark of Agilent Technologies, Inc. ARM7 and ARM7TDMI are registered trademarks of ARM Limited. Bluetooth is a registered trademark of Bluetooth SIG Inc. ECOPACK is a registered trademark of STMicroelectronics. Ericsson is the registered trademark of Telefonaktiebolaget LM Ericsson.
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STA2416
Revision history
12
Revision history
Table 15.
Date 20-Dec-2006
Document revision history
Revision 1 Initial release. General updates Updated various references to system clock frequency New applications sections on page 7 and on page 33 Added sentence for downloading code at 13 MHz in Section 5.2 on page 22. Changes
18-Feb-2008
2
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STA2416
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