Datasheets | Logic, Signal Switches | LED Drivers, Front Panel Controllers | LED Driver (Power Logic)

Low voltage 16-bit constant current LED sink driver with outputs error detection

Datasheet

Format: (740 kb)

Last Updated: 26/10/2009

Pages: 31

Untitled Document

Generic Part Number

Orderable Part Number

Status

STP16DP05	STP16DP05XTTR	Active
	STP16DP05MTR	Active
	STP16DP05PTR	Active
	STP16DP05TTR	Active

Related Application Notes

STP08DP05, STP16DP05 Normal mode and error detection features

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STP16DP05
Low voltage 16-bit constant current LED sink driver with outputs error detection
Features

Low voltage power supply down to 3 V 16 constant current output channels Adjustable output current through external resistor Short and open output error detection Serial data IN/Parallel data OUT 3.3 V micro driver-able Output current: 5-100 mA 30 MHz clock frequency Available in high thermal efficiency TSSOP exposed pad ESD protection 2.5 kV HBM, 200 V MM
TSSOP24 TSSOP24 (exposed pad) QSOP-24 SO-24

The data detection results are loaded in the shift register and shifted out via the serial line output. The detection functionality is implemented without increasing the pin count number, through a secondary function of the output enable and latch pin (DM1 and DM2 respectively), a dedicated logic sequence allows the device to enter or leave from detection mode. Through an external resistor, users can adjust the STP16DP05 output current, controlling in this way the light intensity of LEDs, in addition, user can adjust LED's brightness intensity from 0% to 100% via OE/DM2 pin. The STP16DP05 guarantees a 20 V output driving capability, allowing users to connect more LEDs in series. The high clock frequency, 30 MHz, makes the device suitable for high data rate transmission. The 3.3 V voltage supply is well useful for applications that interface any 3.3V micro. Compared with a standard TSSOP package, the TSSOP exposed pad increases heat dissipation capability by a 2.5 factor.
Package SO-24 (tape and reel) TSSOP24 (tape and reel) TSSOP24 exposed pad (tape and reel) QSOP-24 Packaging 1000 parts per reel 2500 parts per reel 2500 parts per reel 2500 parts per reel

Description
The STP16DP05 is a monolithic, low voltage, low current power 16-bit shift register designed for LED panel displays. The device contains a 16-bit serial-in, parallel-out shift register that feeds a 16-bit D-type storage register. In the output stage, sixteen regulated current sources were designed to provide 5-100 mA constant current to drive the LEDs. The STP16DP05 features open and short LED detections on the outputs.The STP16DP05 is backward compatible with STP16C/L596.The detection circuit checks 3 different conditions that can occur on the output line: short to GND, short to VO or open line. Table 1. Device summary
Order codes STP16DP05MTR STP16DP05TTR STP16DP05XTTR STP16DP05PTR

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Contents

STP16DP05

Contents
1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Pin connection and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2

Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 2.2 2.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 4 5 6 7

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Equivalent circuit and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Detection mode functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1 7.2 7.3 7.4 Phase one: "entering in detection mode" . . . . . . . . . . . . . . . . . . . . . . . . . 16 Phase two: "error detection" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Phase three: "resuming to normal mode" . . . . . . . . . . . . . . . . . . . . . . . . . 19 Error detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8 9

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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STP16DP05

Summary description

1

Summary description
Table 2. Typical current accuracy
Current accuracy Output voltage Between bits 1.3 V 1.5% Between ICs 5% 20 to 100 mA 3.3 V to 5 V 25 C Output current VDD Temperature

1.1

Pin connection and description
Figure 1. Pin connection

Note:

The exposed pad should be electrically connected to a metal land electrically isolated or connected to ground Table 3.
Pin n 1 2 3 4 5-20 21 22 23 24

Pin description
Symbol GND SDI CLK LE-DM1 OUT 0-15 OE-DM2 SDO R-EXT VDD Ground terminal Serial data input terminal Clock input terminal Latch input terminal - detect mode 1 (see operation principle) Output terminal Input terminal of output enable (active low) - detect mode 1 (see operation principle) Serial data out terminal Input terminal of an external resistor for constant current programing Supply voltage terminal Name and function

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Electrical ratings

STP16DP05

2
2.1

Electrical ratings
Absolute maximum ratings
Stressing the device above the rating listed in the "absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4.
Symbol VDD VO IO VI IGND fCLK Supply voltage Output voltage Output current Input voltage GND terminal current Clock frequency

Absolute maximum ratings
Parameter Value 0 to 7 -0.5 to 20 100 -0.4 to VDD 1600 50 Unit V V mA V mA MHz

2.2

Thermal data
Table 5.
Symbol TOPR TSTG

Thermal data
Parameter Operating temperature range Storage temperature range SO-24 TSSOP24 Value -40 to +125 -55 to +150 60 85 37.5 72 Unit C C C/W C/W C/W C/W

RthJC

Thermal resistance junction-case

TSSOP24 exposed pad QSOP-24

(1)

1. The exposed pad should be soldered directly to the PCB to realize the thermal benefits.

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STP16DP05

Electrical ratings

2.3

Recommended operating conditions
Table 6.
Symbol VDD VO IO IOH IOL VIH VIL twLAT twCLK t wEN

Recommended operating conditions
Parameter Supply voltage Output voltage Output current Output current Output current Input voltage Input voltage LE\DM1 pulse width CLK pulse width OE\DM2 pulse width VDD = 3.0 V to 5.0 V OUTn SERIAL-OUT SERIAL-OUT 0.7VDD -0.3 6 8 100 10 5 10 Cascade operation
(1)

Test conditions

Min. 3.0

Typ. -

Max. 5.5 20 100 +1 -1 VDD+0.3 0.3VDD

Unit V V mA mA mA V V ns ns ns ns ns ns

5

-

tSETUP(D) Setup time for DATA tHOLD(D) Hold time for DATA tSETUP(L) Setup time for LATCH fCLK Clock frequency

30

MHz

1. If the device is connected in cascade, it may not be possible achieve the maximum data transfer. Please consider the timings carefully.

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Electrical characteristics

STP16DP05

3

Electrical characteristics
VDD = 3.3 V to 5 V, T = 25 C, unless otherwise specified

Table 7.
Symbol VIH VIL IOH VOL VOH IOL1 IOL2 IOL3 IOL1 IOL2 IOL3 RSIN(up)

Electrical characteristics
Parameter Input voltage high level Input voltage low level Output leakage current Output voltage (Serial-OUT) Output voltage (Serial-OUT) VOH = 20 V IOL = 1 mA IOH = -1 mA VO = 0.3 V, Rext = 3.9 k Output current VO = 0.3 V, Rext = 970 VO = 1.3 V, Rext = 190 Output current error between bit (all output ON) Pull-up resistor VO = 0.3 VREXT = 3.9 k VO = 0.3 VREXT = 970 VO = 1.3 VREXT =190 150 100 REXT = 970 OUT 0 to 15 = OFF Supply current (OFF) REXT = 240 OUT 0 to 15 = OFF REXT = 970 OUT 0 to 15 = ON Supply current (ON) REXT = 240 OUT 0 to 15 = ON Thermal protection (1) VOH -VDD = -0.4 V 4.25 19 96 5 20 100 5 1.5 1.2 300 200 5 13 6 13.5 170 5.75 21 104 8 3 3 600 400 6 14 mA 7 14.5 C K K % mA Test conditions Min. 0.7VDD GND Typ. Max. VDD 0.3VDD 1 0.4 Unit V V A V V

RSIN(down) Pull-down resistor IDD(OFF1) IDD(OFF2) IDD(ON1) IDD(ON2) Thermal

1. Guaranteed by design (not tested) The thermal protection switches OFF only the outputs current

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STP16DP05 VDD = 5 V, T = 25 C, unless otherwise specified Table 8.
Symbol tPLH1

Electrical characteristics

Switching characteristics
Parameter Propagation delay time, CLK-OUTn, LE\DM1 = H, OE\DM2 = L Propagation delay time, LE\DM1 -OUTn, OE\DM2 = L Propagation delay time, OE\DM2-OUTn, LE\DM1 = H Propagation delay time, CLK-SDO Propagation delay time, CLK-OUTn, LE\DM1 = H, OE\DM2 = L Propagation delay time, LE\DM1 -OUTn, OE\DM2 = L Propagation delay time, OE\DM2-OUTn, LE\DM1 = H Propagation delay time, CLK-SDO Output rise time 10~90% of voltage waveform Output fall time 90~10% of voltage waveform CLK rise time (1) CLK fall time (1) Test conditions VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VIH = VDD VIL = GND IO = 20 mA REXT = 1 K CL = 10 pF VL = 3.0 V RL = 60 VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V Min. Typ. 40 20 51 32 49 27 21.5 14.5 15 11 13 9 11.5 8.5 25.5 17.5 34 12.5 5.5 4.5 Max. 65 ns 30 77 ns 47 77 ns 41 32 ns 21.5 25 ns 14.5 20 ns 12.5 18 ns 12 38 ns 25 53.5 ns 18.5 8.5 ns 6.5 5000 5000 ns ns Unit

tPLH2

tPLH3

tPLH

tPHL1

tPHL2

tPHL3

tPHL

tO N

tOFF tr tf

1. In order to achieve high cascade data transfer, please consider tr/tf timings carefully.

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Equivalent circuit and outputs

STP16DP05

4

Equivalent circuit and outputs
Figure 2. OE\DM2 terminal

Figure 3.

LE\DM1 terminal

Figure 4.

CLK, SDI terminal

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STP16DP05 Figure 5. SDO terminal

Equivalent circuit and outputs

Figure 6.

Block diagram

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Timing diagrams

STP16DP05

5

Timing diagrams
Table 9.
CLOCK

Truth table
LE\DM1 H L H X X OE\DM2 L L L L H SERIAL-IN Dn Dn + 1 Dn + 2 Dn + 3 Dn + 3 OUT0 . . .. . .... OUT7 . . .. . .. . .. OUT15 Dn . . . Dn - 7 . . . Dn -15 No change Dn + 2 . . . Dn - 5 . . . Dn -13 Dn + 2 . . . Dn - 5 . . . Dn -13 OFF SDO Dn - 15 Dn - 14 Dn - 13 Dn - 13 Dn - 13

Note:

OUTn = ON when Dn = H OUTn = OFF when Dn = L Figure 7. Timing diagram

Note:

1 2 3 4 5

Latch and output enable are level sensitive and ARE NOT synchronized with rising-or-falling edge of CALK signal. When LE terminal is low level, the latch circuits hold previous set of data When LE terminal is at high level, the latch circuits refresh new set of data from SDI chain. When OE terminal is at low level, the output terminals - Out0 to Out15 respond to data in the latch circuits, either '1' for ON or '0' for OFF When OE terminal is at high level, all output terminals will be switched OFF.

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STP16DP05 Figure 8. Clock, serial-in, serial-out

Timing diagrams

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Timing diagrams Figure 9. Clock, serial-in, latch, enable, outputs

STP16DP05

LE\ D M1

OE\DM2

Figure 10. Outputs

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STP16DP05

Typical characteristics

6

Typical characteristics
Figure 11. Output current-REXT resistor

Table 10.

Output current-REXT resistor
Rext () 976 780 652 560 488 433 389 354 325 300 278 259 241 229 215 Output current (mA) 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90

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Typical characteristics

STP16DP05

Conditions : Temperature = 25 C, VDD = 3.3 V; 5.0 V, ISET = 3 mA; 5 mA; 10 mA; 20 mA; 50 mA; 80 mA. Figure 12. ISET vs drop out voltage (Vdrop)
800 700 600 500 400 300 200 100 0 0 20 40 Iset mA) 60 80

Vdrop (mV)

Avg @ 3.0V Avg @ 5.0V

Table 11.

ISET vs drop out voltage (Vdrop)
Iout (mA) 3 5 10 20 50 80 Avg @ 3.0 V 19.33 36.67 77.33 158.67 406 692 Avg @ 5.0 V 22.66 40.33 80 157.33 406 668

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STP16DP05

Typical characteristics

Figure 13. IDD ON\OFF

14 12 10 Idd (mA) 8 6 4 2 0 0 10 20 30 40 50 Iset (mA) 60 70 80 90
Id dON Avg @ 5.5V Id dON Avg @ 3.6V Id dOFF Avg @ 5.5V Id dOFF Avg @ 3.6V

Figure 14. Power dissipation vs temperature package

Note:

The exposed pad should be soldered to the PBC to realize the thermal benefits.

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Detection mode functionality

STP16DP05

7
7.1

Detection mode functionality
Phase one: "entering in detection mode"
From the "normal mode" condition the device can switch to the "error mode" by a logic sequence on the OE\DM2 and LE/DM1 pins as showed in the following table and diagram: Table 12.
CLK OE/DM2 LE/DM1

Entering in detection truth table
1 H L 2 L L 3 H L 4 H H 5 H L

Figure 15. Entering in detection timing diagram

After these five CLK cycles the device goes into the "error detection mode" and at the 6th rise front of CLK the SDI data are ready for the sampling.

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STP16DP05

Detection mode functionality

7.2

Phase two: "error detection"
The 16 data bits must be set "1" in order to set ON all the outputs during the detection. The data are latched by LE/DM1 and after that the outputs are ready for the detection process. When the micro controller switches the OE\DM2 to LOW, the device drives the LEDs in order to analyze if an OPEN or SHORT condition has occurred. Figure 16. Detection diagram

The LEDs status will be detected at least in 1 microsecond and after this time the microcontroller sets OE\DM2 in HIGH state and the output data detection result will go to the microprocessor via SDO. Detection mode and normal mode use both the same format data. As soon as all the detection data bits are available on the serial line, the device may go back to normal mode of operation. To re-detect the status the device must go back in normal mode and reentering in error detection mode.

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Detection mode functionality Figure 17. Timing example for open and/or short detection

STP16DP05

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STP16DP05

Detection mode functionality

7.3

Phase three: "resuming to normal mode"
The sequence for re-entering in normal mode is showed in the following table and diagram: Figure 18. Resuming to normal mode timing diagram
CLK OE/DM2 LE/DM1 1 H L 2 L L 3 H L 4 H L 5 H L

Note:

For proper device operation the "Entering in detection" sequence must be follow by a "resume mode" sequence, it is not possible to insert consecutive equal sequence.

7.4

Error detection conditions
VDD = 3.3 to 5 V temperature range -40 to 125 C Table 13.
SW-1 or SW-3b SW-2 or SW-3a

Detection conditions
Open line or output ==> IODEC 0.5 x IO short to GND detected Shor t on LED or short ==> VO 2.4 V to V-LED detected No error detected ==> IODEC 0.5 x IO ==> VO 2.2 V

No error detected

Note:

Where: IO = the output current programmed by the REXT, IODEC = the detected output current in detection mode

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Detection mode functionality Figure 19. Detection circuit

STP16DP05

1 6D STP16 P05

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STP16DP05 Figure 20. Error detection sequence
During the error detection are necessary at least 2 CLK signal plus oneat the end

Detection mode functionality

16 CLK pulse are required to load the data setting 1 into shift register

Ev ery CLK pulse shows the results of single Output results:Out15;14; 13 etc. etc

LE LE and OE Key Sequence necessary to Enter in EDM

The LE pulse latch the data loaded during the previous state

After OE signal turn High the SDO pin show the results of Error Detection (Open or Short in this case)

The OE Pulse put the device from EDM to Normal Mode

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Package mechanical data

STP16DP05

8

Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark . Table 14.
Dim. Min. A A1 A2 b c D E E1 e L h < 0.4 0.25 8 0.31 0.254 8.56 5.8 3.8 1.54 0.1 Typ. 1.62 0.15 1.47 0.2 0.17 8.66 6 3.91 0.635 0.635 0.33 0 0.89 0.41 0.016 0.010 8.76 6.2 4.01 0.012 0.010 0.337 0.228 0.150 Max. 1.73 0.25 Min. 0.061 0.004 Typ. 0.064 0.006 0.058 0.008 0.007 0.341 0.236 0.154 0.025 0.025 0.013 0.035 0.016 0.345 0.244 0.158 Max. 0.068 0.010

QSOP-24 mechanical data
mm. inch

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STP16DP05 Figure 21. QSOP-24 package dimensions

Package mechanical data

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Package mechanical data Table 15.
Dim. Min R1 R2 R3 eint e1 1.5 12.8 Typ 13 330 100 16.4 2 2.5 0.591 Max 13.5 Min 5.039 Typ 5.118 129.921 39.37 6.457 0.787

STP16DP05

QSOP-24 tape and reel
mm. inch Max 5.315

0.984

Table 16.

QSOP-24 tape and reel dimensions

4.0+/-0.1 0.3+/-0.05 1.5+1/0 2.0+/-0.1 1.75+/-0.1

7.5+/-0.1

2.1 +/-0.1

10.3 +/-0.1 10.3 +/-0.1

16 +/-0.3

8 +/-0.1
6.5 +/- 0.1

1.6 +1/-0.1

7217811_C

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STP16DP05 Table 17.
Dim. Min. A A1 A2 b c D E e H K L 6.25 0 0.50 0.19 0.09 7.7 4.3 0.65 BSC 6.5 8 0.70 0.246 0 0.020 0.05 0.9 0.30 0.20 7.9 4.5 0.0075 0.0035 0.303 0.169 Typ. Max. 1.1 0.15 0.002 Min.

Package mechanical data TSSOP24 mechanical data
mm. inch Typ. Max. 0.043 0.006 0.035 0.0118 0.0079 0.311 0.177 0.0256 BSC 0.256 8 0.028

Figure 22. TSSOP24 package dimensions

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Package mechanical data Table 18.
Dim. Min. A C D N T Ao Bo Ko Po P 6.8 8.2 1.7 3.9 11.9 12.8 20.2 60 22.4 7 8.4 1.9 4.1 12.1 0.268 0.323 0.067 0.153 0.468 Typ. Max. 330 13.2 0.504 0.795 2.362 Min. Typ.

STP16DP05

Tape and reel TSSOP24
mm. inch Max. 12.992 0.519

0.882 0.276 0.331 0.075 0.161 0.476

Figure 23. Reel dimensions

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STP16DP05 Table 19.
Dim. Min. A a1 a2 b b1 C c1 D E e e3 F L S 7.40 0.50 15.20 10.00 1.27 13.97 7.60 1.27 0.291 0.020 (max.) 8 15.60 10.65 0.35 0.23 0.5 45(typ.) 0.598 0.393 0.1 Typ. Max. 2.65 0.2 2.45 0.49 0.32 0.014 0.009 0.004 Min.

Package mechanical data SO-24 mechanical data
mm. inch Typ. Max. 0.104 0.008 0.096 0.019 0.012 0.020

0.614 0.419 0.050 0.550 0.300 0.050

Figure 24. SO-24 package dimensions

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Package mechanical data Table 20.
Dim. Min. A C D N T Ao Bo Ko Po P 10.8 15.7 2.9 3.9 11.9 12.8 20.2 60 30.4 11.0 15.9 3.1 4.1 12.1 0.425 0.618 0.114 0.153 0.468 Typ. Max. 330 13.2 0.504 0.795 2.362 Min. Typ.

STP16DP05

Tape and reel SO-24
mm. inch Max. 12.992 0.519

1.197 0.433 0.626 0.122 0.161 0.476

Figure 25. Reel dimensions

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STP16DP05 Table 21.
Dim. Min. A A1 Typ. Max. 1.2 0.15 Min.

Package mechanical data TSSOP24 exposed pad
mm inch Typ. Max. 0.047 0.004 0.006

A2 b c D D1 E E1 E2 e K L

0.8 0.19 0.09 7.7 4.7 6.2 4.3 2.9

1

1.05 0.30 0.20

0.031 0.007 0.004 0.303 0.185 0.244 0.169 0.114

0.039

0.041 0.012 0.0089

7.8 5.0 6.4 4.4 3.2 0.65

7.9 5.3 6.6 4.5 3.5

0.307 0.197 0.252 0.173 0.126 0.0256

0.311 0.209 0.260 0.177 0.138

0 0.45 0.60

8 0.75

0 0.018 0.024

8 0.030

Figure 26. TSSOP24 dimensions

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Revision history

STP16DP05

9

Revision history
Table 22.
Date 9-Jan-2007 21-May-2007 10-Jul-2007 28-Feb-2008 23-Oct-2009

Document revision history
Revision 1 2 3 4 5 First release Updated Table 7 on page 6 Updated Table 9: Truth table on page 10 Updated Table 15: TSSOP24 exposed-pad on page 23 Added QSOP-24 package information Table 14 and Figure 21 on page 23 Updated Figure 7 on page 10, Chapter 3 on page 6 Changes

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STP16DP05

Please Read Carefully:

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