PM6670
Complete DDR2/3 memory power supply controller
Preliminary Data
Features switching
Switching section (VDDQ) 4.5V to 28V input voltage range 0.9V, 1% voltage reference 1.8V (DDR2) or 1.5V (DDR3) fixed output voltages 0.9V to 2.6V adjustable output voltage 1.237V 1% reference voltage available Very fast load transient response using constant on-time control loop No RSENSE current sensing using low side MOSFET's RDS(ON) Negative current limit Latched OVP and UVP Soft start internally fixed at 3ms Selectable pulse skipping at light load Selectable No-Audible (33KHz) pulse skip mode Ceramic output capacitors supported Output voltage ripple compensation VTT LDO and VTTREF 2Apk LDO with foldback for VTT Remote VTT sensing High-Z VTT output in S3 Ceramic output capacitors supported 15mA Low noise buffered reference
VFQFPN-24 4x4
Description
The device PM6670 is a complete DDR2/3 power supply regulator designed to meet JEDEC specifications. It integrates a Constant On-Time (C.O.T.) buck controller, a 2Apk sink/source Low Drop Out regulator and a 15mA low noise buffered reference. The C.O.T. architecture assures fast transient response supporting both electrolytic and ceramic output capacitors. An embedded integrator control loop compensates the DC voltage error due to the output ripple. The 2Apk sink/source linear regulator provides the memory termination voltage with fast load transient response. The device is fully compliant with system sleep states S3 and S4/S5, providing LDO output high impedance in Suspend-To-RAM and Tracking Discharge of all outputs in Suspend-To-Disk.
Applications
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DDR2/3 memory supply Notebook computers Handheld and PDAs CPU and chipset I/O supplies SSTL18, SSTL15 and HSTL bus termination
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Table 1. Device summary
Part number PM6670 March 2007 Package VFQFPN-24 4x4 (Exposed Pad) Rev 1 Packaging Tube 1/53
www.st.com 53
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
PM6670
Contents
1 2 Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 2.2 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 3.2 3.3 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 5 6 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1 VDDQ section - constant On-Time PWM controller . . . . . . . . . . . . . . . . . 20
7.1.1 7.1.2 7.1.3 7.1.4 Constant-On-Time architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Output ripple compensation and loop stability . . . . . . . . . . . . . . . . . . . . 23 Pulse-Skip and No-Audible Pulse-Skip Modes . . . . . . . . . . . . . . . . . . . 27 Mode-of-operation selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 POR, UVLO and Soft Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Current sensing and current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Power-Good signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 VDDQ output discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Reference voltage and bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Over Voltage and Under Voltage Protections . . . . . . . . . . . . . . . . . . . . 35 Device thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
O
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7.1.5 7.1.7 7.1.8 7.1.9 7.1.6
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7.1.10 7.1.11 7.1.12
VTTREF buffered reference and VTT LDO section . . . . . . . . . . . . . . . . . 36
7.2.1 7.2.2 VTT and VTTREF Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 VTTREF and VTT outputs discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.3
2/53
S3 and S5 power management pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
PM6670
Contents
8
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.1 External components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.1.7 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 MOSFETs selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Diode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 VDDQ current limit setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 All ceramic capacitors application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9 10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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Typical application circuit
PM6670
1
Figure 1.
Typical application circuit
Application circuit
R
LP
+5V VIN
C
IN3
C IN2
R1 C R2
IN
3
12
DSCG
6
AVCC
18
VCC
8
VOSC
22
BOOT
VDDQ (LDO input) C
IN4
SEL
11
MODE
C BOOT
HGA TE HGATE PHASE LGA TE
21 20 17 19 16 9
23
LDOIN
L
VTTREF
C
OUT3
4 2 24 1
VTTREF
VTTSNS
PM6670
SGND VREF COMP PG S3 S5
CSNS
VTT
R
LIM
VTT VTTGND
PGND VSNS
5
15
14
13
7
10
C
OUT2
C
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VDDQ
INT
4/53
PM6670
Pin settings
2
2.1
Pin settings
Connections
Figure 2. Pin connection (through top view)
HGATE
PHASE
LDOIN
BOOT
24 1 VTTGND VTTSNS DDRSEL VTTREF SGND AVCC 6 7 VREF VOSC
CSNS 19 18 VCC LGATE
VTT
PM6670
PGND PG S3 13
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MODE
COMP
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Pin settings
PM6670
2.2
Pin description
Table 2. Pin functions
N 1 2 Pin VTTGND VTTSNS Function LDO Power Ground. Connect to negative terminal of VTT output capacitor. LDO Remote Sensing. Connect as close as possible to the load via a low noise PCB trace. DDR Voltage Selector (if MODE is tied to VCC) or Pulse-Skip/No-Audible Pulse-Skip Selector in Adjustable Mode (MODE voltage lower than 3V). See Section 7.1.4: Mode-of-operation selection on page 29. Low Noise Buffered DDR Reference Voltage. A 22nF (minimum) ceramic bypass capacitor is required in order to achieve stability. Ground Reference for analog circuitry, control logic and VTTREF buffer. Connect together with the thermal pad and VTTGND to a low impedance ground plane. See the Application Note for details. +5V Supply for internal logic. Connect to +5V rail through a simple RC filtering network.
3
DDRSEL
4
VTTREF
5
SGND
6
AVCC
7
VREF
High accuracy output Voltage Reference (1.237V) for multilevel pins setting. It can deliver up to 50A. Connect a 100nF capacitor between VREF and SGND in order to enhance noise rejection. Frequency Selection. Connect to the central tap of a resistor divider to set the desired switching frequency. The pin cannot be left floating. See Section 7: Device description on page 19 VDDQ Output Remote Sensing. Discharge path for VDDQ in Non-Tracking Discharge. Input for internal resistor divider that provides VDDQ/2 to VTTREF and VTT. Connect as close as possible to the load via a low noise PCB trace. Mode of operation selector. If MODE pin voltage is higher than 4V, the fixed output mode is selected. If MODE pin voltage is lower than 4V, it is used as negative input of the error amplifier. See Section 7.1.4: Mode-of-operation selection on page 29. DC Voltage Error Compensation Input for the switching section. Refer Section 7.1.4: Mode-of-operation selection on page 29. Discharge Mode Selection. Refer to Section 7.1.8: VDDQ output discharge on page 33 for Tracking/Non-tracking Discharge or No-Discharge options. Switching Controller Enable. Connect to S5 system status signal to meet S0-S5 power management states compliance. See Section : Power management section on page 12 Linear Regulator Enable. Connect to S3 system status signal to meet S0-S5 power management states compliance. See Section : Power management section on page 12 Power-Good Signal (open drain output). High when VDDQ output voltage is within 10% of nominal value. Power Ground for the switching section. Low-side Gate Driver Output.
8
VOSC
9
VSNS
10
MODE
11 12
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13
S5
14
S3
15 16 17
PG PGND LGATE
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PM6670 Table 2. Pin functions (continued)
N 18 19 20 21 22 Pin VCC CSNS PHASE HGATE BOOT Function
Pin settings
+5V Low-side Gate Driver Supply. Bypass with a 100nF capacitor to PGND. Current Sense Input for the switching section. This pin must be connected through a resistor to the drain of the synchronous rectifier (RDSon sensing) to set the current limit threshold. Switch Node Connection and return path for the High-side Gate Driver. High-side Gate Driver Output Bootstrap Capacitor Connection. Positive Supply Input of the High-side Gate Driver. Linear Regulator Input. Connect to VDDQ in normal configuration or to a lower supply to reduce the power dissipation. A 10F bypass ceramic capacitor is suggested for noise rejection enhancement. See Section 7: Device description on page 19 LDO Linear Regulator Output. Bypass with a 20F (2x10F MLCC) filter capacitor.
23
LDOIN
24
VTT
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Electrical data
PM6670
3
3.1
Electrical data
Maximum rating
Table 3. Absolute maximum ratings (1)
Symbol VAVCC VVCC AVCC to SGND VCC to SGND PGND, VTTGND to SGND HGATE and BOOT to PHASE HGATE and BOOT to PGND VPHASE PHASE to SGND LGATE to PGND CSNS, PG, S3, S5, DSCG, COMP, VSNS, VOSC, VREF, MODE, DDRSEL to GND VTTREF, VREF, VTT, VTTSNS to SGND LDOIN, VTT, VTTREF, LDOIN to VTTGND PTOT Power dissipation @TA = 25C Parameter Value -0.3 to 6 -0.3 to 6 -0.3 to 0.3 -0.3 to 6 -0.3 to 42 -0.3 to 36 -0.3 to VCC +0.3 V Unit
-0.3 to VAVCC + 0.3 -0.3 to VAVCC + 0.3
1. Free air operating conditions unless otherwise specified. Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
3.2
Thermal data
Table 4. Thermal data
Symbol RthJA
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Table 5. Recommended operating conditions
Symbol VIN VAVCC VVCC Input voltage range IC supply voltage IC supply voltage Parameter Min 4.5 4.5 4.5
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Thermal resistance junction to ambient Storage temperature range Operating ambient temperature range Junction operating temperature range
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-0.3 to VAVCC + 0.3 2.3 W
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Parameter
Value 42 -40 to 150 -40 to 85 0 to 125
Unit C/W C C C
Values Unit Typ Max 28 5.5 5.5 V
8/53
PM6670
Electrical characteristics
4
Electrical characteristics
TA = 0C to 85C , VCC = AVCC = +5V and LDOIN connected to VDDQ output if not otherwise specified.
Table 6. Electrical characteristics
Values Symbol Supply section S3, S5, MODE and DDRSEL connected to AVCC, No Load on VTT and VTTREF Outputs. VCC connected to AVCC S5, MODE and DDRSEL connected to AVCC, S3 tied to SGND, No Load on VTTREF. VCC connected to AVCC S3 and S5 tied to SGND. Discharge Mode active. VCC connected to AVCC Parameter Test condition Min Typ Max Unit
IIN
Operating current
0.8
2 mA
ISTR
Operating current in STR
0.6
1
ISH
Operating current in shutdown AVCC under voltage lockout upper threshold
UVLO
AVCC under voltage lockout lower threshold UVLO hysteresis
ON-time (SMPS)
tON
On-time duration
OFF-time (SMPS) tOFFMIN
Minimum Off time
Voltage reference
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MODE and DDRSEL high, VVSNS = 2V
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A V
10
4.25 4.0
4.4 4.1 mV
3.9 70
VOSC = 300mV VOSC = 500mV
650 390
750 450
850 ns 510
300
350
ns
Voltage accuracy Load regulation Undervoltage lockout fault threshold
4.5V < VIN < 25V -50A< IVREF < 50A
1.224 -4
1.237
1.249 4
V mV
800
9/53
Electrical characteristics Table 6. Electrical characteristics (continued)
Values Symbol VDDQ output VDDQ output voltage, DDR3 VVDDQ VDDQ output voltage, DDR2 Feedback Accuracy MODE connected to AVCC, DDRSEL tied to SGND, No Load MODE and DDRSEL connected to AVCC, No Load 1.5 Parameter Test condition Min Typ Max
PM6670
Unit
V 1.8 -1.5 1.5 %
Current limit and zero crossing comparator ICSNS CSNS input bias current Comparator offset Positive current limit threshold Fixed negative current limit threshold VZC,OFFS Zero crossing comparator offset -10 Rsense = 1k VPGND - VCSNS 90 -5 -100 110 -5 100 110 5 A mV mV
High and low side gate drivers HGATE high state (pull-up) HGATE driver on-resistance HGATE low state (pull-down) LGATE high state (pull-up) LGATE driver on-resistance
LGATE low state (pull-down) UVP/OVP protections and PGOOD SIGNAL (SMPS only) OVP UVP PGOOD Over voltage threshold Under voltage threshold
Power-good upper threshold Power-good lower threshold IPG,LEAK PG leakage current
VPG,LOW PG low-level voltage Soft start section (SMPS)
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mV mV
2.0
1.8 1.4 0.6
2.7 2.1 0.9
112 67 107 86
115 70 110 90
118 73 % 113 93 1 A mV
PG forced to 5V IPG,SINK = 4mA 150
250
Soft-star t ramp time (4 steps current limit) Soft-star t current limit step
2
3 25
4
ms A
10/53
PM6670 Table 6. Electrical characteristics (continued)
Electrical characteristics
Values Symbol Soft end section VDDQ Discharge resistance in non-tracking discharge mode VTT discharge resistance in non-tracking discharge mode VTTREF discharge resistance in non-tracking discharge mode VDDQ Output threshold synchronous for final tracking to non-tracking discharge transition VTT LDO section ILDOIN,ON ILDOIN,
STR
Parameter
Test condition Min Typ Max
Unit
15
25
35
15
25
35
1
1.5
2
k
0.2
0.4
0.6
V
LDO input bias current in full-on state LDO input bias current in suspend-to-RAM state LDO input bias current in suspend-to-disk state VTTSNS bias current VTTSNS leakage current
S3 = S5 = +5V, No Load on VTT S3 = 0V, S5 = +5V, No Load on VTT
1
ILDOIN,
STD
S3 = S5 = 0V, No Load on VTT S3 = +5V, S5 = +5V, VVTTSNS = VVSNS /2
IVTTSNS,
BIAS
IVTTSNS,
LEAK
IVTT,LEAK VTT leakage current LDO linear regulator output voltage (DDR2) LDO linear regulator output voltage (DDR3)
VVTT
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S3 = 0V, S5 = +5V, VVTTSNS = VVSNS /2 S3 = 0V, S5 = +5V, VVTT = VVSNS /2
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A
10
10
-10 0.9
10
S3 = S5= +5V, IVTT = 0A, MODE = DDRSEL = +5V
V S3 = S5= +5V, IVTT = 0A, MODE = +5V, DDRSEL = 0V S3 = S5 = MODE = + 5V, -1mA < IVTT < 1mA -20 -25 -35 2 1 -2.8 -1.4 2.3 1.15 -2.3 -1.15 0.75 20 25 35 2.8 1.4 A -2 -1 11/53 mV
LDO output accuracy respect S3 = S5 = MODE = +5V, -1A < IVTT < 1A to VTTREF S3 = S5 = MODE = +5V, -2A < IVTT < 2A LDO source current limit VVTT < 1.10*( VVSNS /2) VVTT > 1.10*( VVSNS /2) LDO sink current limit VVTT > 0.90*( VVSNS /2) VVTT < 0.90*( VVSNS /2)
IVTT,CL
Electrical characteristics Table 6. Electrical characteristics (continued)
Values Symbol VTTREF section VTTREF output voltage VVTTREF VTTREF output voltage accuracy respect to VSNS/2 IVTTREF VTTREF current limit IVTTREF = 0A, VVSNS = 1.8V -15mA < IVTTREF < 15mA, VVSNS = 1.8V VTTREF= 0 or VSNS -2 40 0.9 2 Parameter Test condition Min Typ Max
PM6670
Unit
V % mA
Power management section Turn OFF level S3,S5 Turn ON level MODE pin high level threshold (1) VMODE MODE pin low level threshold (1) DDRSEL pin high level threshold (1) VDDRSEL DDRSEL pin middle level window (1) DDRSEL pin low level threshold (1) DSCG pin high level threshold (1) VDSCG DSCG pin middle level window (1) DSCG pin low level threshold (1) IIN,LEAK IIN3,LEAK IOSC, VAVCC -0.8 VAVCC -0.7 1.6 0.4
Logic inputs leakage current Multilevel inputs leakage current
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LEAK
Thermal shutdown T SHDN Shutdown temperature (1) 150 C
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VOSC input leakage current
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V
VAVCC 1.5 0.5
VAVCC -0.8 2.0 0.5 10 10 1 A
S3, S5 = 5V MODE, DDRSEL and DSCG = 5V VOSC = 500mV
1. Guaranteed by design. Not production tested.
12/53
PM6670
Typical operating characteristics
5
Figure 3.
Typical operating characteristics
Efficiency vs load - 1.5V and 1.8V, VIN =12V Figure 4.
500 450 400 350 300 250 200 150 100 50 0 0.001
Switching frequency vs load - 1.8V, VIN = 12V
100 80 Efficiency (%) 70 60 50 40 30 20 10 0 0.001 0.01 0.1 Output current (A)
DDR2 - Forced PWM DDR2 - No-Audible P-S DDR2 - Pulse-Skip DDR3 - Forced PWM DDR3 - No-Audible P-S DDR3 - Pulse-Skip
Swiching frequency (kHz)
90
Forced PWM No-Audible P-S Pulse-Skip
1
10
0.01
0.1
Output current (A)
1
Figure 5.
Switching frequency vs input voltage, 1.8V
Figure 6.
Switching frequency vs input voltage, 1.5V
p g
500 450 Switching frequency (kHz) 400 350 300 250 200 150 0.0 5.0 10.0 15.0 Input voltage (V) 20.0
500 450 Switching frequency (kHz) 400 350 300 250 200 150
Figure 7.
1.8000
VDDQ line regulation, 1.8V, 7A
1.7990
Output voltage (V)
1.7980
1.7970
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1.7960 1.7950 1.7940
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5.0
No-Audible P-S Pulse-Skip
Output voltage (V)
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Forced PWM 10.0 15.0 Input voltage (V)
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(s)
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15.0 Input voltage (V)
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5.0
20.0
25.0
30.0
Figure 8.
1.4980 1.4975 1.4970 1.4965 1.4960 1.4955 1.4950 1.4945
VDDQ line regulation, 1.8V, 7A
Forced PWM No-Audible P-S Pulse-Skip
0.0
20.0
25.0
30.0
1.4940 0.0
5.0
10.0
15.0 Input voltage (V)
20.0
25.0
30.0
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Typical operating characteristics
PM6670
Figure 9.
1.860 Output voltage (V)
VDDQ load regulation, 1.8V, VIN=12V Figure 10. VDDQ load regulation, 1.5V, VIN=12V
1.530 Output voltage (V)
Forced PWM No-Audible P-S Pulse-Skip
1.850 1.840 1.830 1.820 1.810 1.800 1.800 0.001 0.01 0.1
1.520 1.510 1.500 1.490 1.480 1.470 0.001 0.01 0.1
Forced PWM No-Audible P-S Pulse-Skip
1
10
1
10
Output current (A)
Output current (A)
Figure 11. VTT load regulation, 0.9V, LDOIN = 1.8V
0.940 0.930 Output voltage (V)
Figure 12. VTT load regulation, 0.75V, LDOIN = 1.5V
0.790 0.780 Output voltage (V) 0.770 0.760 0.750 0.740
0.920 0.910 0.900 0.890 0.880 -2.5
-1.5
-0.5
0.5
1.5
Output current (A)
Figure 13. VTTREF load regulation, 0.9V, VSNS = 1.8V
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0.730 -2.5
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1.5
2.5
Output current (A)
Figure 14. No-audible pulse-skip waveforms
14/53
PM6670
Typical operating characteristics
Figure 15. Power-up sequence - AVCC above UVLO
Figure 16. VDDQ soft-start, 1.8V, heavy load
Figure 17. -1.8A to 1.8A VTT load transient, 0.9V
Figure 18. 0mA to 9mA VTTREF load transient, 0.9V
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Typical operating characteristics Figure 19. Non-tracking (soft) discharge Figure 20. Tracking (fast) discharge, LDOIN = VDDQ
PM6670
Figure 21. 0A to 10A VDDQ load transient, PWM
Figure 22. 10A to 0A VDDQ load transient, PWM
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PM6670 Figure 23. 0A to 10A VDDQ load transient, pulse-skip
Typical operating characteristics Figure 24. 10A to 0A VDDQ load transient, pulse-skip
Figure 25. Over-voltage protection, VDDQ = 1.8V
Figure 26. Under-voltage protection, VDDQ = 1.8V
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Block diagram
PM6670
6
Block diagram
Figure 27. Functional and block diagram
VREF
Vr = 0.9V 1.236V Bandgap
VOSC
BOOT
Level shifter
VTTSNS
Ton
HGATE PHASE
LDOIN
1-shot Ton min 1-shot
Anti Cross Conduction
VCC LGATE PGND
VTT
TD
Toff min 1-shot
NTD HIZ
VTTGND VTTGND
BEN _ R + SWEN NTD R VREF
Zero Crossing & Current Limit
VTTREF
SGND
UVP/OVP
AVCC
UVLO
DDRSEL DSCG
O
bs
let o
TD
Pr e
du o
(s) ct
Ob Vr
so
gm +
Vr
te le
Vr +10% + + Vr -10%
ro P
CSNS
uc d
s) t(
COMP
PG
SWEN TD NTD BEN HIZ
VSNS
DDR3 NTD
Thermal Shutdown
CONTROL LOGIC
adj fix
S3
S5
M OD E
Table 7. Legend
SWEN NTD BEN HIZ Switching controller enable Tracking discharge enable Non-tracking discharge enable VTTREF buffer enable LDO high impedance mode enable
18/53
PM6670
Device description
7
Device description
The PM6670 is designed to satisfy DDR2-3 power supply requirements combining a synchronous buck controller, a 15mA buffered reference and a high-current Low-Drop Out (LDO) linear regulator capable of sourcing and sinking up to 2Apk. The switching controller section is a high-performance, pseudo-fixed frequency, Constant-On-Time (COT) based regulator specifically designed for handling fast load transient over a wide range of input voltages. The DDR2-3 supply voltage VDDQ can be easily set to 1.8V (DDR2) or 1.5V (DDR3) without additional components. The output voltage can also be adjusted in the 0.9V to 2.6V range using an external resistor divider. The Switching Mode Power Supply (SMPS) can handle different modes of operation in order to minimize noise or power consumption, depending on the application needs. A lossless current sensing scheme, based on the Low-Side MOSFET's on resistance avoids the need for an external current sense resistor. The output of the linear regulator (VTT) tracks the memory's reference voltage VTTREF within 30mV over the full operating load conditions. The input of the LDO can be either VDDQ or a lower voltage rail in order to reduce the total power dissipation. Linear regulator stability is achieved by filtering its output with a ceramic capacitor (20F or greater). The reference voltage (VTTREF) section provides a voltage equal to one half of VSNS with an accuracy of 1%. This regulator can source and sink up to 15mA. A 10nF to 100nF bypass capacitor is required between VTTREF and SGND for stability. According to DDR2/3 JEDEC specifications, when the system enters the Suspend-To-RAM state the LDO output is left in high impedance while VTTREF and VDDQ are still alive. When the Suspend-To-Disk state (S3 and S5 tied to ground) is entered, all outputs are actively discharged when either tracking or non-tracking discharge is selected.
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
19/53
Device description
PM6670
7.1
VDDQ section - constant On-Time PWM controller
The PM6670 uses a pseudo-fixed frequency, Constant On-Time (COT) controller as the core of the switching section. It is well known that the COT controller uses a relatively simple algorithm and uses the ripple voltage derived across the output capacitor's ESR to trigger the On-Time one-shot generator. In this way, the output capacitor's ESR acts as a current sense resistor providing the appropriate ramp signal to the PWM comparator. Nearly constant switching frequency is achieved by the system's loop in steady-state operating conditions by varying the On-Time duration, avoiding thus the need for a clock generator. The On-Time one shot duration is directly proportional to the output voltage, sensed at VSNS pin, and inversely proportional to the input voltage, sensed at the VOSC pin, as follows: Equation 1
TON = K OSC
VSNS + VOSC
where KOSC is a constant value (130ns typ.) and is the internal propagation delay (40ns typ.). The one-shot generator directly drives the high-side MOSFET at the beginning of each switching cycle allowing the inductor current to increase; after the On-Time has expired, an Off-Time phase, in which the low-side MOSFET is turned on, follows. The OffTime duration is solely determined by the output voltage: when lower than the set value (i.e. the voltage at VSNS pin is lower than the internal reference VR = 0.9V), the synchronous rectifier is turned off and a new cycle begins (Figure 28). Figure 28. Inductor current and output voltage in steady state conditions
Inductor current
bs O
let o
Pr e
du o
Output voltage
(s) ct
Ton
so Ob -
te le
ro P
uc d
s) t(
Vreg
Toff
t
20/53
PM6670
Device description
The duty-cycle of the buck converter is, in steady-state conditions, given by
Equation 2
VO U D = ------------T -VI N
The switching frequency is thus calculated as
Equation 3
fSW
VOUT VIN D 1 = = = OSC VSNS TON OUT K OSC K OSC VOSC
where
Equation 4a
O S C VO S C = -------------VI N
Equation 4b
VS S O U T = --------N----VO U T
Referring to the typical application schematic (figures on cover page and Figure 29), the final expression is then:
Equation 5
Even if the switching frequency is theoretically independent from battery and output voltages, parasitic parameters involved in power path (like MOSFETs' on-resistance and inductor's DCR) introduce voltage drops responsible for slight dependence on load current. In addition, the internal delay is due to a small dependence on input voltage. The PM6670 switching frequency can be set by an external divider connected to the VOSC pin.
O
bs
let o
Figure 29. Switching frequency selection and VOSC pin
VIN
Pr e
du o
(s) ct
fSW =
so Ob -
te le
ro P
uc d
s) t(
OSC R2 1 = K OSC R1 + R 2 K OSC
PM6670
R1
VOSC
R2
The voltage seen at this pin must be greater than 0.8V and lower than 2V in order to ensure the system's linearity.
21/53
Device description
PM6670
7.1.1
Constant-On-Time architecture
Figure 30 shows the simplified block diagram of the Constant-On-Time controller.
The switching regulator of the PM6670 owns a one-shot generator that ignites the high-side MOSFET when the following conditions are simultaneously satisfied: the PWM comparator is high (i.e. output voltage is lower than Vr = 0.9V), the synchronous rectifier current is below the current limit threshold and the minimum off-time has expired. A minimum Off-Time constraint (300ns typ.) is introduced to assure the boot capacitor charge and allow inductor valley current sensing on low-side MOSFET. A minimum On-Time is also introduced to assure the start-up switching sequence. Once the On-Time has timed out, the high side switch is turned off, while the synchronous rectifier is ignited according to the anti-cross conduction management circuitry. When the output voltage reaches the valley limit (determined by internal reference Vr = 0.9V), the low-side MOSFET is turned off according to the anti-cross conduction logic once again, and a new cycle begins.
Figure 30. Switching section simplified block diagram
VOSC
Positive Current Limit comparator
VOSC Toff-min
CSNS
100uA
+ 1-Shot generator
VBG
+ PWM Comparator
COMP
Integrator gm
0.9V
MODE
VSNS
DDRSEL
O
bs
let o
Pr e
Min fsw Min fsw counter
od
+
ct u
MODE<4V
(s)
Ob R Q
Ton-min Ton VSNS
S
Q
so
+ -
te le
+ + -
Level Level shifter shifter
ro P
2.5V 500mV
uc d
HS HS driver driver
s) t(
BOOT HGATE PHASE
Anti crossconduction circuitry
+ S Q R Q _
Zero-crossing Comparator
-
VCC
2.5V
S
VOSC
Q
LS LS driver driver
LGATE PGND
R
0.9V VBG bandgap 1.236V PULSE - SKIP PULSE
SGND
VREF
22/53
PM6670
Device description
7.1.2
Output ripple compensation and loop stability
The loop is closed connecting the center tap of the output divider (internally, when the fixed output voltage is chosen, or externally, using the MODE pin in the adjustable output voltage mode). The feedback node is the negative input of the error comparator, while the positive input is internally connected to the reference voltage (Vr = 0.9V). When the feedback voltage becomes lower than the reference voltage, the PWM comparator goes to high and sets the control logic, turning on the high-side MOSFET. After the On-Time (calculated as previously described) the system releases the high-side MOSFET and turns on the synchronous rectifier. The voltage drop along ground and supply PCB paths, used to connect the output capacitor to the load, is a source of DC error. Furthermore the system regulates the output voltage valley, not the average, as shown in Figure 28. Thus, the voltage ripple on the output capacitor is an additional source of DC error. To compensate this error, an integrative network is introduced in the control loop, by connecting the output voltage to the COMP pin through a capacitor (CINT) as shown in Figure 31.
Figure 31. Circuitry for output ripple compensation
COMP PIN VOLTAGE Vr t OUTPUT VOLTAGE V V VREF
COMP CFILT CINT
I=gm(V1-Vr)
t
bs O
let o
The additional capacitor is used to reduce the voltage on the COMP pin when higher than 300mVpp and is unnecessary for most of applications. The trans conductance amplifier (gm) generates a current, proportional to the DC error, used to charge the CINT capacitor. The voltage across the CINT capacitor feeds the negative input of the PWM comparator, forcing the loop to compensate the total static error. An internal voltage clamp forces the COMP pin voltage range to 150mV with respect to VREF. This is useful to avoid or smooth output voltage overshoot during a load transient. When the Pulse-Skip Mode is entered, the clamping range is automatically reduced to 60mV in order to enhance the recovering capability. In the ripple amplitude is larger than 150mV, an additional capacitor CFILT can be connected between the COMP pin and ground to reduce ripple amplitude, otherwise the integrator will operate out of its linearity range. This capacitor is unnecessary for most of applications and can be omitted.
ro P e
uc d
(s) t
ESR
COUT
so Ob RINT VSNS
VCINT
te le
Vr
gm
ro P
+
RFb1
+
uc d
s) t(
PWM Comparator
V1
RFb2
23/53
Device description
PM6670
The design of the external feedback network depends on the output voltage ripple. If the ripple is higher than approximately 20mV, the correct CINT capacitor is usually enough to keep the loop stable. The stability of the system depends firstly on the output capacitor zero frequency. The following condition must be satisfied:
Equation 6
fSW > k fZout =
k 2 C out ESR
where k is a fixed design parameter (k > 3). It determines the minimum integrator capacitor value:
Equation 7
CINT >
gm Vr fSW Vout 2 - fZout k
where gm = 50s is the integrator trans conductance. In order to ensure stability it must be also verified that:
Equation 8
CINT >
If the ripple on the COMP pin is greater than the integrator 150mV, the auxiliary capacitor CFILT can be added. If q is the desired attenuation factor of the output ripple, CFILT is given by:
Equation 9
O
bs
let o
In order to reduce the noise on the COMP pin, it is possible to add a resistor RINT that, together with CINT and CFILT, becomes a low pass filter. The cutoff frequency fCUT must be much greater (10 or more times) than the switching frequency:
Equation 10
ro P e
du
(s) ct
so Ob CFILT =
gm Vr 2 fZout VOUT
te le
ro P
uc d
s) t(
CINT (1 - q) q
RINT =
2 fCUT
1 C C INT FILT CINT + CFILT
If the ripple is very small (lower than approximately 20mV), a different compensation network, called "Virtual-ESR" Network, is needed. This additional circuit generates a triangular ripple that is added to the output voltage ripple at the input of the integrator. The complete control scheme is shown in Figure 32.
24/53
PM6670 Figure 32. "Virtual-ESR" Network
T NODE VOLTAGE V1 COMP PIN VOLTAGE VREF t t VREF I=gm(V1-Vr)
Device description
V2
COMP RINT CINT CFILT
T
+ PWM Comparator
gm
+
V1
-
R1 R
OUTPUT VOLTAGE V
RFb1
Vr
C
VSNS ESR COUT
t
RFb2
The ripple on the COMP pin is the sum of the output voltage ripple and the triangular ripple generated by the Virtual-ESR Network. In fact the Virtual-ESR Network behaves like a another equivalent series resistor RVESR. A good trade-off is to design the network in order to achieve an RVESR given by:
Equation 11
where IL is the inductor current ripple and VRIPPLE is the total ripple at the T node, chosen greater than approximately 20mV. The new closed-loop gain depends on CINT. In order to ensure stability it must be verified that:
bs O
let o
Equation 12
Pr e
du o
(s) ct
R VESR =
so Ob -
te le
ro P
uc d
s) t(
VRIPPLE - ESR IL
CINT >
gm Vr 2 fZ Vout
where:
Equation 13
fZ = and:
1 2 C out R TOT
25/53
Device description Equation 14
PM6670
RTOT = ESR + RVESR Moreover, the CINT capacitor must meet the following condition:
Equation 15
fSW > k fZ =
k 2 C out R TOT
where RTOT is the sum of the ESR of the output capacitor and the equivalent ESR given by the Virtual-ESR Network (RVESR). The k parameter must be greater than unity (k > 3) and determines the minimum integrator capacitor value CINT:
Equation 16
CINT >
gm Vr fSW Vout 2 - fZ k
The capacitor of the Virtual-ESR Network, C, is chosen as follows:
Equation 17
C > 5 CINT
and R is calculated to provide the desired triangular ripple voltage:
Equation 18
Finally the R1 resistor is calculated according to expression 19:
Equation 19
bs O
let o
ro P e
uc d
(s) t
so Ob R= L
te le
ro P
uc d
s) t(
R VESR C
1 R Cf Z R1 = 1 R- C fZ
26/53
PM6670
Device description
7.1.3
Pulse-Skip and No-Audible Pulse-Skip Modes
High efficiency at light load conditions is achieved by PM6670 entering the Pulse-Skip Mode (if enabled). When one of the two fixed output voltages is set, Pulse-Skip power saving is a default feature. At light load conditions the zero-crossing comparator truncates the low-side switch On-Time as soon as the inductor current becomes negative; in this way the comparator determines the On-Time duration instead of the output ripple (see Figure 33).
Figure 33. Inductor current and output voltage at light load with Pulse-Skip
Inductor current
VDDQ Output
Vreg
TON TOFF TIDLE
As a consequence, the output capacitor is left floating and its discharge depends solely on the current drained from the load. When the output ripple on the pin COMP falls under the reference, a new shot is triggered and the next cycle begins. The Pulse-Skip mode is naturally obtained enabling the zero-crossing comparator and automatically takes part in the C.O.T. algorithm when the inductor current is about half the ripple current amount, i.e. migrating from continuous conduction mode (C.C.M.) to discontinuous conduction mode (D.C.M.). The output current threshold related to the transition between PWM Mode and Pulse-Skip Mode can be approximately calculated as:
Equation 20
bs O
let o
At higher loads, the inductor current never crosses zero and the device works in pure PWM mode with a switching frequency around the nominal value. A physiological consequence of Pulse-Skip Mode is a more noisy and asynchronous (than normal conditions) output, mainly due to very low load. If the Pulse-Skip is not compatible with the application, the PM6670, when set in adjustable mode-of-operation, allows the user to choose between forced-PWM and No-Audible Pulse-Skip alternative modes (see 4.1.4 for details).
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
t
ILOAD (PWM2Skip) =
VIN - VOUT TON 2 L
27/53
Device description
PM6670
No-Audible Pulse-Skip Mode
Some audio-noise sensitive applications cannot accept the switching frequency to enter the audible range as is possible in Pulse-Skip mode with very light loads. For this reason, the PM6670 implements an additional feature to maintain a minimum switching frequency of 33kHz despite a slight efficiency loss. At very light load conditions, if any switching cycle has taken place within 30s (typ.) since the last one (because the output voltage is still higher than the reference), a No-Audible Pulse-Skip cycle begins. The low-side MOSFET is turned on and the output is driven to fall until the reference has been crossed. Then, the high-side switch is turned on for a TON period and, once it has expired, the synchronous rectifier is enabled until the inductor current reaches the zero-crossing threshold (see Figure 34).
Figure 34. Inductor current and output voltage at light load with non-audible pulse-skip
Inductor current
VDDQ Output
Vreg TMAX TON TOFF TIDLE
For frequencies higher than 33kHz (due to heavier loads) the device works in the same way as in Pulse-Skip mode. It is important to notice that in both Pulse-Skip and No-Audible Pulse-Skip modes the switching frequency changes not only with the load but also with the input voltage.
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
t
28/53
PM6670
Device description
7.1.4
Mode-of-operation selection
Figure 35. MODE and DDRSEL multifunction pin configurations
VDDQ VDDQ
+5V PM6670
R9 R8 R9
+5V PM6670
MODE MODE
R8
VREF
DDRSEL
DDRSEL
(a)
(b)
The PM6670 has been designed to satisfy the widest range of applications involving DDR2/3 memories, SSTL15-18 buses termination and I/O supplies for CPU/Chipset. The device is provided with multilevel pins which allow the user to choose the appropriate configuration. The MODE pin is used to firstly decide between fixed preset or adjustable (user defined) output voltages. When the MODE pin is connected to +5V, the PM6670 allows setting the VDDQ voltage to 1.8V or 1.5V just forcing the DDRSEL multilevel pin to +5V or to ground respectively (see Figure 35a). In this condition the Pulse-Skip feature is enabled. This device configuration is suitable for standard DDR2/3 memory supply applications avoiding the need for an external, high accuracy, divider for output voltage setting. Applications requiring different output voltages can be managed by PM6670 simply setting the adjustable mode. If MODE pin voltage is higher than 4V, the fixed output mode is selected. Connecting an external divider to the MODE pin (Figure 35b), it is used as negative input of the error amplifier and the output voltage is given by expression (21).
Equation 21
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
VDDQ ADJ = 0.9
R8 + R9 R8
29/53
Device description
PM6670
VDDQ output voltage can be set in the range from 0.9V to 2.6V. Adjustable mode automatically switches DDRSEL pin to become the power saving algorithm selector: if tied to +5V, the forced-PWM (fixed frequency) control is performed. If grounded or connected to VREF pin (1.237V reference voltage), the Pulse-Skip or Non-Audible Pulse-Skip Modes are respectively selected.
Table 8. Mode-Of-Operation settings summary
Mode DDRSEL VDDRSEL > 4.2V VMODE > 4.3V 1V < VDDRSEL < 3.5V <0.5V VDDRSEL > 4.2V VMODE < 3.7V 1V < VDDRSEL < 3.5V VDDRSEL < 0.5V ADJ Forced-PWM Non-Audible Pulse-skip Pulse-Skip VDDQ 1.8V Pulse-Skip 1.5V Operating mode
7.1.5
Current sensing and current limit
The PM6670 switching controller uses a valley current sensing algorithm to properly handle the current limit protection and the inductor current zero-crossing information. The current is sensed during the conduction time of the low-side MOSFET. The current sensing element is the on-resistance of the low-side switch. The sensing scheme is visible in Figure 36.
Figure 36. Current sensing scheme
bs O
let o
Pr e
du o
(s) ct
PGND
PM6670
HGATE
so Ob VI N
100AˇRILIM
te le
ro P
uc d
s) t(
VOUT
PHASE CSNS LGATE
IVALLEYˇRDSon
An internal 100A current source is connected to CSNS pin that is also the non-inverting input of the positive current limit comparator. When the voltage drop developed across the sensing parameter equals the voltage drop across the programming resistor RILIM, the controller skips subsequent cycles until the overcurrent condition is detected or the output UV protection latches off the device (see Section 7.1.11: Over Voltage and Under Voltage Protections on page 35 ).
30/53
PM6670
Device description
Referring to Figure 36, the RDSon sensing technique allows high efficiency performance without the need for an external sensing resistor. The on-resistance of the MOSFET is affected by temperature drift and nominal value spread of the parameter itself; this must be considered during the RILIM setting resistor design. It must be taken into account that the current limit circuit actually regulates the inductor valley current. This means that RILIM must be calculated to set a limit threshold given by the maximum DC output current plus half of the inductor ripple current:
Equation 22
ICL = 100A
RILIM RDSon
The PM6670 provides also a fixed negative current limit to prevent excessive reverse inductor current when the switching section sinks current from the load in forced-PWM (3rd quadrant working conditions). This negative current limit threshold is measured between PHASE and PGND pins, comparing the drop magnitude on PHASE pin with an internal 120mV fixed threshold.
7.1.6
POR, UVLO and Soft Start
The PM6670 automatically performs an internal startup sequence during the rising phase of the analog supply of the device (AVCC). The switching controller remains in a stand-by state until AVCC crosses the upper UVLO threshold (4.2V typ.), keeping active the internal discharge MOSFETs (only if AVCC > 1V). The soft-start allows a gradual increase of the internal current limit threshold during start-up reducing the input/output surge currents. At the beginning of start-up, the PM6670 current limit is set to 25% of nominal value and the Under Voltage Protection is disabled. Then, the current limit threshold is sequentially brought to 100% in four steps of approximately 750s (Figure 37).
Figure 37. Soft-start waveforms
bs O
let o
Pr e
du o
Switching output
(s) ct
so Ob -
te le
ro P
uc d
s) t(
Current limit threshold
S5
Time
31/53
Device description
PM6670
After a fixed 3ms total time, the soft-start finishes and UVP is released: if the output voltage doesn't reach the Power-Good lower threshold within soft-start duration, the UVP condition is detected and the device performs a soft end and latches off. Depending on the load conditions, the inductor current may or may not reach the nominal value of the current limit during the soft-start (Figure 38 shows two examples).
Figure 38. Soft-start at heavy load (a) and short-circuit (b) conditions, Pulse-Skip enabled
(a)
7.1.7
Power-Good signal
The PG pin is an open drain output used to monitor output voltage through VSNS (in fixed output voltage mode) or MODE (in adjustable output voltage mode) pins and is enabled after the soft-start timer has expired. PG signal is held low if the VDDQ output voltage drops 10% below or rises 10% above the nominal regulated value. The PG output can sink current up to 4mA.
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
(b)
uc d
s) t(
32/53
PM6670
Device description
7.1.8
VDDQ output discharge
Active discharge of VDDQ output occurs when PM6670 enters the Suspend-To-Disk system state (S3 and S5 tied to GND) and DSCG pin has been properly set.
Figure 39. DSCG pin connection for discharge mode selection
+5V PM6670
VREF
DSCG
The PM6670 allows the user to choose between fast discharge (Tracking Discharge), soft discharge (Non-Tracking Discharge) or no discharge modes. Voltage on DSCG multilevel pin determines discharge mode as shown in Table 2 on page 6.
Table 9. Discharge mode selection
DSCG voltage VDSCG >4.2V 1V< VDSCG <3.5V VDSCG <0.5V Soft-End type No Discharge Fast (Tracking) Soft (Non-Tracking)
Description All outputs left floating.
Tracking discharge allows the fastest discharge of all outputs but requires the LDOIN to be self-supplied from VDDQ output voltage. When an external supply rail is connected to LDOIN, it must be taken into account to avoid damage to the device. Discharge current (1A) flows through the LDOIN pin until the output has reached approximately 400mV and then a soft discharge completes the process by discharging the output with an internal 22 switch.
Figure 40. Fast discharge and soft discharge options
bs O
let o
Pr e
400mV
du o
(s) ct
so Ob -
VDDQ and VTT actively discharged by LDO trough LDOIN and VTT pins;
All outputs discharged by dedicated internal MOS.
te le
ro P
uc d
s) t(
VDDQ
Fast discharge Soft discharge
VDDQ Soft discharge VTT
VTT
33/53
Device description
PM6670
7.1.9
Gate drivers
The integrated high-current gate drivers allow using different power MOSFETs. The highside driver uses a bootstrap circuit which is supplied by the +5V rail. The BOOT and PHASE pins work respectively as supply and return path for the high-side driver, while the low-side driver is directly fed through VCC and PGND pins. An important feature of the PM6670 gate drivers is the Adaptive Anti-Cross-Conduction circuitry, which prevents high-side and low-side MOSFETs from being turned on at the same time. When the high-side MOSFET is turned off, the voltage at the PHASE node begins to fall. The low-side MOSFET is turned on only when the voltage at the PHASE node reaches an internal threshold (2.5V typ.). Similarly, when the low-side MOSFET is turned off, the high-side one remains off until the LGATE pin voltage is above 1V. The power dissipation of the drivers is a function of the total gate charge of the external power MOSFETs and the switching frequency, as shown in the following equation:
Equation 23
PD (driver ) = VDRV Q g fSW
The low-side driver has been designed to have a low-resistance pull-down transistor (0.6 typ.) in order to prevent undesired ignition of the low-side MOSFET due to the Miller effect.
7.1.10
Reference voltage and bandgap
The 1.237V internal bandgap reference has a granted accuracy of 1% over the 0C to 85C temperature range. The VREF pin is a buffered replica of the bandgap voltage. It can supply up to 100A and is suitable to set the intermediate level of MODE, DDRSEL and DSCG multifunction pins. A 100nF (min.) bypass capacitor toward SGND is required to enhance noise rejection. If VREF falls below 0.87V (typ.), the system detects a fault condition and all the circuitry is turned OFF. An internal divider derives a 0.9V1% voltage (Vr) from the bandgap. This voltage is used as a reference by the switching regulator output. The Over-Voltage Protection, the UnderVoltage Protection and the Power-Good signal are also referred to Vr.
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
34/53
PM6670
Device description
7.1.11
Over Voltage and Under Voltage Protections
When the switching output voltage is about 115% of its nominal value, a latched OverVoltage Protection (OVP) occurs. In this case the synchronous rectifier immediately turns on while the high-side MOSFET turns OFF. The output capacitor is rapidly discharged and the load is preserved from being damaged. The OVP is also active during the soft start. Once an OVP has occured, a toggle on S5 pin or a Power-On-Reset is necessary to exit from the latched state. When the switching output voltage is below 70% of its nominal value, a latched UnderVoltage Protection occurs. This event causes the switching section to be immediately disabled and both switches to be opened. The controller enters in Soft-End mode and the output is eventually kept to ground, turning the low side MOSFET on when the voltage is lower than 400mV. If S3 and S5 are forced low, the low-side MOSFET is released and only the 22 switch is active. The Under-Voltage Protection circuit is enabled only at the end of the soft-start. Once an UVP has toccured, a toggle on S5 pin or a Power-On-Reset is necessary to clear the fault state and restart the device.
7.1.12
Device thermal protection
The internal control circuitry of the PM6670 self-monitors the junction temperature and turns all outputs off when the 150C limit has been overrun. This event causes the switching section to be immediately disabled and both switches to be opened. The controller enters in Soft-End Mode and the output is eventually kept to ground, turning the low side MOSFET on when the voltage is lower than 400mV. If S3 and S5 are forced low, the low-side switch is released and only the 22 discharge MOSFET is active. The thermal fault is a latched protection and normal operating condition is restored by a Power-On Reset or toggling S5.
Table 10. OV, UV and OT faults management
Fault VDDQ over voltage Conditions
VDDQ under voltage
bs O
let o
Pr e
od
ct u
VDDQ > 115% of the LGATE pin is forced high and the device latches off. nominal value Exit by a Power-On Reset or toggling S5 VDDQ < 70% of the nominal value LGATE pin is forced high after the Soft-End, then the device latches off. Exit by a Power-On Reset or toggling S5. LGATE pin is forced high after the Soft-End, then the device latches off. Exit by a Power-On Reset or toggling S5 after 15C temperature drop.
(s)
so Ob -
te le
ro P
Action
uc d
s) t(
Junction over temperature
TJ > +150C
35/53
Device description
PM6670
7.2
VTTREF buffered reference and VTT LDO section
The PM6670 provides the required DDR2/3 reference voltage on the VTTREF pin. The internal buffer tracks half the voltage on the VSNS pin and has a sink and source capability up to 15mA. Higher currents rapidly deteriorate the output accuracy. A 10nF to 100nF (33nF typ.) bypass capacitor to SGND is required for stability. The VTT Low-Drop-Out linear regulator has been designed to sink and source up to 2A peak current and 1A continuously. The VTT voltage tracks VTTREF within 35mV. A remote voltage sensing pin (VTTSNS) is provided to recovery voltage drops due to parasitic resistance. In DDR2/3 applications, the linear regulator input LDOIN is typically connected to VDDQ output; connecting LDOIN pin to a lower voltage, if available in the system, reduces the power dissipation of the LDO. A minimum output capacitance of 20F (2x10F MLCC capacitors) is enough to assure stability and fast load transient response.
7.2.1
VTT and VTTREF Soft-Start
Soft-Star t on VTT and VTTREF outputs is achieved by current clamping.
The LDO linear regulator is provided with a current foldback protection: when the output voltage exits the internal 10% VTT-Good window, the output current is clamped at 1A. Reentering VTT-Good window releases the current limit clamping. The foldback mechanism naturally implements a two steps soft-start charging the output capacitors with a 1A constant current. Something similar occurs at VTTREF pin, where the output capacitor is smoothly charged at a fixed 40mA current limit.
7.2.2
VTTREF and VTT outputs discharge
The Tracking Discharge mechanism involves the VTT linear regulator. When the SuspendTo-Disk state is entered, the switching regulator is turned OFF.
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At the same time the LDO drains a 1A constant current from LDOIN and keeps VTT in track with VTTREF that, in turn, is half the voltage at the VSNS pin. When the VDDQ output reaches 400mV, the PM6670 switches on the internal discharge MOSFETs to complete the process (see Section 7.1.8: VDDQ output discharge on page 33). In Soft Discharge (i.e. Non-Tracking Discharge) the PM6670 disables the internal regulators and suddenly turns on the discharge MOSFETs on each output.
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Device description
7.3
S3 and S5 power management pins
According to DDR2/3 memories supply requirements, the PM6670 can manage all S0 to S5 system states by connecting S3-S5 pins to their respective sleep-mode signals in the notebook's motherboard. Keeping S3 and S5 high, the S0 (Full-On) state is decoded and the outputs are alive. In S3 state (S5 = 1, S3 = 0), the PM6670 maintains VDDQ and VTTREF outputs active and VTT output in high-impedance as needed. In S4/S5 states (S5 = S3 = 0) all outputs are turned off and, according to DSCG pin voltage, the proper Soft-End is performed.
Table 11. S3 and S5 Sleep-states decoding
S3 1 0 0 S5 1 1 0 System State S0 (Full-On) S3 (Suspend-To-RAM) S4/S5 (Suspend-To-Disk) VDDQ On On Off (Discharge) VTTREF On On Off (Discharge) VTT On Off (Hi-Z)
Off (Discharge)
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Application information
PM6670
8
Application information
The purpose of this chapter is to show the design procedure of the switching section. The design starts from three main specifications:
The input voltage range, provided by the battery or the AC adapter. The two extreme values (VINMAX and VINmin ) are important for the design. The maximum load current, indicated by ILOAD,MAX. The maximum allowed output voltage ripple VRIPPLE,MAX.
It's also possible that specific designs should involve other specifications. The following paragraphs will guide the user into a step-by-step design.
8.1
External components selection
The PM6670 uses a pseudo-fixed frequency, Constant On-Time (COT) controller as the core of the switching section. The switching frequency can be set by connecting an external divider to the VOSC pin. The voltage seen at this pin must be greater than 0.8V and lower than 2V in order to ensure system's linearity. Nearly constant switching frequency is achieved by the system's loop in steady-state operating conditions by varying the On-Time duration, avoiding thus the need for a clock generator. The On-Time one shot duration is directly proportional to the output voltage, sensed at VSNS pin, and inversely proportional to the input voltage, sensed at the VOSC pin, as follows:
Equation 24
TON = K OSC
where KOSC is a constant value (130ns typ.) and is the internal propagation delay (40ns typ.). The duty cycle of the buck converter is, under steady state conditions, given by
Equation 25
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VSNS + VOSC
D=
VOUT VIN
The switching frequency is thus calculated as
Equation 26
fSW
VOUT VIN 1 D = = = OSC VSNS TON OUT K OSC K OSC VOSC
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PM6670
Application information
where
Equation 27a
OSC =
VOSC VIN
Equation 27b
OUT =
VSNS VOUT
Referring to the typical application schematic (figure in cover page and Figure 29), the final expression is then:
Equation 28
fSW =
OSC R2 1 = K OSC R1 + R 2 K OSC
The switching frequency directly affects two parameters:
Inductor size: greater frequencies mean smaller inductances. In notebook applications, real estate solutions (i.e. low-profile power inductors) are mandatory also with high saturation and r.m.s. currents. Efficiency: switching losses are proportional to the frequency. Generally, higher frequencies imply lower efficiency.
Even if the switching frequency is theoretically independent from battery and output voltages, parasitic parameters involved in power path (like MOSFETs' on-resistance and inductor's DCR) introduce voltage drops responsible for a slight dependence on load current. In addition, the internal delay is due to a light dependence on input voltage.
Table 12. Typical values for switching frequency selection
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R1 (k) 330 330 330 330 330 330
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R2 (k)
Approx switching frequency (kHz) 250 300 350 400 450 500
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Application information
PM6670
8.1.1
Inductor selection
Once the switching frequency has been defined, the inductance value depends on the desired inductor ripple current. Low inductance value means great ripple current that brings poor efficiency and great output noise. On the other hand a great current ripple is desirable for fast transient response when a load step is applied. High inductance brings higher efficiency, but the transient response is critical, especially if VINmin - VOUT is small. Moreover a minimum output ripple voltage is necessary to assure system stability and jitter-free operations (see Output capacitor selection paragraph). The product of the output capacitor's ESR multiplied by the inductor ripple current must be taken into consideration. A good trade-off between the transient response time, the efficiency, the cost and the size is choosing the inductance value in order to maintain the inductor ripple current between 20% and 50% (usually 40%) of the maximum output current. The maximum inductor ripple current, IL,MAX , occurs at the maximum input voltage. Given these considerations, the inductance value can be calculated with the following expression:
Equation 29
L=
VIN - VOUT VOUT fsw IL VIN
where fSW is the switching frequency, VIN is the input voltage, VOUT is the output voltage and IL is the inductor ripple current. Once the inductor value is determined, the inductor ripple current is then recalculated:
Equation 30
IL,MAX =
The next step is the calculation of the maximum r.m.s. inductor current:
Equation 31
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The inductor must have an r.m.s. current greater than IL,RMS in order to assure thermal stability. Then the calculation of the maximum inductor peak current follows:
Equation 32
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VIN,MAX - VOUT
VOUT VIN,MAX
IL,RMS = (ILOAD,MAX )2 +
(IL,MAX )2 12
IL,PEAK = ILOAD,MAX +
IL,MAX 2
IL,PEAK is important in inductor selection in term of its saturation current.
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Application information
The saturation current of the inductor should be greater than IL,PEAK not only in case of hard saturation core inductors. Using soft-ferrite cores it is possible (but not advisable) to push the inductor working near its saturation current. In Table 13 some inductors suitable for notebook applications are listed.
Table 13. Evaluated inductors (@fsw = 400kHz)
Manufacturer COILCRAFT COILCRAFT COILCRAFT WURTH COILTRONICS Series MLC1538-102 MLC1240-901 MVR1261C-112 7443552100 HC8-1R2 Inductance (ěH) 1 0.9 1.1 1 1.2 +40C rms current (A) 13.4 12.4 20 16 16.0 -30% saturation current (A) 21.0 24.5 20 20 25.4
In Pulse-Skip Mode, low inductance values produce a better efficiency versus load curve, while higher values result in higher full-load efficiency because of the smaller current ripple.
8.1.2
Input capacitor selection
In a buck topology converter the current that flows through the input capacitor is pulsed and with zero average value. The RMS input current can be calculated as follows:
Equation 33
2
ICinRMS = ILOAD D (1 - D) +
Neglecting the second term, the equation 10 is reduced to:
Equation 34
The losses due to the input capacitor are thus maximized when the duty-cycle is 0.5:
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Equation 35
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1 D (IL )2 12
ICinRMS = ILOAD D (1 - D)
Ploss = ESR Cin ICinRMS (max)2 = ESR Cin (0.5 ILOAD (max))2
The input capacitor should be selected with a RMS rated current higher than ICINRMS(max). Tantalum capacitors are good in terms of low ESR and small size, but they occasionally can burn out if subjected to very high current during operation. Multi-Layers-Ceramic-Capacitors (MLCC) have usually a higher RMS current rating with smaller size and they remain the best choice. The drawback is their quite high cost.
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Application information
PM6670
It must be taken into account that in some MLCC the capacitance decreases when the operating voltage is near the rated voltage. In Table 14 some MLCC suitable for most of applications are listed.
Table 14. Evaluated MLCC for input filtering
Manufacturer Series Capacitance (F) Rated Voltage (V) 10 10 10 10 10 50 35 35 35 25 Maximum Irms @100kHz (A) 2 2.2 2.2 2.5
TAIYO YUDEN UMK325BJ106KM-T TAIYO YUDEN TAIYO YUDEN TAIYO YUDEN TDK GMK316F106ZL-T GMK325F106ZH-T GMK325BJ106KN C3225X5R1E106M
8.1.3
Output capacitor selection
Using tantalum or electrolytic capacitors, the selection is made referring to ESR and voltage rating rather than by a specific capacitance value. The output capacitor has to satisfy the output voltage ripple requirements. At a given switching frequency, small inductor values are useful to reduce the size of the choke but increase the inductor current ripple. Thus, to reduce the output voltage ripple a low ESR capacitor is required.
To reduce jitter noise between different switching regulators in the system, it is preferable to work with an output voltage ripple greater than 25mV. As far as it concerning the load transient requirements, the Equivalent Series Resistance (ESR) of the output capacitor must satisfy the following relationship:
Equation 36
where VRIPPLE is the maximum tolerable ripple voltage. In addition, the ESR must be high enough high to meet stability requirements. The output capacitor zero must be lower than the switching frequency:
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Equation 37
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VRIPPLE,MAX IL,MAX
fSW > fZ =
1 2 ESR C out
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PM6670
Application information
If ceramic capacitors are used, the output voltage ripple due to inductor current ripple is negligible. Then the inductance could be smaller, reducing the size of the choke. In this case it is important that output capacitor can adsorb the inductor energy without generating an over-voltage condition when the system changes from a full load to a no load condition. The minimum output capacitance can be chosen by the following equation:
Equation 38
COUT,min =
L ILOAD,MAX Vf 2 - Vi 2
where Vf is the output capacitor voltage after the load transient, while VI is the output capacitor voltage before the load transient. In Table 15 are listed some tested polymer capacitors are listed.
Table 15. Evaluated output capacitors
Manufacturer Series 4TPE220MF SANYO 4TPE150MI 4TPC220M HITACHI TNCB OE227MTRYF Capacitance (F) 220 220 220 220 Rated voltage (V) 4V 4V 4V
ESR max @100kHz (m)
8.1.4
MOSFETs selection
In a notebook application, power management efficiency is a high level requirement. Power dissipation on the power switches becomes animportant factor in the selection of switches. Losses of high-side and low-side MOSFETs depend on their working condition. Considering the high-side MOSFET, the power dissipation is calculated as:
Equation 39
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Maximum conduction losses are approximately given by:
Equation 40
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40
25
PDHighSide = Pconduction + Pswitching
Pconduction = RDSon
VOUT 2 ILOAD,MAX VIN. min
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Application information
PM6670
where RDSon is the drain-source on-resistance of the control MOSFET. Switching losses are approximately given by:
Equation 41
Pswitching =
VIN (ILOAD (max) - 2
IL I ) t on fsw VIN (ILOAD (max) + L ) t off fsw 2 2 + 2
where tON and tOFF are the turn-on and turn-off times of the MOSFET and depend on the gate-driver current capability and the gate charge Qgate. A greater efficiency is achieved with low RDSon. Unfortunately low RDSon MOSFETs have a great gate charge. As general rule, the RDSon x Qgate product should be minimized to find out the suitable MOSFET. Logic-level MOSFETs are recommended, as long as low-side and high-side gate drivers are powered by VVCC = +5V. The breakdown voltage of the MOSFETs (VBRDSS) must be greater than the maximum input voltage .VINmax. Table 15 lists tested high-side MOSFETs.
Table 16. Evaluated high-side MOSFETs
Manufacturer ST IR Type STS12NH3LL IRF7811 RDSon (m) 10.5 9
In buck converters the power dissipation of the synchronous MOSFET is mainly due to conduction losses:
Equation 42
Maximum conduction losses occur at the maximum input voltage:
Equation 43
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12 18
Gate charge (nC)
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30 30
Rated reverse voltage (V)
PDLowSide Pconduction
V Pconduction = RDSon 1 - OUT V IN,MAX
ILOAD,MAX 2
The synchronous rectifier should have the lowest RDSon as possible. When the high-side MOSFET turns on, high dV/dt of the phase node can bring up even the low-side gate through its gate-drain capacitance CRRS, causing a cross-conduction problem. Once again, the choice of the low-side MOSFET is a trade-off between on resistance and gate charge; a good selection should minimize the ratio CRSS / CGS where
Equation 44
CGS = CISS - CRSS
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Application information
Tested low-side MOSFETs are listed in Table 16.
Table 17. Evaluated low-side MOSFETs
Manufacturer ST ST IR Type STS12NH3LL STS25NH3LL IRF7811 RDSon (m) 13.5 40 24 CGD \ CGS 0.069 0.011 0.054 Rated reverse voltage (V) 30 30 30
Dual N-MOS can be used in applications with lower output current.
Table 18 shows some suitable dual MOSFETs for applications requiring about 3A. Table 18. Suitable dual MOSFETs
Manufacturer ST IR Type STS8DNH3LL IRF7313 RDSon (m) 25 46 Gate Charge (nC) 10 33 Rated reverse voltage (V) 30 30
8.1.5
Diode selection
A rectifier across the synchronous switch is recommended. The rectifier works as a voltage clamp across the synchronous rectifier and reduces the negative inductor swing during the dead time between turning the high-side MOSFET off and the synchronous rectifier on. Moreover it increases the efficiency of the system. Choose a schottky diode as long as its forward voltage drop is very little (0.3V). The reverse voltage should be greater than the maximum input voltage VINmax and a minimum recovery reverse charge is preferable. Table 19 shows some evaluated diodes.
Table 19. Evaluated recirculation rectifiers
Manufacturer ST ST
STPS1L30M STPS1L30A
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Forward voltage (V) 0.34 0.34
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Rated reverse voltage (V) 30 30
Reverse current (A) 0.00039 0.00039
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Application information
PM6670
8.1.6
VDDQ current limit setting
The valley current limit is set by RCSNS and must be chosen to support the maximum load current. The valley of the inductor current ILvalley is:
Equation 45
ILvalley = ILOAD (max) -
IL 2
The output current limit depends on the current ripple as shown I Figure 41:
Figure 41. Valley current limit waveforms
Inductor current
Current Inductor current
MAX LOAD 2 MAX LOAD 1
Valley current limit
As the valley threshold is fixed, the greater the current ripple, the greater the DC output current will be. If an output current limit greater than ILOAD(max) over all the input voltage range is required, the minimum current ripple must be considered in the previous formula. Then the resistor RCSNS is:
Equation 46
where RDSon is the drain-source on-resistance of the low-side switch. Consider the temperature effect and the worst case value in RDSon calculation (typically +0.4%/C).
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The accuracy of the valley current also depends on the offset of the internal comparator (5mV). The negative valley-current limit (if the device works in forced-PWM mode) is given by:
Equation 47
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RCSNS =
RDSon ILvalley 100uA
INEG =
120mV RDSon
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PM6670
Application information
8.1.7
All ceramic capacitors application
Design of external feedback network depends on the output voltage ripple across the output capacitors' ESR. If the ripple is great enough (at least 20mV), the compensation network simply consists of a CINT capacitor.
Figure 42. Integrative compensation
Ton One-shot generator
VSNS
PWM Comparator VREF
VDDQ
+ -
+
COMP
Integrator
gm
-
Vr=0.9
CFILT
RINT
CINT
The stability of the system depends firstly on the output capacitor zero frequency. It must be verified that:
Equation 48
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fSW > k fZout =
k 2 R out C out
where k is a free design parameter greater than unity (k > 3) . It determines the minimum integrator capacitor value CINT:
Equation 49
CINT >
Vref f Vo 2 SW - fZout k
gm
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Application information
PM6670
If the ripple on pin COMP is greater than the integrator output dynamic (150mV), an additional capacitor Cfilt could be added in order to reduce its amplitude. If q is the desired attenuation factor of the output ripple, select:
Equation 50
C filt =
CINT (1 - q) q
In order to reduce noise on pin COMP, it's possible to introduce a resistor RINT that, together with CINT and Cfilt, becomes a low psas filter. The cutoff frequency fCUT must be much greater (10 or more times) than the switching frequency of the section:
Equation 51
RINT =
2 fCUT
1 CINT CFILT CINT + CFILT
For most of applications both RINT and Cfilt are unnecessary.
If the ripple is very small (e.g. such as with ceramic capacitors), an additional compensation network, called "Virtual ESR" network, is needed. This additional part generates a triangular ripple that substitutes the ESR output voltage ripple. The complete compensation scheme is represented in Figure 43.
Figure 43. Virtual ESR network
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R1
VDDQ
C RINT
PWM Comparator
+
gm
Ton Generation Block
VREF
0.9V
CFILT
Integrator
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Application information
Select C as shown:
Equation 52
C > 5 CINT Then calculate R in order to have enough ripple voltage on the integrator input:
Equation 53
R=
L R VESR C
Where RVESR is the new virtual output capacitor ESR. A good trade-off is to consider an equivalent ESR of 30-50m , even though the choice depends on inductor current ripple. Then choose R1 as follows:
Equation 54
1 R Cf Z R1 = 1 R- CfZ
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Package mechanical data
PM6670
9
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Table 20. VFQFPN-24 4mm x 4mm mechanical data
mm. Dim. Typ A A1 A2 D D1 E E1 0.00 0.65 4.00 3.75 4.00 3.75 Min. 0.80 Max. 1.00 0.05 0.80
P e N Nd Ne L b 0.42 0.50
24.00 6.00
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6.00
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0.24 0.30 0.18
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12 0.60
0.40
0.50 0.30 2.25 2.25
2.10 2.10
1.95 1.95
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Package mechanical data
Figure 44. Package dimensions
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Revision history
PM6670
10
Revision history
Table 21. Revision history
Date 1-Mar-2007 Revision 1 Initial release Changes
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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
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