STLQ50XX
50 mA, 3 A supply current low drop linear regulator
Features
2.3 V to 12 V input voltage range 50 mA maximum output current 3 A quiescent current Available in 1.8 V, 2.5 V, 3.3 V, 5.0 V and adjustable 200 mV dropout voltage at 25 mA output current Internal thermal protection Available in SOT323-5L package, and SOT235L package (upon request)
SOT323-5L SOT23-5L (available on request)
Description
The STLQ50 is a BiCMOS linear regulator specifically designed for operating in environment with very low power consumption constraints. Due to the very low quiescent current (3 A) the device is suitable for those application that have very long stand-by time allowing extension of battery life. The P-MOS pass element allows also a very good drop-out figure (200 mV at 25 mA IO and 350 mV at full load) without affecting the consumption characteristics. Housed in the very small SOT323-5L or SOT235L, it fulfils the space saving requirements in battery powered equipments.
Applications
Portable/battery powered equipments Electronic sensors Microcontroller power Real time clock backup power
Table 1.
Device summary
Order codes
Part number SOT323-5L (T&R) STLQ50XX18 STLQ50XX25 STLQ50XX33 STLQ50XX50 STLQ50
1. Available upon request.
Packages SOT23-5L (T&R) (1) STLQ50M18R STLQ50M25R STLQ50M33R STLQ50M50R STLQ50M-R
Output voltage
STLQ50C18R STLQ50C25R STLQ50C33R STLQ50C50R STLQ50C-R
Fixed VO = 1.8V Fixed VO = 2.5V Fixed VO = 3.3V Fixed VO = 5.0V Adjustable
November 2007
Rev. 4
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STLQ50XX
Contents
1 2 3 4 5 6 7 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7.1 7.2 7.3 External components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
8 9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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Diagram
1
Figure 1.
Diagram
Block diagram
Vin
V bandgap 1.22V
Vout
Adjustable
Fixed
A DJ
Short circuit & thermal protection
GND
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Pin configuration
STLQ50XX
2
Figure 2.
Pin configuration
Pin connections (top view)
ADJ GND N/C N/C
OUT
STLQ 5 0
IN
Table 2.
Pin n 1
Pin description
Symbol ADJ N/C STLQ50: output voltage adjust STLQ50xx: not connected Ground Not connected Input voltage Output voltage Note
2 3 4 5
GND N/C IN OUT
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Maximum ratings
3
Table 3.
Symbol VI VFB ESD TJ TSTG
Maximum ratings
Absolute maximum ratings
Parameter DC Input voltage FB voltage Human body model (all pins) Junction temperature Storage temperature range Value -0.3 to +14 -0.3 to +7 2 -40 to 150 -55 to 150 Unit V V kV C C
Note:
Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Thermal data
Parameter Thermal resistance junction-ambient SOT323-5L 331.4 (1) SOT23-5L 191 (1) Unit C/W
Table 4.
Symbol RthJA
1. This value is referred to a 4-layer PCB, JEDEC standard test board.
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Electrical characteristics
STLQ50XX
4
Table 5.
Electrical characteristics
Electrical characteristics (VI = VO(NOM) +1 V or VI = 2.5 V if VO + 1.5 V; TA= -40 C to 125 C; IO = 1 mA; typical values are at TA = 25 C, CO = 1 F unless otherwise specified)
Parameter Input voltage range Quiescent current (Measured on ground pin, fixed version) Output voltage range (STLQ50ADJ) VO Accuracy as percentage of nominal voltage at TJ=25C IO=50mA; 1mA < IO <50mA VO=1.5V: VO+1V < VI <12V; VO=1.5V: 2.5V < VI <12V; VRIPPLE = 0.1V, IO= 20mA f=120Hz BW from 200Hz to 100KHZ; IO=10mA 30 560 160 VO=0V 500 Test conditions IO=20mA IO=50mA VI=5V VI=12V 1.222 -2 0.4 Min. 2.3 2.5 3.5 4.1 Typ. Max. 12 V 12 5.0 A 6.0 11 +2 0.7 0.15 V % V %/mA Unit
Symbol VI
IQ
VDROP-MAX Max dropout voltage (1)
VO VO
Load regulation
Line regulation
0.3
%/V
SVR eN Th IOMAX
Supply voltage rejection Output noise voltage Thermal protection Maximum output current (2)
dB VRMS C mA
1. VI=2.5V when VO(NOM) 2.1V 2. The maximum power dissipation must not be exceeded, see application information for details.
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Typical application
5
Figure 3.
Typical application
Fixed versions: STLQ5018- STLQ5025- STLQ5033- STLQ5050
Figure 4.
Adjustable version STLQ50ADJ
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Typical characteristics
STLQ50XX
6
Figure 5.
1.84 1.82 1.8 VO [V] 1.78 1.76 1.74 1.72 -50
Typical characteristics
VO vs TJ Figure 6. VO vs VI
2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 1 2 VI [V] 3
VO [V]
VI=2.8V, IO=20mA
-2 5 0 25 50 75 100 125
IO=50mA, VO=1.8V
4 5
Temp [C]
Figure 7.
IQ vs TJ
Figure 8.
VDROP vs IO
3.5 3.4 3.3 Iq [A] 3.2 3.1 3 2.9 2.8 -5 0 - 25 0 25 50 75 100 125 Temp [C]
0.5 0.45 0.4 VDROP [V] 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 0 10 20 IO [mA] 30
VI=5V, IO=1mA, VO=1.8V
TA=25C
40 50
Figure 9.
VDROP vs TJ
Figure 10. Stability
12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 2 CO [ F ] 3 4
0.7 0.6 0.5 VDROP [V] 0.4 0.3 0.2 0.1 0 -5 0 - 25 0 25 50 75 1 00 12 5 Temp [C]
TA=25C
VO=2.45V, IO=50mA
ESR[ ]
5
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Typical characteristics
Figure 11. S.V.R. vs Freq.
Figure 12. S.V.R. vs IO
37 32 SVR [dB] 27 22 17 12 7 2 1 00 100 0
VO=1.8V, IO=20mA
SVR [dB]
40 38 36 34 32 30 28 26 24 22 20 0 10 20 IO [mA] 30
VO=1.8V, f=120Hz
40 50
10 000
1 000 00
Frequency [Hz]
Figure 13. Line transient response
Figure 14. Load transient response
IO=50mA; CO=10F; VI=2.8V, VI rise/fall=5ms
CO=1F; VO=1.8V; VI=2.8V, Curr. rise/fall=1s
Figure 15. Short circuit current
0.6 0.5 0.4 IO [A]
Figure 16. Thermal protection
2 1.75 1.5 VO[V] 1.25 1 0.75
V I =2.8V
0.3 0.2 0.1 0 2 4 6 8 VI [V]
0.5 0.25
VO=0, TA=25C
10 12 14
0 155 157 159 161 163 165 167 169 171 173 175 TJ[C]
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Application information
STLQ50XX
7
Application information
The STLQ50 is a BiCMOS linear regulator specifically designed for operating in environment with very low power consumption constraints. The very low quiescent current of 3 A is obtained with use of CMOS technology that makes the device suitable for those application that have very long stand-by time. The very low power consumption allows extending the battery life and the tiny packages (SOT323-5L or SOT23-5L) fulfil the space saving requirements of battery powered equipments. Moreover the STLQ50 provides wide input voltage operation from 2.5 V up to 12 V. The P-MOS pass element allows also a very good drop-out figure: 0.7 V at full load and at 125 C without affecting the consumption characteristics.
7.1
External components
The typical application schematic of STLQ50 is shown in Figure 1 - Figure 2, a 1 F input and output capacitors placed close to the device are needed in order to provide proper operation. The device is stable with electrolytic and ceramic output capacitors having values higher than 1 F (see figure typical characteristics for stability details). In the adjustable version (STLQ50) the output voltage is programmed using an external resistor divider as shown in Figure 2. The output voltage can be adjusted from 1.22 to 11 V and it can be calculated using the following formula: VO = VFB x (1+R1/R2) where VFB=1.222 V is the internal reference voltage; The sum between R1 and R2 resistors should be chosen in order to guarantee 1 A of divider current at least. Lower value resistors will improve the noise performances but the quiescent current will increase. Higher value resistors should be avoided because the ADJ leakage current will influence the voltage set by the resistor divider making the above formula no more valid. The suggested design procedure is to choose R2 = 1 M and then calculate R1 using the following formula: R1 = (VO/VFB-1) x R2
7.2
Power dissipation
In order to ensure proper operation, the STLQ50 junction temperature should never exceed 125 C, this limits the maximum power dissipation the regulator can sustain in any application. The maximum power dissipation can be calculated as: PDMAX = (TJMAX - TA)/RthJA where TJMAX = 125 C; TA is the ambient temperature; RthJA is the junction to ambient thermal resistance of the package (seeTable 4 thermal data). The power dissipation can be calculated simply as: PD = (VI - VO) x IO In every application condition, PD must be lower than PDMAX.
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Application information
7.3
Protection
The P-MOS pass element has an internal diode with anode connected to VO and cathode to VI. In case VO > VI the current will flow from output to the input without any limitation. In this case proper limiting network is recommended. The current limitation is automatically provided by the characteristics of the PMOS pass element (see typical characteristics), so the short circuit current is dependent on the input voltage. When considering the short circuit current take care, in any case, to not exceed the maximum power dissipation sustainable by the device. The STLQ50 features an internal thermal protection that linearly reduces the output current when the internal temperature increases, consequently, at a given load, also the output voltage decreases. The action of the thermal protection starts at 125 C when the output voltage slightly decreases, while close to 163 C the output voltage drops to 0 V. Since this is a linear control, sudden over current conditions can quickly rise the chip temperature without time for the thermal protection to act, so it cannot be used as a limitation for the output current.
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Package mechanical data
STLQ50XX
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Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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Package mechanical data
SOT323-5L mechanical data
mm . Dim. Min. A A1 A2 b C D E E1 e e1 L 0 .10 0.80 0.00 0.80 0.15 0 .10 1.80 1.80 1.15 0 .65 1.3 0. 3 0 3.9 Typ. Max. 1.10 0.10 1.00 0. 3 0 0.1 8 2.20 2.40 1.35 Min. 31.5 0.0 31.5 5.9 3 .9 70.9 70.9 45.3 25.6 51.2 11.8 Typ. Max. 43.3 3.9 39.4 11.8 7.1 86.6 94.5 53.1 mi l s .
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Package mechanical data
STLQ50XX
SOT23-5L mechanical data
mm . Dim. Min. A A1 A2 b C D E e H L 2.60 0 .10 0.90 0.00 0.90 0.35 0 .09 2.80 1.50 0 .95 3.00 0.60 102.3 3.9 Typ. Max. 1.45 0.10 1.30 0.50 0.20 3.00 1.75 Min. 35.4 0.0 35.4 13.7 3 .5 110.2 59.0 37.4 118.1 23.6 Typ. Max. 57.1 3.9 51.2 19.7 7. 8 118.1 68.8 mi l s .
7049676D
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Package mechanical data
Tape & reel SOT323-xL mechanical data
mm. Dim. Min. A C D N T Ao Bo Ko Po P 3.9 3.8 2.25 2.7 1.2 4 4 4.1 4.2 0.153 0.149 175 12.8 20.2 59.5 60 60.5 14.4 0.088 0.106 0.047 0.157 0.157 0.161 0.165 Typ. 180 13 Max. 185 13.2 Min. 6.889 0.504 0.795 2.362 0.567 Typ. 7.086 0.512 Max. 7.283 0.519 inch.
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Package mechanical data
STLQ50XX
Tape & reel SOT23-xL mechanical data
mm. Dim. Min. A C D N T Ao Bo Ko Po P 3.13 3.07 1.27 3.9 3.9 3.23 3.17 1.37 4.0 4.0 12.8 20.2 60 14.4 3.33 3.27 1.47 4.1 4.1 0.123 0.120 0.050 0.153 0.153 0.127 0.124 0.054 0.157 0.157 13.0 Typ. Max. 180 13.2 0.504 0.795 2 .362 0.567 0.131 0.128 0.0.58 0.161 0.161 0.512 Min. Typ. Max. 7.086 0.519 inch.
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Revision history
9
Table 6.
Date
Revision history
Document revision history
Revision 1 2 3 4 Initial release. Typo in cover page 350mA ==> 350mV. Added part number. Added Table 1. Changes
07-Feb-2007 13-Feb-2007 06-Jul-2007 14-Nov-2007
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STLQ50XX
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