STM32F103x8 STM32F103xB
Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces
Features
Core: ARM 32-bit CortexTM-M3 CPU 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access Single-cycle multiplication and hardware division Memories 64 or 128 Kbytes of Flash memory 20 Kbytes of SRAM Clock, reset and supply management 2.0 to 3.6 V application supply and I/Os POR, PDR, and programmable voltage detector (PVD) 4-to-16 MHz crystal oscillator Internal 8 MHz factory-trimmed RC Internal 40 kHz RC PLL for CPU clock 32 kHz oscillator for RTC with calibration Low power Sleep, Stop and Standby modes VBAT supply for RTC and backup registers 2 x 12-bit, 1 s A/D converters (up to 16 channels) Conversion range: 0 to 3.6 V Dual-sample and hold capability Temperature sensor DMA 7-channel DMA controller Peripherals supported: timers, ADC, SPIs, I2Cs and USARTs Up to 80 fast I/O ports 26/37/51/80 I/Os, all mappable on 16 external interrupt vectors, all 5 V-tolerant except for analog inputs
LQFP48 7 x 7 mm
LQFP100 14 x 14 mm
LQFP64 10 x 10 mm
VFQFPN36 6 × 6 mm
BGA100 10 x 10 mm
Debug mode Serial wire debug (SWD) & JTAG interfaces 7 timers Three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter 16-bit, 6-channel advanced control timer: up to 6 channels for PWM output, deadtime generation and emergency stop 2 watchdog timers (Independent and Window) SysTick timer: a 24-bit downcounter Up to 9 communication interfaces Up to 2 x I2C interfaces (SMBus/PMBus) Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) Up to 2 SPIs (18 Mbit/s) CAN interface (2.0B Active) USB 2.0 full-speed interface CRC calculation unit, 96-bit unique ID Packages are ECOPACK Device summary
Part number STM32F103C8, STM32F103R8 STM32F103V8, STM32F103T8 STM32F103RB STM32F103VB, STM32F103CB
Table 1.
Reference
STM32F103x8 STM32F103xB
September 2008
Rev 9
1/84
www.st.com 1
Contents
STM32F103x8, STM32F103xB
Contents
1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 2.3 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 4 5
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1 Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2 5.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 5.3.10 5.3.11 5.3.12 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 32 Embedded reset and power control block characteristics . . . . . . . . . . . 32 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 51 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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STM32F103x8, STM32F103xB 5.3.13 5.3.14 5.3.15 5.3.16 5.3.17 5.3.18
Contents
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . . 62 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.1 6.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.2.1 6.2.2 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 76
7 8
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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List of tables
STM32F103x8, STM32F103xB
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F103xx medium-density device features and peripheral counts . . . . . . . . . . . . . . . . 8 STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Medium-density STM32F103xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 33 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 37 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 38 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Typical current consumption in Sleep mode, code with data processing code running from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 HSE 4-16 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 USB: Full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
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STM32F103x8, STM32F103xB Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55.
List of tables
RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 69 LFBGA100 - low profile fine pitch ball grid array package mechanical data. . . . . . . . . . . . 70 LQPF100, 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . 72 LQFP64, 64-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . 73 LQFP48, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . 74 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
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List of figures
STM32F103x8, STM32F103xB
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. STM32F103xx performance line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 STM32F103xx performance line BGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 STM32F103xx performance line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 STM32F103xx performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 STM32F103xx performance line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 STM32F103xx Performance Line VFQFPN36 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 36 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 36 Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 66 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . 67 VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Recommended footprint (dimensions in mm)(1)(2)(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 LFBGA100 - low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . 70 Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . 71 LQFP100, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 LQFP64, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 LQFP48, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
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STM32F103x8, STM32F103xB
Introduction
1
Introduction
This datasheet provides the ordering information and mechanical device characteristics of the STM32F103x8 and STM32F103xB medium-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family, please refer to Section 2.2: Full compatibility throughout the family. The medium-density STM32F103xx datasheet should be read in conjunction with the low-, medium- and high-density STM32F10xxx reference manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the CortexTM-M3 core please refer to the CortexTM-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.
2
Description
The STM32F103x8 and STM32F103xB performance line family incorporates the highperformance ARM CortexTM-M3 32-bit RISC core operating at a 72 MHz frequency, highspeed embedded memories (Flash memory up to 128 Kbytes and SRAM up to 20 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer two 12-bit ADCs, three general purpose 16-bit timers plus one PWM timer, as well as standard and advanced communication interfaces: up to two I2Cs and SPIs, three USARTs, an USB and a CAN. The STM32F103xx medium-density performance line family operates from a 2.0 to 3.6 V power supply. It is available in both the 40 to +85 C temperature range and the 40 to +105 C extended temperature range. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F103xx medium-density performance line family includes devices in 5 different package types: from 36 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the STM32F103xx medium-density performance line microcontroller family suitable for a wide range of applications:
Motor drive and application control Medical and handheld equipment PC peripherals gaming and GPS platforms Industrial applications: PLC, inverters, printers, and scanners Alarm systems, Video intercom, and HVAC
Figure 1 shows the general block diagram of the device family.
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Description
STM32F103x8, STM32F103xB
2.1
Device overview
Table 2. STM32F103xx medium-density device features and peripheral counts
STM32F103Tx 64 20 3 1 1 1 2 1 1 26 2 10 channels 2 2 3 1 1 37 2 10 channels STM32F103Cx 64 20 3 1 2 2 3 1 1 128 20 3 STM32F103Rx 64 20 3 1 2 2 3 1 1 51 2 16 channels 128 STM32F103Vx 64 20 3 1 2 2 3 1 1 80 2 16 channels 128
Peripheral
Flash - Kbytes SRAM - Kbytes Timers Communication General-purpose Advanced-control SPI I2C USART USB CAN GPIOs 12-bit synchronized ADC Number of channels CPU frequency Operating voltage Operating temperatures Packages
72 MHz 2.0 to 3.6 V Ambient temperatures: 40 to +85 C /40 to +105 C (see Table 8) Junction temperature: 40 to + 125 C (see Table 8) VFQFPN36 LQFP48 LQFP64 LQFP100, BGA100
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STM32F103x8, STM32F103xB
Description
2.2
Full compatibility throughout the family
The STM32F103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as medium-density devices, and the STM32F103xC, STM32F103xD and STM32F103xE are referred to as high-density devices. Low- and high-density devices are an extension of the STM32F103x8/B devices, they are specified in the STM32F103x4/6 and STM32F103xC/D/E datasheets, respectively. Lowdensity devices feature lower Flash memory and RAM capacities, less timers and peripherals. High-density devices have higher Flash memory and RAM capacities, and additional peripherals like SDIO, FSMC, I2S and DAC, while remaining fully compatible with the other members of the STM32F103xx family. The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD and STM32F103xE are a drop-in replacement for STM32F103x8/B medium-density devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. Moreover, the STM32F103xx performance line family is fully compatible with all existing STM32F101xx access line and STM32F102xx USB access line devices. Table 3. STM32F103xx family
Low-density devices Pinout 16 KB Flash 32 KB Flash(1) Medium-density devices 64 KB Flash 128 KB Flash High-density devices 256 KB Flash 384 KB Flash 512 KB Flash
6 KB RAM 10 KB RAM 20 KB RAM 20 KB RAM 48 KB RAM 64 KB RAM 64 KB RAM 144 100 64 48 36 2 × USARTs 2 × 16-bit timers 1 × SPI, 1 × I2C, USB, CAN, 1 × PWM timer 2 × ADCs 3 × USARTs 3 × 16-bit timers 2 × SPIs, 2 × I2Cs, USB, CAN, 1 × PWM timer 2 × ADC 5 × USARTs 4 × 16-bit timers, 2 × basic timers 3 × SPIs, 2 × I2Ss, 2 × I2Cs USB, CAN, 2 × PWM timers 3 × ADCs, 1 × DAC, 1 × SDIO FSMC (100 and 144 pins)
1. For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7), the reference datasheet for electrical characteristics is that of the STM32F103x8/B medium-density devices.
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Description
STM32F103x8, STM32F103xB
2.3
Overview
ARM CortexTM-M3 core with embedded Flash and SRAM
The ARM CortexTM-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM CortexTM-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The STM32F103xx performance line family having an embedded ARM core, is therefore compatible with all ARM tools and software. Figure 1 shows the general block diagram of the device family.
Embedded Flash memory
64 or 128 Kbytes of embedded Flash is available for storing programs and data.
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
Embedded SRAM
Twenty Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.
Nested vectored interrupt controller (NVIC)
The STM32F103xx performance line embeds a nested vectored interrupt controller able to handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of CortexTM-M3) and 16 priority levels.
Closely coupled NVIC gives low-latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving higher priority interrupts Suppor t for tail-chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt latency.
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STM32F103x8, STM32F103xB
Description
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected to the 16 external interrupt lines.
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator). Several prescalers allow the configuration of the AHB frequency, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the high-speed APB domains is 72 MHz. The maximum allowed frequency of the low-speed APB domain is 36 MHz. See Figure 2 for details on the clock tree.
Boot modes
At startup, boot pins are used to select one of three boot options:
Boot from User Flash Boot from System Memory Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1. For further details please refer to AN2606.
Power supply schemes
VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.
For more details on how to connect power pins, refer to Figure 11: Power supply scheme.
Power supply supervisor
The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher
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Description
STM32F103x8, STM32F103xB than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table 10: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD.
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
MR is used in the nominal regulation mode (Run) LPR is used in the Stop mode Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high impedance output.
Low-power modes
The STM32F103xx performance line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:
Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
Stop mode The Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB wakeup.
Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode.
DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer.
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STM32F103x8, STM32F103xB
Description
Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose and advanced-control timers TIMx and ADC.
RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are ten 16-bit registers used to store 20 bytes of user application data when VDD power is not present. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-power RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural crystal deviation. The RTC features a 32-bit programmable counter for long-term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. The counter can be frozen in debug mode.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.
SysTick timer
This timer is dedicated for OS, but could also be used as a standard downcounter. It features:
A 24-bit downcounter Autoreload capability Maskable system interrupt generation when the counter reaches 0 Programmable clock source
General-purpose timers (TIMx)
There are up to three synchronizable general-purpose timers embedded in the STM32F103xx performance line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages.
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Description
STM32F103x8, STM32F103xB The general-purpose timers can work together with the advanced-control timer via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.
Advanced-control timer (TIM1)
The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead-times. It can also be seen as a complete general-purpose timer. The 4 independent channels can be used for
Input capture Output compare PWM generation (edge- or center-aligned modes) One-pulse mode output
If configured as a general-purpose 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%). In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switch driven by these outputs. Many features are shared with those of the general-purpose TIM timers which have the same architecture. The advanced-control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining.
I²C bus
Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes. They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. A hardware CRC generation/verification is embedded. They can be served by DMA and they support SM Bus 2.0/PM Bus.
Universal synchronous/asynchronous receiver transmitter (USART)
One of the USART interfaces is able to communicate at speeds of up to 4.5 Mbit/s. The other available interfaces communicate at up to 2.25 Mbit/s. They provide hardware management of the CTS and RTS signals, IrDA SIR ENDEC support, are ISO 7816 compliant and have LIN Master/Slave capability. All USART interfaces can be served by the DMA controller.
Serial peripheral interface (SPI)
Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in fullduplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. Both SPIs can be served by the DMA controller.
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STM32F103x8, STM32F103xB
Description
Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks.
Universal serial bus (USB)
The STM32F103xx performance line embeds a USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator).
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-currentcapable except for analog inputs. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. I/Os on APB2 with up to 18 MHz toggling speed
ADC (analog-to-digital converter)
Two 12-bit analog-to-digital converters are embedded into STM32F103xx performance line devices and each ADC shares up to 16 external channels, performing conversions in singleshot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow:
Simultaneous sample and hold Interleaved sample and hold Single shunt
The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the general-purpose timers (TIMx) and the advanced-control timer (TIM1) can be internally connected to the ADC start trigger, injection trigger, and DMA trigger respectively, to allow the application to synchronize A/D conversion and timers.
Temperature sensor
The temperature sensor has to generate a linear voltage with any variation in temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC12_IN16 input channel which is used to convert the sensor output voltage into a digital value.
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Description
STM32F103x8, STM32F103xB
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. Figure 1.
TRACECLK TRACED[0:3] as AS
STM32F103xx performance line block diagram
TPIU SW/JTAG Trace/trig
pbu s Ibu s
Tra ce Controlle r
f l ash obl Inte rfac e
POWER VOLT. REG. 3.3V TO 1.8V @VDD
JN TRST JT DI JT CK/ SWCL K J TMS/SWDIO JT DO as AF
VDD = 2 to 3.6V
VSS
Cortex-M3 CPU
Fmax : 72 MHz Dbus
Flash 128 KB 64 bit
BusM atrix
NVIC
Syst em
SRAM 20 KB
PCL K 1 PCL K 2 HCL K FCL K RC 8 MHz RC 40 kHz @VDDA @VBAT PLL & CLO CK MANAGT
@VDD XTAL OSC 4-16 MHz OSC_IN OSC_OUT
GP DMA
AH B:F ma x =48/72 MHz
7 channels
IWDG Stand b y in t er f ac e
@VDDA SUPPL Y SUPERVISION POR / PDR PVD 80AF PA[ 15: 0] PB[ 15: 0] PC[ 15: 0] PD[ 15: 0] PE[ 15: 0] EXTI WA KE UP GPIOA GPIOB GPIOC GPIOD GPIOE
AP B 2 : F ma x =48 / 72 MHz
VBAT OSC32_IN OSC32_OUT TAMPER-RTC
NRST VDDA VSSA
Rs t Int
XTAL 32 kHz AH B2 AP B2 AH B2 APB 1 RTC AW U B ack up re g
Ba cku p i n t erf ac e TIM2 TIM3
APB1 : Fma x =24 / 36 MHz
4 Chann el s 4 Chann el s 4 Chann el s RX,TX, CTS, RTS, CK, SmartCard as AF RX,TX, CTS, RTS, CK, SmartCard as AF MOSI,MISO,SCK ,NSS as AF SCL ,SDA ,SMBA L as AF SCL ,SDA as AF USBDP /CA NTX USBDM/CANRX
TIM 4 USAR T2 USAR T3 S 2x(8x16bit) PI2 I2C1 I2C2 bx CA N USB 2.0 FS
4 Chann el s 3 co m p l . Chann el s Brk i npu t MOSI,MISO, SCK ,NSS as AF RX,TX, CTS, RTS, Smart Card as AF
TIM1 SPI1 USA RT1 @VDDA
16AF VREF+ VREF-
12b i t A DC1 IF SRA M 512B 12bi t ADC 2 IF WWDG Tem p sensor
ai14390b
1. TA = 40 C to +105 C (junction temperature up to 125 C). 2. AF = alternate function on I/O port pin.
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STM32F103x8, STM32F103xB Figure 2. Clock tree
8 MHz HSI RC
HSI
Description
/2
USB Prescaler /1, 1.5
48 MHz
USBCLK to USB interface HCLK to AHB bus, core, memory and DMA to Cortex System timer FCLK Cortex free running clock PCLK1 to APB1 peripherals Peripheral Clock
Enable (13 bits)
72 MHz max Clock Enable (3 bits)
PLLSRC
PLLMUL ..., x16 x2, x3, x4 PLL
HSI PLLCLK HSE
SW
SYSCLK
/8
72 MHz /1, 2..512 max
AHB Prescaler
APB1 Prescaler /1, 2, 4, 8, 16
36 MHz max
CSS
to TIM2, 3 TIM2,3, 4 and 4 If (APB1 prescaler =1) x1 TIMXCLK else x2 Peripheral Clock
En able (3 bits)
PLLXTPRE OSC_OUT OSC_IN 4-16 MHz HSE OSC /2
APB2 Prescaler /1, 2, 4, 8, 16
72 MHz max Peripheral Clock Enable (11 bits)
PCLK2 to APB2 peripherals
TIM1 timer to TIM1 If (APB2 prescaler =1) x1 TIM1CLK else x2 Peripheral Clock
LSE to RTC
/128 OSC32_IN OSC32_OUT LSE OSC 32.768 kHz ADC Prescaler /2, 4, 6, 8
Enable (1 bit) to ADC
RTCCLK RTCSEL[1:0]
ADCCLK
LSI RC 40 kHz
LSI
to Independent Watchdog (IWDG)
IWDGCLK
Legend:
Main Clock Output
/2
PLLCLK HSI HSE SYSCLK
MCO
HSE = high-speed external clock signal HSI = high-speed internal clock signal LSI = low-speed internal clock signal LSE = low-speed external clock signal
MCO
ai14903
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz. 2. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either 48 MHz or 72 MHz. 3. To have an ADC conversion time of 1 s, APB2 must be at 14 MHz, 28 MHz or 56 MHz.
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Pin descriptions
STM32F103x8, STM32F103xB
3
Figure 3.
1
Pin descriptions
STM32F103xx performance line BGA100 ballout
2 3 4 5 6 7 8 9 10
A
PC14PC13OSC32_IN TAMPER-RTC
PE2
PB9
PB7
PB4
PB3
PA15
PA14
PA13
B
PC15OSC32_OUT
VBAT
PE3
PB8
PB6
PD5
PD2
PC11
PC10
PA12
C
OSC_IN
VSS_5
PE4
PE1
PB5
PD6
PD3
PC12
PA9
PA11
D
OSC_OUT
VDD_5
PE5
PE0
BOOT0
PD7
PD4
PD0
PA8
PA10
E
NRST
PCD
PE6
VSS_4
VSS_3
VSS_2
VSS_1
PD1
PC9
PC7
F
PC0
PC1
PC3
VDD_4
VDD_3
VDD_2
VDD_1
NC
PC8
PC6
G
VSSA
PA0-WKUP
PA4
PC4
PB2
PE10
PE14
PB15
PD11
PD15
H
VREF
PA1
PA5
PC5
PE7
PE11
PE15
PB14
PD10
PD14
J
VREF+
PA2
PA6
PB0
PE8
PE12
PB10
PB13
PD9
PD13
K
VDDA
PA3
PA7
PB1
PE9
PE13
PB11
PB12
PD8
PD12
AI16001b
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STM32F103x8, STM32F103xB Figure 4. STM32F103xx performance line LQFP100 pinout
Pin descriptions
PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP PA1 PA2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14
LQFP100
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VDD_2 VSS_2 NC PA 13 PA 12 PA 11 PA 10 PA 9 PA 8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12
PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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Pin descriptions Figure 5.
STM32F103x8, STM32F103xB STM32F103xx performance line LQFP64 pinout
VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14
VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0 OSC_IN PD1 OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12
PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1
ai14392
Figure 6.
STM32F103xx performance line LQFP48 pinout
VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14
VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0-OSC_IN PD1-OSC_OUT NRST VSSA VDDA PA0-WKUP PA1 PA2
48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 3 34 33 4 32 5 31 6 LQFP48 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24
VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12
PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1
ai14393b
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STM32F103x8, STM32F103xB Figure 7. STM32F103xx Performance Line VFQFPN36 pinout
BOOT0 VSS_3 PA15 PA14 PB7 PB6 PB5 PB4 PB3
Pin descriptions
36 VDD_3 OSC_IN/PD0 OSC_OUT/PD1 NRST VSSA VDDA PA0-WKUP PA1 PA2 1 2 3 4 5 6 7 8 9 10
35
34
33
32
31
30
29
28 27 26 25 24 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 VDD_1
QFN36
23 22 21 20 19 18
11
12
13
14
15
16
17
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
VSS_1
ai14654
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Pin descriptions Table 4. Medium-density STM32F103xx pin definitions
I / O Level(2) Pins VFQFPN36 LQFP100 BGA100 LQFP48 LQFP64 Pin name Type(1)
STM32F103x8, STM32F103xB
Alternate functions Main function(3) (after reset)
Default
Remap
A3 B3 C3 D3 E3 B2 A2 A1 B1 C2 D2 C1 D1 E1 F1 F2 E2 F3 G1 H1 J1 K1
1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 9 10 11 12 13
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
2 3 4 5 6
PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPERRTC(4) PC14-OSC32_IN(4) PC15OSC32_OUT(4) VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA
I/O FT I/O FT I/O FT I/O FT I/O FT S I/O I/O I/O S S I O I/O I/O I/O I/O I/O S S S S
PE2 PE3 PE4 PE5 PE6 VBAT PC13(5) PC14(5) PC15(5) VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA
TRACECK TRACED0 TRACED1 TRACED2 TRACED3
TAMPER-RTC OSC32_IN OSC32_OUT
ADC12_IN10 ADC12_IN11 ADC12_IN12 ADC12_IN13
G2
10
14
23
7
PA0-WKUP
I/O
PA0
WKUP/USART2_ CTS(6)/ ADC12_IN0/ TIM2_CH1_ETR(6) USART2_RTS(6)/ ADC12_IN1/ TIM2_CH2(6) USART2_TX(6)/ ADC12_IN2/ TIM2_CH3(6)
H2
11
15
24
8
PA1
I/O
PA1
J2
12
16
25
9
PA2
I/O
PA2
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STM32F103x8, STM32F103xB Table 4. Medium-density STM32F103xx pin definitions (continued)
I / O Level(2) Pins VFQFPN36 LQFP100 BGA100 LQFP48 LQFP64 Pin name Type(1)
Pin descriptions
Alternate functions Main function(3) (after reset)
Default USART2_RX(6)/ ADC12_IN3/ TIM2_CH4(6)
Remap
K2 E4 F4 G3
13 14
17 18 19 20
26 27 28 29
10 11
PA3 VSS_4 VDD_4 PA4
I/O S S I/O
PA3 VSS_4 VDD_4 PA4
SPI1_NSS(6)/ USART2_CK(6)/ ADC12_IN4 SPI1_SCK(6)/ ADC12_IN5 SPI1_MISO(6)/ ADC12_IN6/ TIM3_CH1(6) SPI1_MOSI(6)/ ADC12_IN7/ TIM3_CH2(6) ADC12_IN14 ADC12_IN15 ADC12_IN8/ TIM3_CH3(6) ADC12_IN9/ TIM3_CH4(6) TIM1_CH2N TIM1_CH3N TIM1_BKIN
H3
15
21
30
12
PA5
I/O
PA5
J3
16
22
31
13
PA6
I/O
PA6
K3 G4 H4 J4 K4 G5 H5 J5 K5 G6 H6 J6 K6 G7 H7 J7 K7 E7
17 18 19 20 21 22 23
23 24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49
14
PA7 PC4 PC5
I/O I/O I/O I/O I/O I /O FT I/O F T I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S
PA7 PC4 PC5 PB0 PB1 PB2/BOOT1 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1
TIM1_CH1N
15 16 17 18
PB0 PB1 PB2 / BOOT1 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1
TIM1_ETR TIM1_CH1N TIM1_CH1 TIM1_CH2N TIM1_CH2 TIM1_CH3N TIM1_CH3 TIM1_CH4 TIM1_BKIN I2C2_SCL/ USART3_TX(6) I2C2_SDA/ USART3_RX(6) TIM2_CH3 TIM2_CH4
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Pin descriptions Table 4.
STM32F103x8, STM32F103xB
Medium-density STM32F103xx pin definitions (continued)
I / O Level(2) Pins VFQFPN36 LQFP100 Alternate functions Main function(3) (after reset) Type(1)
BGA100
LQFP48
LQFP64
Pin name
Default
Remap
F7
24
32
50
19
VDD_1
S
VDD_1 SPI2_NSS/ I2C2_SMBAl/ USART3_CK(6)/ TIM1_BKIN(6) SPI2_SCK/ USART3_CTS(6)TI M1_CH1N (6) SPI2_MISO/ USART3_RTS(6) TIM1_CH2N (6) SPI2_MOSI/ TIM1_CH3N(6) USART3_TX USART3_RX USART3_CK USART3_CTS TIM4_CH1 / USART3_RTS TIM4_CH2 TIM4_CH3 TIM4_CH4 TIM3_CH1 TIM3_CH2 TIM3_CH3 TIM3_CH4 USART1_CK/ TIM1_CH1(6)/MCO USART1_TX(6)/ TIM1_CH2(6) USART1_RX(6)/ TIM1_CH3(6) USART1_CTS/ CANRX(6)/ TIM1_CH4(6) / USBDM
K8
25
33
51
-
PB12
I/O FT
PB12
J8
26
34
52
-
PB13
I/O FT
PB13
H8
27
35
53
-
PB14
I/O FT
PB14
G8 K9 J9 H9 G9 K10 J10 H10 G10 F10 E10 F9 E9 D9 C9
28 -
36 37 38 39
54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69
20 21 22
PB15 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PC6 PC7 PC8 PC9 PA8 PA9 PA10
I /O FT I/O FT I/O FT I/O FT I/O FT I/O F T I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT
PB15 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PC6 PC7 PC8 PC9 PA8 PA9 PA10
29 30
40 41 42 43
D10 31
C10 32
44
70
23
PA11
I/O FT
PA11
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STM32F103x8, STM32F103xB Table 4. Medium-density STM32F103xx pin definitions (continued)
I / O Level(2) Pins VFQFPN36 LQFP100 BGA100 LQFP48 LQFP64 Pin name Type(1)
Pin descriptions
Alternate functions Main function(3) (after reset)
Default
Remap
B10 33
45
71
24
PA12
I/O FT
PA12
USART1_RTS/ CANTX(6) / TIM1_ETR(6) / USBDP PA13
A10 34 F8 E6 F6 A9 A8 B9 B8 C8 D8 E8 B7 C7 D7 B6 C6 D6 A7 A6 C5 B5 A5 D5 B4 39 40 41 42 43 44 45 35 36 37 38 5 6
46 47 48 49 50 51 52 53 5 6 54 55 56 57 58 59 60 61
72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95
25 26 27 28 29
PA13/JTMS/SWDIO
I/O FT
JTMS/SWDIO
Not connected VSS_2 VDD_2 S S VSS_2 VDD_2 JTCK/SWCLK JTDI PC10 PC11 PC12 OSC_IN(7) OSC_OUT(7) PD2 PD3 PD4 PD5 PD6 PD7 JTDO JNTRST PB5 PB6 PB7 BOOT0 PB8 TIM4_CH3(6) I2C1_SCL / CANRX PB3/TRACESWO PB4 I2C1_SMBAl I2C1_SCL(6)/ TIM4_CH1(6) I2C1_SDA(6)/ TIM4_CH2(6) TIM3_ETR USART2_CTS USART2_RTS USART2_TX USART2_RX USART2_CK TIM2_CH2 / SPI1_SCK TIM3_CH1 / SPI1_MISO TIM3_CH2 / SPI1_MOSI USART1_TX USART1_RX PA14 PA15 TIM2_CH1_ETR/ SPI1_NSS USART3_TX USART3_RX USART3_CK CANRX CANTX
PA14/JTCK/SWCLK I/O FT PA15/JTDI PC10 PC11 PC12 I/O FT I /O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O I/O FT I/O FT I I/O FT
2 3 30 31 32 33 34 35 -
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PB3/JTDO PB4/JNTRST PB5 PB6 PB7 BOOT0 PB8
25/84
Pin descriptions Table 4.
STM32F103x8, STM32F103xB
Medium-density STM32F103xx pin definitions (continued)
I / O Level(2) Pins VFQFPN36 LQFP100 Alternate functions Main function(3) (after reset) Type(1)
BGA100
LQFP48
LQFP64
Pin name
Default
Remap
A4 D4 C4 E5 F5
46 47 48
62 63 64
96 97 98 99 100
36 1
PB9 PE0 PE1 VSS_3 VDD_3
I/O FT I/O FT I/O FT S S
PB9 PE0 PE1 VSS_3 VDD_3
TIM4_CH4(6) TIM4_ETR
I2C1_SDA / CANTX
1. I = input, O = output, S = supply, HiZ = high impedance. 2. FT = 5 V tolerant. 3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1 and USART1 & USART2, respectively. Refer to Table 2 on page 8. 4. PC13, PC14 and PC15 are supplied through the power switch and since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 is restricted: only one I/O at a time can be used as an output, the speed has to be limited to 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED). 5. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 6. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 7. The pins number 2 and 3 in the VFQFPN36 package, and 5 and 6 in the LQFP48 and LQFP64 packages are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 package, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode.
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STM32F103x8, STM32F103xB
Memory mapping
4
Memory mapping
The memory map is shown in Figure 8. Figure 8. Memory map
APB memory space
0xFFFF FFFF
r ese rved
0xE010 0000
0xFFFF FFFF
r ese rved
0x6000 0000
r ese rved
0x4002 3400
7
0xE010 0000 0xE000 0000 Co rtex- M3 Internal Peripherals
CRC
0x4002 3000
r ese rved
0x4002 2400
Fl as h Interface
0x4002 2000
r ese rved
0x4002 1400 0x4002 1000
R CC r ese rved
6
0xC000 0000
0x4002 0400
DMA
0x4002 0000
r ese rved
0x4001 3C00 0x4001 3800 0x4001 3400
USART 1 r ese rved SPI1
5
0xA000 0000
0x4001 3000
TIM1
0x4001 2C00
ADC2
0x4001 2800
ADC1
0x4001 2400
4
0x8000 0000
rese rve d
0x1FFF FFFF
0x4001 1C00
rese rved
0x1FFF F80F Option Bytes 0x1FFF F800
Por t E
0x4001 1800
Po r t D
0x4001 1400
Po r t C
0x4001 1000
Po r t B
0x4001 0C00
3
0x1FFF F000 0x6000 0000
System memory
Po r t A
0x4001 0800
EXTI
0x4001 0400
AF IO
0x4001 0000
r ese rved
0x4000 7400
PWR BKP
2
rese rved
0x4000 0000 Peripherals
0x4000 7000 0x4000 6C00
r ese rved
0x4000 6800 0x4000 6400 0x4000 6000
b x CAN
shared 512 byte USB/CAN SRAM
USB Reg i s t ers
1
0x2000 0000 SRAM 0x0801 FFFF
0x4000 5C00
I2C2
0x4000 5800
I2C1
0x4000 5400
r ese rved
0x4000 4C00
USART 3
0x4000 4800
USART 2
0
0x0000 0000 0x0800 0000
0x4000 4400
Flash memory
r ese rved
0x4000 3C00
SPI2
0x4000 3800
Aliased to Flash, system memory or SRAM depending on BOOT pins
r ese rved
0x4000 3400
IWDG
0x4000 3000
0x0000 0000
WWDG
0x4000 2C00
RTC
0x4000 2800
Reserve d
r ese rved
0x4000 0C00
TIM4
0x4000 0800 0x4000 0400 0x4000 0000
TIM3 TIM2
ai14394e
27/84
Electrical characteristics
STM32F103x8, STM32F103xB
5
5.1
Electrical characteristics
Test conditions
Unless otherwise specified, all voltages are referenced to VSS.
5.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3).
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.3 V (for the 2 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2).
5.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
5.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 9.
5.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 10.
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STM32F103x8, STM32F103xB
Electrical characteristics
Figure 9.
Pin loading conditions
Figure 10. Pin input voltage
STM32F103xx pin C = 50 pF
VIN
STM32F103xx pin
ai14141
ai14142
5.1.6
Power supply scheme
Figure 11. Power supply scheme
VBAT
1. 8-3. 6V
Po wer swi tch
Backup circuitry (OSC32K,RTC, Wake-up logic Backup registers)
O UT
Level shifter
GP I/Os
IN
IO Logic Kernel logic (CPU, Digital & Memories)
VDD
VDD 1/2/3/4/5 VSS
Regulator
5 × 100 nF + 1 × 4.7 F
VDD VREF
1/2/3/4/5
VDDA VREF+ VREFVSSA
ai14125d
10 nF + 1 F
10 nF + 1 F
ADC
An alo g: RCs, PLL, ...
Caution:
In Figure 11, the 4.7 F capacitor must be connected to VDD3.
29/84
Electrical characteristics
STM32F103x8, STM32F103xB
5.1.7
Current consumption measurement
Figure 12. Current consumption measurement scheme
IDD_VBAT VBAT
IDD VDD
VDDA
ai14126
5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 5: Voltage characteristics, Table 6: Current characteristics, and Table 7: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 5.
Symbol VDDVSS VIN |VDDx| |VSSX - VSS| VESD(HBM)
Voltage characteristics
Ratings External main supply voltage (including VDDA and VDD)(1) Input voltage on five volt tolerant pin(2) Input voltage on any other pin(2) Variations between different VDD power pins Variations between all the different ground pins Electrostatic discharge voltage (human body model) Min 0.3 VSS -0.3 VSS - 0.3 Max 4.0 +5.5 VDD+0.3 50 mV 50 see Section 5.3.11: Absolute maximum ratings (electrical sensitivity) V Unit
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded (see Table 6: Current characteristics). This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN> VINmax while a negative injection is induced by VIN < VSS.
30/84
STM32F103x8, STM32F103xB Table 6.
Symbol IVDD IVSS IIO
Electrical characteristics
Current characteristics
Ratings Total current into VDD/VDDA power lines (source)(1) Total current out of VSS ground lines (sink)
(1)
Max. 150 150 25 -25 5 5 5 25
Unit
Output current sunk by any I/O and control pin Output current source by any I/Os and control pin Injected current on NRST pin IINJ(PIN) (2)(3) IINJ(PIN)(2) Injected current on HSE OSC_IN and LSE OSC_IN pins Injected current on any other pin
(4)
mA
Total injected current (sum of all I/O and control pins)(4)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. 3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.17: 12-bit ADC characteristics. 4. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with IINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 7.
Thermal characteristics
Ratings Storage temperature range Maximum junction temperature Value 65 to +150 150 Unit C C
Symbol TSTG TJ
5.3
5.3.1
Operating conditions
General operating conditions
Table 8.
Symbol fHCLK fPCLK1 fPCLK2 VDD
General operating conditions
Parameter Internal AHB clock frequency Internal APB1 clock frequency Internal APB2 clock frequency Standard operating voltage Analog operating voltage (ADC not used) Analog operating voltage (ADC used) Backup operating voltage Conditions Min 0 0 0 2 2 Must be the same potential as VDD(2) 2.4 1.8 Max 72 36 72 3.6 3.6 V 3.6 3.6 V V MHz Unit
VDDA(1)
VBAT
31/84
Electrical characteristics Table 8.
Symbol
STM32F103x8, STM32F103xB
General operating conditions (continued)
Parameter Conditions LFBGA100 LQFP100 Power dissipation at TA = 85 C LQFP64 for suffix 6 or TA = 105 C for suffix 7(3) LQFP48 VFQFPN36 Ambient temperature for 6 suffix version Maximum power dissipation Low power dissipation
(4)
Min
Max 487 434 444 363 1110
Unit
PD
mW
40 40 40 40 40 40
85 C 105 105 C 125 105 C 125
TA Ambient temperature for 7 suffix version TJ Junction temperature range 7 suffix version
1. When the ADC is used, refer to Table 44: ADC characteristics. 2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and operation. 3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 75). 4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 75).
Maximum power dissipation Low power dissipation 6 suffix version
(4)
5.3.2
Operating conditions at power-up / power-down
Subject to general operating conditions for TA. Table 9.
Symbol tVDD
Operating conditions at power-up / power-down
Parameter VDD rise time rate VDD fall time rate Conditions Min 0 20 Max Unit s/V
5.3.3
Embedded reset and power control block characteristics
The parameters given in Table 10 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8.
32/84
STM32F103x8, STM32F103xB Table 10.
Symbol
Electrical characteristics
Embedded reset and power control block characteristics
Parameter Conditions PLS[2:0]=000 (rising edge) PLS[2:0]=000 (falling edge) PLS[2:0]=001 (rising edge) PLS[2:0]=001 (falling edge) PLS[2:0]=010 (rising edge) PLS[2:0]=010 (falling edge) PLS[2:0]=011 (rising edge) Min 2.1 2 2.19 2.09 2.28 2.18 2.38 2.28 2.47 2.37 2.57 2.47 2.66 2.56 2.76 2.66 Typ 2.18 2.08 2.28 2.18 2.38 2.28 2.48 2.38 2.58 2.48 2.68 2.58 2.78 2.68 2.88 2.78 100 Falling edge Rising edge 1.8(1) 1.84 1.88 1.92 40 1 2.5 4.5 1.96 2.0 Max 2.26 2.16 2.37 2.27 2.48 2.38 2.58 2.48 2.69 2.59 2.79 2.69 2.9 2.8 3 2.9 Unit V V V V V V V V V V V V V V V V mV V V mV ms
VPVD
Programmable voltage detector level selection
PLS[2:0]=011 (falling edge) PLS[2:0]=100 (rising edge) PLS[2:0]=100 (falling edge) PLS[2:0]=101 (rising edge) PLS[2:0]=101 (falling edge) PLS[2:0]=110 (rising edge) PLS[2:0]=110 (falling edge) PLS[2:0]=111 (rising edge) PLS[2:0]=111 (falling edge)
VPVDhyst
(2)
PVD hysteresis Power on/power down reset threshold PDR hysteresis
VPOR/PDR VPDRhyst
(2)
TRSTTEMPO(2) Reset temporization
2. Guaranteed by design, not tested in production.
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
33/84
Electrical characteristics
STM32F103x8, STM32F103xB
5.3.4
Embedded reference voltage
The parameters given in Table 11 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 11.
Symbol VREFINT
Embedded internal reference voltage
Parameter Internal reference voltage Conditions 40 C < TA < +105 C 40 C < TA < +85 C Min 1.16 1.16 Typ 1.20 1.20 5.1 Max 1.26 1.24 17.1(2) Unit V V s
ADC sampling time when TS_vrefint(1) reading the internal reference voltage
1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production.
5.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 12: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code.
Maximum current consumption
The MCU is placed under the following conditions:
All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except when explicitly mentioned The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above) Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK
The parameters given in Table 12, Table 13 and Table 14 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8.
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STM32F103x8, STM32F103xB Table 12.
Electrical characteristics
Maximum current consumption in Run mode, code with data processing running from Flash
Max(1) Parameter Conditions fHCLK TA = 85 C 72 MHz 48 MHz External clock(2), all peripherals enabled 36 MHz 24 MHz 16 MHz 50 36.1 28.6 19.9 14.7 8.6 32.8 24.4 19.8 13.9 10.7 6.8 TA = 105 C 50.3 36.2 28.7 20.1 14.9 8.9 mA 72 MHz 48 MHz External clock(2), all 36 MHz peripherals disabled 24 MHz 16 MHz 8 MHz 32.9 24.5 19.9 14.2 11 7.1 Unit
Symbol
IDD
Supply current in Run mode
8 MHz
1. Based on characterization, tested in production at VDD max, fHCLK max. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Table 13.
Maximum current consumption in Run mode, code with data processing running from RAM
Max(1) Parameter Conditions fHCLK 72 MHz 48 MHz External clock(2), all peripherals enabled 36 MHz 24 MHz 16 MHz Unit TA = 85 C 48 31.5 24 17.5 12.5 7.5 29 20.5 16 11.5 8.5 5.5 TA = 105 C 50 32 25.5 18 13 8 29.5 21 16.5 12 9 6 mA
Symbol
IDD
Supply current in Run mode
8 MHz 72 MHz 48 MHz External clock(2), all 36 MHz peripherals disabled 24 MHz 16 MHz 8 MHz
1. Based on characterization, tested in production at VDD max, fHCLK max. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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Electrical characteristics
STM32F103x8, STM32F103xB
Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled
45 40 35 Cons umption (mA) 30 25 20 15 10 5 0 - 40 0 25 70 85 105 T emperature (C) 72 MHz 36 MHz 16 MHz 8 MHz
Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled
30
25
Cons umption (mA)
20 72 MHz 36 MHz 16 MHz 8 MHz
15
10
5
0 -40 0 25 70 85 105 T emperature (C)
36/84
STM32F103x8, STM32F103xB Table 14.
Electrical characteristics
Maximum current consumption in Sleep mode, code running from Flash or RAM
Max(1) Parameter Conditions fHCLK 72 MHz 48 MHz External clock(2), all peripherals enabled 36 MHz 24 MHz 16 MHz Unit TA = 85 C 30 20 15.5 11.5 8.5 5.5 7.5 6 5 4.5 4 3 TA = 105 C 32 20.5 16 12 9 6 8 6.5 5.5 5 4.5 4 mA
Symbol
IDD
Supply current in Sleep mode
8 MHz 72 MHz 48 MHz External clock(2), all peripherals disabled 36 MHz 24 MHz 16 MHz 8 MHz
1. Data based on characterization results, tested in production at VDD max, fHCLK max. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
37/84
Electrical characteristics Table 15.
Symbol
STM32F103x8, STM32F103xB
Typical and maximum current consumptions in Stop and Standby modes
Typ(1) Parameter Conditions Max TA = Unit VDD/VBAT VDD/VBAT TA = = 2.4 V = 3.3 V 85 C 105 C
IDD
Regulator in Run mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no Supply current in independent watchdog) Stop mode Regulator in Low Power mode, lowspeed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) Low-speed internal RC oscillator and independent watchdog ON Low-speed internal RC oscillator ON, Supply current in independent watchdog OFF Standby mode Low-speed internal RC oscillator and independent watchdog OFF, low-speed oscillator and RTC OFF
23.5
24
200
370
13.5
14
180
340
2.6 2.4
3.4 3.2
-
-
A
1.7
2
4 1.9(2)
5
IDD_VBAT
Backup domain supply current
Low-speed oscillator and RTC ON
1.1
1.4
2.2
1. Typical values are measured at TA = 25 C. 2. Based on characterization, not tested in production.
Figure 15. Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V
300 250 Con su mp tio n (A) 200 150 100 50 0 -4 5 25 70 Te mperature (C) 90 110 3.3 V 3.6 V
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STM32F103x8, STM32F103xB
Electrical characteristics
Figure 16. Current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V
300 250 Cons umpt ion (A) 200 150 100 50 0 -40 0 25 70 85 105 Temperat ure (C) 3. 3 V 3. 6 V
Figure 17. Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V
4.5 4 3.5 Con su mp tio n (A) 3 2.5 2 1.5 1 0.5 0 4 5 C 25 C 85 C 1 05 C Tempe ra tu re (C) 3.3 V 3.6 V
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Electrical characteristics
STM32F103x8, STM32F103xB
Typical current consumption
The MCU is placed under the following conditions:
All I/O pins are in input mode with a static value at VDD or VSS (no load). All peripherals are disabled except if it is explicitly mentioned. The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above). Ambient temperature and VDD supply voltage conditions summarized in Table 8. Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK = fPCLK2/4 Typical current consumption in Run mode, code with data processing running from Flash
Typ(1) Parameter Conditions fHCLK Unit
Table 16.
Symbol
All peripherals All peripherals disabled enabled(2) 36 24.2 19 12.9 9.3 5.5 3.3 2.2 1.6 1.3 1.08 31.4 23.5 18.3 12.2 8.5 4.9 2.7 1.6 1.02 0.73 0.5 27 18.6 14.8 10.1 7.4 4.6 2.8 1.9 1.45 1.25 1.06 23.9 17.9 14.1 9.5 6.8 4 2.2 1.4 0.9 0.67 0.48
72 MHz 48 MHz 36 MHz 24 MHz 16 MHz External clock
(3)
8 MHz 4 MHz 2 MHz 1 MHz 500 kHz
mA
IDD
Supply current in Run mode
125 kHz 64 MHz 48 MHz 36 MHz Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency 24 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 125 kHz
mA
1. Typical values are measures at TA = 25 C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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STM32F103x8, STM32F103xB Table 17.
Electrical characteristics
Typical current consumption in Sleep mode, code with data processing code running from Flash or RAM
Typ(1) Conditions fHCLK Unit
Symbol Parameter
All peripherals All peripherals enabled(2) disabled 14.4 9.9 7.6 5.3 3.8 2.1 1.6 1.3 1.11 1.04 0.98 12.3 9.3 7 4.8 3.2 1.6 1 0.72 0.56 0.49 0.43 5.5 3.9 3.1 2.3 1.8 1.2 1.1 1 0.98 0.96 0.95
72 MHz 48 MHz 36 MHz 24 MHz 16 MHz External clock
(3)
8 MHz 4 MHz 2 MHz 1 MHz 500 kHz
IDD
Supply current in Sleep mode
125 kHz 64 MHz 48 MHz 36 MHz 24 MHz Running on high 16 MHz speed internal RC (HSI), AHB prescaler 8 MHz used to reduce the 4 MHz frequency 2 MHz 1 MHz 500 kHz 125 kHz
mA 4.4 3.3 2.5 1.8 1.2 0.6 0.5 0.47 0.44 0.42 0.41
1. Typical values are measures at TA = 25 C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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Electrical characteristics
STM32F103x8, STM32F103xB
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 18. The MCU is placed under the following conditions:
all I/O pins are in input mode with a static value at VDD or VSS (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption with all peripherals clocked off with only one peripheral clocked on
ambient operating temperature and VDD supply voltage conditions summarized in Table 5 Peripheral current consumption(1) Peripheral
TIM2 TIM3 TIM4 SPI2 USART2
Table 18.
Typical consumption at 25 C
1.2 1.2 0.9 0.2 0.35
Unit
APB1 USART3 I2C1 I2C2 USB CAN GPIO A GPIO B GPIO C GPIO D GPIO E APB2 ADC1(2) ADC2 TIM1 SPI1 USART1 0.35 0.39 0.39 0.65 0.72 0.47 0.47 0.47 0.47 0.47
mA
mA 1.81 1.78 1.6 0.43 0.85
1. fHCLK = 72 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral. 2. Specific conditions for ADC: fHCLK = 56 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/4, ADON bit in the ADC_CR2 register is set to 1.
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STM32F103x8, STM32F103xB
Electrical characteristics
5.3.6
External clock source characteristics
High-speed external user clock generated from an external source
The characteristics given in Table 19 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 8. Table 19.
Symbol fHSE_ext VHSEH VHSEL tw(HSE) tw(HSE) tr(HSE) tf(HSE) IL
High-speed external user clock characteristics
Parameter User external clock source frequency(1) OSC_IN input pin high level voltage OSC_IN input pin low level voltage OSC_IN high or low time(1) OSC_IN rise or fall time(1) OSC_IN Input leakage current VSS VIN VDD Conditions Min 0 0.7VDD VSS 16 ns 5 1 A Typ 8 Max 25 VDD 0.3VDD Unit MHz
V
1. Guaranteed by design, not tested in production.
Low-speed external user clock generated from an external source
The characteristics given in Table 20 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 8. Table 20.
Symbol fLSE_ext VLSEH VLSEL tw(LSE) tw(LSE) tr(LSE) tf(LSE) IL
Low-speed external user clock characteristics
Parameter User External clock source frequency(1) OSC32_IN input pin high level voltage OSC32_IN input pin low level voltage OSC32_IN high or low time(1) OSC32_IN rise or fall time(1) VSS VIN VDD 0.7VDD VSS 450 ns 5 1 A Conditions Min Typ 32.768 Max 1000 VDD V 0.3VDD Unit kHz
OSC32_IN Input leakage current
1. Guaranteed by design, not tested in production.
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Electrical characteristics
STM32F103x8, STM32F103xB
Figure 18. High-speed external clock source AC timing diagram
VHSEH 90% VHSEL 10% tr(HSE) THSE tf(HSE) tW(HSE) tW(HSE) t
EXTER NAL CLO CK SO URC E
fHSE_ext OSC _I N
IL STM32F103xx ai14143
Figure 19. Low-speed external clock source AC timing diagram
VLSEH 90% VLSEL 10% tr(LSE) TLSE tf(LSE) tW(LSE) tW(LSE) t
EXTER NAL CLO CK SO URC E
fLSE_ext
OSC32_I N
IL STM32F103xx ai14144b
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 21. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
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STM32F103x8, STM32F103xB Table 21.
Symbol fOSC_IN RF CL1 CL2(3) i2 gm tSU(HSE
(5)
Electrical characteristics
HSE 4-16 MHz oscillator characteristics(1) (2)
Parameter Oscillator frequency Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(4) HSE driving current Oscillator transconductance star tup time RS = 30 VDD = 3.3 V, VIN = VSS with 30 pF load Star tup VDD is stabilized 25 2 Conditions Mi n 4 Typ 8 200 30 Max 16 Unit MHz k pF
1
mA mA/V ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization, not tested in production. 3. For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. 4. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 5. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer
Figure 20. Typical application with an 8 MHz crystal
Resonator with integrated capacitors CL1
OSC_IN 8 MH z resonator REXT(1) OSC_OU T RF Bias controlled gain STM32F103xx fHS E
CL2
ai14145
1. REXT value depends on the crystal characteristics. Typical value is in the range of 5 to 6RS.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 22. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
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Electrical characteristics Note:
STM32F103x8, STM32F103xB
For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF, then CL1 = CL2 = 8 pF. Table 22.
Symbol RF CL1 CL2(2) I2 gm tSU(LSE)(4)
Caution:
LSE oscillator characteristics (fLSE = 32.768 kHz) (1)
Parameter Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) LSE driving current Oscillator Transconductance star tup time VDD is stabilized RS = 30 k VDD = 3.3 V, VIN = VSS 5 3 Conditions Min Typ 5 15 1.4 Max Unit M pF A A/V s
1. Based on characterization, not tested in production. 2. Refer to the note and caution paragraphs above the table. 3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details 4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer
Figure 21. Typical application with a 32.768 kHz crystal
Resonator with integrated capacitors CL1
OSC32_IN 32.768 kH z resonator CL2 RF OSC32_OU T Bias controlled gain STM32F103xx fLSE
ai14146
5.3.7
Internal clock source characteristics
The parameters given in Table 23 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8.
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STM32F103x8, STM32F103xB
Electrical characteristics
High-speed internal (HSI) RC oscillator
Table 23.
Symbol fHSI
HSI oscillator characteristics(1) (2)
Parameter Frequency TA = 40 to 105 C Conditions Min Typ 8 1 1 1 1 1 80 3 2.5 2.2 2 2 100 Ma x Unit MHz % % % % s A
ACCHSI Accuracy of HSI oscillator
TA = 10 to 85 C TA = 0 to 70 C TA = 25 C
tsu(HSI) IDD(HSI)
HSI oscillator start up time HSI oscillator power consumption
1. Guaranteed by design, not tested in production. 2. VDD = 3.3 V, TA = 40 to 105 C unless otherwise specified.
Low-speed internal (LSI) RC oscillator
Table 24.
Symbol fLSI(2) tsu(LSI)
(3)
LSI oscillator characteristics (1)
Parameter Frequency LSI oscillator startup time LSI oscillator power consumption 0.65 Min 30 Typ 40 Max 60 85 1.2 Unit kHz s A
IDD(LSI)(3)
1. VDD = 3 V, TA = 40 to 105 C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production.
Wakeup time from low-power mode
The wakeup times given in Table 25 is measured on a wakeup phase with a 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode:
Stop or Standby mode: the clock source is the RC oscillator Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8.
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Electrical characteristics Table 25.
Symbol
STM32F103x8, STM32F103xB
Low-power mode wakeup timings
Parameter Conditions Wakeup on HSI RC clock HSI RC wakeup time = 2 s HSI RC wakeup time = 2 s, Regulator wakeup from LP mode time = 5 s HSI RC wakeup time = 2 s, Regulator wakeup from power down time = 38 s Typ 1.8 3.6 s Wakeup from Stop mode (regulator in low power mode) 5.4 50 s Unit s
tWUSLEEP(1) Wakeup from Sleep mode Wakeup from Stop mode (regulator in run mode)
tWUSTOP(1)
tWUSTDBY(1) Wakeup from Standby mode
1. The wakeup times are measured from the wakeup event to the point in which the user application code reads the first instruction.
5.3.8
PLL characteristics
The parameters given in Table 26 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 26.
Symbol
PLL characteristics
Value Parameter PLL input clock(2) Test conditions Min(1) 1 40 16 Typ 8.0 Max(1) 25 60 72 200 Unit MHz % MHz s
fPLL_IN fPLL_OUT tLOCK
PLL input clock duty cycle PLL multiplier output clock PLL lock time
1. Based on characterization, not tested in production. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT.
5.3.9
Memory characteristics
Flash memory
The characteristics are given at TA = 40 to 105 C unless otherwise specified. Table 27.
Symbol tprog t ERASE tME
Flash memory characteristics
Parameter Conditions Min(1) 40 20 20 Typ 52.5 Max(1) 70 40 40 Unit s ms ms
16-bit programming time TA = 40 to +105 C Page (1 KB) erase time Mass erase time TA = 40 to +105 C TA = 40 to +105 C
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STM32F103x8, STM32F103xB Table 27.
Symbol
Electrical characteristics
Flash memory characteristics (continued)
Parameter Conditions Read mode fHCLK = 72 MHz with 2 wait states, VDD = 3.3 V Min(1) Typ Max(1) 20 Unit mA
IDD
Supply current
Write / Erase modes fHCLK = 72 MHz, VDD = 3.3 V Power-down mode / Halt, VDD = 3.0 to 3.6 V
5 50 2 3.6
mA A V
Vprog
Programming voltage
1. Guaranteed by design, not tested in production.
Table 28.
Symbol
Flash memory endurance and data retention
Value Parameter Conditions TA = 40 to +85 C (6 suffix versions) TA = 40 to +105 C (7 suffix versions) 1 kcycle(2) at TA = 85 C 1 kcycle(2) at TA = 105 C 10 kcycles
(2)
Min(1) 10 30 10 20
Unit Typ Max kcycles
N END
Endurance
tRET
Data retention
Years
at TA = 55 C
1. Based on characterization, not tested in production. 2. Cycling performed over the whole temperature range.
5.3.10
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 1000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in Table 29. They are based on the EMS levels and classes defined in application note AN1709.
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Electrical characteristics Table 29.
Symbol
STM32F103x8, STM32F103xB
EMS characteristics
Parameter Conditions Level/ Class 2B
VFESD
VDD = 3.3 V, TA = +25 C, Voltage limits to be applied on any I/O pin to fHCLK = 72 MHz induce a functional disturbance conforms to IEC 1000-4-2 Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, TA = +25 C, fHCLK = 72 MHz conforms to IEC 1000-4-4
VEFTB
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as:
Corrupted program counter Unexpected reset Critical Data corruption (control registers...)
Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with SAE J 1752/3 standard which specifies the test board and the pin loading. Table 30.
Symbol
EMI characteristics
Parameter Conditions Monitored frequency band 0.1 to 30 MHz 30 to 130 MHz 130 MHz to 1GHz SAE EMI Level Max vs. [fHSE/fHCLK] Unit 8/48 MHz 8/72 MHz 12 22 23 4 12 19 29 4 dBV
SEMI
Peak level
VDD = 3.3 V, TA = 25 C, LQFP100 package compliant with SAE J 1752/3
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STM32F103x8, STM32F103xB
Electrical characteristics
5.3.11
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) su |
