STA5620
Fully integrated RF front-end receiver for GPS applications
Features
Low IF architecture (fIF = 4fO) Minimum external components VGA gain internally regulated On chip programmable PLL Typ. 2.7 V supply voltage SPI interface 2 kV HBM ESD protected Compatible with GPS L1 Standard QFN-32 package Low power for portable designs The magnitude data is internally integrated in order to control the variable gain amplifiers in accordance to the RF input signal strength. An excellent quality of reception in critical environments is ensured by the good noise figure and linearity of the receiver. The on-chip oscillator supports crystal frequencies in the range of 10MHz to 40MHz. It is able to support TCXO providing also a buffered copy of the oscillator frequency. The chip, using STMicroelectronics BiCMOS SiGe technology, is housed in a QFN-32 package. VFQFPN32
Description
The chip is a fully integrated RF front-end able to down-convert the GPS L1 signal from 1575.42 MHz to 4.092 MHz. The IF signal is converted by a two bit ADC. Sign (SIGN), Magnitude (MAG) and the 16.368 MHz sampling clock (GPS_CLK) are provided to the baseband. Table 1. Device summary
Marking STA5620
Order code STA5620TR
Package VFQFPN32
Packing Tape & reel
February 2008
Rev 4
1/29
www.st.com 1
Contents
STA5620
Contents
1 2 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 RFA and MIXER section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 IF section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Variable gain amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PLL synthesizer and VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Output buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power control modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 4.2 4.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5
Pin and I/O cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 5.2 5.3 5.4 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 RF_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 CHIP_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TEST_EN1, TEST_EN2 and TEST_CLK . . . . . . . . . . . . . . . . . . . . . . . . . 15
6
SPI bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 6.2 6.3 6.4 SPI_CS/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI_DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI_DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7
2/29
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
STA5620
Contents
7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PLL N divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PLL R divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Radio configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Debug register (sub-circuit enables) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Radio trimming register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Receiver chain register (enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8
Chip enable and reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.1 8.2 Principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.1.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9 10 11
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/29
List of tables
STA5620
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pins list description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PLL N divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PLL R divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Radio configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Debug register (sub-circuit enables) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Radio trimming register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Receiver chain register (enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4/29
STA5620
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pins connection diagram (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SPI byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Chip enable and reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 VFQFPN32 (5x5x1.0 mm) mechanical data and package dimensions . . . . . . . . . . . . . . . 25 Reel, leader and trailer dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Carrier tape requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5/29
Block diagram
STA5620
1
Block diagram
Figure 1. Block diagram
RF chain IR Mixer IF filter SIGN RF_IN RFA Combiner Polyphase Filter Buffer 0 90 mag mag GCE & RFE CP PFD CMOS Drivers AGC ADC 2 bits MAG AGC_CTRL IF_TEST IFB
GPS_CLK /N TEST_EN1 TEST_EN2 TEST_CLK SPI_CS/ SPI_CLK SPI_DI SPI_DO MODE RF_EN Test Logic / 48 /2 /R GCE
LO96
MST
Xtal
SPI Interface
reset xtal_clk Reset Generator xtal_clk Xtal Osc XCE
XTAL_CLK
CHIP_EN
XO
XI
AC00324
6/29
STA5620
Pins description
2
Pins description
Table 2.
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Pins list description
Symbol VCC AGC_CTRL VCC RF_IN VCC GND GND VCC VCC VCC VCC XTAL_IN XTAL_OUT TEST_EN1 CHIP_EN RF_EN MODE XTAL_CLK GPS_CLK TEST_CLK TEST_EN2 SPI_DI SPI_CLK SPI_CS/ SPI_DO MAG SIGN GND_IO VCC_IO VCC VCC IF_TEST Description IF section power supply Automatic Gain Control Pin Mixer power supply RF section input RF amplifier power supply Negative Supply Pin Negative Supply Pin Charge pump power supply Digital section power supply VCO power supply Cr ystal oscillator power supply Input Side of Crystal Oscillator or TCXO Input Output Side of Crystal Oscillator Test enable 1. Only for ST internal use Chip Enable RF/IF Receiver Chain Enable Power-On Default Configuration Selector Cr ystal Oscillator Buffered Output GPS Reference Clock Test Clock. Only for ST internal use Type Supply pin Analog input Supply pin Analog RF input Supply pin Gnd Gnd Supply pin Supply pin Supply pin Supply pin Analog input Analog output Digital input Digital input Digital input Digital input Digital output Digital output Digital output Digital input Digital input Digital input Digital input Digital output Digital output Digital output Gnd Supply pin Supply pin Supply pin Analog output
Test enable 2. Only for ST internal use
Serial Parallel Interface Data Input Serial Parallel Interface Clock Serial Parallel Interface Chip Select (Active Low) Serial Parallel Interface Data Output Magnitude Data Sign Data Output Drivers Ground I/Os power supply SPI power supply A/D converter power supply RF/IF Receiver Chain Test Output
7/29
Pins description Figure 2. Pins connection diagram (bottom view)
XTAL_OUT TEST_EN1 XTAL_IN CHIP_EN RF_EN
STA5620
V CC
V CC
9 VCC GND GND VCC RF_IN VCC AGC_CTRL VCC 8 7 6 5 4 3 2 1 32
IF_TEST
10
11
V CC
12
13
14
15
16 17 18 19 20 21 22 23 24 MODE XTAL_CLK GPS_CLK TEST_CLK TEST_EN2 SPI_DI SPI_CLK SPI_CS
31
VCC
30
VCC
29
VCC_IO
28
GND_IO
27
SIGN
26
MAG
25
SPI_DO
AC00325
8/29
STA5620
Functional description
3
3.1
Functional description
RFA and MIXER section
The 1575.42 MHz RF signal at the output of the external SAW filter is amplified by a RF amplifier (RFA) and then down converted by an image rejection mixer. The good performances of the cascade configuration and the technology choice guarantee a noise figure better than 4.5 dB in typical conditions. In fact, the RFA gain is high enough to minimize the effects on the noise figure of the following integrated stages. The linearity of the RFA and Mixer section ensures immunity to RF blockers close to the GPS signal. Then it allows the use of low quality external pre-selection filters. Two ninety degrees out of phase signals are derived from the VCO and send to the input of the image rejection mixer. A minimum image rejection ratio of 20 dB is guaranteed. The chosen IF frequency is 4fo = 4.092 MHz.
3.2
IF section
The output of the mixer combiner is processed through an integrated filter able to select the GPS L1 bands. The IF filter cuts any out-of-band signal including the mixer products. In addition it acts as an anti-aliasing filter for the A/D converter. An attenuation of 20 dB is guaranteed at 12fo = 12.276 MHz. The IF filter characteristic is calibrated by an internal loop which compensates process, temperature and voltage variations. In order to let the baseband reconstruct the received information, the IF filter must not introduce an excessive phase shift within the signal bandwidth.
3.3
Variable gain amplifiers
A cascade of variable gain amplifiers and the relevant control circuit balance the system gain in relationship to the RF input signal strength. In that way the signal level at the input of the A/D converter is suitably compensated. The device is able to self-adjust the AGC gain by integrating the MAG output by a dedicated circuit in order to obtain 33 % of MAG bit duty cycle. The loop is compensated by an external capacitor connected to the AGC_CTRL pin. The relevant voltage is used to control the variable gain amplifiers. The internal loop can be by-passed by setting a voltage to the AGC_CTRL input pin. A dynamic range of around 55 dB is typically achieved.
3.4
A/D converter
The task of the A/D converter is to determine the sign and the magnitude of the received signal. The A/D converter sampling frequency is 16fo = 16.368 MHz. Those baseband chips with just one bit input will use only the sign bit. In that case the AGC_CTRL pin must be connected to ground through an external capacitor (~ 10 F).
9/29
Functional description
STA5620
3.5
PLL synthesizer and VCO
The PLL synthesizer is fully integrated on-chip, it is made by the voltage controlled oscillator (VCO), prescaler, dividers, phase-frequency detector (PFD), charge pump (CP) and loop filter. Both the reference divider R and the feedback divider N are programmable helping the user to choose the reference clock. The R divider ranges from 1 to 63 while the N divider from 56 to 4095. In order to achieve good phase noise performances, a LC voltage controlled oscillator has been chosen. Quadrature signals are provided by means of a polyphase filter. A programmable loop filter is integrated on-chip to reduce the number of external components. The loop stability is guaranteed for any of the supported crystals and comparison frequencies. The charge pump is programmable and the output current can be selected among the following values: 50 A, 100 A, 150 A and 200 A.
3.6
Crystal oscillator
The reference oscillator circuit is a CMOS inverter able to work with external crystals up to 40 MHz. The crystal must be connected between the xtal input and the xtal output pins. The load capacitances must be chosen in accordance to the values specified by the crystal manufacturer. A limiting resistor can be placed at the output of the inverter in order to contain the power dissipated in the crystal within its specified maximum value. When a TCXO is used the external reference clock must be applied to the XTAL_IN terminal.
3.7
Output buffers
The RF front-end provides a set of four different signals to the baseband chip. The SIGN and the MAG outputs are the sampled bit streams of the down-converted received signal. GPS_CLK, nominally equal to 16.368 MHz, is the clock signal used by the baseband. Its source can be chosen among the crystal oscillator signal and the VCO signal by means of a 96 divider. XTAL_CLK is the buffered copy of either the crystal oscillator or the TCXO signal. In order to let the application find the best compromise between electro-magnetic interferences and the drivers speed, the output stages slew-rate can be programmed by SPI.
3.8
SPI interface
A SPI interface manages the communication between the baseband chip and the RF frontend. Four lines are required to accomplish this task: a data input line (SPI_DI), a data output line (SPI_DO), a clock line (SPI_CLK) and a chip select line (SPI_CS/) active low. Any information can be passed to the RF receiver through the SPI interface depending on the CHIP_EN and RF_EN input pins status.
10/29
STA5620
Functional description
3.9
Power control modes
Three different power control modes can be chosen by means of the CHIP_EN and the RF_EN pins. If the CHIP_EN pin is forced low the device goes to stand-by mode with very low power consumption. On the other hand, if CHIP_EN is set high, two scenarios are possible: 1. 2. IIf RF_EN = 0 the crystal oscillator and only one output buffer are enabled, XTAL_CLK if MODE = 1 or GPS_CLK if MODE = 0; If RF_EN = 1 the whole chip is active and functional. Only if MODE = 0 the XTAL_CLK output is disabled.
A logic reset of the SPI registers is generated by the low to high transitions of the CHIP_EN pin. External pin strapping dominates until some SPI commands reverse the priority and overrides the strapping until next reset.
11/29
Electrical specifications
STA5620
4
4.1
Electrical specifications
Absolute maximum ratings
Table 3.
Symbol VCC TJ TS
Absolute maximum ratings
Parameter All supply voltages Junction operating temperature Storage temperature Min -0.3 -40 -65 Max 3.6 125 150 2 200 750 Unit V C C kV V V
ESDHBM Electro static discharge Human body model ESDMM Electro static discharge Machine model
ESDCDM Electro static discharge - Charged device model
4.2
Thermal data
Table 4.
Symbol Tamb Rth j-amb
Thermal data
Parameter Ambient operating temperature Thermal resistance junction to ambient Value -40 to 85 40 Unit C C/W
4.3
Table 5.
Symbol Supply VCC Vcc_IO ICC ICC_CLK ICC_STB
Electrical characteristics
Electrical characteristics (VCC = 2.7 V, TJ = 25 C unless otherwise noted)
Parameter Test conditions Min Typ Max Unit
Analog, Digital I/O supply Total power consumption Clock only power consumption Stand-by power consumption Internal blocks ON Crystal oscillator ON Internal blocks OFF
2.56 1.7
2.7
3.3 3.3
V V mA mA A
15 1.5 1
19 1.8
RFA MIXER IF FILTER VGA fIN fIF GC RFA Input frequency IF frequency VGA at max gain Conversion gain VGA at min gain 50 1575.42 4.092 105 dB MHz MHz
12/29
STA5620 Table 5.
Symbol GC VGA range
Electrical specifications Electrical characteristics (continued) (VCC = 2.7 V, TJ = 25 C unless otherwise noted)
Parameter Test conditions Set VAGC_CTRL < 0.3 V for maximum gain 0 Min Typ 55 Vcc 36 f = 4.092 MHz VGA at max gain VGA at min gain f = 2 to 6 MHz 4.5 -57 20 6 f = 12.276 MHz ZS = 50 20 2:1 Max Unit dB V dB/V dB dBm dB MHz dB -
VAGC_CTRL AGC Control Voltage Range GSENS NF_RF-IF P_1dB IRR IFF3dB IFFATT VSWRIN VGA sensitivity RF-IF-VGA noise figure RF-IF-VGA 1dB input compression point Mixer image rejection ratio IF filter cut-off frequency IF filter out of band attenuation RFA Input voltage stat. wave ratio
Crystal oscillator Integer-N synthesizer VCO FXTAL tSTART-UP XTAL frequency XTAL oscillator start-up time XTAL_IN pin DC blocked. No crystal mounted. XTAL_OUT load <10 pF. 1 1571.328 56 f = 1571.328 MHz 100 kHz offset 1 kHz offset 50 50 -65 200 300 -80 4095 10 40 10 MHz msec
PXTAL_IN
Reference input signal sensitivity
-20
dBm
RDIV FLO NDIV KV (1) PNVCO
(1)
Reference divider range LO operating frequency VCO divider range VCO gain VCO phase noise PLL phase noise Charge pump current Charge pump current steps
63
MHz MHz/V dBc/Hz dBc/Hz A A
PNPLL ICP(1) ICP(1)
ADC Output signals GPS clock f ADC MAG SIGN fCLOCK CLOCK ADC sampling frequency MAG duty cycle SIGN duty cycle Output clock frequency Output clock duty cycle Internally regulated 16.368 33 50 16.368 50 MHz % % MHz %
13/29
Electrical specifications Table 5.
Symbol
STA5620
Electrical characteristics (continued) (VCC = 2.7 V, TJ = 25 C unless otherwise noted)
Parameter Test conditions Min Typ Max Unit
Input and output buffers VIH VIL CIN VOH VOL tRISE(2) CMOS input high level CMOS input low level CMOS input capacitance CMOS output high level CMOS output low level CMOS output rise time CL=10 pF, from 10 % to 90 % Slew-rate = fast CL=10 pF, from 10 % to 90 % Slew-rate = slow tFALL(2) CMOS output fall time CL=10 pF, from 10 % to 90 % Slew-rate = fast CL=10 pF, from 10 % to 90 % Slew-rate = slow
1. This value is guaranteed by design. 2. Simulation data.
0.8·VCC 0.2·VCC 1 0.9·VCC 0.1·VCC 3
V V pF V V ns
6
ns
3
ns
6
ns
14/29
STA5620
Pin and I/O cells
5
5.1
Pin and I/O cells
Mode
This pin allows a choice of initial configuration of the registers at reset. This pin will always be an input. In application this pin will be connected either LO or HI. When it is low the chip is configured to use 16.368 MHz as reference frequency, otherwise the reference frequency is 19.2 MHz. To use other reference frequencies the MODE bit must be overwritten by SPI.
5.2
RF_EN
This pin provides control over the operating state of the RF and PLL sections. When it is low those blocks are off, when high the status of the blocks depends of CHIP_EN. This pin will always be an input.
5.3
CHIP_EN
This pin provides control over the operating state of the chip. When it is low the entire chip is disabled and only a leakage current is present (< 10 A). On the rising edge it provides the SPI with a reset signal, the SPI default status depends on MODE and RF_EN pins status. When it is high the entire chip is enabled. This pin will always be an input.
5.4
TEST_EN1, TEST_EN2 and TEST_CLK
Those PINs are for ST test only. In the application TEST_EN1 must be set LOW, TEST_EN2 must be set HIGH (VCC_IO) and TEST_CLK must be not connected.
15/29
SPI bus protocol
STA5620
6
SPI bus protocol
The SPI port is used for data exchange between STA5620 and a GPS base band. The SPI port is controlled by four pins SPI_CLK, SPI_DI, SPI_DO and SPI_CS/. These pins are inputs only, except for SPI_DO, the data output. The SPI Bus protocol is based on a 2-phase transfer made of an address cycle and a data cycle. The two functions in the bus interface layer are: Figure 3.
CS/
SPI byte write
SCLK SDI A7 SDO A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
AC00327
Figure 4.
CS/
SPI byte read
SCLK SDI A7 SDO D7 D6 D5 D4 D3 D2 D1 D0
AC00326
A6
A5
A4
A3
A2
A1
A0
6.1
SPI_CS/
This package pin provides the frame and CS/ connection for the serial interface (SPI). This pin will always be an input.
6.2
SPI_CLK
This package pin provides the clock connection for the serial interface (SPI). This pin will always be an input.
6.3
SPI_DI
This package pin provides the data input connection for the serial interface (SPI). This pin will always be an input.
6.4
SPI_DO
This package pin provides the data output connection for the serial interface (SPI). This pin will always be an output.
16/29
STA5620
Registers
7
7.1
Table 6.
Address R/W 0xC0/40 0xC1/41 0xC2/42 0xC3/43
Registers Register map
Register map
Bit 7 6 5 4 3 2 1 0
----------------- NDIV[11:8] -----------------
--------------------------------------------------- NDIV[7:0] ---------------------------------------------------Reser ved ----------------------------------- RDIV[5:0] ---------------------------------GCE XCE LSR MST
0xD0/50 0xD1/51 0xD2/52
ENM Reserved AGC IF
Reserved MIX RFA PLL
IFB VCO
-------------- LFC[2:0] ---------------
----- CPI[1,0] -----
0xE0/60
RFE
-
Reserved
7.2
Table 7.
Register address 0x40
PLL N divider
PLL N divider
Name Bit XXXX nnnn [3:0] NDIV 0x41 nnnn nnnn [7:0] 96 1555 Default value MODE = 0 (decimal) Default value MODE = 1 (decimal) Description
PLL Feedback Divider Division Ratio
7.3
Table 8.
Register address 0x42
PLL R divider
PLL R divider
Name Bit Default value MODE = 0 (decimal) 1 Default value MODE = 1 (decimal) 19 Description Reference Divider Division Ratio
RDIV
XXrr rrrr [5:0]
Note that registers 40, 41 and 42 are delivered on a single 24 bit bus. New register values are delivered synchronously to the bus only after register 42 is written.
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Registers
STA5620
7.4
Table 9.
Register address
Radio configuration register
Radio configuration register
Name Bit Default value MODE = 0 Default value MODE = 1 Description MST = 0 GPS_CLK output equal to Xtal MST XXXX XXX y [0] 0 1 MST = 1 GPS_CLK output equal to LO96 LSR = 0 slow slew rate mode not active LSR XXXX XX y X [1] 1 1 LSR = 1 slow slew rate mode active
0x43 XCE XXXX X y XX [2] 0 1
XCE = 0 XTAL_CLK buffer is OFF XCE = 1 XTAL_CLK buffer is ON GCE = 0 GPS_CLK buffer is OFF GCE XXXX y XXX [3] 1 1 GCE = 1 GPS_CLK buffer is ON Reserved yyyy XXXX [7:4] 0100 0100 Reserved bits
7.5
Table 10.
Register address
Test register
Test register
Name Bit Default value MODE = 0 Default value MODE = 1 Description IFB = 0 The IF Buffer is OFF IFB XXXX XXX y [0] 0 0 IFB = 1 The IF Buffer is ON Reserved X yyyyyy X [6:1] 0 0 00 0 0 00 Reserved bits
0x50
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STA5620
Registers
7.6
Table 11.
Register address
Debug register (sub-circuit enables)
Debug register (sub-circuit enables)
Name Bit Default value MODE = 0 Default value MODE = 1 Description VCO = 0 The VCO block is OFF VCO XXXX XXX y [0] 1 1 VCO = 1 The VCO block is ON PLL = 0 The PLL block is OFF PLL XXXX XX y X [1] 1 1 PLL = 1 The PLL block is ON RFA = 0 The RF Amplifier is OFF RFA XXXX X y XX [2] 1 1 RFA = 1 The RF Amplifier is ON MIX = 0 The Mixer is OFF MIX XXXX y XXX [3] 1 1 MIX = 1 The Mixer is ON
0x51 IF XXX y XXXX [4] 1 1
IF = 0 The IF chain from Polyphase filter to ADC is OFF IF = 1 The IF chain from Polyphase filter to ADC is ON AGC = 0 The Automatic Gain Control is OFF AGC XX y X XXXX [5] 1 1 AGC = 1 The Automatic Gain Control is ON Reserved X y XXXXXX [6] 1 1 Reserved bits ENM = 0 The whole chip is OFF except the Xtal Osc and the GPS_CLK and/or XTAL_CLK buffers ENM = 1 RF chain is On (If RFE bit or RF_EN pin = 1)
ENM
y XXX XXXX [7]
1
1
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Registers
STA5620
7.7
Table 12.
Register address
Radio trimming register
Radio trimming register
Name Bit Default value MODE = 0 Default value MODE = 1 Description CPI = 00 50A charge pump current CPI = 01 100A charge pump current CPI XXXX XX yy [1:0] 11 11 CPI = 10 150A charge pump current CPI = 11 200A charge pump current LFC XXXy yyXX [4:2] 1 10 110 Loop filter control
0x52
7.8
Table 13.
Register address
Receiver chain register (enable)
Receiver chain register (enable)
Name Reser ved Bit XX yyyyyy [5:0] Default value MODE = 0 110011 Default value MODE = 1 110011 Description Reserved bits RFE = 0 The RF chain is controlled by RF_EN pin RFE = 1 The RF chain is ON
0x60 RFE y XXX XXXX [7] 0 0
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STA5620
Chip enable and reset timing
8
Chip enable and reset timing
Figure 5. Chip enable and reset timing
VDD Power
CHIP_EN Mode = 1 MODE Mode = 0
Internal Oscillator reset
Xce (XTAL_CLK enable)
Power -on
MODE Clock Out Pin setting Enable (min 1s)
Internal reset (min. 4ms)
Chip Config setting
AC00328
8.1
Principle of operation
With power supply applied and CHIP_EN inactive the chip is in stand-by mode consuming just a minimal leakage current (<10 A). Applying CHIP_EN High turns-on the chip and starts the Crystal oscillator. Two internal counters driven by the Oscillator output are used to create two timing periods to:
The first time period (Clock Out Enable) is long enough to safely enable XTAL_CLK as early as possible by default during oscillator startup. The second period (Internal reset) generates an internal reset pulse long enough to guarantee open-loop clock stabilization (driven either by internal oscillator or by off-chip TCXO) and be able to load the chip default configuration.
The default initial configurations depend on the state of the MODE input pin. After this phase, the chip configuration may be modified by the baseband unit with a set of SPI commands, allowing a more specific configuration to be set
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Chip enable and reset timing
STA5620
8.1.1
Operating modes
The below table shows how select a particular default operating mode: Table 14. Operating modes
STA5620 current consumption 15 mA HIGH MODE = 1 RF Chain OFF Crystal oscillator ON Stand-by All internal blocks OFF
HIGH = VCC_IO; LOW = GND
Operating modes MODE = 0 Fully operating
CHIP_EN
RF_EN
TEST_EN1 TEST_EN2
HIGH
LOW
HIGH
16 mA 1.5 mA 1 A HIGH LOW LOW x LOW LOW HIGH HIGH
MODE LOW sets the STA5620 internal dividers to work with 16.368 MHz reference and GPS_CLK = ON and XTAL_CLK = OFF; HIGH sets the STA5620 internal dividers to work with 19.2 MHz reference and GPS_CLK = ON and XTAL_CLK = ON; In both cases GPS_CLK pin provides 16.368 MHz clock to Base Band and SIGN pin provides the DATA to Base Band. CHIP_EN LOW the device goes to stand-by mode with very low power consumption. HIGH sets ON the internal blocks of the IC according to the RF_EN status; A logic reset of the SPI registers is generated by the low to high transitions of the CHIP_EN pin while the RF_EN is LOW. RF_E N LOW the crystal oscillator and only one output buffer are enabled, XTAL_CLK if MODE = 1 or GPS_CLK if MODE = 0; HIGH the whole chip is active and functional; TEST_EN1 must be set LOW; TEST_EN2 'must be set HIGH (VCC_IO);
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STA5620
Chip enable and reset timing
8.2
Table 15.
Bit name
Default configuration
This table describes the default configuration of the STA5620 internal registers. Default configuration
Description Values (MODE_EN=0) (MODE_EN=1)
Sample mode configuration MST Sample clock Source Selector Default xtal/TCXO frequency Power enable configuration RF Chain Enable (From the RFA Input to the AGC Output) RF Chain Enable (From the RFA Input to the AGC Output) GPS Clock Enable Automatic Control Gain Enable Xtal Clock Enable IF Output Buffer Enable Voltage Controlled Oscillator Enable IF enable Mixer enable RF Amplifier enable Phase Locked Loop Enable (Dividers, PFD, Charge Pump). 0 = RF chain OFF, 1 = RF chain On If RFE bit or RF_EN pin = 1 0 = controlled by RF_EN pin, 1 = RF chain On 0 = GPS clock Off, 1 = GPS clock On 0 = AGC function Off, 1 = AGC function On 0 = Off, 1 = On 0 = Off, 1 = On 0 = Off, 1 = On 0 = Off, 1 = On 0 = Off, 1 = On 0 = Off, 1 = On 0 = Off, 1 = On 0 = Xtal Osc 1 = VCO/96, 0 16.368 MHz 1 19.200 MHz
ENM
1
1
RFE
0
0
GCE AGC XCE IFB VCO IF MIX RFA
1 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1
PLL
1
1
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Chip enable and reset timing Table 15.
Bit name Divider configuration PLL Feedback Divider Division Ratio (mapped as 2 byte registers) Reference Divider Division Ratio (write of this register updates all of the ndiv, rdiv vector)
STA5620
Default configuration (continued)
Description Values (MODE_EN=0) (MODE_EN=1)
NDIV[11:0]
56 to 4095
96
1555
RDIV[5:0]
1 to 63
1
19
Charge pump current selector 00 = 50 A 01 = 100 A 10 = 150 A 11 = 200 A
CPI[1:0]
Charge Pump Current Selector
11
11
Output slew rate control XTAL_CLK, GPS_CLK, 0 = Fast TEST_CLK, SPI_DO, SIGN and MAG Output Drivers Slew 1 = Slow Rate
LSR
1
1
Note:
Disabling a digital output buffer means driving it low.
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STA5620
Package information
9
Package information
In order to meet environmental requirements, ST (also) offers these devices in ECOPACK packages. ECOPACK packages are lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 6. VFQFPN32 (5x5x1.0 mm) mechanical data and package dimensions
mm D IM . MIN. A A A1 A3 b D D2 E E2 e L ddd 0.300 0.180 4.850 3.500 4.850 3.500 0.800 0.800 TYP. 0.900 0.900 0.020 0.200 0.250 5.000 3.600 5.000 3.600 0.500 0.400 M AX . 1.000 MIN. 0.031 TYP. 0.035 MAX. 0.039 inch
OUTLINE AND MECHANICAL DATA
1.000 0.0315 0.0354 0.0394 0.050 0.0008 0.0020 0.0079 0.300 0.0071 0.0098 0.0118 5.150 0.1909 0.1969 0.2028 3.700 0.1378 0.1417 0.1457 5.150 0.1909 0.1969 0.2028 3.700 0.1378 0.1417 0.1457 0.0197 0.500 0.0118 0.0157 0.0197 0.050 0.0020
VFQFPN32 (5x5x1.0mm) Very Fine Quad Flat Package No lead
7376875 F
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Packing information
STA5620
10
Packing information
Figure 7. Reel, leader and trailer dimensions
Tape sizes 12 mm
A max 330
B min 1.5
C 13 0.2
D min 20.2
N min 60
G 12.4 +2/-0
T max 18.4
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STA5620 Figure 8. Carrier tape requirements
Packing information
Figure 9.
Orientation
27/29
Revision history
STA5620
11
Revision history
Table 16.
Date 24-Jul-2007 15-Nov-2007 14-Jan-2008 18-Feb-2008
Document revision history
Revision 1 2 3 4 Initial release. Modified the tables 7, 8, 10, 12 and 13. Updated Figure 3 and 4. Updated the following tables: 9, 10, 11 and 13. Updated the Figure 3 on page 16. Document status promoted from preliminary data to datasheet. Updated the Section 3.4: A/D converter. Changes
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STA5620
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