VNI4140K
Quad high side smart power solid state relay
Features
Type Vdemag(1) RDSon(1) 0.08 Iout(1) 0.7 A VCC 41 V PowerSSO-24
VNI4140K VCC-41 V
1. Per channel
Description
The VNI4140K is a monolithic device made using STMicroelectronics VIPower technology, intended for driving four independent resistive or inductive loads with one side connected to ground. Active current limitation avoids dropping the system power supply in case of shorted load. Built-in thermal shut-down protects the chip from overtemperature and short circuit. In overload condition, channel turns OFF and back ON automatically so as to maintain junction temperature between TTSD and TR. If this condition makes case temperature reach TCSD, overloaded channel is turned OFF and will restart only when case temperature has decreased down to TCR. In case of more than one channel in overload, re-start of the overloaded channels will not be simultaneous, in order to avoid high peak current from the supply. Non overloaded channels continue to operate normally. The open drain diagnostics outputs indicates over-temperature conditions.
Output current: 0.7 A per channel Shorted load protections Junction over-temperature protection Case overtemperature protection for thermal independence of the channels Thermal case shut-down restart not simultaneous for the various channels Protection against loss of ground Current limitation Undervoltage shut-down Open drain diagnostic outputs 3.3 V CMOS/TTL compatible inputs Fast demagnetization of inductive loads Conforms to IEC 61131-2
Figure 1.
Block diagram
July 2008
Rev 3
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www.st.com 24
Contents
VNI4140K
Contents
1 2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 4 5 6 7 8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.1 VNI4140K thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
9 10 11 12
Reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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VNI4140K
Pin connection
1
Pin connection
Figure 2. Pin connection (top view)
VCC IN1 STAT1 IN2 STAT2 GND STAT3 IN3 STAT4 IN4 NC NC
OUT1 OUT1 OUT1 OUT2 OUT2 OUT2 OUT3 OUT3 OUT3 OUT4 OUT4 OUT4
Table 1.
Pin Tab 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Pin description
Name TAB Vcc IN1 STAT1 IN2 STA2 GND STAT3 IN3 STAT4 IN4 NC NC OUT4 OUT4 OUT4 OUT3 OUT3 Channel 4 power stage output, internally protected Channel 4 power stage output, internally protected Channel 4 power stage output, internally protected Channel 3 power stage output, internally protected Channel 3 power stage output, internally protected Description Exposed tab internally connected to Vcc Supply voltage Channel 1 input 3.3 V CMOS/TTL compatible Channel 1 status in open drain configuration Channel 2 input 3.3 V CMOS/TTL compatible Channel 2 status in open drain configuration Device ground connection Channel 3 status in open drain configuration Channel 3 input 3.3 V CMOS/TTL compatible Channel 4 status in open drain configuration Channel 4 input 3.3 V CMOS/TTL compatible
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Pin connection Table 1.
Pin 18 19 20 21 22 23 24
VNI4140K Pin description (continued)
Name OUT3 OUT2 OUT2 OUT2 OUT1 OUT1 OUT1 Description Channel 3 power stage output, internally protected Channel 2 power stage output, internally protected Channel 2 power stage output, internally protected Channel 2 power stage output, internally protected Channel 1 power stage output, internally protected Channel 1 power stage output, internally protected Channel 1 power stage output, internally protected
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VNI4140K
Maximum ratings
2
Maximum ratings
Table 2.
Symbol VCC -VCC IGND IOUT IR IIN VIN VSTAT ISTAT VESD EAS PTOT TJ TSTG Power supply voltage Reverse supply voltage DC ground reverse current Output current (continuos) Reverse output current (per channel) Input current (per channel) Input voltage Status pin voltage Status pin current Electrostatic discharge (R = 1.5 k; C = 100 pF) Single pulse avalanche energy per channel not simultaneously Power dissipation at Tc = 25 C Junction operating temperature Storage temperature
Absolute maximum rating
Parameter Value 41 -0.3 -250 Internally limited -5 10 +VCC +VCC 10 2000 300 Internally limited Internally limited -55 to 150 Unit V V mA A A mA V V mA V mJ W C C
2.1
Thermal data
Table 3.
Symbol Rth(JC) Rth(JA)
Thermal data
Parameter Thermal resistance junction-case (1) Thermal resistance junction-ambient Max Max Value 2 see Figure 11 Unit C/W C/W
1. Per channel
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Electrical characteristics
VNI4140K
3
Electrical characteristics
(10.5 V < VCC < 36 V; -25 C < TJ < 125 C; unless otherwise specified) Table 4.
Symbol Vcc RDS(on) Vclamp IS Supply current OFF state output voltage OFF state output current Charge pump frequency
Power section
Parameter Supply voltage On state resistance IOUT = 0.5 A at TJ = 25 C IOUT = 0.5 A Is = 20 mA All channel in OFF state ON state with VIN =5 V (TJ = 125 C) VIN = 0 V and IOUT =0 A VIN = VOUT = 0 V Channel in ON state (1) 0 1450 41 45 250 2.4 Test condition Min 10.5 Typ Max 36 0.080 0.140 52 4 Unit V V A mA
VOUT(OFF) IOUT(OFF) FCP
1 5
V A kHz
1. To cover EN55022 class A and class B normative
Table 5.
Symbol td(ON) tr td(OFF) tf
Switching (VCC = 24 V; -25 C < TJ < 125 C, RL = 48 , input rise time < 0.1 s)
Parameter Turn ON delay Rise time Turn OFF Fall time Test condition Min Typ 20 10 30 8 3 4 Ma x Unit S S S S V/S V/S
dV/dt(ON) Turn ON voltage slope dV/dt(off) Turn OFF voltage slope
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VNI4140K
Electrical characteristics
Table 6.
Symbol VIL VIH VI(HYST) IIN
Logical input
Parameter Input low level voltage Input high level voltage Input hysteresis voltage Input current VIN = 15 V VIN = 36 V 2.20 0.15 10 210 Test conditions Min Typ Max 0.8 Unit V V V
Table 7.
Symbol vSTAT VUSD VUSDHYS ILIM IPEAK Hyst ILSTAT TTSD TR THIST TCSD TCR TCHYST Vdemag
Protection and diagnostic
Parameter Status voltage output low Undervoltage protection Undervoltage hysteresis DC short circuit current Maximum DC output Current Traking limits Status leakage current VCC = VSTAT = 36 V Junction shut down temperature Junction reset temperature Junction thermal hysteresis Case shut-down temperature Case reset temperature Case thermal hysteresis Output voltage at turn-OFF IOUT = 0.5 A; LLOAD >= 1 mH 150 135 7 125 110 15 130 135 VCC = 24 V; RLOAD < 10 m Dynamic load Test conditions ISTAT = 1.6 mA 7 0.4 0.7 0.5 1 1.3 0.2 30 170 190 1.7 Min Typ Max 0.6 10.5 Unit V V V A A A C C C C C
7 VCC41
15 VCC45 VCC52
C V
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Electrical characteristics Figure 3. Current and voltage conventions
VNI4140K
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VNI4140K
Truth table
4
Truth table
Table 8. Truth table
INPUTn Normal operation Over temperature Undervoltage Shor ted load (Current limitation) L H L H L H L H OUTPUTn L H L L L L L X STATUSn H H H L X X H H
5
Typical application circuit
Figure 4. Typical application circuit
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Typical application circuit Figure 5. Thermal behavior
VNI4140K
Vi n(i ) = H
OUT i ) On (
ST T i) Off (H) A(
1)
NO T(i) > T sd j t YES
OUT i ) Off (
ST T i) On (L) A(
YES
4)
T > T sd cc
NO
YES T >T r cc
NO
2)
NO T(i) > Tr j j YES
3)
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VNI4140K
Switching waveforms
6
Switching waveforms
Figure 6. Switching waveforms
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Pin functions
VNI4140K
7
Pin functions
Figure 7. Input circuit
Figure 8.
Status circuits
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VNI4140K Figure 9. Charge pump switching frequency (typical) vs temperature
Freq_CP 200 0
Pin functions
180 0 CP_frequency (KHz)
160 0 F r eq _CP
140 0 120 0
100 0
80 0 - 50 0 50 10 0 15 0 2 00 temperature("C)
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Package and PC board thermal data
VNI4140K
8
8.1
Package and PC board thermal data
VNI4140K thermal data
Figure 10. VNI4140K PC board
Note:
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area = 77 mm x 86 mm, PCB thickness=1.6 mm, Cu thickness = 70 mm (front and back side), Copper areas: from minimum pad lay-out to 8 cm2). Figure 11. RthJA vs PCB copper area in open box free air condition (one channel ON)
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VNI4140K
Package and PC board thermal data Figure 12. VNI4140K thermal impedance junction ambient single pulse (one channel on)
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Reverse polarity protection
VNI4140K
9
Reverse polarity protection
A schematic solution to protect the IC against a reverse polarity condition is proposed. This schematic is effective with any type of load connected to the outputs of the IC. The RGND resistor value can be selected according to the following conditions to be met: 1. 2. RGND 600 mV / (IS in ON state max). RGND (-VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. The power dissipation associated to RGNG during reverse polarity condition is: PD = (-VCC)2/RGND This resistor can be shared by several different ICs. In such case IS value on formula (1) is the sum of the maximum ON-state currents of the different devices. Please note that if the microprocessor ground and the device ground are separated then the voltage drop across the RGND (given by IS in ON state max * RGND) produce a difference between the generated input level and the IC input signal level. This voltage drop will vary depending on how many devices are ON in the case of several high side switches sharing the same RGND. Figure 13. Reverse polarity protection
+ Vcc Status Statusi Inputi GND Outputi
RGND (Optional)
Load
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VNI4140K
Package mechanical data
10
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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Package mechanical data Table 9. PowerSSO-24TM mechanical data
mm Symbol Min A A2 a1 b c D E e e3 G G1 H h L N X Y 4.1 6.5 0.55 10.1 2.15 2.15 0 0.33 0.23 10.10 7.4 0.8 8.8 Typ
VNI4140K
Max 2.47 2.40 0.075 0.51 0.32 10.50 7.6
0.1 0.06 10.5 0.4 0.85 10deg 4.7 7.1
Figure 14. PowerSSO-24TM package dimensions
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VNI4140K Figure 15. PowerSSO-24TM tube shipment (no suffix)
Package mechanical data
Table 10.
PowerSSO-24TM tube shipment
49 1225 532 3.5 13.8 0.6
Base quantity Bulk quantity Tube length ( 0.5) A B C ( 0.1)
Note:
All dimensions are in mm.
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Package mechanical data Figure 16. PowerSSO-24TM reel shipment (suffix "TR")
VNI4140K
Table 11.
PowerSSO-24TM reel dimensions
1000 1000 330 1.5 13 20.2 24.4 100 30.4
Base quantity Bulk quantity A (max) B (min) C ( 0.2) F G (2 0) N (min) T (max)
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VNI4140K Figure 17. PowerSSO-24TM tape dimensions
Package mechanical data
Table 12.
PowerSSO-24TM tape dimensions
Tape width W P0 ( 0.1) P D ( 0.05) D1 (min) F ( 0.1) K (max) P1 ( 0.1) 24 4 12 1.55 1.5 11.5 2.85 2
Tape hole spacing Component spacing Hole diameter Hole diameter Hole position Compartment depth Hole spacing
Note:
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986
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Order codes
VNI4140K
11
Order codes
Table 13. Order codes
Order codes VNI4140K VNI4140KTR Package PowerSSO-24 PowerSSO-24 Packaging Tube Tape and reel
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VNI4140K
Revision history
12
Revision history
Table 14.
Date 16-Nov-2007 26-Nov-2007 08-Jul-2008
Document revision history
Revision 1 2 3 Initial release Updated electrical parameters values Inser ted: Figure 4 on page 9 and Section 9: Reverse polarity protection on page 16 Changes
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VNI4140K
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