STM32F101xC STM32F101xD STM32F101xE
High-density access line, ARM-based 32-bit MCU with 256 to 512 KB Flash, 9 timers, 1 ADC and 10 communication interfaces
Features
Core: ARM 32-bit CortexTM-M3 CPU 36 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access Single-cycle multiplication and hardware division Memories 256 to 512 Kbytes of Flash memory up to 48 Kbytes of SRAM Flexible static memory controller with 4 Chip Select. Supports Compact Flash, SRAM, PSRAM, NOR and NAND memories LCD parallel interface, 8080/6800 modes Clock, reset and supply management 2.0 to 3.6 V application supply and I/Os POR, PDR, and programmable voltage detector (PVD) 4-to-16 MHz crystal oscillator Internal 8 MHz factory-trimmed RC Internal 40 kHz RC with calibration capability 32 kHz oscillator for RTC with calibration Low power Sleep, Stop and Standby modes VBAT supply for RTC and backup registers 1 x 12-bit, 1 s A/D converters (up to 16 channels) Conversion range: 0 to 3.6 V Temperature sensor 2-channel, 12-bit D/A converter DMA 12-channel DMA controller Peripherals supported: timers, ADC, DAC, SPIs, I2Cs and USARTs Up to 112 fast I/O ports
LQFP100 14 x 14 mm
LQFP144 20 x 20 mm
LQFP64 10 x 10 mm
51/80/112 I/Os, all mappable on 16 external interrupt vectors, all 5 V-tolerant except for analog inputs
Debug mode Serial wire debug (SWD) & JTAG interfaces Cor tex-M3 Embedded Trace MacrocellTM Up to 9 timers Up to four 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter 2 x watchdog timers (Independent and Window) SysTick timer: a 24-bit downcounter 2 × 16-bit basic timers to drive the DAC Up to 10 communication interfaces Up to 2 x I2C interfaces (SMBus/PMBus) Up to 5 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) Up to 3 SPIs (18 Mbit/s) CRC calculation unit, 96-bit unique ID ECOPACK packages Device summary
Part number STM32F101RC STM32F101VC STM32F101ZC STM32F101RD STM32F101VD STM32F101ZD STM32F101RE STM32F101ZE STM32F101VE
Table 1.
Reference STM32F101xC STM32F101xD STM32F101xE
July 2008
Rev 3
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www.st.com 1
Contents
STM32F101xC, STM32F101xD, STM32F101xE
Contents
1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 4 5
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1 Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.2 5.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 5.3.10 5.3.11 5.3.12 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 35 Embedded reset and power control block characteristics . . . . . . . . . . . 36 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 77
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STM32F101xC, STM32F101xD, STM32F101xE 5.3.13 5.3.14 5.3.15 5.3.16 5.3.17 5.3.18 5.3.19
Contents
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.1 6.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.2.1 6.2.2 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Evaluating the maximum junction temperature for an application . . . . . 99
7 8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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List of tables
STM32F101xC, STM32F101xD, STM32F101xE
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F101xC, STM32F101xD and STM32F101xE features and peripheral counts . . . . . 9 STM32F101xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 36 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 39 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 40 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Typical current consumption in Sleep mode, code with data processing code running from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Low-speed user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Asynchronous non-multiplexed SRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . 52 Asynchronous non-multiplexed SRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . 53 Asynchronous multiplexed SRAM/NOR write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Asynchronous multiplexed SRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 62 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Switching characteristics for CF read and write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Switching characteristics for NAND Flash read and write cycles . . . . . . . . . . . . . . . . . . . . 75 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
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STM32F101xC, STM32F101xD, STM32F101xE Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62.
List of tables
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 SCL frequency (fPCLK1= 36 MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 LQFP144, 20 x 20 mm, 144-pin thin quad flat package mechanical data . . . . . . . . . . . . . 95 LQPF100 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . 96 LQFP64 64 pin low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . 97 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
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List of figures
STM32F101xC, STM32F101xD, STM32F101xE
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. STM32F101xC, STM32F101xD and STM32F101xE access line block diagram . . . . . . 18 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 STM32F101xC, STM32F101xD and STM32F101xE access line LQFP144 pinout . . . . . . 20 STM32F101xC, STM32F101xD and STM32F101xE access line LQFP100 pinout . . . . . . 21 STM32F101xC, STM32F101xD and STM32F101xE access line access line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 38 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 39 Current consumption in Stop mode with regulator in main mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Current consumption in Standby mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Asynchronous non-multiplexed SRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . 52 Asynchronous non-multiplexed SRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . 53 Asynchronous multiplexed SRAM/NOR write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Asynchronous multiplexed SRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 61 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 PC-card controller timing for common memory read access . . . . . . . . . . . . . . . . . . . . . . . 65 PC-card controller timing for common memory write access . . . . . . . . . . . . . . . . . . . . . . . 66 PC-card controller timing for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . 67 PC-card controller timing for attribute memory write access . . . . . . . . . . . . . . . . . . . . . . . 68 PC-card controller timing for I/O space read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 PC-card controller timing for I/O space write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 NAND controller timing for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 NAND controller timing for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 NAND controller timing for common memory read access . . . . . . . . . . . . . . . . . . . . . . . . . 74 NAND controller timing for common memory write access. . . . . . . . . . . . . . . . . . . . . . . . . 74 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 I2C bus AC waveforms and measurement circuit(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 SPI timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 SPI timing diagram - slave mode and CPHA=1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
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STM32F101xC, STM32F101xD, STM32F101xE Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54.
List of figures
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 91 Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . . 91 LQFP144, 20 x 20 mm, 144-pin thin quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 LQFP100, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 LQFP64 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
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Introduction
STM32F101xC, STM32F101xD, STM32F101xE
1
Introduction
This datasheet provides the ordering information and mechanical device characteristics of the STM32F101xC, STM32F101xD and STM32F101xE High-density access line microcontrollers. For more details on the whole STMicroelectronics STM32F101xx family, please refer to Section 2.2: Full compatibility throughout the family. The High-density STM32F101xx datasheet should be read in conjunction with the Mediumand High-density STM32F10xxx reference manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the CortexTM-M3 core please refer to the CortexTM-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.
2
Description
The STM32F101xC, STM32F101xD and STM32F101xE access line family incorporates the high-performance ARM CortexTM-M3 32-bit RISC core operating at a 36 MHz frequency, high-speed embedded memories (Flash memory up to 512 Kbytes and SRAM up to 48 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer one 12-bit ADC, four general purpose 16-bit timers, as well as standard and advanced communication interfaces: up to two I2Cs, three SPIs and five USARTs. The STM32F101xx High-density access line family operates in the 40 to +85 C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F101xx High-density access line family offers devices in 3 different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the STM32F101xx High-density access line microcontroller family suitable for a wide range of applications:
Medical and handheld equipment PC peripherals gaming and GPS platforms Industrial applications: PLC, printers, and scanners Alarm systems and Video intercom
Figure 1 shows the general block diagram of the device family.
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STM32F101xC, STM32F101xD, STM32F101xE
Description
2.1
Device overview
Table 2. STM32F101xC, STM32F101xD and STM32F101xE features and peripheral counts
STM32F101Rx 256 32 No Generalpurpose Basic SPI Comm I2C USART GPIOs 12-bit ADC Number of channels 12-bit DAC Number of channels CPU frequency Operating voltage Operating temperatures Package 51 1 16 384 48 512 STM32F101Vx 256 32 Yes 4 2 3 2 5 80 1 16 1 2 36 MHz 2.0 to 3.6 V Ambient temperature: 40 to +85 C (see Table 9) Junction temperature: 40 to +105 C (see Table 9) LQFP64 LQFP100(1) LQFP144 112 1 16 384 48 512 STM32F101Zx 256 32 Yes 384 48 512
Peripherals Flash memory in Kbytes SRAM in Kbytes FSMC
Timers
1. For the LQFP100 package, only FSMC Bank1 and Bank2 are available. Bank1 can only support a multiplexed NOR Flash memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package.
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Description
STM32F101xC, STM32F101xD, STM32F101xE
2.2
Full compatibility throughout the family
The STM32F101xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F101x6, STM32F101x8 and STM32F101xB are referred to as Medium-density devices, while the STM32F101xC, STM32F101xD and STM32F101xE are referred to as High-density devices. High-density devices are an extension of the STM32F101x6/8/B devices specified in the STM32F101xx datasheet. They feature higher Flash memory and RAM densities, and additional peripherals like FSMC and DAC, while remaining fully compatible with the other members of the family. The STM32F101xC, STM32F101xD and STM32F101xE are a drop-in replacement for the STM32F101x6/8/B devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. Table 3. STM32F101xx family
Memory size Medium-density STM32F101xx devices Pinout 32 KB Flash 6 KB RAM 144 100 64 48 36 3 × USARTs 3 × 16-bit timers 2 × USARTs 2 × 16-bit timers 2 × SPIs, 2 × I2Cs, 1 × ADC 1 × SPI, 1 × I2C 1 × ADC 64 KB Flash 10 KB RAM 128 KB Flash 16 KB RAM High-density STM32F101xx devices 256 KB Flash 32 KB RAM 384 KB Flash 48 KB RAM 512 KB Flash 48 KB RAM
5 × USARTs 4 × 16-bit timers, 2 × basic timers 3 × SPIs, 2 × I2Cs, 1 × ADC, 1 × DAC FSMC (100 and 144 pins)
2.3
Overview
ARM CortexTM-M3 core with embedded Flash and SRAM
The ARM CortexTM-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM CortexTM-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The STM32F101xC, STM32F101xD and STM32F101xE access line family having an embedded ARM core, is therefore compatible with all ARM tools and software. Figure 1 shows the general block diagram of the device family.
Embedded Flash memory
Up to 512 Kbytes of embedded Flash is available for storing programs and data.
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STM32F101xC, STM32F101xD, STM32F101xE
Description
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
Embedded SRAM
Up to 48 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.
FSMC (flexible static memory controller)
The FSMC is embedded in the STM32F101xC, STM32F101xD and STM32F101xE access line family. It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash, RAM, PSRAM, NOR and NAND. Functionality overview:
The three FSMC interrupt lines are ORed in order to be connected to the NVIC No read FIFO Code execution from external memory except for NAND Flash and PC Card No boot capability The targeted frequency is HCLK/2, so external access is at 18 MHz when HCLK is at 36 MHz
LCD parallel interface
The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration.
Nested vectored interrupt controller (NVIC)
The STM32F101xC, STM32F101xD and STM32F101xE access line embeds a nested vectored interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16 interrupt lines of CortexTM-M3) and 16 priority levels.
Closely coupled NVIC gives low-latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving higher priority interrupts Suppor t for tail-chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead
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Description
STM32F101xC, STM32F101xD, STM32F101xE This hardware block provides flexible interrupt management features with minimal interrupt latency.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected to the 16 external interrupt lines.
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock is available when necessary (for example with failure of an indirectly used external oscillator). Several prescalers are used to configure the AHB frequency, the high-speed APB (APB2) domain and the low-speed APB (APB1) domain. The maximum frequency of the AHB and APB domains is 36 MHz. See Figure 2 for details on the clock tree.
Boot modes
At startup, boot pins are used to select one of three boot options:
Boot from User Flash Boot from System Memory Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1.
Power supply schemes
VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.
For more details on how to connect power pins, refer to Figure 9: Power supply scheme.
Power supply supervisor
The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit.
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STM32F101xC, STM32F101xD, STM32F101xE
Description
The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table 11: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD.
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
MR is used in the nominal regulation mode (Run) LPR is used in the Stop modes. Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode.
Low-power modes
The STM32F101xC, STM32F101xD and STM32F101xE access line supports three lowpower modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:
Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
Stop mode Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output or the RTC alarm.
Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode.
DMA
The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-toperipheral transfers.
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Description
STM32F101xC, STM32F101xD, STM32F101xE The two DMA controllers support circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose and basic timers TIMx, DAC and ADC.
RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are forty-two 16-bit registers used to store 84 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, and they are not reset when the device wakes up from the Standby mode. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the High Speed External clock divided by 128. The internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:
A 24-bit down counter Autoreload capability Maskable system interrupt generation when the counter reaches 0. Programmable clock source
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STM32F101xC, STM32F101xD, STM32F101xE
Description
General-purpose timers (TIMx)
There are up to 4 synchronizable standard timers (TIM2, TIM3, TIM4 and TIM5) embedded in the STM32F101xC, STM32F101xD and STM32F101xE access line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or one pulse mode output. This gives up to 16 input captures / output compares / PWMs on the largest packages. They can work together with the advanced control timer via the Timer Link feature for synchronization or event chaining. The counter can be frozen in debug mode. Any of the standard timers can be used to generate PWM outputs. Each of the timers has independent DMA request generations.
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base.
I²C bus
Up to two I²C bus interfaces can operate in multi-master and slave modes. They can support standard and fast modes. They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus.
Universal synchronous/asynchronous receiver transmitters (USARTs)
The STM32F101xC, STM32F101xD and STM32F101xE access line embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4 and UART5). These five interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The five interfaces are able to communicate at speeds of up to 2.25 Mbit/s. USART1, USART2 and USART3 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller except for UART5.
Serial peripheral interface (SPI)
Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller.
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Description
STM32F101xC, STM32F101xD, STM32F101xE
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable except for analog inputs. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.
ADC (analog to digital converter)
A 12-bit analog-to-digital converter is embedded into STM32F101xC, STM32F101xD and STM32F101xE access line devices. It has up to 16 external channels, performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the standard timers (TIMx) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers.
DAC (digital-to-analog converter)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. This dual digital Interface supports the following features:
two DAC converters: one for each output channel 8-bit or 12-bit monotonic output left or right data alignment in 12-bit mode synchronized update capability noise-wave generation triangular-wave generation dual DAC channel independent or simultaneous conversions DMA capability for each channel external triggers for conversion input voltage reference VREF+
Seven DAC trigger inputs are used in the STM32F101xC, STM32F101xD and STM32F101xE access line family. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels.
Temperature sensor
The temperature sensor has to generate a linear voltage with any variation in temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value.
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STM32F101xC, STM32F101xD, STM32F101xE
Description
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
Embedded Trace MacrocellTM
The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F10xxx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools.
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Description Figure 1.
STM32F101xC, STM32F101xD, STM32F101xE STM32F101xC, STM32F101xD and STM32F101xE access line block diagram
TRACECLK TRACED[0:3] as AS JNTRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO as AF
TPIU SW/JTAG Trace/trig Pbus Ibus Cortex-M3 CPU Fmax: 36 MHz Dbus System NVIC GP DMA1 7 channels GP DMA2 Trace controller VDD Flash 512 Kbytes 64 bit
@VDD Power Volt. reg. 3.3 V to 1.8 V @VDDA Supply supervision POR /PDR PVD @VDD XTAL OSC 4-16 MHz IWDG Standby interface @VBAT XTAL32kHz RTC Backup reg AWU Backup interface VBAT =1.8 V to 3.6 V OSC32_IN OSC32_OUT TAMPER-RTC/ ALARM/SECOND OUT VSS
Flash obl interface
Bus Matri x
SRAM 48 KB @V DA D RC 8 MHz RC 40 kHz PLL PCLK1 PCLK2 HCLK FCLK
POR Reset Int
NRST VDDA VSSA
OSC_IN OSC_OUT
A[25:0] D[15:0] CLK NOE NWE NE[4:1] NBL[1:0] NWAIT NL as AF
5 channels
Reset & Clock control
FSMC
AHB2 APB2 112AF PA[15:0] PB[15:0] PC[15:0] PD[15:0] PE[15:0] PF[15:0] PG[15:0] MOSI, MISO, SCK, NSS as AF RX, TX, CTS, RTS as AF EXT.IT WKUP
AHB2 APB1
TIM2 TIM3
4 channels as AF 4 channels as AF 4 channels as AF 4 channels as AF RX, TX CTS, RTS , , CK, as AF RX, TX, CTS, RTS, CK, as AF RX,TX as AF RX, TX as AF MOSI, MISO SCK, NSS as AF MOSI, MISO SCK, NSS as AF SCL, SDA, SMBAL as AF SCL, SDA, SMBAL as AF DAC_1 as AF DAC_2 as AF
APB1: Fmax = 24/36 MHz
GPIO port A GPIO port B GPIO port C GPIO port D GPIO port E GPIO port F GPIO port G SPI1 USART1 WWDG Temp. sensor
TIM4 TIM5 USART 2 USART 3 UART4 UART5 SPI2 SPI3 I2C1 I2C2
ADC_IN[0:15]
APB2: Fmax = 24/36 MHz
12-bit ADC
IF
TIM6 TIM7
IF 12 bit DAC @VDDA
VREF VREF+
VREF+
@ VDDA
ai14693b
1. TA = 40 C to +85 C (junction temperature up to 105 C). 2. AF = alternate function on I/O port pin.
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STM32F101xC, STM32F101xD, STM32F101xE Figure 2. Clock tree
Description
8 MHz HSI RC
HSI FSMCCLK
/2
Peripheral clock enable 36 MHz max Clock Enable (7 bits)
to FSMC
HCLK to AHB bus, core, memory and DMA to Cortex System timer FCLK Cortex free running clock PCLK1 to APB1 peripherals Peripheral Clock
Enable (18 bits)
PLLSRC
PLLMUL ..., x16 x2, x3, x4 PLL
HSI PLLCLK HSE
SW
SYSCLK
/8
36 MHz /1, 2..512 max
AHB Prescaler
APB1 Prescaler /1, 2, 4, 8, 16
36 MHz max
CSS
TIM2,3,4,5,6,7 If (APB1 prescaler =1) x1 else x2
to TIM2,3,4,5,6 and 7 TIMXCLK
Peripheral Clock Enable (6 bits)
PLLXTPRE OSC_OUT OSC_IN 4-16 MHz HSE OSC /2
APB2 Prescaler /1, 2, 4, 8, 16
36 MHz max Peripheral Clock Enable (11 bits)
PCLK2 peripherals to APB2
/128 OSC32_IN OSC32_OUT LSE OSC 32.768 kHz
LSE to RTC
ADC Prescaler /2, 4, 6, 8 RTCCLK
to ADC
ADCCLK
RTCSEL[1:0] LSI RC 40 kHz
LSI to Independent Watchdog (IWDG)
IWDGCLK
Main Clock Output
/2
PLLCLK HSI HSE SYSCLK
Legend: HSE = High Speed External clock signal HSI = High Speed Internal clock signal LSI = Low Speed Internal clock signal LSE = Low Speed External clock signal ai15100
MCO
MCO
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 36 MHz. 2. To have an ADC conversion time of 1 s, APB2 must be at 14 MHz or 28 MHz.
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Pin descriptions
STM32F101xC, STM32F101xD, STM32F101xE
3
Figure 3.
Pin descriptions
STM32F101xC, STM32F101xD and STM32F101xE access line LQFP144 pinout
VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD_11 VSS_11 PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD_10 VSS_10 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14
PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PF0 PF1 PF2 PF3 PF4 PF5 VSS_5 VDD_5 PF6 PF7 PF8 PF9 PF10 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-W KUP PA1 PA2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
LQFP144
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
VDD_2 VSS_2 NC PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDD_9 VSS_9 PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD_8 VSS_8 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12
PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12
VDD_6 PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS_7 VDD_7 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1
VSS_6
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
ai14667
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STM32F101xC, STM32F101xD, STM32F101xE Figure 4.
Pin descriptions
STM32F101xC, STM32F101xD and STM32F101xE access line LQFP100 pinout
VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14
PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP PA1 PA2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
LQFP100
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VDD_2 VSS_2 NC PA 13 PA 12 PA 11 PA 10 PA 9 PA 8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12
PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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Pin descriptions Figure 5.
STM32F101xC, STM32F101xD, STM32F101xE
STM32F101xC, STM32F101xD and STM32F101xE access line access line LQFP64 pinout
VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14
VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0 OSC_IN PD1 OSC_OUT NRST PC0 PC1 PC2 PC3 V SSA V DDA PA0-WKUP PA1 PA2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12
PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1
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Table 4.
Pins LQFP100
Pin definitions
I / O Level(2) Alternate functions Main function(3) (after reset) PE2 PE3 PE4 PE5 PE6 VBAT PC13(5) PC14(5) PC15(5) PF0 PF1 PF2 PF3 PF4 PF5 VSS_5 TAMPER-RTC OSC32_IN OSC32_OUT FSMC_A0 FSMC_A1 FSMC_A2 FSMC_A3 FSMC_A4 FSMC_A5 Type(1)
LQFP144
LQFP64
Pin name
Default TRACECLK/ FSMC_A23 TRACED0/FSMC_A19 TRACED1/FSMC_A20 TRACED2/FSMC_A21 TRACED3/FSMC_A22
Remap
1 2 3 4 -
1 2 3 4 5 6 7 8 9 10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPER-RTC
(4)
I/O I/O I/O I/O I/O S I/O I/O I/O
FT FT FT FT FT
PC14-OSC32_IN(4) PC15-OSC32_OUT(4) PF0 PF1 PF2 PF3 PF4 PF5 VSS_5
I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S
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STM32F101xC, STM32F101xD, STM32F101xE Table 4.
Pins LQFP100 LQFP144 LQFP64 Pin name Type(1)
Pin descriptions
Pin definitions (continued)
I / O Level(2) Alternate functions Main function(3) (after reset) VDD_5 PF6 PF7 PF8 PF9 PF10 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA WKUP/ USART2_CTS(6)/ ADC_IN0/TIM5_CH1/ TIM2_CH1_ETR(6) USART2_RTS(6)/ ADC_IN1/TIM5_CH2 TIM2_CH2(6) USART2_TX(6)/ TIM5_CH3/ADC_IN2/ TIM2_CH3(6) USART2_RX(6)/ TIM5_CH4/ ADC_IN3/ TIM2_CH4(6) ADC_IN10 ADC_IN11 ADC_IN12 ADC_IN13 FSMC_NIORD FSMC_NREG FSMC_NIOWR FSMC_CD FSMC_INTR
Default
Remap
5 6 7 8 9 10 11 12 13
11 12 13 14 15 16 17 18 19 20 21 22
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
VDD_5 PF6 PF7 PF8 PF9 PF10 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA
S I/O I/O I/O I/O I/O I O I/O I/O I/O I/O I/O S S S S
14
23
34
PA0-WKUP
I/O
PA0
15
24
35
PA1
I/O
PA1
16
25
36
PA2
I/O
PA2
17 18 19 20
26 27 28 29
37 38 39 40
PA3 VSS_4 VDD_4 PA4
I/O S S I/O
PA3 VSS_4 VDD_4 PA4
SPI1_NSS/ DAC_OUT1//ADC_IN4 USART2_CK(6) SPI1_SCK/ DAC_OUT2 ADC_IN5
21
30
41
PA5
I/O
PA5
23/102
Pin descriptions Table 4.
Pins LQFP100 LQFP144 LQFP64 Pin name Type(1)
STM32F101xC, STM32F101xD, STM32F101xE
Pin definitions (continued)
I / O Level(2) Alternate functions Main function(3) (after reset)
Default SPI1_MISO/ ADC_IN6/ TIM3_CH1(6) SPI1_MOSI/ ADC_IN7/ TIM3_CH2(6) ADC_IN14 ADC_IN15 ADC_IN8/ TIM3_CH3(6) ADC_IN9/TIM3_CH4(6)
Remap
22
31
42
PA6
I/O
PA6
23 24 25 26 27 28 29
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69
PA7 PC4 PC5 PB0 PB1 PB2/BOOT1 PF11 PF12 VSS_6 VDD_6 PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS_7 VDD_7 PE10 PE11 PE12 PE13 PE14 PE15 PB10
I/O I/O I/O I/O I/O I/O FT I/O I/O S S I/O I/O I/O I/O I/O I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT
PA7 PC4 PC5 PB0 PB1 PB2/BOOT1
FSMC_NIOS16 FSMC_A6
FSMC_A7 FSMC_A8 FSMC_A9 FSMC_A10 FSMC_A11 PE7 PE8 PE9 FSMC_D4 FSMC_D5 FSMC_D6
PE10 PE11 PE12 PE13 PE14 PE15 PB10
FSMC_D7 FSMC_D8 FSMC_D9 FSMC_D10 FSMC_D11 FSMC_D12 I2C2_SCL/ USART3_TX(6) TIM2_CH3
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STM32F101xC, STM32F101xD, STM32F101xE Table 4.
Pins LQFP100 LQFP144 LQFP64 Pin name Type(1)
Pin descriptions
Pin definitions (continued)
I / O Level(2) Alternate functions Main function(3) (after reset)
Default I2C2_SDA/ USART3_RX(6)
Remap
30 31 32 33
48 49 50 51
70 71 72 73
PB11 VSS_1 VDD_1 PB12
I/O FT S S I/O FT
PB11 VSS_1 VDD_1 PB12
TIM2_CH4
SPI2_NSS(6)/ I2C2_SMBAl/ USART3_CK(6) SPI2_SCK(6)/ USART3_CTS(6) SPI2_MISO(6)/ USART3_RTS(6) SPI2_MOSI(6) FSMC_D13 FSMC_D14 FSMC_D15 FSMC_A16 FSMC_A17 FSMC_A18 USART3_TX USART3_RX USART3_CK USART3_CTS TIM4_CH1 / USART3_RTS TIM4_CH2
34 35 36 37 38 39
52 53 54 55 56 57 58 59 60 61 62 63 64 65
74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98
PB13 PB14 PB15 PD8 PD9 PD10 PD11 PD12 PD13 VSS_8 VDD_8 PD14 PD15 PG2 PG3 PG4 PG5 PG6 PG7 PG8 VSS_9 VDD_9 PC6 PC7 PC8
I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT
PB13 PB14 PB15 PD8 PD9 PD10 PD11 PD12 PD13
PD14 PD15
FSMC_D0 FSMC_D1 FSMC_A12 FSMC_A13 FSMC_A14 FSMC_A15 FSMC_INT2 FSMC_INT3
TIM4_CH3 TIM4_CH4
PC6 PC7 PC8
TIM3_CH1 TIM3_CH2 TIM3_CH3
25/102
Pin descriptions Table 4.
Pins LQFP100 LQFP144 LQFP64 Pin name Type(1)
STM32F101xC, STM32F101xD, STM32F101xE
Pin definitions (continued)
I / O Level(2) Alternate functions Main function(3) (after reset) PC9 PA8 PA9 PA10 PA11 PA12 JTMS-SWDIO USART1_CK/ MCO USART1_TX(6) USART1_RX(6) USART1_CTS USART1_RTS PA13
Default
Remap TIM3_CH4
40 41 42 43 44 45 46 47 48 49 50 51 52 53 5 6 54 -
66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 -
99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
PC9 PA8 PA9 PA10 PA11 PA12 PA13/JTMS-SWDIO
I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT
Not connected VSS_2 VDD_2 PA14/JTCK-SWCLK PA15/JTDI PC10 PC11 PC12 PD0 PD1 PD2 PD3 PD4 PD5 VSS_10 VDD_10 PD6 PD7 PG9 PG10 PG11 PG12 PG13 S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT PD6 PD7 FSMC_NWAIT FSMC_NE1/ FSMC_NCE2 FSMC_NE2/ FSMC_NCE3 FSMC_NE3/ FSMC_NCE4_1 FSMC_NCE4_2 FSMC_NE4 FSMC_A24 USART2_RX USART2_CK VSS_2 VDD_2 JTCK-SWCLK JTDI PC10 PC11 PC12 OSC_IN(7) OSC_OUT(7) PD2 PD3 PD4 PD5 PA14 PA15/SPI3_NSS UART4_TX UART4_RX UART5_TX FSMC_D2 FSMC_D3 TIM3_ETR/UART5_RX FSMC_CLK FSMC_NOE FSMC_NWE USART2_CTS USART2_RTS USART2_TX TIM2_CH1_ETR / SPI1_NSS USART3_TX USART3_RX USART3_CK
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STM32F101xC, STM32F101xD, STM32F101xE Table 4.
Pins LQFP100 LQFP144 LQFP64 Pin name Type(1)
Pin descriptions
Pin definitions (continued)
I / O Level(2) Alternate functions Main function(3) (after reset)
Default FSMC_A25
Remap
55 56 57 58 59 60 61 62 63 64
89 90 91 92 93 94 95 96 97 98 99
129 130 131 132 133 134 135 136 137 138 139 140 141 142 143
PG14 VSS_11 VDD_11 PG15 PB3/JTDO PB4/JNTRST PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS_3 VDD_3
I/O FT S S I/O I/O FT I/O FT I/O I/O FT I/O FT I I/O FT I/O FT I/O FT I/O FT S S JTDO JNTRST PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS_3 VDD_3
PB3/TRACESWO/ JTDO/ SPI3_SCK PB4/SPI3_MISO I2C1_SMBAl/ SPI3_MOSI I2C1_SCL/ TIM4_CH1(6) I2C1_SDA/FSMC_NADV / TIM4_CH2(6)
TIM2_CH2 / SPI1_SCK TIM3_CH1 / SPI1_MISO TIM3_CH2 / SPI1_MOSI USART1_TX USART1_RX
TIM4_CH3 (6) TIM4_CH4
(6)
I2C1_SCL I2C1_SDA
TIM4_ETR(6)/ FSMC_NBL0 FSMC_NBL1
100 144
1. I = input, O = output, S = supply, HiZ = high impedance. 2. FT = 5 V tolerant. 3. Function availability depends on the chosen device. 4. PC13, PC14 and PC15 are supplied through the power switch, and so their use in output mode is limited: they can be used only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time. 5. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 6. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 7. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 and LQFP144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual
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Pin descriptions Table 5.
Pins CF PE2 PE3 PE4 PE5 PE6 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PF8 PF9 PF10 PF11 PF12 PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PD8 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 A0 A1 A2 A3 A4 A5 NIORD NREG NIOWR CD INTR NIOS16 A6 A7 A8 A9 A10 NIORD NREG NIOWR CD INTR NIOS16 A6 A7 A8 A9 A10 A11 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 A0 A1 A2 CF/IDE
STM32F101xC, STM32F101xD, STM32F101xE FSMC pin definition
FSMC NOR/PSRAM NOR/SRAM Mux NAND 16 bit A23 A19 A20 A21 A22 A0 A1 A2 A3 A4 A5 A23 A19 A20 A21 A22 LQFP100 BGA100(1) Yes Yes Yes Yes Yes DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 DA13 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
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STM32F101xC, STM32F101xD, STM32F101xE Table 5.
Pins CF PD9 PD10 PD11 PD12 PD13 PD14 PD15 PG2 PG3 PG4 PG5 PG6 PG7 PD0 PD1 PD3 PD4 PD5 PD6 PD7 PG9 PG10 PG11 PG12 PG13 PG14 PB7 PE0 PE1 NCE4_1 NCE4_2 NCE4_1 NCE4_2 NE4 A24 A25 NADV NBL0 NBL1 NE4 A24 A25 NADV NBL0 NBL1 NOE NWE NWAIT NOE NWE NWAIT D2 D3 D2 D3 D2 D3 CLK NOE NWE NWAIT NE1 NE2 NE3 DA2 DA3 CLK NOE NWE NWAIT NE1 NE2 NE3 D0 D1 D0 D1 D14 D15 CF/IDE D14 D15
Pin descriptions
FSMC pin definition (continued)
FSMC NOR/PSRAM NOR/SRAM Mux NAND 16 bit D14 D15 A16 A17 A18 D0 D1 A12 A13 A14 A15 INT2 INT3 D2 D3 DA14 DA15 A16 A17 A18 DA0 DA1 D0 D1 D14 D15 CLE ALE LQFP100 BGA100(1) Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes NOE NWE NWAIT NCE2 NCE3 Yes Yes Yes Yes Yes Yes Yes Yes
1. Ports F and G are not available in devices delivered in 100-pin packages.
29/102
Memory mapping
STM32F101xC, STM32F101xD, STM32F101xE
4
Memory mapping
The memory map is shown in Figure 6. Figure 6. Memory map
Reserved FSMC register FSMC bank 4 PCCARD FSMC bank 3 NAND (NAND2) FSMC bank 2 NAND (NAND1) FSMC bank 1 NOR/PSRAM 4 FSMC bank 1 NOR/PSRAM 3 FSMC bank 1 NOR/PSRAM 2 FSMC bank 1 NOR/PSRAM 1 Reserved CRC Reserved Flash interface Reserved RCC Reserved DMA2 DMA1 Reserved Reserved 0xA000 1000 - 0xBFFF FFFF 0xA000 0000 - 0xA000 0FFF 0x9000 0000 - 0x9FFF FFFF 0x8000 0000 - 0x8FFF FFFF 0x7000 0000 - 0x7FFF FFFF 0x6C00 0000 - 0x6FFF FFFF 0x6800 0000 - 0x6BFF FFFF 0x6400 0000 - 0x67FF FFFF 0x6000 0000 - 0x63FF FFFF 0x4002 3400 - 0x5FFF FFFF 0x4002 3000 - 0x4002 33FF 0x4002 2400 - 0x4002 2FFF 0x4002 2000 - 0x4002 23FF 0x4002 1400 - 0x4002 1FFF 0x4002 1000 - 0x4002 13FF 0x4002 0400 - 0x4002 0FFF 0x4002 0400 - 0x4002 07FF 0x4002 0000 - 0x4002 03FF 0x4001 8400 - 0x4001 FFFF 0x4001 8000 - 0x4001 83FF 0x4001 3C00 - 0x4001 7FFF 0x4001 3800 - 0x4001 3BFF 0x4001 3400 - 0x4001 37FF 0x4001 3000 - 0x4001 33FF 0x4001 2800 - 0x4001 2FFF 0x4001 2400 - 0x4001 27FF 0x4001 2000 - 0x4001 23FF 0x4001 1C00 - 0x4001 1FFF 0x4001 1800 - 0x4001 1BFF 0x4001 1400 - 0x4001 17FF 0x4001 1000 - 0x4001 13FF 0x4001 0C00 - 0x4001 0FFF 0x4001 0800 - 0x4001 0BFF 0x4001 0400 - 0x4001 07FF 0x4001 0000 - 0x4001 03FF 0x4000 7800 - 0x4000 FFFF 0x4000 7400 - 0x4000 77FF 0x4000 7000 - 0x4000 73FF 0x4000 6C00 - 0x4000 6FFF 0x4000 5C00 - 0x4000 6BFF 0x4000 5800 - 0x4000 5BFF 0x4000 5400 - 0x4000 57FF 0x4000 5000 - 0x4000 53FF 0x4000 4C00 - 0x4000 4FFF 0x4000 4800 - 0x4000 4BFF 0x4000 4400 - 0x4000 47FF 0x4000 4000 - 0x4000 43FF 0x4000 3C00 - 0x4000 3FFF 0x4000 3800 - 0x4000 3BFF 0x4000 3400 - 0x4000 37FF 0x4000 3000 - 0x4000 33FF 0x4000 2C00 - 0x4000 2FFF 0x4000 2800 - 0x4000 2BFF 0x4000 1800 - 0x4000 27FF 0x4000 1400 - 0x4000 17FF 0x4000 1000 - 0x4000 13FF 0x4000 0C00 - 0x4000 0FFF 0x4000 0800 - 0x4000 0BFF 0x4000 0400 - 0x4000 07FF 0x4000 0000 - 0x4000 03FF
0xFFFF FFFF
0xE000 0000 0xDFFF FFFF
512-Mbyte block 7 Cor tex-M3's internal peripherals 512-Mbyte block 6 Not used
Reserved USART1 Reserved SPI1 Reserved ADC1 Por t G Por t F Por t E Por t D Por t C Por t B Por t A EXTI AFIO Reserved DAC PWR BKP Reserved I2C2 I2C1 UART5 UART4 USART3 USART2 Reserved SPI3 SPI2 Reserved IWDG WWDG RTC Reserved TIM7 TIM6 TIM5
0xC000 0000 0xBFFF FFFF 512-Mbyte block 5 FSMC register 0xA000 0000 0x9FFF FFFF 512-Mbyte block 4 FSMC bank3 & bank4 512-Mbyte block 3 FSMC bank1 & bank2 512-Mbyte block 2 Peripherals 0x4000 0000 0x3FFF FFFF 512-Mbyte block 1 SRAM 0x2000 0000 0x1FFF FFFF 512-Mbyte block 0 Code 0x0000 0000 Reserved SRAM (48 KB aliased by bit-banding) Option Bytes System memory Reserved Flash Reserved Aliased to Flash, system memory or SRAM depending on BOOT pins
0x3FFF FFFF 0x2000 C000 0x2000 BFFF 0x2000 0000
0x8000 0000 0x7FFF FFFF
0x6000 0000 0x5FFF FFFF
TIM4 TIM3 TIM2
0x1FFF F800 - 0x1FFF F80F 0x1FFF F000- 0x1FFF F7FF 0x1FFF EFFF 0x0808 0000 0x0807 FFFF 0x0800 0000 0x07FF FFFF 0x0008 0000 0x0007 FFFF 0x0000 0000
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STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
5
5.1
Electrical characteristics
Test conditions
Unless otherwise specified, all voltages are referenced to VSS.
5.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3).
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.3 V (for the 2 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2).
5.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
5.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 7.
31/102
Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
5.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 8. Figure 7. Pin loading conditions Figure 8. Pin input voltage
STM32F101 PIN C=50pF
VIN
STM32F101 PIN
ai14123
ai14124
5.1.6
Power supply scheme
Figure 9. Power supply scheme
VBAT
1. 8-3. 6V
Po wer swi tch
Backup circuitry (OSC32K,RTC, Wake-up logic Backup registers)
O UT
Level shifter
GP I/Os
IN
IO Logic Kernel logic (CPU, Digital & Memories)
VDD VDD1/2/.../11
Regulator
11 × 100 nF + 1 × 4.7 F
VSS1/2/.../11 VDD VREF VDDA VREF+ VREFVSSA
ai15401
10 nF + 1 F
10 nF + 1 F
ADC
An alo g: RCs, PLL, ...
Caution:
In Figure 9, the 4.7 F capacitor must be connected to VDD3.
32/102
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
5.1.7
Current consumption measurement
Figure 10. Current consumption measurement scheme
IDD_VBAT VBAT
IDD VDD
VDDA
ai14126
5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 6: Voltage characteristics, Table 7: Current characteristics, and Table 8: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 6.
Symbol VDD -VSS VIN |VDDx| |VSSX - VSS|
Voltage characteristics
Ratings External main supply voltage (including VDDA and VDD)(1) Input voltage on five volt tolerant pin(2) Input voltage on any other pin(2) Variations between different power pins Variations between all the different ground pins Electrostatic discharge voltage (human body model) Mi n 0.3 VSS -0.3 VSS - 0.3 50 50 Max 4.0 +5.5 VDD+0.3 50 mV 50 V Unit
VESD(HBM)
see Section 5.3.12: Absolute maximum ratings (electrical sensitivity)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded (see Table 7: Current characteristics). This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN
33/102
Electrical characteristics Table 7.
Symbol IVDD IVSS IIO
STM32F101xC, STM32F101xD, STM32F101xE
Current characteristics
Ratings Total current into VDD power lines (source)(1) Total current out of VSS ground lines (sink)
(1)
Max. 150 150 25 -25 5 5 5 pins)(4) 25
Unit
Output current sunk by any I/O and control pin Output current source by any I/Os and control pin Injected current on NRST pin IINJ(PIN) (2)(3) Injected current on High-speed external OSC_IN and Lowspeed external OSC_IN pins Injected current on any other pin(4) IINJ(PIN)
(2)
mA
Total injected current (sum of all I/O and control
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN
Table 8.
Thermal characteristics
Ratings Storage temperature range Maximum junction temperature Value 65 to +150 150 Unit C C
Symbol TSTG TJ
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STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
5.3
5.3.1
Operating conditions
General operating conditions
Table 9.
Symbol fHCLK fPCLK1 fPCLK2 VDD
General operating conditions
Parameter Internal AHB clock frequency Internal APB1 clock frequency Internal APB2 clock frequency Standard operating voltage Analog operating voltage (ADC not used) Analog operating voltage (ADC used) Backup operating voltage LQFP144 Power dissipation at TA = 85 C(2) Conditions Min 0 0 0 2 2 Must be the same potential as VDD 2.4 1.8 Max 36 36 36 3.6 3.6 V 3.6 3.6 444 434 444 40 40 40 85 105 105 C C C mW V V MHz Unit
VDDA(1)
VBAT
PD
LQFP100 LQFP64 Maximum power dissipation
TA TJ
Ambient temperature Junction temperature range
Low power dissipation(3)
1. When the ADC is used, refer to Table 52: ADC characteristics. 2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 98). 3. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 98).
5.3.2
Operating conditions at power-up / power-down
The parameters given in Table 10 are derived from tests performed under the ambient temperature condition summarized in Table 9. Table 10.
Symbol tVDD
Operating conditions at power-up / power-down
Parameter VDD rise time rate VDD fall time rate Conditions Mi n 0 20 Max Unit s/V
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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
5.3.3
Embedded reset and power control block characteristics
The parameters given in Table 11 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 11.
Symbol
.
Embedded reset and power control block characteristics
Parameter Conditions PLS[2:0]=000 (rising edge) PLS[2:0]=000 (falling edge) PLS[2:0]=001 (rising edge) PLS[2:0]=001 (falling edge) PLS[2:0]=010 (rising edge) PLS[2:0]=010 (falling edge) PLS[2:0]=011 (rising edge) Mi n 2.1 2 2.19 2.09 2.28 2.18 2.38 2.28 2.47 2.37 2.57 2.47 2.66 2.56 2.76 2.66 Typ 2.18 2.08 2.28 2.18 2.38 2.28 2.48 2.38 2.58 2.48 2.68 2.58 2.78 2.68 2.88 2.78 100 Falling edge Rising edge 1.8(1) 1.84 1.88 1.92 40 1.5 2.5 3.5 1.96 2.0 Max 2.26 2.16 2.37 2.27 2.48 2.38 2.58 2.48 2.69 2.59 2.79 2.69 2.9 2.8 3 2.9 Unit V V V V V V V V V V V V V V V V mV V V mV ms
VPVD
Programmable voltage detector level selection
PLS[2:0]=011 (falling edge) PLS[2:0]=100 (rising edge) PLS[2:0]=100 (falling edge) PLS[2:0]=101 (rising edge) PLS[2:0]=101 (falling edge) PLS[2:0]=110 (rising edge) PLS[2:0]=110 (falling edge) PLS[2:0]=111 (rising edge) PLS[2:0]=111 (falling edge)
VPVDhyst(2) VPOR/PDR VPDRhyst
(2)
PVD hysteresis Power on/power down reset threshold PDR hysteresis Reset temporization
tRSTTEMPO(2)
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value. 2. Guaranteed by design, not tested in production.
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STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
5.3.4
Embedded reference voltage
The parameters given in Table 12 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 12.
Symbol VREFINT TS_vrefint(1)
Embedded internal reference voltage
Parameter Internal reference voltage ADC sampling time when reading the internal reference voltage Conditions 40 C < TA < +85 C Min 1.16 Typ 1.20 5.1 Ma x 1.24 17.1(2) Unit V s
1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production.
5.3.5
Supply current characteristics
The current consumption is measured as described in Figure 10: Current consumption measurement scheme.
Maximum current consumption
The MCU is placed under the following conditions:
All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except if it is explicitly mentioned The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 36 MHz) Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK
The parameters given in Table 13 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 13. Maximum current consumption in Run mode, code with data processing running from Flash
Max(1) Symbol Parameter Conditions fHCLK TA = 85 C 36 MHz External clock (2), all peripherals enabled IDD Supply current in Run mode External clock (2), all peripherals Disabled 24 MHz 16 MHz 8 MHz 36 MHz 24 MHz 16 MHz 8 MHz
1. Based on characterization, tested in production at VDD max, fHCLK max. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Unit 39 27 20 11 mA 22 16.5 12.5 8
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Electrical characteristics Table 14.
STM32F101xC, STM32F101xD, STM32F101xE
Maximum current consumption in Run mode, code with data processing running from RAM
Max(1) Parameter Conditions fHCLK TA = 85 C 36 MHz External clock (2), all peripherals enabled 24 MHz 16 MHz 8 MHz 36 MHz External clock(2) all peripherals disabled 24 MHz 16 MHz 8 MHz 34 24 17 10 mA 18 13 10 6 Unit
Symbol
IDD
Supply current in Run mode
1. Based on characterization, tested in production at VDD max, fHCLK max. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Figure 11. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled
35
30
8 MHz 16 MHz 24 MHz 36 MHz
25 Consumption (mA)
20
15
10
5
0 -45 25 Temperat ure (C) 70 85
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STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled
18 16 8 MHz 14 12 10 8 6 4 2 0 -45 25 Temperat ure (C) 70 85 16 MHz 24 MHz 36 MHz
Table 15.
Consumption (mA)
Maximum current consumption in Sleep mode, code running from Flash or RAM
Max Parameter Conditions fHCLK 36 MHz External clock(2) all peripherals enabled 24 MHz 16 MHz 8 MHz 36 MHz External clock(2), all peripherals disabled 24 MHz 16 MHz 8 MHz Unit
Symbol
TA = 85 C(1) 24 17 12.5 8
IDD
Supply current in Sleep mode
mA 6 5 4.5 4
1. Based on characterization, tested in production at VDD max, fHCLK max. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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Electrical characteristics Table 16.
Symbol
STM32F101xC, STM32F101xD, STM32F101xE
Typical and maximum current consumptions in Stop and Standby modes
Typ(1) Parameter Conditions VDD/ VBAT = 2.4 V VDD/VBAT = 3.3 V Max Unit TA = 85 C
Supply current in Stop mode
Regulator in Run mode, Low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) Regulator in Low-power mode, Low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) Low-speed internal RC oscillator and independent watchdog ON
34.5
35
TBD
24.5
25
TBD
IDD
3 2.8
3.8 3.6
-
A
Supply current in Standby mode
Low-speed internal RC oscillator ON, independent watchdog OFF Low-speed internal RC oscillator and independent watchdog OFF, low-speed oscillator and RTC OFF
1.9
2.1
5 (2)
IDD_VBAT
Backup domain supply current
Low-speed oscillator and RTC ON
1.1
1.4
2.0(2)
1. Typical values are measured at TA = 25 C. 2. Based on characterization, not tested in production.
Figure 13. Current consumption in Stop mode with regulator in main mode versus temperature at different VDD values
300
250
Consumption (A)
200
150
100 2.4V 2.7V 3.0V 3.3V 3.6V - 45 25 Temper atur e (C) 70 85
50
0
40/102
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
Figure 14. Current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values
300
250
Consumption (A)
200
150
100 2.4V 2.7V 3.0V 3.3V 3.6V - 45 25 Temper atur e (C) 70 85
50
0
Figure 15. Current consumption in Standby mode versus temperature at different VDD values
3.5
3
2.5 Consumption (A)
2
1.5
1
0.5
2.4V 2. 7V 3. 0V 3. 3V 3. 6V
0 -45 25 Temperat ure (C) 70 85
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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Typical current consumption
The MCU is placed under the following conditions:
All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except if it is explicitly mentioned The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 36 MHz) Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK = fPCLK2/4
The parameters given in Table 17 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 17. Typical current consumption in Run mode, code with data processing running from Flash
Typ(1) Symbol Parameter Conditions fHCLK All peripherals enabled(2) 26.6 18.5 12.8 7.2 4.2 2.7 2 1.6 1.3 26 17.9 12.2 6.6 3.6 2.1 1.4 1 0.7 Typ(1) All peripherals disabled 16.2 11.4 8.2 5 3.1 2.1 1.7 1.4 1.2 mA 36 MHz 24 MHz Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 125 kHz
1. Typical values are measures at TA = 25 C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Unit
36 MHz 24 MHz 16 MHz 8 MHz External clock(3) 4 MHz 2 MHz 1 MHz 500 kHz IDD Supply current in Run mode 125 kHz
15.6 10.8 7.6 4.4 2.5 1.5 1.1 0.8 0.6
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STM32F101xC, STM32F101xD, STM32F101xE Table 18.
Electrical characteristics
Typical current consumption in Sleep mode, code with data processing code running from Flash or RAM
Typ(1) Typ(1) Unit Parameter Conditions fHCLK
Symbol
All peripherals All peripherals enabled(2) disabled 15.1 10.4 7.2 3.9 2.6 1.85 1.5 1.3 1.2 14.5 9.8 6.6 3.3 2 1.25 0.9 0.7 0.6 3.6 2.6 2 1.3 1.2 1.15 1.1 1.05 1.05
36 MHz 24 MHz 16 MHz 8 MHz External clock
(3)
4 MHz 2 MHz 1 MHz 500 kHz
IDD
Supply current in Sleep mode
125 kHz 36 MHz 24 MHz Running on High Speed Internal RC (HSI), AHB prescaler used to reduce the frequency 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 125 kHz
mA 3 2 1.4 0.7 0.6 0.55 0.5 0.45 0.45
1. Typical values are measures at TA = 25 C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 19. The MCU is placed under the following conditions:
all I/O pins are in input mode with a static value at VDD or VSS (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption with all peripherals clocked off with only one peripheral clocked on
ambient operating temperature and VDD supply voltage conditions summarized in Table 6.
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Electrical characteristics Table 19.
STM32F101xC, STM32F101xD, STM32F101xE
Peripheral current consumption
Peripheral TIM2 TIM3 TIM4 TIM5 TIM6 TIM7 SPI2 Typical consumption at 25 C(1) 0.6 0.6 0.6 0.6 0.2 0.2 0.15 0.15 0.25 0.25 0.3 0.3 0.22 0.22 0.72 0.3 0.4 0.4 0.3 0.5 0.4 0.5 1.4 0.3 0.6 mA Unit
APB1
SPI3 USART2 USART3 UART4 UART5 I2C1 I2C2 DAC GPIOA GPIOB GPIOC GPIOD GPIOE
APB2 GPIOF GPIOG ADC
(2)
SPI1 USART1
1. fHCLK = 36 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral. 2. Specific conditions for ADC: fHCLK = 28 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/2, ADON bit in the ADC_CR2 register is set to 1.
5.3.6
External clock source characteristics
High-speed external user clock generated from an external source
The characteristics given in Table 20 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 9.
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STM32F101xC, STM32F101xD, STM32F101xE Table 20.
Symbol fHSE_ext VHSEH VHSEL tw(HSE) tw(HSE) tr(HSE) tf(HSE) IL
Electrical characteristics
High-speed external user clock characteristics
Parameter User external clock source frequency(1) OSC_IN input pin high level voltage OSC_IN input pin low level voltage OSC_IN high or low time(1) OSC_IN rise or fall time(1) OSC_IN Input leakage current VSS VIN VDD Conditions Min 0 0.7VDD VSS 16 ns 5 1 A Typ 8 Max 25 VDD V 0.3VDD Unit MHz
1. Guaranteed by design, not tested in production
Low-speed external user clock generated from an external source
The characteristics given in Table 21 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 9. Table 21.
Symbol fLSE_ext VLSEH VLSEL tw(LSE) tw(LSE) tr(LSE) tf(LSE) IL
Low-speed user external clock characteristics
Parameter User external clock source frequency(1) OSC32_IN input pin high level voltage OSC32_IN input pin low level voltage OSC32_IN high or low time(1) OSC32_IN rise or fall time(1) VSS VIN VDD 0.7VDD VSS 450 ns 5 1 A Conditions Min Typ 32.768 Max 1000 VDD V 0.3VDD Unit kHz
OSC32_IN Input leakage current
1. Guaranteed by design, not tested in production.
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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Figure 16. High-speed external clock source AC timing diagram
VHSEH 90% VHSEL 10% tr(HSE) THSE tf(HSE) tW(HSE) tW(HSE) t
EXTER NAL CLO CK SO URC E
fHSE_ext OSC _I N
IL STM32F101 ai14127
Figure 17. Low-speed external clock source AC timing diagram
VLSEH 90% VLSEL 10% tr(LSE) TLSE tf(LSE) tW(LSE) tW(LSE) t
EXTER NAL CLO CK SO URC E
fLSE_ext
OSC32_I N
IL STM32F101 ai14140b
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STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 22. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 22.
Symbol fOSC_IN RF CL1 CL2(3) i2 gm
HSE 4-16 MHz oscillator characteristics(1)(2)
Parameter Oscillator frequency Feedback resistor Recommended load capacitance RS = 30 versus equivalent serial resistance of the crystal (RS)(4) HSE driving current Oscillator transconductance VDD = 3.3 V VIN = VSS with 30 pF load Star tup VDD is stabilized 25 2 Conditions Min 4 Typ 8 200 30 Max 16 Unit M Hz k pF
1
mA mA/V ms
tSU(HSE)(5) Star tup time
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization results, not tested in production. 3. For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. 4. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 5. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer
Figure 18. Typical application with an 8 MHz crystal
RESO NAT OR W I TH IN TEG RAT ED CAPAC IT O RS CL1 OSC_IN 8 MH z resonator CL2 REXT(1) OSC_OU T RF Bias controlled gain STM32F101xx ai14128 fHS E
1. REXT value depends on the crystal characteristics. Typical value is in the range of 5 to 6RS.
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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 23. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Note: For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF, then CL1 = CL2 = 8 pF. Table 23.
Symbol RF CL1 CL2(2) I2 gm tSU(LSE)(4)
Caution:
LSE oscillator characteristics (fLSE = 32.768 kHz)(1)
Parameter Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) LSE driving current Oscillator transconductance Star tup time VDD is stabilized RS = 30 K VDD = 3.3 V VIN = VSS 5 3 Conditions Min Typ 5 15 Max Unit M pF
1.4
A A/V s
1. Based on characterization, not tested in production. 2. Refer to the note and caution paragraphs above the table. 3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32.768 kHz. Refer to crystal manufacturer for more details 4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer
48/102
STM32F101xC, STM32F101xD, STM32F101xE Figure 19. Typical application with a 32.768 kHz crystal
RESO NAT OR W I TH IN TEG RAT ED CAPAC IT O RS CL1 OSC32_IN 32.768 KH z resonator CL2 RF OSC32_OU T Bias controlled gain
Electrical characteristics
fLSE
STM32F101xx
ai14129
5.3.7
Internal clock source characteristics
The parameters given in Table 24 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9.
High-speed internal (HSI) RC oscillator
Table 24.
Symbol fHSI Frequency TA = 40 to 85 C TA = 25 C 1 80 1
HSI oscillator characteristics(1) (2)
Parameter Conditions Min Typ 8 3 2 2 100 Ma x Unit MHz % % s A
ACCHSI Accuracy of HSI oscillator tsu(HSI) IDD(HSI) HSI oscillator startup time HSI oscillator power consumption
1. VDD = 3.3 V, TA = 40 to 85 C unless otherwise specified. 2. Guaranteed by design, not tested in production.
Low-speed internal (LSI) RC oscillator
Table 25.
Symbol fLSI(2) tsu(LSI)(3) IDD(LSI)(3) Frequency LSI oscillator startup time LSI oscillator power consumption 0.65
LSI oscillator characteristics (1)
Parameter Min 30 Typ 40 Max 60 85 1.2 Unit kHz s A
1. VDD = 3 V, TA = 40 to 85 C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production.
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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Wakeup time from low-power mode
The wakeup times given in Table 26 is measured on a wakeup phase with a 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode:
Stop or Standby mode: the clock source is the RC oscillator Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 26.
Symbol
Low-power mode wakeup timings
Parameter Conditions Wakeup on HSI RC clock HSI RC wakeup time = 2 s HSI RC wakeup time = 2 s, Regulator wakeup from LP mode time = 5 s HSI RC wakeup time = 2 s, Regulator wakeup from power down time = 38 s Typ 1.8 3.6 s 5.4 Unit s
tWUSLEEP(1) Wakeup from Sleep mode Wakeup from Stop mode (regulator in run mode) tWUSTOP(1) Wakeup from Stop mode (regulator in low-power mode)
tWUSTDBY(1) Wakeup from Standby mode
50
s
1. The wakeup times are measured from the wakeup event to the point at which the user application code reads the first instruction.
5.3.8
PLL characteristics
The parameters given in Table 27 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 27.
Symbol
PLL characteristics
Value Parameter PLL input clock(2) Min(1) 1 40 16 Typ 8.0 Max(1) 25 60 36 200 Unit MHz % MHz s
fPLL_IN fPLL_OUT tLOCK
PLL input clock duty cycle PLL multiplier output clock PLL lock time
1. Based on characterization, not tested in production. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT.
50/102
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
5.3.9
Memory characteristics
Flash memory
The characteristics are given at TA = 40 to 85 C unless otherwise specified. Table 28.
Symbol tprog tERASE t ME
Flash memory characteristics
Parameter Word programming time Page (2 KB) erase time Mass erase time Conditions TA = 40 to +85 C TA = 40 to +85 C TA = 40 to +85 C Read mode fHCLK = 36 MHz with 2 wait states, VDD = 3.3 V Write mode fHCLK = 36 MHz, VDD = 3.3 V Erase mode fHCLK = 36 MHz, VDD = 3.3 V Power-down mode / Halt, VDD = 3.0 to 3.6 V Min 40 20 20 Typ 52.5 Max(1) 70 40 40 28 Unit s ms ms mA
7
mA
IDD
Supply current
5
mA
50 2 3.6
A V
Vprog
Programming voltage
1. Guaranteed by design, not tested in production.
Table 29.
Symbol N END tRET
Flash memory endurance and data retention
Value Parameter Endurance Data retention Conditions TA = 40 C to 85 C TA = 85 C, 1 kcycle(2)
(2)
Min(1) 10 30
Unit Typ Max kcycles Years
TA = 55 C, 10 kcycle
20
1. Based on characterization, not tested in production. 2. Cycling performed over the whole temperature range.
51/102
Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
5.3.10
FSMC characteristics
Flexible static memory controller (FSMC) timings
All the timing characteristics are relative to the FSMC_CLK signal for synchronous SRAM/NOR Flash memory accesses. Figure 20. Asynchronous non-multiplexed SRAM/NOR write timings
t w(NE)
FSMC_NEx
FSMC_NOE
t v(NWE_NE) t w(NWE) t h(NE_NWE)
FSMC_NWE
tv(A_NE)
FSMC_A[25:0]
Address
t h(A_NWE)
tv(BL_NE)
FSMC_NBL[3:0]
t v(Data_NE) NBL
th(BL_NWE)
t h(Data_NWE) Data
FSMC_D[15:0]
t v(NADV_NE) t w(NADV)
FSMC_NADV(1)
ai14990
1. Modes 2/B, C and D only.
Table 30.
Asynchronous non-multiplexed SRAM/NOR write timings(1)
VDD_IO = V and CL = 15 pF
Symbol tw(NE) tv(WEN_NE) tw(NWE) th(NE_NWE) tv(A_NE) th(A_NWE) tv(BL_NE) th(BL_NWE) tv(Data_NE) th(Data_NWE) tv(NADV_NE) tw(NADV)
Parameter FSMC_NE low time FSMC_NEx low to FSMC_NWE low FSMC_NWE low time FSMC_NWE high to FSMC_NE high hold time FSMC_NEx low to FSMC_A valid Address hold time after FSMC_NWE high FSMC_NEx low to FSMC_BL valid FSMC_BL hold time after FSMC_NWE high FSMC_NEx low to Data valid Data hold time after FSMC_NWE high FSMC_NEx low to FSMC_NADV low FSMC_NADV low time
Min TBD TBD TBD TBD
Max TBD TBD TBD
Unit tCK/ns tCK/ns tCK/ns tCK/ns ns tCK/ns
TBD TBD TBD TBD TBD TBD TBD TBD
ns tCK/ns tCK/ns tCK/ns tCK/ns tCK/ns
1. TBD = to be determined.
52/102
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
Figure 21. Asynchronous non-multiplexed SRAM/NOR read timings
tw(NE)
FSMC_NE
t v(NOE_NE) t w(NOE) t h(NE_NOE)
FSMC_NOE
FSMC_NWE
tv(A_NE)
FSMC_A[25:0]
Address
t h(A_NOE)
tv(BL_NE)
FSMC_NBL[3:0]
NBL
t h(BL_NOE)
t h(Data_NE) t su(Data_NOE) t su(Data_NE) th(Data_NOE)
FSMC_D[15:0]
t v(NADV_NE) t w(NADV)
Data
FSMC_NADV(1)
ai14991
1. Modes 2/B, C and D only.
Table 31.
Asynchronous non-multiplexed SRAM/NOR read timings(1)
VDD_IO = V and CL = 15 pF
Symbol tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) th(A_NOE) tv(BL_NE) th(BL_NOE) tsu(Data_NE) tsu(Data_NOE) th(Data_NOE) th(Data_NE) tv(NADV_NE) tw(NADV)
Parameter FSMC_NE low time FSMC_NEx low to FSMC_NOE low FSMC_NOE low time FSMC_NOE high to FSMC_NE high hold time FSMC_NEx low to FSMC_A valid Address hold time after FSMC_NOE high FSMC_NEx low to FSMC_BL valid FSMC_BL hold time after FSMC_NOE high Data to FSMC_NEx high setup time Data to FSMC_NOEx high setup time Data hold time after FSMC_NOE high Data hold time after FSMC_NEx high FSMC_NEx low to FSMC_NADV low FSMC_NADV low time
Min TBD TBD TBD TBD
Max TBD TBD TBD
Unit tCK/ns tCK/ns tCK/ns tCK/ns
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
ns tCK/ns ns tCK/ns tCK/ns tCK/ns tCK/ns ns tCK/ns tCK/ns
1. TBD = to be determined.
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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Figure 22. Asynchronous multiplexed SRAM/NOR write timings
t wNE
FSMC_NEx
FSMC_NOE
t v(NWE_NE) t w(WENL) t h(NE_NWE)
FSMC_NWE
tv(A_NE)
FSMC_A[25:16]
Address
t h(A_NWE)
tv(BL_NE)
FSMC_NBL[3:0]
t v(A_NE) NBL
th(BL_NWE)
t v(Data_NL) Data
t h(Data_NW)
F S M C _ AD[15:0]
Address t v(NADV_NE) t w(NADV)
th(AD_NADV)
FSMC_NADV
tdis(AD_NADV)
ai14891
Table 32.
Asynchronous multiplexed SRAM/NOR write timings(1)
VDD_IO = V and CL = 15 pF
Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) FSMC_NE low time
Parameter
Min TBD TBD TBD TBD
Max T BD TBD TBD
Unit tCK/ns tCK/ns tCK/ns tCK/ns
FSMC_NEx low to FSMC_NWE low FSMC_NWE low time FSMC_NWE high to FSMC_NE high hold time FSMC_NEx low to FSMC_A valid FSMC_NEx low to FSMC_NADV low FSMC_NADV low time FSMC_AD (address) valid hold time after FSMC_NADV high
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD T BD
ns tCK/ns tCK/ns tCK/ns tCK/ns tCK/ns ns tCK/ns tCK/ns tCK/ns
tdis(AD_NADV) FSMC_AD (address) disable time after FSMC_NADV high th(A_NWE) tv(BL_NE) th(BL_NWE) Address hold time after FSMC_NWE high FSMC_NEx low to FSMC_BL valid FSMC_BL hold time after FSMC_NWE high
tv(Data_NADV) FSMC_NADV high to Data valid th(Data_NWE) Data hold time after FSMC_NWE high
1. TBD = to be determined.
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STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
Figure 23. Asynchronous multiplexed SRAM/NOR read timings
t w(NE)
FSMC_NE
t v(NOE_NE) t h(NE_NOE)
FSMC_NOE
t w(NOE)
FSMC_NWE
tv(A_NE)
FSMC_A[25:16]
Address
t h(A_NOE)
tv(BL_NE)
FSMC_NBL[3:0]
NBL
t h(BL_NOE)
t h(Data_NE) t su(Data_NE) t v(A_NE) tsu(Data_NOE) Data t h(Data_NOE)
F S M C _ AD[15:0]
Address t v(NADV_NE) t w(NADV)
th(AD_NADV) tdis(AD_NADV)
FSMC_NADV
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Electrical characteristics Table 33.
STM32F101xC, STM32F101xD, STM32F101xE
Asynchronous multiplexed SRAM/NOR read timings(1)
VDD_IO = V and CL = 15 pF
Symbol tw(NE) tv(NOE_NE) tw(NOE) th(NE_WEN) th(NE_NOE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) tdis(AD_NADV) th(A_NOE) th(BL_NOE) tv(BL_NE) tsu(Data_NE) tsu(Data_NOE) th(Data_NE) th(Data_NOE) FSMC_NE low time
Parameter
Mi n TBD T BD TBD TBD TBD
Max TBD TBD TBD
Unit tCK/ns tCK/ns tCK/ns tCK/ns tCK/ns
FSMC_NEx low to FSMC_NOE low FSMC_NOE low time FSMC_WEN high to FSMC_NE high hold time FSMC_NOE high to FSMC_NE high hold time FSMC_NEx low to FSMC_A valid FSMC_NEx low to FSMC_NADV low FSMC_NADV low time FSMC_AD (address) valid hold time after FSMC_NADV high FSMC_AD (address) disable time after FSMC_NADV high Address hold time after FSMC_NOE high FSMC_BL hold time after FSMC_NOE high FSMC_NEx low to FSMC_BL valid Data to FSMC_NEx high setup time Data to FSMC_NOE high setup time Data hold time after FSMC_NEx high Data hold time after FSMC_NOE high
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
ns tCK/ns tCK/ns tCK/ns tCK/ns tCK/ns tCK/ns ns tCK/ns tCK/ns ns ns
1. TBD = to be determined.
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STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
Figure 24. Synchronous multiplexed NOR/PSRAM read timings
BUSTURN = 0
tw(CLK) FSMC_CLK
tw(CLK)
Data latency = 1 td(CLKH-NExL) FSMC_NEx td(CLKH-NADVL) FSMC_NADV td(CLKH-AV) FSMC_A[24:16] td(CLKH-NWEH) FSMC_NWE td(CLKH-NOEL) FSMC_NOE td(CLKH-ADIV) td(CLKH-ADV) FSMC_AD[15:0] AD[15:0] tsu(NWAITV-CLKH) FSMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) tsu(ADV-CLKH) th(CLKH-ADV) tsu(ADV-CLKH) D1 D2 th(CLKH-NWAITV) td(CLKH-NADVH)
td(CLKH-NExH)
td(CLKH-AIV)
td(CLKH-NWEL
td(CLKH-NOEH)
th(CLKH-ADV)
ai14893
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Electrical characteristics Table 34.
STM32F101xC, STM32F101xD, STM32F101xE
Synchronous multiplexed NOR/PSRAM read timings(1)
VDD_IO = V and CL = 15 pF
Symbol tw(CLK) td(CLKH-NExL) td(CLKH-NExH) td(CLKH-NADVL) td(CLKH-NADVH) td(CLKH-AV) td(CLKH-AIV) td(CLKH-NWEL) td(CLKH-NWEH) td(CLKH-NOEL) td(CLKH-NOEH) td(CLKH-ADV) td(CLKH-ADIV) tsu(ADV-CLKH) th(CLKH-ADV) FSMC_CLK period
Parameter
Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Max TBD TBD TBD TBD TBD TBD -
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
FSMC_CLK high to FSMC_NEx low (x = 0...2) FSMC_CLK high to FSMC_NEx high (x = 0...2) FSMC_CLK high to FSMC_NADV low FSMC_CLK high to FSMC_NADV high FSMC_CLK high to FSMC_Ax valid (x = 16...25) FSMC_CLK high to FSMC_Ax invalid (x = 16...25) FSMC_CLK high to FSMC_NWE low FSMC_CLK high to FSMC_NWE high FSMC_CLK high to FSMC_NOE low FSMC_CLK high to FSMC_NOE high FSMC_CLK high to FSMC_AD[15:0] valid FSMC_CLK high to FSMC_AD[15:0] invalid FSMC_A/D[15:0] valid data before FSMC_CLK high FSMC_A/D[15:0] valid data after FSMC_CLK high
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high
1. TBD = to be determined.
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STM32F101xC, STM32F101x |
