STM32F103xC STM32F103xD STM32F103xE
High-density performance line ARM-based 32bit MCU with 256 to 512 KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces
Features
FBGA
Core: ARM 32-bit CortexTM-M3 CPU 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access Single-cycle multiplication and hardware division Memories 256 to 512 Kbytes of Flash memory up to 64 Kbytes of SRAM Flexible static memory controller with 4 Chip Select. Supports Compact Flash, SRAM, PSRAM, NOR and NAND memories LCD parallel interface, 8080/6800 modes Clock, reset and supply management 2.0 to 3.6 V application supply and I/Os POR, PDR, and programmable voltage detector (PVD) 4-to-16 MHz crystal oscillator Internal 8 MHz factory-trimmed RC Internal 40 kHz RC with calibration 32 kHz oscillator for RTC with calibration Low power Sleep, Stop and Standby modes VBAT supply for RTC and backup registers 3 × 12-bit, 1 s A/D converters (up to 21 channels) Conversion range: 0 to 3.6 V Triple-sample and hold capability Temperature sensor 2-channel 12-bit D/A converter DMA: 12-channel DMA controller Suppor ted peripherals: timers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs Debug mode Serial wire debug (SWD) & JTAG interfaces Cor tex-M3 Embedded Trace MacrocellTM
LQFP64 10 × 10 mm, LQFP100 14 × 14 mm, LQFP144 20 × 20 mm
LFBGA100 10 × 10 mm LFBGA144 10 × 10 mm
Up to 112 fast I/O ports 51/80/112 I/Os, all mappable on 16 external interrupt vectors, all 5 V-tolerant except for analog inputs Up to 11 timers Up to four 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter 2 × 16-bit, 6-channel timers with PWM output and dead-time generation 2 × watchdog timers (Independent and Window) SysTick timer: a 24-bit downcounter 2 × 16-bit basic timers to drive the DAC Up to 13 communication interfaces Up to 2 × I2C interfaces (SMBus/PMBus) Up to 5 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) Up to 3 SPIs (18 Mbit/s), 2 with I2S interface multiplexed CAN interface (2.0B Active) USB 2.0 full speed interface SDIO interface CRC calculation unit, 96-bit unique ID ECOPACK packages Device summary
Part number STM32F103RC STM32F103VC STM32F103ZC STM32F103RD STM32F103VD STM32F103ZD STM32F103RE STM32F103ZE STM32F103VE
Table 1.
Reference STM32F103xC STM32F103xD STM32F103xE
July 2008
Rev 3
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www.st.com 1
Contents
STM32F103xC, STM32F103xD, STM32F103xE
Contents
1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 4 5
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1 Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2 5.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 5.3.10 5.3.11 5.3.12 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 39 Embedded reset and power control block characteristics . . . . . . . . . . . 39 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 82
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STM32F103xC, STM32F103xD, STM32F103xE 5.3.13 5.3.14 5.3.15 5.3.16 5.3.17 5.3.18 5.3.19 5.3.20
Contents
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . . 97 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.1 6.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.2.1 6.2.2 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 113
7 8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
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List of tables
STM32F103xC, STM32F103xD, STM32F103xE
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts . . . . . 9 STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 39 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 43 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 44 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Typical current consumption in Sleep mode, code with data processing code running from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Asynchronous non-multiplexed SRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . 57 Asynchronous non-multiplexed SRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . 58 Asynchronous multiplexed SRAM/NOR write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Asynchronous multiplexed SRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 67 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Switching characteristics for CF read and write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Switching characteristics for NAND Flash read and write cycles . . . . . . . . . . . . . . . . . . . . 80 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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STM32F103xC, STM32F103xD, STM32F103xE Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69.
List of tables
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 USB: full-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 106 LFBGA100 - low profile fine pitch ball grid array package mechanical data. . . . . . . . . . . 107 LQPF100 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . 109 LQFP64 64 pin low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . 110 LFBGA144 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
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List of figures
STM32F103xC, STM32F103xD, STM32F103xE
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram . 19 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 STM32F103xC, STM32F103xD and STM32F103xE performance line LQFP144 pinout. . 21 STM32F103xC, STM32F103xD and STM32F103xE performance line LQFP100 pinout. . 22 STM32F103xC, STM32F103xD and STM32F103xE performance line LQFP64 pinout. . . 23 STM32F103xC, STM32F103xD and STM32F103xE performance line BGA100 ballout . . 24 STM32F103xC, STM32F103xD and STM32F103xE performance line BGA144 ballout . . 25 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 42 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 42 Current consumption in Stop mode with regulator in main mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Current consumption in Standby mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Typical application with a 8-MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Asynchronous non-multiplexed SRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . 57 Asynchronous non-multiplexed SRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . 58 Asynchronous multiplexed SRAM/NOR write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Asynchronous multiplexed SRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 66 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 PC-card controller timing for common memory read access . . . . . . . . . . . . . . . . . . . . . . . 70 PC-card controller timing for common memory write access . . . . . . . . . . . . . . . . . . . . . . . 71 PC-card controller timing for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . 72 PC-card controller timing for attribute memory write access . . . . . . . . . . . . . . . . . . . . . . . 73 PC-card controller timing for I/O space read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 PC-card controller timing for I/O space write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 NAND controller timing for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 NAND controller timing for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 NAND controller timing for common memory read access . . . . . . . . . . . . . . . . . . . . . . . . . 79 NAND controller timing for common memory write access. . . . . . . . . . . . . . . . . . . . . . . . . 79 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
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STM32F103xC, STM32F103xD, STM32F103xE Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64.
List of figures
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 I2S slave timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 I2S master timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 101 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 102 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 LFBGA100 - low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . 107 Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . 108 LQFP100, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . 109 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 LQFP64 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 LFBGA144 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
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Introduction
STM32F103xC, STM32F103xD, STM32F103xE
1
Introduction
This datasheet provides the ordering information and mechanical device characteristics of the STM32F103xC, STM32F103xD and STM32F103xE High-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family, please refer to Section 2.2: Full compatibility throughout the family. The High-density STM32F103xx datasheet should be read in conjunction with the Mediumand High-density STM32F10xxx reference manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the CortexTM-M3 core please refer to the CortexTM-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.
2
Description
The STM32F103xC, STM32F103xD and STM32F103xE performance line family incorporates the high-performance ARM CortexTM-M3 32-bit RISC core operating at a 72 MHz frequency, high-speed embedded memories (Flash memory up to 512 Kbytes and SRAM up to 64 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer three 12-bit ADCs, four general purpose 16bit timers plus two PWM timer, as well as standard and advanced communication interfaces: up to two I2Cs, three SPIs, two I2Ss, one SDIO, five USARTs, an USB and a CAN. The STM32F103xx High-density performance line family operates in the - 0 to +105 C 4 temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F103xx High-density performance line family offers devices in 5 different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the STM32F103xx High-density performance line microcontroller family suitable for a wide range of applications:
Motor drive and application control Medical and handheld equipment PC peripherals gaming and GPS platforms Industrial applications: PLC, inverters, printers, and scanners Alarm systems, Video intercom, and HVAC
Figure 1 shows the general block diagram of the device family.
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Description
2.1
Device overview
Table 2. STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts
STM32F103Rx 256 48 No Generalpurpose Timers Advancedcontrol Basic SPI(I2S)(1) I2C USART Comm USB CAN SDIO GPIOs 12-bit ADC Number of channels 12-bit DAC Number of channels CPU frequency Operating voltage Operating temperatures Package 51 3 16 1 1 1 80 3 16 1 2 72 MHz 2.0 to 3.6 V Ambient temperatures: 40 to +85 C /40 to +105 C (see Table 9) Junction temperature: 40 to + 125 C (see Table 9) LQFP64 LQFP100(2), BGA100 LQFP144, BGA144 112 3 21 384 64 512 STM32F103Vx 256 48 Yes 4 2 2 3(2) 2 5 384 64 512 STM32F103Zx 256 48 Yes 384 64 512
Peripherals Flash memory in Kbytes SRAM in Kbytes FSMC
1. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. 2. For the LQFP100 and BGA100 packages, only FSMC Bank1 and Bank2 are available. Bank1 can only support a multiplexed NOR Flash memory using the NE1 Chip Select. Bank2 can only support a 16- or 8bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package.
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Description
STM32F103xC, STM32F103xD, STM32F103xE
2.2
Full compatibility throughout the family
The STM32F103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x6, STM32F103x8 and STM32F103xB are referred to as Medium-density devices, while the STM32F103xC, STM32F103xD and STM32F103xE are referred to as High-density devices. High-density devices are an extension of the Medium-density STM32F103x6/8/B/C devices specified in the STM32F103xx datasheet. High-density STM32F103xx devices feature higher Flash memory and RAM capacities, and additional peripherals like SDIO, FSMC, I2S and DAC, while remaining fully compatible with the other members of the family. The STM32F103xC, STM32F103xD and STM32F103xE are a drop-in replacement for the STM32F103x6/8/B devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. Table 3. STM32F103xx family
Memory size Medium-density STM32F103xx devices Pinout 32 KB Flash 10 KB RAM 144 100 64 48 36 2 × USARTs 2 × 16-bit timers 1 × SPI, 1 × I2C, USB, CAN, 1 × PWM timer 2 × ADCs 3 × USARTs 3 × 16-bit timers 2 × SPIs, 2 × I2Cs, USB, CAN, 1 × PWM timer 2 × ADCs 64 KB Flash 20 KB RAM 128 KB Flash 20 KB RAM High-density STM32F103xx devices 256 KB Flash 48 KB RAM 384 KB Flash 64 KB RAM 512 KB Flash 64 KB RAM
5 × USARTs 4 × 16-bit timers, 2 × basic timers 3 × SPIs, 2 × I2Ss, 2 × I2Cs USB, CAN, 2 × PWM timers 3 × ADCs, 1 × DAC, 1 × SDIO FSMC (100- and 144-pin packages(1))
1. Ports F and G are not available in devices delivered in 100-pin packages.
2.3
Overview
ARM CortexTM-M3 core with embedded Flash and SRAM
The ARM CortexTM-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM CortexTM-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. With its embedded ARM core, STM32F103xC, STM32F103xD and STM32F103xE performance line family is compatible with all ARM tools and software. Figure 1 shows the general block diagram of the device family.
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STM32F103xC, STM32F103xD, STM32F103xE
Description
Embedded Flash memory
Up to 512 Kbytes of embedded Flash is available for storing programs and data.
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
Embedded SRAM
Up to 64 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.
FSMC (flexible static memory controller)
The FSMC is embedded in the STM32F103xC, STM32F103xD and STM32F103xE performance line family. It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash, RAM, PSRAM, NOR and NAND. Functionality overview:
The three FSMC interrupt lines are ORed in order to be connected to the NVIC Write FIFO Code execution from external memory except for NAND Flash and PC Card The targeted frequency is HCLK/2, so external access is at 36 MHz when HCLK is at 72 MHz and external access is at 24 MHz when HCLK is at 48 MHz
LCD parallel interface
The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration.
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Description
STM32F103xC, STM32F103xD, STM32F103xE
Nested vectored interrupt controller (NVIC)
The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds a nested vectored interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16 interrupt lines of CortexTM-M3) and 16 priority levels.
Closely coupled NVIC gives low latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving higher priority interrupts Suppor t for tail-chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt latency.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected to the 16 external interrupt lines.
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator). Several prescalers allow the configuration of the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 MHz. The maximum allowed frequency of the low speed APB domain is 36 MHz. See Figure 2 for details on the clock tree.
Boot modes
At startup, boot pins are used to select one of three boot options:
Boot from User Flash Boot from System Memory Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1.
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STM32F103xC, STM32F103xD, STM32F103xE
Description
Power supply schemes
VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.
For more details on how to connect power pins, refer to Figure 11: Power supply scheme.
Power supply supervisor
The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table 11: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD.
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
MR is used in the nominal regulation mode (Run) LPR is used in the Stop modes. Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode.
Low-power modes
The STM32F103xC, STM32F103xD and STM32F103xE performance line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:
Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
Stop mode Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
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Description
STM32F103xC, STM32F103xD, STM32F103xE source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB wakeup.
Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode.
DMA
The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-toperipheral transfers. The two DMA controllers support circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose, basic and advanced control timers TIMx, DAC, I2S, SDIO and ADC.
RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are forty-two 16-bit registers used to store 84 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, and they are not reset when the device wakes up from the Standby mode. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.
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STM32F103xC, STM32F103xD, STM32F103xE
Description
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:
A 24-bit down counter Autoreload capability Maskable system interrupt generation when the counter reaches 0. Programmable clock source
General-purpose timers (TIMx)
There are up to 4 synchronizable standard timers (TIM2, TIM3, TIM4 and TIM5) embedded in the STM32F103xC, STM32F103xD and STM32F103xE performance line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or one pulse mode output. This gives up to 16 input captures / output compares / PWMs on the largest packages. They can work together with the Advanced Control timer via the Timer Link feature for synchronization or event chaining. The counter can be frozen in debug mode. Any of the standard timers can be used to generate PWM outputs. Each of the timers has independent DMA request generations.
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base.
Advanced control timers (TIM1 and TIM8)
The two advanced control timers (TIM1 and TIM8) can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead-times. They can also be seen as a complete general-purpose timer. The 4 independent channels can be used for
Input Capture Output Compare PWM generation (edge or center-aligned modes) One-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%). The counter can be frozen in debug mode. Many features are shared with those of the standard TIM timers which have the same architecture. The advanced control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining.
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Description
STM32F103xC, STM32F103xD, STM32F103xE
I²C bus
Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes. They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus.
Universal synchronous/asynchronous receiver transmitters (USARTs)
The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4 and UART5). These five interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 interface is able to communicate at speeds of up to 4.5 Mbit/s. The other available interfaces communicate at up to 2.25 Mbit/s. USART1, USART2 and USART3 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller except for UART5.
Serial peripheral interface (SPI)
Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller.
Inter-integrated sound (I2S)
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available, that can be operated in master or slave mode. These interfaces can be configured to operate with 16/32 bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to 48 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency.
SD IO
An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with SD Memory Card Specifications Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. In addition to SD/SDIO/MMC, this interface is also fully compliant with the CE-ATA digital protocol Rev1.1.
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STM32F103xC, STM32F103xD, STM32F103xE
Description
Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks.
Universal serial bus (USB)
The STM32F103xC, STM32F103xD and STM32F103xE performance line embed a USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator).
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable except for analog inputs. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. I/Os on APB2 with up to 18 MHz toggling speed
ADC (analog to digital converter)
Three 12-bit analog-to-digital converters are embedded into STM32F103xC, STM32F103xD and STM32F103xE performance line devices and each ADC shares up to 21 external channels, performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow:
Simultaneous sample and hold Interleaved sample and hold Single shunt
The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the standard timers (TIMx) and the advanced-control timers (TIM1 and TIM8) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers.
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Description
STM32F103xC, STM32F103xD, STM32F103xE
DAC (digital-to-analog converter)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. This dual digital Interface supports the following features:
two DAC converters: one for each output channel 8-bit or 12-bit monotonic output left or right data alignment in 12-bit mode synchronized update capability noise-wave generation triangular-wave generation dual DAC channel independent or simultaneous conversions DMA capability for each channel external triggers for conversion input voltage reference VREF+
Eight DAC trigger inputs are used in the STM32F103xC, STM32F103xD and STM32F103xE performance line family. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels.
Temperature sensor
The temperature sensor has to generate a linear voltage with any variation in temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value.
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
Embedded Trace MacrocellTM
The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F10xxx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools.
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STM32F103xC, STM32F103xD, STM32F103xE Figure 1.
Description
STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram
TRACECLK TRACED[0:3] as AS JNTRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO as AF
TPIU SW/JTAG Trace/trig Pbus Ibus Cortex-M3 CPU Fmax: 48/72 MHz Dbus System NVIC Bus Matri x POR Reset Int Trace controller Flash obl interface Flash 512 Kbytes 64 bit VDD
@VDD Power Volt. reg. 3.3 V to 1.8 V @VDDA Supply supervision POR /PDR PVD @VDD XTAL OSC 4-16 MHz IWDG Standby interface @VBAT XTAL32kHz RTC Backup reg AWU Backup interface AHB2 APB1 TIM2 TIM3 APB1: Fmax = 24/36 MHz TIM4 TIM5 USART 2 USART 3 UART4 UART5 S xI )6 I2S2 2x(8Pit2 /b 1 SPiI3 / 2x(8x16b I2S3 t) I2C1 SRAM 512 B WWDG I2C2 bxCAN device USB 2.0 FS device TIM6 IF 12 bit DAC @VDDA USBDP/CANTX USBDM/CANRX VBAT =1.8 V to 3.6 V OSC32_IN OSC32_OUT TAMPER-RTC/ ALARM/SECOND OUT
VSS
SRAM 64 KB
@V DA D RC 8 MHz RC 40 kHz PLL PCLK1 PCLK2 HCLK FCLK
NRST VDDA VSSA
GP DMA2 5 channels
AHB: Fmax = 48/72 MHz
A[25:0] D[15:0] CLK NOE NWE NE[4:1] NBL[1:0] NWAIT NL (or NADV) as AF D[7:0] CMD CK as AF
GP DMA1 7 channels
OSC_IN OSC_OUT
FSMC
Reset & Clock control
SDIO AHB2 APB2 EXT.IT WKUP GPIO port A GPIO port B GPIO port C GPIO port D GPIO port E GPIO port F GPIO port G TIM1 TIM8 SPI1 USART1 Temp. sensor APB2: Fmax = 48/72 MHz
4 channels, ETR as AF 4 channels, ETR as AF 4 channels, ETR as AF 4 channels as AF RX, TX CTS, RTS, , CK as AF RX, TX, CTS, RTS, CK as AF RX,TX as AF RX, TX as AF MOSI/SD, MISO SCK/CK, MCK, NSS/WS as AF MOSI/SD, MISO SCK/CK, MCK, NSS/WS as AF SCL, SDA, SMBAL as AF SCL, SDA, SMBAL as AF
112AF PA[15:0] PB[15:0] PC[15:0] PD[15:0] PE[15:0] PF[15:0] PG[15:0] 4 channels 3 compl. channels BKIN as AF 4 channels 3 compl. channels BKIN as AF MOSI, MISO, SCK, NSS as AF RX, TX, CTS, RTS, CK as AF
8 ADC123_INs common to the 3 ADCs 8 ADC12_INs common to ADC1 & ADC2 5 ADC3_INs on ADC3 VREF VREF+
12-bit ADC1 IF 12-bit ADC2 IF 12-bit ADC3 IF @ VDDA TIM7
DAC_OUT1 as AF DAC_OUT2 as AF VREF+
ai14666d
1. TA = 40 C to +85 C (suffix 6, see Table 69) or 40 C to +105 C (suffix 7, see Table 69), junction temperature up to 105 C or 125 C, respectively. 2. AF = alternate function on I/O port pin.
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Description Figure 2. Clock tree
STM32F103xC, STM32F103xD, STM32F103xE
USB Prescaler /1, 1.5
48 MHz
USBCLK to USB interface
I2S3CLK Peripheral clock enable
to I2S3
I2S2CLK
to I2S2 SDIOCLK FSMCCLK to SDIO to FSMC
8 MHz HSI RC
HSI
Peripheral clock enable Peripheral clock enable
/2
Peripheral clock enable 72 MHz max Clock Enable (4 bits)
HCLK to AHB bus, core, memory and DMA to Cortex System timer FCLK Cortex free running clock PCLK1 to APB1 peripherals Peripheral Clock
Enable (20 bits)
PLLSRC
PLLMUL ..., x16 x2, x3, x4 PLL
HSI PLLCLK HSE
SW
SYSCLK
/8
72 MHz /1, 2..512 max
AHB Prescaler
APB1 Prescaler /1, 2, 4, 8, 16
36 MHz max
CSS
TIM2,3,4,5,6,7 If (APB1 prescaler =1) x1 else x2
to TIM2,3,4,5,6 and 7 TIMXCLK
Peripheral Clock Enable (6 bits)
PLLXTPRE OSC_OUT OSC_IN 4-16 MHz HSE OSC /2
APB2 Prescaler /1, 2, 4, 8, 16
72 MHz max Peripheral Clock Enable (15 bits)
PCLK2 peripherals to APB2
TIM1 & 8 timers If (APB2 prescaler =1) x1 else x2
to TIM1 and TIM8 TIMxCLK
Peripheral Clock Enable (2 bit) to ADC1, 2 or 3
/128 OSC32_IN OSC32_OUT LSE OSC 32.768 kHz
LSE to RTC
RTCCLK RTCSEL[1:0]
ADC Prescaler /2, 4, 6, 8
/2
ADCCLK
HCLK/2
LSI RC 40 kHz
LSI
to Independent Watchdog (IWDG)
To SDIO AHB interface Peripheral clock enable
IWDGCLK
Main Clock Output
/2
PLLCLK HSI HSE SYSCLK
Legend: HSE = High Speed External clock signal HSI = High Speed Internal clock signal LSI = Low Speed Internal clock signal LSE = Low Speed External clock signal ai14752b
MCO
MCO
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz. 2. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either 48 MHz or 72 MHz. 3. To have an ADC conversion time of 1 s, APB2 must be at 14 MHz, 28 MHz or 56 MHz.
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STM32F103xC, STM32F103xD, STM32F103xE
Pin descriptions
3
Figure 3.
Pin descriptions
STM32F103xC, STM32F103xD and STM32F103xE performance line LQFP144 pinout
VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD_11 VSS_11 PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD_10 VSS_10 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14
PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PF0 PF1 PF2 PF3 PF4 PF5 VSS_5 VDD_5 PF6 PF7 PF8 PF9 PF10 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-W KUP PA1 PA2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
LQFP144
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
VDD_2 VSS_2 NC PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDD_9 VSS_9 PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD_8 VSS_8 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12
PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12
VDD_6 PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS_7 VDD_7 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1
VSS_6
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
ai14667
21/118
Pin descriptions Figure 4.
STM32F103xC, STM32F103xD, STM32F103xE STM32F103xC, STM32F103xD and STM32F103xE performance line LQFP100 pinout
VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14
PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP PA1 PA2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
LQFP100
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VDD_2 VSS_2 NC PA 13 PA 12 PA 11 PA 10 PA 9 PA 8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12
PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
ai14391
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STM32F103xC, STM32F103xD, STM32F103xE Figure 5.
Pin descriptions
STM32F103xC, STM32F103xD and STM32F103xE performance line LQFP64 pinout
VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14
VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0 OSC_IN PD1 OSC_OUT NRST PC0 PC1 PC2 PC3 V SSA V DDA PA0-WKUP PA1 PA2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12
PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1
ai14392
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Pin descriptions Figure 6.
1
STM32F103xC, STM32F103xD, STM32F103xE
STM32F103xC, STM32F103xD and STM32F103xE performance line BGA100 ballout
2 3 4 5 6 7 8 9 10
A
PC14PC13OSC32_IN TAMPER-RTC PE2
PB9
PB7
PB4
PB3
PA15
PA14
APA13
B
PC15OSC32_OUT
VBAT
PE3
PB8
PB6
PD5
PD2
PC11
PC10
PA12
C
OSC_IN
VSS_5
PE4
PE1
PB5
PD6
PD3
PC12
PA9
PA11
D
OSC_OUT
VDD_5
PE5
PE0
BOOT0
PD7
PD4
PD0
PA8
PA10
E
NRST
PCD
PE6
VSS_4
VSS_3
VSS_2
VSS_1
PD1
PC9
PC7
F
PC0
PC1
PC3
VDD_4
VDD_3
VDD_2
VDD_1
NC
PC8
PC6
G
VSSA
PA0-WKUP
PA4
PC4
PB2
PE10
PE14
PB15
PD11
PD15
H
VREF
PA1
PA5
PC5
PE7
PE11
PE15
PB14
PD10
PD14
J
VREF+
PA2
PA6
PB0
PE8
PE12
PB10
PB13
PD9
PD13
K
VDDA
PA3
PA7
PB1
PE9
PE13
PB11
PB12
PD8
PD12
AI16001
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STM32F103xC, STM32F103xD, STM32F103xE Figure 7.
1
Pin descriptions
STM32F103xC, STM32F103xD and STM32F103xE performance line BGA144 ballout
2 3 4 5 6 7 8 9 10 11 12
A
PC13TAMPER-RTC
PE3
PE2
PE1
PE0
PB4 JTRST
PB3 JTDO
PD6
PD7
PA15 JTDI
PA14 JTCK
PA13 JTMS
B
PC14OSC32_IN
PE4
PE5
PE6
PB9
PB5
PG15
PG12
PD5
PC11
PC10
PA12
C
PC15OSC32_OUT
VBAT
PF0
PF1
PB8
PB6
PG14
PG11
PD4
PC12
NC
PA11
D
OSC_IN
VSS_5
VDD_5
PF2
BOOT0
PB7
PG13
PG10
PD3
PD1
PA10
PA9
E
OSC_OUT
PF3
PF4
PF5
VSS_3
VSS_11
VSS_10
PG9
PD2
PD0
PC9
PA8
F
NRST
PF7
PF6
VDD_4
VDD_3
VDD_11
VDD_10
VDD_8
VDD_2
VDD_9
PC8
PC7
G
PF10
PF9
PF8
VSS_4
VDD_6
VDD_7
VDD_1
VSS_8
VSS_2
VSS_9
PG8
PC6
H
PC0
PC1
PC2
PC3
VSS_6
VSS_7
VSS_1
PE11
PD11
PG7
PG6
PG5
J
VSSA
PA0-WKUP
PA4
PC4
PB2/ BOOT1
PG1
PE10
PE12
PD10
PG4
PG3
PG2
K
VREF
PA1
PA5
PC5
PF13
PG0
PE9
PE13
PD9
PD13
PD14
PD15
L
VREF+
PA2
PA6
PB0
PF12
PF15
PE8
PE14
PD8
PD12
PB14
PB15
M
VDDA
PA3
PA7
PB1
PF11
PF14
PE7
PE15
PB10
PB11
PB12
PB13
AI14789b
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Pin descriptions Table 4. Pin definitions
Pins LQFP100 LQFP144 BGA144 BGA100 LQFP64 Pin name Type(1) I / O Level(2)
STM32F103xC, STM32F103xD, STM32F103xE
Alternate functions Main function(3) (after reset) PE2 PE3 PE4 PE5 PE6 VBAT PC13(5) PC14(5) PC15(5) PF0 PF1 PF2 PF3 PF4 PF5 VSS_5 VDD_5 PF6 PF7 PF8 PF9 PF10 OSC_IN OSC_OUT NRST PC0 PC1 PC2 ADC123_IN10 ADC123_IN11 ADC123_IN12 ADC3_IN4/ FSMC_NIORD ADC3_IN5/ FSMC_NREG ADC3_IN6/ FSMC_NIOWR ADC3_IN7/ FSMC_CD ADC3_IN8/ FSMC_INTR TAMPER-RTC OSC32_IN OSC32_OUT FSMC_A0 FSMC_A1 FSMC_A2 FSMC_A3 FSMC_A4 FSMC_A5
Default TRACECK/ FSMC_A23 TRACED0/FSMC_A19 TRACED1/FSMC_A20 TRACED2/FSMC_A21 TRACED3/FSMC_A22
Remap
A3 A2 B2 B3 B4 C2 A1 B1 C1 C3 C4 D4 E2 E3 E4 D2 D3 F3 F2 G3 G2 G1 D1 E1 F1 H1 H2 H3
A3 B3 C3 D3 E3 B2 A2 A1 B1 C2 D2 C1 D1 E1 F1 F2
1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPERRTC(4)
I/O I/O I/O I/O I/O S I/O
FT FT FT FT FT
PC14-OSC32_IN(4) I/O PC15OSC32_OUT(4) PF0 PF1 PF2 PF3 PF4 PF5 VSS_5 VDD_5 PF6 PF7 PF8 PF9 PF10 OSC_IN OSC_OUT NRST PC0 PC1 PC2 I/O I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O I/O I/O I/O I/O I O I/O I/O I/O I/O
E2 10
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STM32F103xC, STM32F103xD, STM32F103xE Table 4. Pin definitions (continued)
Pins LQFP100 LQFP144 BGA144 BGA100 LQFP64 Pin name Type(1) I / O Level(2)
Pin descriptions
Alternate functions Main function(3) (after reset) PC3 VSSA VREFVREF+ VDDA WKUP/USART2_CTS(6) ADC123_IN0 TIM2_CH1_ETR TIM5_CH1/TIM8_ETR USART2_RTS(6) ADC123_IN1/TIM5_CH2 TIM2_CH2(6) USART2_TX(6)/ TIM5_CH3/ADC123_IN2/ TIM2_CH3 (6) USART2_RX(6)/ TIM5_CH4/ADC123_IN3 TIM2_CH4(6)
Default ADC123_IN13
Remap
H4 J1 K1 L1 M1
F3 11 G1 12 H1 J1 -
18 19 20 21 22
29 30 31 32 33
PC3 VSSA VREFVREF+ VDDA
I/O S S S S
K1 13
J2
G2 14
23
34
PA0-WKUP
I/O
PA0
K2
H2 15
24
35
PA1
I/O
PA1
L2
J2
16
25
36
PA2
I/O
PA2
M2 G4 F4 J3
K2 17 E4 18 F4 19 G3 20
26 27 28 29
37 38 39 40
PA3 VSS_4 VDD_4 PA4
I/O S S I/O
PA3 VSS_4 VDD_4 PA4
SPI1_NSS(6)/DAC_OUT1 USART2_CK(6) ADC12_IN4 SPI1_SCK(6) DAC_OUT2 ADC12_IN5 SPI1_MISO(6) TIM8_BKIN/ADC12_IN6 TIM3_CH1(6) SPI1_MOSI(6) TIM8_CH1N/ADC12_IN7 TIM3_CH2(6) ADC12_IN14 ADC12_IN15 ADC12_IN8/TIM3_CH3 TIM8_CH2N ADC12_IN9 TIM3_CH4(6) TIM8_CH3N TIM1_CH2N TIM1_BKIN
K3
H3 21
30
41
PA5
I/O
PA5
L3
J3
22
31
42
PA6
I/O
PA6
M3 J4 K4 L4
K3 23 G4 24 H4 25 J4 26
32 33 34 35
43 44 45 46
PA7 PC4 PC5 PB0
I/O I/O I/O I/O
PA7 PC4 PC5 PB0
TIM1_CH1N
M4 J5
K4 27 G5 28
36 37
47 48
PB1 PB2/BOOT1
I/O I/O FT
PB1 PB2/BOOT1
TIM1_CH3N
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Pin descriptions Table 4. Pin definitions (continued)
Pins LQFP100 LQFP144 BGA144 BGA100 LQFP64 Pin name Type(1) I / O Level(2)
STM32F103xC, STM32F103xD, STM32F103xE
Alternate functions Main function(3) (after reset)
Default FSMC_NIOS16 FSMC_A6
Remap
M5 L5 H5 G5 K5 M6 L6 K6 J6 M7 L7 K7 H6 G6 J7 H8 J8 K8 L8 M8 M9
H5 J5 K5 G6 H6 J6 K6 G7 H7 J7
29
38 39 40 41 42 43 44 45 46 47 48 49 50
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PF11 PF12 VSS_6 VDD_6 PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS_7 VDD_7 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1
I/O I/O S S I/O I/O I/O I/O I/O I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 PE7 PE8 PE9
FSMC_A7 FSMC_A8 FSMC_A9 FSMC_A10 FSMC_A11 FSMC_D4 FSMC_D5 FSMC_D6 TIM1_ETR TIM1_CH1N TIM1_CH1
FSMC_D7 FSMC_D8 FSMC_D9 FSMC_D10 FSMC_D11 FSMC_D12 I2C2_SCL USART3_TX(6) I2C2_SDA USART3_RX(6)
TIM1_CH2N TIM1_CH2 TIM1_CH3N TIM1_CH3 TIM1_CH4 TIM1_BKIN TIM2_CH3 TIM2_CH4
M10 K7 30 H7 G7 E7 31 F7 32
M11 K8 33
51
73
PB12
I/O FT
PB12
SPI2_NSS/I2S2_WS/ I2C2_SMBAl/ USART3_CK(6)/ TIM1_BKIN(6) SPI2_SCK/I2S2_CK USART3_CTS(6)/ TIM1_CH1N SPI2_MISO/TIM1_CH2N USART3_RTS(6)
M12 J8
34
52
74
PB13
I/O FT
PB13
L11 H8 35
53
75
PB14
I/O FT
PB14
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STM32F103xC, STM32F103xD, STM32F103xE Table 4. Pin definitions (continued)
Pins LQFP100 LQFP144 BGA144 BGA100 LQFP64 Pin name Type(1) I / O Level(2)
Pin descriptions
Alternate functions Main function(3) (after reset)
Default SPI2_MOSI/I2S2_SD TIM1_CH3N(6) FSMC_D13 FSMC_D14 FSMC_D15 FSMC_A16 FSMC_A17 FSMC_A18
Remap
L12 G8 36 L9 K9 J9 H9 K9 J9 H9 G9 -
54 55 56 57 58 59 60 61 62 63 64 65 66
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
PB15 PD8 PD9 PD10 PD11 PD12 PD13 VSS_8 VDD_8 PD14 PD15 PG2 PG3 PG4 PG5 PG6 PG7 PG8 VSS_9 VDD_9 PC6 PC7 PC8 PC9 PA8 PA9 PA10
I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT
PB15 PD8 PD9 PD10 PD11 PD12 PD13
USART3_TX USART3_RX USART3_CK USART3_CTS TIM4_CH1 / USART3_RTS TIM4_CH2
L10 K10 K10 J10 G8 F8 -
K11 H10 K12 G10 J12 J11 J10 H12 H11 H10 G11 G10 F10 -
PD14 PD15
FSMC_D0 FSMC_D1 FSMC_A12 FSMC_A13 FSMC_A14 FSMC_A15 FSMC_INT2 FSMC_INT3
TIM4_CH3 TIM4_CH4
G12 F10 37 F12 E10 38 F11 F9 39 E11 E9 40 E12 D9 41 D12 C9 42 D11 D10 43
PC6 PC7 PC8 PC9 PA8 PA9 PA10
I2S2_MCK/ TIM8_CH1/SDIO_D6 I2S3_MCK/ TIM8_CH2/SDIO_D7 TIM8_CH3/SDIO_D0 TIM8_CH4/SDIO_D1 USART1_CK/ TIM1_CH1(6)/MCO USART1_TX(6)/ TIM1_CH2(6) USART1_RX(6)/ TIM1_CH3(6)
TIM3_CH1 TIM3_CH2 TIM3_CH3 TIM3_CH4
67 100 68 101 69 102
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Pin descriptions Table 4. Pin definitions (continued)
Pins LQFP100 LQFP144 BGA144 BGA100 LQFP64 Pin name Type(1) I / O Level(2)
STM32F103xC, STM32F103xD, STM32F103xE
Alternate functions Main function(3) (after reset)
Default USART1_CTS/CANRX TIM1_CH4(6)/USBDM USART1_RTS/USBDP/ CANTX(6)/TIM1_ETR(6) PA13
Remap
C12 C10 44 B12 B10 45 A12 A10 46 C11 F8 G9 F9 -
70 103 71 104
PA11 PA12
I/O FT I/O FT
PA11 PA12
72 105 PA13/JTMS-SWDIO I/O FT JTMS-SWDIO 73 106 74 107 75 108 VSS_2 VDD_2 S S Not connected VSS_2 VDD_2
E6 47 F6 48
A11 A9 49 A10 A8 50 B11 B9 51 B10 B8 52 C10 C8 53 E10 D8 D10 E8 E9 D9 C9 B9 E7 F7 A8 A9 E8 D8 C8 B8 D7 C7 E6 5 6
76 109 PA14/JTCK-SWCLK I/O FT JTCK-SWCLK 77 110 78 111 79 112 80 113 81 114 82 115 83 116 84 117 85 118 86 119 120 121 PA15/JTDI PC10 PC11 PC12 PD0 PD1 PD2 PD3 PD4 PD5 VSS_10 VDD_10 PD6 PD7 PG9 PG10 PG11 PG12 PG13 PG14 VSS_11 I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S PD6 PD7 JTDI PC10 PC11 PC12 OSC_IN(7) OSC_OUT(7) PD2 PD3 PD4 PD5
PA14 PA15/SPI3_NSS/ I2S3_WS UART4_TX/SDIO_D2 UART4_RX/SDIO_D3 UART5_TX/SDIO_CK FSMC_D2 FSMC_D3 TIM3_ETR/UART5_RX SDIO_CMD FSMC_CLK FSMC_NOE FSMC_NWE USART2_CTS USART2_RTS USART2_TX TIM2_CH1_ETR SPI1_NSS USART3_TX USART3_RX USART3_CK CANRX CANTX
B7 54 C7 D7 B6 C6 D6 -
87 122 88 123 124 125 126 127 128 129 130
FSMC_NWAIT FSMC_NE1/ FSMC_NCE2 FSMC_NE2/ FSMC_NCE3 FSMC_NCE4_1/ FSMC_NE3 FSMC_NCE4_2 FSMC_NE4 FSMC_A24 FSMC_A25
USART2_RX USART2_CK
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STM32F103xC, STM32F103xD, STM32F103xE Table 4. Pin definitions (continued)
Pins LQFP100 LQFP144 BGA144 BGA100 LQFP64 Pin name Type(1) I / O Level(2)
Pin descriptions
Alternate functions Main function(3) (after reset)
Default
Remap
F6 B7 A7
-
-
-
131 132
VDD_11 PG15 PB3/JTDO
S I/O I/O FT JTDO PB3/TRACESWO JTDO SPI3_SCK/I2S3_CK/ PB4/SPI3_MISO I2C1_SMBAl/ SPI3_MOSI/I2S3_SD I2C1_SCL(6)/ TIM4_CH1(6) I2C1_SDA(6)/ FSMC_NADV/ TIM4_CH2(6) TIM2_CH2 / SPI1_SCK TIM3_CH1 / SPI1_MISO TIM3_CH2 / SPI1_MOSI USART1_TX
A7 55
89 133
A6 B6 C6
A6 56 C5 57 B5 58
90 134 91 135 92 136
PB4/JNTRST PB5 PB6
I/O FT I/O I/O FT
JNTRST PB5 PB6
D6 D5 C5 B5 A5 A4 E5 F5
A5 59 D5 60 B4 61 A4 62 D4 C4 -
93 137 94 138 95 139 96 140 97 141 98 142 99 143
PB7 BOOT0 PB8 PB9 PE0 PE1 VSS_3 VDD_3
I/O FT I I/O FT I/O FT I/O FT I/O FT S S
PB7 BOOT0 PB8 PB9 PE0 PE1 VSS_3 VDD_3
USART1_RX
TIM4_CH3(6)/SDIO_D4 TIM4_CH4(6)/SDIO_D5 TIM4_ETR FSMC_NBL0 FSMC_NBL1
I2C1_SCL/ CANRX I2C1_SDA / CANTX
E5 63
F5 64 100 144
1. I = input, O = output, S = supply, HiZ = high impedance. 2. FT = 5 V tolerant. 3. Function availability depends on the chosen device. 4. PC13, PC14 and PC15 are supplied through the power switch, and so their use in output mode is limited: they can be used only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time. 5. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 6. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 7. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100/BGA100 and LQFP144/BGA144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.
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Pin descriptions Table 5.
Pins CF PE2 PE3 PE4 PE5 PE6 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PF8 PF9 PF10 PF11 PF12 PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PD8 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 A0 A1 A2 A3 A4 A5 NIORD NREG NIOWR CD INTR NIOS16 A6 A7 A8 A9 A10 NIORD NREG NIOWR CD INTR NIOS16 A6 A7 A8 A9 A10 A11 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 A0 A1 A2 CF/IDE
STM32F103xC, STM32F103xD, STM32F103xE FSMC pin definition
FSMC NOR/PSRAM NOR/SRAM Mux NAND 16 bit A23 A19 A20 A21 A22 A0 A1 A2 A3 A4 A5 A23 A19 A20 A21 A22 LQFP100 BGA100(1) Yes Yes Yes Yes Yes DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 DA13 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
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STM32F103xC, STM32F103xD, STM32F103xE Table 5.
Pins CF PD9 PD10 PD11 PD12 PD13 PD14 PD15 PG2 PG3 PG4 PG5 PG6 PG7 PD0 PD1 PD3 PD4 PD5 PD6 PD7 PG9 PG10 PG11 PG12 PG13 PG14 PB7 PE0 PE1 NCE4_1 NCE4_2 NCE4_1 NCE4_2 NE4 A24 A25 NADV NBL0 NBL1 NE4 A24 A25 NADV NBL0 NBL1 NOE NWE NWAIT NOE NWE NWAIT D2 D3 D2 D3 D2 D3 CLK NOE NWE NWAIT NE1 NE2 NE3 DA2 DA3 CLK NOE NWE NWAIT NE1 NE2 NE3 D0 D1 D0 D1 D14 D15 CF/IDE D14 D15
Pin descriptions
FSMC pin definition (continued)
FSMC NOR/PSRAM NOR/SRAM Mux NAND 16 bit D14 D15 A16 A17 A18 D0 D1 A12 A13 A14 A15 I NT2 I NT3 D2 D3 DA14 DA15 A16 A17 A18 DA0 DA1 D0 D1 D14 D15 CLE ALE LQFP100 BGA100(1) Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes NOE NWE NWAIT NCE2 NCE3 Yes Yes Yes Yes Yes Yes Yes Yes
1. Ports F and G are not available in devices delivered in 100-pin packages.
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Memory mapping
STM32F103xC, STM32F103xD, STM32F103xE
4
Memory mapping
The memory map is shown in Figure 8. Figure 8. Memory map
Reserved FSMC register FSMC bank4 PCCARD FSMC bank3 NAND (NAND2) FSMC bank2 NAND (NAND1) FSMC bank1 NOR/PSRAM 4 FSMC bank1 NOR/PSRAM 3 FSMC bank1 NOR/PSRAM 2 FSMC bank1 NOR/PSRAM 1 Reserved CRC Reserved Flash interface Reserved RCC Reserved DMA2 DMA1 Reserved SDIO Reserved ADC3 USART1 TIM8 SPI1 TIM1 ADC2 ADC1 Por t G Por t F Por t E Por t D Por t C Por t B Por t A EXTI AFIO Reserved DAC PWR BKP Reserved BxCAN Shared USB/CAN SRAM 512 bytes USB registers I2C2 I2C1 UART5 UART4 USART3 USART2 Reserved SPI3/I2 S3 0xA000 1000 - 0xBFFF FFFF 0xA000 0000 - 0xA000 0FFF 0x9000 0000 - 0x9FFF FFFF 0x8000 0000 - 0x8FFF FFFF 0x7000 0000 - 0x7FFF FFFF 0x6C00 0000 - 0x6FFF FFFF 0x6800 0000 - 0x6BFF FFFF 0x6400 0000 - 0x67FF FFFF 0x6000 0000 - 0x63FF FFFF 0x4002 4400 - 0x5FFF FFFF 0x4002 3000 - 0x4002 33FF 0x4002 2400 - 0x4002 2FFF 0x4002 2000 - 0x4002 23FF 0x4002 1400 - 0x4002 1FFF 0x4002 1000 - 0x4002 13FF 0x4002 0400 - 0x4002 0FFF 0x4002 0400 - 0x4002 07FF 0x4002 0000 - 0x4002 03FF 0x4001 8400 - 0x4001 FFFF 0x4001 8000 - 0x4001 83FF 0x4001 400 - 0x4001 7FFF 0x4001 3C00 - 0x4001 3FFF 0x4001 3800 - 0x4001 3BFF 0x4001 3400 - 0x4001 37FF 0x4001 3000 - 0x4001 33FF 0x4001 2C00 - 0x4001 2FFF 0x4001 2800 - 0x4001 2BFF 0x4001 2400 - 0x4001 27FF 0x4001 2000 - 0x4001 23FF 0x4001 1C00 - 0x4001 1FFF 0x4001 1800 - 0x4001 1BFF 0x4001 1400 - 0x4001 17FF 0x4001 1000 - 0x4001 13FF 0x4001 0C00 - 0x4001 0FFF 0x4001 0800 - 0x4001 0BFF 0x4001 0400 - 0x4001 07FF 0x4001 0000 - 0x4001 03FF 0x4000 7800 - 0x4000 FFFF 0x4000 7400 - 0x4000 77FF 0x4000 7000 - 0x4000 73FF 0x4000 6C00 - 0x4000 6FFF 0x4000 6800 - 0x4000 6BFF 0x4000 6400 - 0x4000 67FF 0x4000 6000 - 0x4000 63FF 0x4000 5C00 - 0x4000 5FFF 0x4000 5800 - 0x4000 5BFF 0x4000 5400 - 0x4000 57FF 0x4000 5000 - 0x4000 53FF 0x4000 4C00 - 0x4000 4FFF 0x4000 4800 - 0x4000 4BFF 0x4000 4400 - 0x4000 47FF 0x4000 4000 - 0x4000 43FF 0x4000 3C00 - 0x4000 3FFF 0x4000 3800 - 0x4000 3BFF 0x4000 3400 - 0x4000 37FF 0x4000 3000 - 0x4000 33FF 0x4000 2C00 - 0x4000 2FFF 0x4000 2800 - 0x4000 2BFF 0x4000 1800 - 0x4000 27FF 0x4000 1400 - 0x4000 17FF 0x4000 1000 - 0x4000 13FF 0x4000 0C00 - 0x4000 0FFF 0x4000 0800 - 0x4000 0BFF 0x4000 0400 - 0x4000 07FF 0x4000 0000 - 0x4000 03FF
0xFFFF FFFF
0xE000 0000 0xDFFF FFFF
512-Mbyte block 7 Cor tex-M3's internal peripherals 512-Mbyte block 6 Not used
0xC000 0000 0xBFFF FFFF 512-Mbyte block 5 FSMC register 0xA000 0000 0x9FFF FFFF 512-Mbyte block 4 FSMC bank 3 & bank4 512-Mbyte block 3 FSMC bank1 & bank2 512-Mbyte block 2 Peripherals 0x4000 0000 0x3FFF FFFF 512-Mbyte block 1 SRAM 0x2000 0000 0x1FFF FFFF 512-Mbyte block 0 Code 0x0000 0000 Reserved SRAM (64 KB aliased by bit-banding) Option Bytes System memory Reserved Flash Reserved Aliased to Flash, system memory or SRAM depending on BOOT pins
0x8000 0000 0x7FFF FFFF
0x6000 0000 0x5FFF FFFF
SPI2/I2S2 Reserved IWDG WWDG RTC Reserved TIM7 TIM6 TIM5 TIM4 TIM3 TIM2
0x3FFF FFFF 0x2001 0000 0x2000 FFFF 0x2000 0000 0x1FFF F800 - 0x1FFF F80F 0x1FFF F000- 0x1FFF F7FF 0x1FFF EFFF 0x0808 0000 0x0807 FFFF 0x0800 0000 0x07FF FFFF 0x0008 0000 0x0007 FFFF 0x0000 0000
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STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
5
5.1
Electrical characteristics
Test conditions
Unless otherwise specified, all voltages are referenced to VSS.
5.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3).
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.3 V (for the 2 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2).
5.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
5.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 9.
5.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 10. Figure 9. Pin loading conditions Figure 10. Pin input voltage
STM32F103xx pin C = 50 pF
VIN
STM32F103xx pin
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Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
5.1.6
Power supply scheme
Figure 11. Power supply scheme
VBAT
1. 8-3. 6V
Po wer swi tch
Backup circuitry (OSC32K,RTC, Wake-up logic Backup registers)
O UT
Level shifter
GP I/Os
IN
IO Logic Kernel logic (CPU, Digital & Memories)
VDD VDD1/2/.../11
Regulator
11 × 100 nF + 1 × 4.7 F
VSS1/2/.../11 VDD VREF VDDA VREF+ VREFVSSA
ai15401
10 nF + 1 F
10 nF + 1 F
ADC
An alo g: RCs, PLL, ...
Caution:
In Figure 11, the 4.7 F capacitor must be connected to VDD3.
5.1.7
Current consumption measurement
Figure 12. Current consumption measurement scheme
IDD_VBAT VBAT
IDD VDD
VDDA
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STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 6: Voltage characteristics, Table 7: Current characteristics, and Table 8: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 6.
Symbol VDDVSS VIN |VDDx| |VSSX - VSS| VESD(HBM)
Voltage characteristics
Ratings External main supply voltage (including VDDA and VDD)(1) Input voltage on five volt tolerant pin(2) Input voltage on any other pin(2) Variations between different power pins Variations between all the different ground pins Electrostatic discharge voltage (human body model) Min 0.3 VSS -0.3 VSS - 0.3 50 50 Max 4.0 +5.5 VDD+0.3 50 mV 50 see Section 5.3.12: Absolute maximum ratings (electrical sensitivity) V Unit
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded (see Table 7: Current characteristics). This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN < VSS.
Table 7.
Symbol IVDD IVSS IIO
Current characteristics
Ratings Total current into VDD power lines (source)(1) Total current out of VSS ground lines (sink)(1) Output current sunk by any I/O and control pin Output current source by any I/Os and control pin Injected current on NRST pin Max. 150 150 25 -25 5 5 5 pins)(4) 25 mA Unit
IINJ(PIN) (2)(3) IINJ(PIN)
(2)
Injected current on HSE OSC_IN and LSE OSC_IN pins Injected current on any other pin(4) Total injected current (sum of all I/O and control
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. 3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.18: 12-bit ADC characteristics. 4. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with IINJ(PIN) maximum current injection on four I/O port pins of the device.
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Electrical characteristics Table 8. Thermal characteristics
STM32F103xC, STM32F103xD, STM32F103xE
Symbol TSTG TJ
Ratings Storage temperature range Maximum junction temperature
Value 65 to +150 150
Unit C C
5.3
5.3.1
Operating conditions
General operating conditions
Table 9.
Symbol fHCLK fPCLK1 fPCLK2 VDD
General operating conditions
Parameter Internal AHB clock frequency Internal APB1 clock frequency Internal APB2 clock frequency Standard operating voltage Analog operating voltage (ADC not used) Analog operating voltage (ADC used) Backup operating voltage LQFP144 Power dissipation at TA = 85 C for suffix 6 or TA = 105 C for suffix 7(2) LQFP100 LQFP64 LFBGA100 LFBGA144 Ambient temperature for 6 suffix version Maximum power dissipation Low power dissipation(4) Maximum power dissipation Low power dissipation 6 suffix version
(4)
Conditions
Min 0 0 0 2 2
Max 72 36 72 3.6 3.6
Unit
MHz
V
VDDA(1)
Must be the same potential as VDD
V 2.4 1.8 3.6 3.6 TBD(3) 434 444 487 TBD(3) 40 40 40 40 40 40 85 C 105 105 C 125 105 C 125 mW V
VBAT
PD
TA Ambient temperature for 7 suffix version TJ Junction temperature range 7 suffix version
1. When the ADC is used, refer to Table 57: ADC characteristics. 2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 112). 3. TBD = to be determined. 4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 112).
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STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
5.3.2
Operating conditions at power-up / power-down
The parameters given in Table 10 are derived from tests performed under the ambient temperature condition summarized in Table 9. Table 10.
Symbol tVDD
Operating conditions at power-up / power-down
Parameter VDD rise time rate VDD fall time rate Conditions Min 0 20 Max Unit s/V
5.3.3
Embedded reset and power control block characteristics
The parameters given in Table 11 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 11.
Symbol
Embedded reset and power control block characteristics
Parameter Conditions PLS[2:0]=000 (rising edge) PLS[2:0]=000 (falling edge) PLS[2:0]=001 (rising edge) PLS[2:0]=001 (falling edge) PLS[2:0]=010 (rising edge) PLS[2:0]=010 (falling edge) PLS[2:0]=011 (rising edge) Min 2.1 2 2.19 2.09 2.28 2.18 2.38 2.28 2.47 2.37 2.57 2.47 2.66 2.56 2.76 2.66 Typ 2.18 2.08 2.28 2.18 2.38 2.28 2.48 2.38 2.58 2.48 2.68 2.58 2.78 2.68 2.88 2.78 100 Falling edge Rising edge 1.8(1) 1.88 1.84 1.92 40 1 2.5 4.5 1.96 2.0 Max 2.26 2.16 2.37 2.27 2.48 2.38 2.58 2.48 2.69 2.59 2.79 2.69 2.9 2.8 3 2.9 Unit V V V V V V V V V V V V V V V V mV V V mV mS
VPVD
Programmable voltage detector level selection
PLS[2:0]=011 (falling edge) PLS[2:0]=100 (rising edge) PLS[2:0]=100 (falling edge) PLS[2:0]=101 (rising edge) PLS[2:0]=101 (falling edge) PLS[2:0]=110 (rising edge) PLS[2:0]=110 (falling edge) PLS[2:0]=111 (rising edge) PLS[2:0]=111 (falling edge)
VPVDhyst
(2)
PVD hysteresis Power on/power down reset threshold PDR hysteresis
VPOR/PDR VPDRhyst(2)
TRSTTEMPO(2) Reset temporization
2. Guaranteed by design, not tested in production.
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
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Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
5.3.4
Embedded reference voltage
The parameters given in Table 12 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 12.
Symbol VREFINT
Embedded internal reference voltage
Parameter Internal reference voltage Conditions 40 C < TA < +105 C 40 C < TA < +85 C Min 1.16 1.16 Typ 1.20 1.20 5.1 Max 1.26 1.24 17.1(2) Unit V V s
ADC sampling time when TS_vrefint(1) reading the internal reference voltage
1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production.
5.3.5
Supply current characteristics
The current consumption is measured as described in Figure 12: Current consumption measurement scheme.
Maximum current consumption
The MCU is placed under the following conditions:
All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except when explicitly mentioned The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above) Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK
The parameters given in Table 13, Table 14 and Table 15 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9.
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STM32F103xC, STM32F103xD, STM32F103xE Table 13.
Electrical characteristics
Maximum current consumption in Run mode, code with data processing running from Flash
Max(1) Parameter Conditions fHCLK 72 MHz 48 MHz External clock(2), all peripherals enabled 36 MHz 24 MHz 16 MHz Unit TA = 85 C 69 50 39 27 20 11 37 28 22 16.5 12.5 8 TA = 105 C 70 50.5 39.5 28 20.5 11.5 37.5 28.5 22.5 17 13 8 mA
Symbol
IDD
Supply current in Run mode
8 MHz 72 MHz 48 MHz External clock(2), all 36 MHz peripherals disabled 24 MHz 16 MHz 8 MHz
1. Based on characterization, tested in production at VDD max, fHCLK max. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Table 14.
Maximum current consumption in Run mode, code with data processing running from RAM
Max(1) Parameter Conditions fHCLK 72 MHz 48 MHz all External clock peripherals enabled
(2),
Symbol
Unit TA = 85 C 66 43.5 33 23 16 9 33 23 18 13 10 6 TA = 105 C 67 45.5 35 24.5 18 10.5 33.5 23.5 18.5 13.5 10.5 6.5 mA
36 MHz 24 MHz 16 MHz
IDD
Supply current in Run mode
8 MHz 72 MHz 48 MHz External clock(2), all 36 MHz peripherals disabled 24 MHz 16 MHz 8 MHz
1. Data based on characterization results, tested in production at VDD max, fHCLK max. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled
70 60 50 Consumption (mA) 40 30 20 10 0 -45 25 70 Temper atur e (C) 85 105 8 MHz 16 MHz 24 MHz 36 MHz 48 MHz 72 MHz
Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled
35 30 25 Consumption (mA) 20 15 10 5 0 -45 25 70 Temper atur e (C) 85 105 8 MHz 16 MHz 24 MHz 36 MHz 48 MHz 72 MHz
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STM32F103xC, STM32F103xD, STM32F103xE Table 15.
Electrical characteristics
Maximum current consumption in Sleep mode, code running from Flash or RAM
Max(1) Parameter Conditions fHCLK TA = 85 C 72 MHz 48 MHz External clock(2), all peripherals enabled 36 MHz 24 MHz 16 MHz 66 43.5 33 23 16 9 33 23 18 13 10 6 TA = 105 C 67 45.5 35 24.5 18 10.5 mA 72 MHz 48 MHz External clock(2), all peripherals disabled 36 MHz 24 MHz 16 MHz 8 MHz 33.5 23.5 18.5 13.5 10.5 6.5 Unit
Symbol
IDD
Supply current in Sleep mode
8 MHz
1. Based on characterization, tested in production at VDD max, fHCLK max. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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Electrical characteristics Table 16.
Symbol
STM32F103xC, STM32F103xD, STM32F103xE
Typical and maximum current consumptions in Stop and Standby modes(1)
Typ(2) Parameter Conditions Max TA = 105 C Unit
VDD/VBAT VDD/VBAT TA = = 2.4 V = 3.3 V 85 C
Regulator in main mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no Supply current in independent watchdog) Stop mode Regulator in low-power mode, lowspeed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) Low-speed internal RC oscillator and independent watchdog ON Low-speed internal RC oscillator ON, Supply current in independent watchdog OFF Standby mode Low-speed internal RC oscillator and independent watchdog OFF, lowspeed oscillator and RTC OFF IDD_VBAT Backup domain supply current Low-speed oscillator and RTC ON
34.5
35
TBD
1130
24.5
25
TBD
1110
IDD
3 2.8
3.8 3.6
5(3) 2.0(3)
6.5(3) 2.3(3)
A
1.9
2.1
1.1
1.4
1. TBD stands for to be determined. 2. Typical values are measured at TA = 25 C. 3. Based on characterization, not tested in production.
Figure 15. Current consumption in Stop mode with regulator in main mode versus temperature at different VDD values
700
600
500 Consumption (A)
400
300
200 2.4V 2. 7V 3. 0V 3. 3V 3. 6V -45 25 70 Temperat ure (C) 85 105
100
0
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STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
Figure 16. Current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values
700
600
500 Consumption (A)
400
300
200 2.4V 2. 7V 3. 0V 3. 3V 3. 6V -45 25 70 Temperat ure (C) 85 105
100
0
Figure 17. Current consumption in Standby mode versus temperature at different VDD values
4.5 4 3.5 Consumption (A) 3 2.5 2 1.5 1 0.5 0 - 45 25 70 Temper atur e (C) 85 105 2.4V 2.7V 3.0V 3.3V 3.6V
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Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
Typical current consumption
The MCU is placed under the following conditions:
All I/O pins are in input mode with a static value at VDD or VSS (no load). All peripherals are disabled except if it is explicitly mentioned. The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHZ and 2 wait states above). Ambient temperature and VDD supply voltage conditions summarized in Table 9.
Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK = fPCLK2/4
Table 17.
Typical current consumption in Run mode, code with data processing running from Flash
Typ(1) Parameter Conditions fHCLK 72 MHz 48 MHz 36 MHz 24 MHz 16 MHz External clock
(3)
Symbol
All peripherals All peripherals disabled enabled(2) 51 34.6 26.6 18.5 12.8 7.2 4.2 2.7 2 1.6 1.3 45 34 26 17.9 12.2 6.6 3.6 2.1 1.4 1 0.7 30.5 20.7 16.2 11.4 8.2 5 3.1 2.1 1.7 1.4 1.2 27 20.1 15.6 10.8 7.6 4.4 2.5 1.5 1.1 0.8 0.6
Unit
8 MHz 4 MHz 2 MHz 1 MHz 500 kHz
mA
IDD
Supply current in Run mode
125 kHz 64 MHz 48 MHz 36 MHz Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency 24 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 125 kHz
mA
1. Typical values are measures at TA = 25 C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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STM32F103xC, STM32F103xD, STM32F103xE Table 18.
Electrical characteristics
Typical current consumption in Sleep mode, code with data processing code running from Flash or RAM
Typ(1) Conditions fHCLK Unit
Symbol Parameter
All peripherals All peripherals enabled(2) disabled 29.5 20 15.1 10.4 7.2 3.9 2.6 1.85 1.5 1.3 1.2 25.6 19.4 14.5 9.8 6.6 3.3 2 1.25 0.9 0.7 0.6 6.4 4.6 3.6 2.6 2 1.3 1.2 1.15 1.1 1.05 1.05
72 MHz 48 MHz 36 MHz 24 MHz 16 MHz External clock
(3)
8 MHz 4 MHz 2 MHz 1 MHz 500 kHz
IDD
Supply current in Sleep mode
125 kHz 64 MHz 48 MHz 36 MHz 24 MHz Running on high 16 MHz speed internal RC (HSI), AHB prescaler 8 MHz used to reduce the 4 MHz frequency 2 MHz 1 MHz 500 kHz 125 kHz
mA 5.1 4 3 2 1.4 0.7 0.6 0.55 0.5 0.45 0.45
1. Typical values are measures at TA = 25 C, |
