STM32F105xx STM32F107xx
Connectivity line, ARM-based 32-bit MCU with 64/256 KB Flash, USB OTG, Ethernet, 10 timers, 2 CANs, 2 ADCs, 14 communication interfaces
Features
FBGA
Core: ARM 32-bit CortexTM-M3 CPU 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access Single-cycle multiplication and hardware division Memories 64 to 256 Kbytes of Flash memory up to 64 Kbytes of general-purpose SRAM Clock, reset and supply management 2.0 to 3.6 V application supply and I/Os POR, PDR, and programmable voltage detector (PVD) 3-to-25 MHz crystal oscillator Internal 8 MHz factory-trimmed RC Internal 40 kHz RC with calibration 32 kHz oscillator for RTC with calibration Low power Sleep, Stop and Standby modes VBAT supply for RTC and backup registers 2 × 12-bit, 1 s A/D converters (16 channels) Conversion range: 0 to 3.6 V Sample and hold capability Temperature sensor up to 2 MSPS in interleaved mode 2 × 12-bit D/A converters DMA: 12-channel DMA controller Suppor ted peripherals: timers, ADCs, DAC, I2Ss, SPIs, I2Cs and USARTs Debug mode Serial wire debug (SWD) & JTAG interfaces Cor tex-M3 Embedded Trace MacrocellTM Up to 80 fast I/O ports 51/80 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant CRC calculation unit, 96-bit unique ID
LQFP100 14 × 14 mm LQFP64 10 × 10 mm
LFBGA100 10 × 10 mm
Up to 10 timers with pinout remap capability Up to four 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input 1 × 16-bit motor control PWM timer with dead-time generation and emergency stop 2 × watchdog timers (Independent and Window) SysTick timer: a 24-bit downcounter 2 × 16-bit basic timers to drive the DAC Up to 14 communication interfaces with pinout remap capability Up to 2 × I2C interfaces (SMBus/PMBus) Up to 5 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) Up to 3 SPIs (18 Mbit/s), 2 with a multiplexed I2S interface that offers audio class accuracy via advanced PLL schemes 2 × CAN interfaces (2.0B Active) with 512 bytes of dedicated SRAM USB 2.0 full-speed device/host/OTG controller with on-chip PHY that supports HNP/SRP/ID with 1.25 Kbytes of dedicated SRAM 10/100 Ethernet MAC with dedicated DMA and SRAM (4 Kbytes): IEEE1588 hardware support, MII/RMII available on all packages Device summary
Part number STM32F105R8, STM32F105V8 STM32F105RB, STM32F105VB STM32F105RC, STM32F105VC STM32F107RB, STM32F107VB STM32F107RC, STM32F107VC
Table 1.
Reference STM32F105xx
STM32F107xx
May 2010
Doc ID 15274 Rev 5
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www.st.com 1
Contents
STM32F105xx, STM32F107xx
Contents
1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 2.2 2.3 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.3.8 2.3.9 2.3.10 2.3.11 2.3.12 2.3.13 2.3.14 2.3.15 2.3.16 2.3.17 2.3.18 2.3.19 2.3.20 2.3.21 2.3.22 2.3.23 2.3.24 2.3.25 2.3.26 2.3.27 2.3.28 ARM CortexTM-M3 core with embedded Flash and SRAM . . . . . . . . . 13 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 13 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 13 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 14 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 16 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Universal synchronous/asynchronous receiver transmitters (USARTs) 18 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 19 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Universal serial bus on-the-go full-speed (USB OTG FS) . . . . . . . . . . . 20 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 20 Remap capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ADCs (analog-to-digital converters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 22
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Embedded Trace MacrocellTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3 4 5
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.2 5.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 5.3.10 5.3.11 5.3.12 5.3.13 5.3.14 5.3.15 5.3.16 5.3.17 5.3.18 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 36 Embedded reset and power control block characteristics . . . . . . . . . . . 36 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 PLL, PLL2 and PLL3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 53 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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6.1 6.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.2.1 6.2.2 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 85
7
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Appendix A Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
A.1 A.2 A.3 A.4 USB OTG FS interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Complete audio player solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 USB OTG FS interface + Ethernet/I2S interface solutions . . . . . . . . . . . . 94
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
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List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F105xx and STM32F107xx features and peripheral counts . . . . . . . . . . . . . . . . . . 10 STM32F105xx and STM32F107xx family versus STM32F103xx family . . . . . . . . . . . . . . 11 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 36 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 39 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 39 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 HSE 3-25 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 PLL2 and PLL3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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List of tables Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64.
STM32F105xx, STM32F107xx
USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 USB OTG FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Ethernet DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Dynamic characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Dynamic characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Dynamic characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 LQPF100 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . 82 LQFP64 64 pin low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . 83 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 PLL configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Applicative current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
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List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. STM32F105xx and STM32F107xx connectivity line block diagram . . . . . . . . . . . . . . . . . 12 STM32F105xxx and STM32F107xxx connectivity line BGA100 ballout top view. . . . . . . . 23 STM32F105xxx and STM32F107xxx connectivity line LQFP100 pinout . . . . . . . . . . . . . . 24 STM32F105xxx and STM32F107xxx connectivity line LQFP64 pinout . . . . . . . . . . . . . . . 25 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Typical current consumption in Stop mode with regulator in Run mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Typical current consumption in Standby mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . 68 Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 75 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . 75 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . 81 LQFP100, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 LQFP64 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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List of figures Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56.
STM32F105xx, STM32F107xx
Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 USB OTG FS device mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Host connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 OTG connection (any protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 RMII with a 25 MHz crystal and PHY with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 RMII with a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Complete audio player solution 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Complete audio player solution 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 USB OTG FS + Ethernet solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 USB OTG FS + I2S (Audio) solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
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STM32F105xx, STM32F107xx
Introduction
1
Introduction
This datasheet provides the description of the STM32F105xx and STM32F107xx connectivity line microcontrollers. For more details on the whole STMicroelectronics STM32F10xxx family, please refer to Section 2.2: Full compatibility throughout the family. The STM32F105xx and STM32F107xx datasheet should be read in conjunction with the STM32F10xxx reference manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the CortexTM-M3 core please refer to the CortexTM-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.
2
Description
The STM32F105xx and STM32F107xx connectivity line family incorporates the highperformance ARM CortexTM-M3 32-bit RISC core operating at a 72 MHz frequency, highspeed embedded memories (Flash memory up to 256 Kbytes and SRAM up to 64 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer two 12-bit ADCs, four general-purpose 16-bit timers plus a PWM timer, as well as standard and advanced communication interfaces: up to two I2Cs, three SPIs, two I2Ss, five USARTs, an USB OTG FS and two CANs. Ethernet is available on the STM32F107xx only. The STM32F105xx and STM32F107xx connectivity line family operates in the 40 to +105 C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F105xx and STM32F107xx connectivity line family offers devices in three different package types: from 64 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family.
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Description
STM32F105xx, STM32F107xx These features make the STM32F105xx and STM32F107xx connectivity line microcontroller family suitable for a wide range of applications:
Motor drive and application control Medical and handheld equipment Industrial applications: PLC, inverters, printers, and scanners Alarm systems, Video intercom, and HVAC Home audio equipment
Figure 1 shows the general block diagram of the device family.
2.1
Table 2.
Device overview
STM32F105xx and STM32F107xx features and peripheral counts
Peripherals(1) STM32F105Rx 64 20 128 32 256 64 LQFP64 No General-pur pose Yes 4 1 2 3(2) 2 3(2) 1 5 Yes 2 51 2 16 2 2 72 MHz 2.0 to 3.6 V Ambient temperatures: 40 to +85 C /40 to +105 C Junction temperature: 40 to + 125 C 80 3(2) 2 3(2) 1 STM32F107Rx 128 48 256 64 STM32F105Vx 64 20 LQFP 100 128 32 256 64 STM32F107Vx 128 48 256 64
Flash memory in Kbytes SRAM in Kbytes Package Ethernet
LQFP100, BGA100 No
LQFP100 Yes
Timers
Advanced-control Basic SPI(I2S)(2)
I Communication USART interfaces USB OTG FS CAN GPIOs 12-bit ADC Number of channels 12-bit DAC Number of channels CPU frequency Operating voltage Operating temperatures
2C
1. Please refer to Table 5: Pin definitions for peripheral availability when the I/O pins are shared by the peripherals required by the application. 2. The SPI2 and SPI3 interfaces give the flexibility to work in either the SPI mode or the I2S audio mode.
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STM32F105xx, STM32F107xx
Description
2.2
Full compatibility throughout the family
The STM32F105xx and STM32F107xx constitute the connectivity line family whose members are fully pin-to-pin, software and feature compatible. The STM32F105xx and STM32F107xx are a drop-in replacement for the low-density (STM32F103x4/6), medium-density (STM32F103x8/B) and high-density (STM32F103xC/D/E) performance line devices, allowing the user to try different memory densities and peripherals providing a greater degree of freedom during the development cycle.
Table 3.
STM32F105xx and STM32F107xx family versus STM32F103xx family(1)
Medium-density STM32F103xx devices 32 64 128 High-density STM32F103xx devices 256 384 512 STM32F 105xx ST M32F107x x
ST M32 Low-density device STM32F103xx devices Flash size (KB) RAM size (KB) 144 pins 100 pins 16 32
64
128
256
128
256
6
10
10
20
20
48
64
64
20
32
64
48
64
2 × USARTs 64 pins 2 × 16-bit timers 1 × SPI, 1 × I2C, USB, CAN, 1 × PWM timer 2 × ADCs 48 pins 36 pins
5 × USARTs, 5 × USARTs 4 × 16-bit timers, 4 × 16-bit timers, 2 × basic timers, 3 × USARTs 2 × basic timers, 3 × SPIs, 3 × SPIs, 2Ss, 2 × I2Cs, USB, 2 × USARTs 3 × 16-bit 2×I 2 × I2Ss, timers 2 × 16-bit CAN, 2 × PWM timers 2 × I2Cs, 2 × SPIs, timers 3 × ADCs, 2 × DACs, 2 USB OTG FS, 2 × I Cs, USB, 1 × SDIO, FSMC (1001 × SPI, 2 × CANs, CAN, (2)) 1 × I2C, and 144-pin packages 1 × PWM timer, USB, CAN, 1 × PWM timer 2 × ADCs, 2 × ADCs 1 × PWM 2 × DACs timer 2 × ADCs
5 × USARTs, 4 × 16-bit timers, 2 × basic timers, 3 × SPIs, 2 × I2S, 1 × I2C, USB OTG FS, 2 × CANs, 1 × PWM timer, 2 × ADCs, 2 × DACs, Ether net
1. Please refer to Table 5: Pin definitions for peripheral availability when the I/O pins are shared by the peripherals required by the application. 2. Por ts F and G are not available in devices delivered in 100-pin packages.
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Description
STM32F105xx, STM32F107xx
2.3
Figure 1.
Overview
STM32F105xx and STM32F107xx connectivity line block diagram
TRACE CLK TRAC ED[ 0:3 ]
as AF
NJTRST JTD I JT CK /SWCL K J TMS/SWDIO JTD O as A F
TPIU SW/JTAG
ETM Tr ac e/Tr i g
VDD18
Power Voltage reg. 3.3 V to 1.8 V @VDD
VDD = 2 to 3.6 V
VSS
Flashl obl
Ibus
In t er f ac e
Flash 256 KB 64 bit POR Rese t In t
Cortex-M3 CPU
Fmax : 72 MHz Dbus System NVIC
SRAM 64 KB
Bus Matri x
@VDDA RC HS RC LS PLL3 PLL2 PLL
Supply supervision POR / PDR PVD @VDDA @VDD
NRST VDDA VSSA
AHB
MII_TXD[3:0]/RMII_TXD[1:0] MII_TX_CLK/RMII_TX_CLK MII_TX_EN/RMII_TX_EN MII_RXD[3:0]/RMII_RXD[1:0] MII_RX_ER/RMII_RX_ER MII_RX_CLK/RMII_REF_CLK MII_RX_DV/RMII_CRS_DV MII_CRS MII_COL/RMII_COL MDC MDIO PPS_OUT SOF VBUS ID DM DP
GP DMA1
7 channels
GP DMA2
5 channels Reset & clock control PCLK1 PCLK2 HCL K FCLK PLL3
XTAL osc 3-25 MHz IWDG St an dby interface @V BAT
OSC_IN OSC_OUT
Et hernet MAC 10/100 DMA Ethernet DPRA M 2 KB DPRA M 2 KB USB OTG FS
VBAT =1.8 V to 3.6 V
OSC32_IN OSC32_OUT TAMPER-RTC/ ALARM/SECOND OUT
XTA L 32kHz RTC AW U Bac k up register
Backup interface TIM2 SRAM 1.25 KB EXT.IT WKUP AP B2 : F max = 72 MHz GPIO port A GPIO port B GPIO port C GPIO port D GPIO port E AP B1 : Fmax = 36 MHz AHB to APB2 AHB to APB1 TIM3 TIM4 TIM5 USA RT2 USA RT3 UART 4 UART 5 Si t ) 2x(8x16b PI2 TIM1 S i t) 2x(8x16b PI3 / I2S2(1) / I2S3 4 Channels , ETR as AF 4 Channels , ETR as AF 4 Channels , ETR as AF 4 Channel s , ETR as A F RX,TX, CTS, RTS, CK as AF RX,TX, CTS, RTS, CK as AF RX,TX as AF RX,TX as AF MOSI/SD, MISO, MCK, SCK/CK, NSS/WS as AF MOSI/SD, MISO, MCK, SCK/CK, NSS/WS as AF SCL,SDA, SMBA as AF SCL,S DA,SM BA as AF CAN1_TX as AF CAN 1_RX as AF Tem p sensor 12bi t ADC1 IF 12bit ADC2 IF TIM6 TIM7 SRAM 512B CAN2 _TX a AF s CAN 2_RX as AF IF 12bit DAC1 IF 12bit DAC 2 @VDDA DAC_OUT1 as AF DAC_OUT2 as AF
80 AF PA[ 15:0 ] PB[ 15:0 ] PC[ 15:0 ] PD[ 15:0 ] PE[ 15:0 ] 4 Channels 4 compl. Channels BKIN, ETR input as AF
I2C1 MOSI,MISO, SCK,NS S as AF RX,TX, CTS, RTS, CK as AF SPI1 USA RT1 WWDG I2C2 bx CAN1
16 ADC12_INs common to ADC1 & ADC2
bx CA N 2
VREF VREF+
@VDDA
ai15411
1. TA = 40 C to +85 C (suffix 6, see Table 61) or 40 C to +105 C (suffix 7, see Table 61), junction temperature up to 105 C or 125 C, respectively. 2. AF = alternate function on I/O port pin.
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STM32F105xx, STM32F107xx
Description
2.3.1
ARM CortexTM-M3 core with embedded Flash and SRAM
The ARM CortexTM-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM CortexTM-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. With its embedded ARM core, STM32F105xx and STM32F107xx connectivity line family is compatible with all ARM tools and software. Figure 1 shows the general block diagram of the device family.
2.3.2
Embedded Flash memory
64 to 256 Kbytes of embedded Flash is available for storing programs and data.
2.3.3
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
2.3.4
Embedded SRAM
20 to 64 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.
2.3.5
Nested vectored interrupt controller (NVIC)
The STM32F105xx and STM32F107xx connectivity line embeds a nested vectored interrupt controller able to handle up to 67 maskable interrupt channels (not including the 16 interrupt lines of CortexTM-M3) and 16 priority levels.
Closely coupled NVIC gives low latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving higher priority interrupts Suppor t for tail-chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt latency.
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Description
STM32F105xx, STM32F107xx
2.3.6
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 20 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected to the 16 external interrupt lines.
2.3.7
Clocks and startup
System clock selection is performed on startup, however, the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 3-25 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator). A single 25 MHz crystal can clock the entire system including the ethernet and USB OTG FS peripherals. Several prescalers and PLLs allow the configuration of the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 MHz. The maximum allowed frequency of the low speed APB domain is 36 MHz. Refer to Figure 55: USB OTG FS + Ethernet solution on page 94. The advanced clock controller clocks the core and all peripherals using a single crystal or oscillator. In order to achieve audio class performance, an audio crystal can be used. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 96 kHz with less than 0.5% accuracy error. Refer to Figure 56: USB OTG FS + I2S (Audio) solution on page 94. To configure the PLLs, please refer to Table 62 on page 95, which provides PLL configurations according to the application type.
2.3.8
Boot modes
At startup, boot pins are used to select one of three boot options:
Boot from User Flash Boot from System Memory Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1, USART2 (remapped), CAN2 (remapped) or USB OTG FS in device mode (DFU: device firmware upgrade). For remapped signals refer to Table 5: Pin definitions. The USART peripheral operates with the internal 8 MHz oscillator (HSI), however the CAN and USB OTG FS can only function if an external 8 MHz, 14.7456 MHz or 25 MHz clock (HSE) is present. For full details about the boot loader, please refer to AN2606.
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Description
2.3.9
Power supply schemes
VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.
2.3.10
Power supply supervisor
The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
2.3.11
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
MR is used in the nominal regulation mode (Run) LPR is used in the Stop modes. Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode.
2.3.12
Low-power modes
The STM32F105xx and STM32F107xx connectivity line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:
Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
Stop mode Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB OTG FS wakeup.
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Description
STM32F105xx, STM32F107xx Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode.
2.3.13
DMA
The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-toperipheral transfers. The two DMA controllers support circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose, basic and advanced control timers TIMx, DAC, I2S and ADC. In the STM32F107xx, there is a DMA controller dedicated for use with the Ethernet (see Section 2.3.20: Ethernet MAC interface with dedicated DMA and IEEE 1588 support for more information).
2.3.14
RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are forty-two 16-bit registers used to store 84 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, and they are not reset when the device wakes up from the Standby mode. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. For more information, please refer to AN2604: "STM32F101xx and STM32F103xx RTC calibration", available from www.st.com.
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STM32F105xx, STM32F107xx
Description
2.3.15
Timers and watchdogs
The STM32F105xx and STM32F107xx devices include an advanced-control timer, four general-purpose timers, two basic timers, two watchdog timers and a SysTick timer. Table 4 compares the features of the general-purpose and basic timers. Table 4.
Timer
Timer feature comparison
Counter resolution 16-bit Counter type Up, down, up/down Up, down, up/down Prescaler factor Any integer between 1 and 65536 Any integer between 1 and 65536 Any integer between 1 and 65536 DMA request Capture/compare Complementary generation channels outputs Yes 4 Yes
TIM1 TIMx (TIM2, TIM3, TIM4, TIM5) TIM6, TIM7
16-bit
Yes
4
No
16-bit
Up
Yes
0
No
Advanced-control timer (TIM1)
The advanced control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead-times. It can also be seen as a complete general-purpose timer. The 4 independent channels can be used for:
Input capture Output compare PWM generation (edge or center-aligned modes) One-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%). The counter can be frozen in debug mode. Many features are shared with those of the standard TIM timers which have the same architecture. The advanced control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining.
General-purpose timers (TIMx)
There are up to 4 synchronizable standard timers (TIM2, TIM3, TIM4 and TIM5) embedded in the STM32F105xx and STM32F107xx connectivity line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or one pulse mode output. This gives up to 16 input captures / output compares / PWMs on the largest packages. They can work together with the Advanced Control timer via the Timer Link feature for synchronization or event chaining. The counter can be frozen in debug mode.
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Description
STM32F105xx, STM32F107xx Any of the standard timers can be used to generate PWM outputs. Each of the timers has independent DMA request generations.
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:
A 24-bit down counter Autoreload capability Maskable system interrupt generation when the counter reaches 0. Programmable clock source
2.3.16
I²C bus
Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes. They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus.
2.3.17
Universal synchronous/asynchronous receiver transmitters (USARTs)
The STM32F105xx and STM32F107xx connectivity line embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4 and UART5). These five interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 interface is able to communicate at speeds of up to 4.5 Mbit/s. The other available interfaces communicate at up to 2.25 Mbit/s.
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STM32F105xx, STM32F107xx
Description
USART1, USART2 and USART3 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller except for UART5.
2.3.18
Serial peripheral interface (SPI)
Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC/SDHC(a) modes. All SPIs can be served by the DMA controller.
2.3.19
Inter-integrated sound (I2S)
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available, that can be operated in master or slave mode. These interfaces can be configured to operate with 16/32 bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to 96 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency with less than 0.5% accuracy error owing to the advanced clock controller (see Section 2.3.7: Clocks and startup). Please refer to the "Audio frequency precision" tables provided in the "Serial peripheral interface (SPI)" section of the STM32F10xxx reference manual.
2.3.20
Ethernet MAC interface with dedicated DMA and IEEE 1588 support
Peripheral not available on STM32F105xx devices. The STM32F107xx devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard media-independent interface (MII) or a reduced media-independent interface (RMII). The STM32F107xx requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). the PHY is connected to the STM32F107xx MII port using as many as 17 signals (MII) or 9 signals (RMII) and can be clocked using the 25 MHz (MII) or 50 MHz (RMII) output from the STM32F107xx. The STM32F107xx includes the following features:
Suppor ts 10 and 100 Mbit/s rates Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors (see the STM32F105xx/STM32F107xx reference manual for details) Tagged MAC frame support (VLAN support) Half-duplex (CSMA/CD) and full-duplex operation MAC control sublayer (control frames) support
a. SDHC = Secure digital high capacity.
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Description
STM32F105xx, STM32F107xx 32-bit CRC generation and removal Several address filtering modes for physical and multicast address (multicast and group addresses) 32-bit status code for each transmitted or received frame Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes, that is 4 Kbytes in total Suppor ts hardware PTP (precision time protocol) in accordance with IEEE 1588 with the timestamp comparator connected to the TIM2 trigger input Triggers interrupt when system time becomes greater than target time
2.3.21
Controller area network (CAN)
The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). The 256 bytes of SRAM which are allocated for each CAN (512 bytes in total) are not shared with any other peripheral.
2.3.22
Universal serial bus on-the-go full-speed (USB OTG FS)
The STM32F105xx and STM32F107xx connectivity line devices embed a USB OTG fullspeed (12 Mb/s) device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are:
1.25 KB of SRAM used exclusively by the endpoints (not shared with any other peripheral) 4 bidirectional endpoints HNP/SNP/IP inside (no need for any external resistor) for OTG/Host modes, a power switch is needed in case bus-powered devices are connected the SOF output can be used to synchronize the external audio DAC clock in isochronous mode in accordance with the USB 2.0 Specification, the supported transfer speeds are: in Host mode: full speed and low speed in Device mode: full speed
2.3.23
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable except for analog inputs. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. I/Os on APB2 with up to 18 MHz toggling speed
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STM32F105xx, STM32F107xx
Description
2.3.24
Remap capability
This feature allows the use of a maximum number of peripherals in a given application. Indeed, alternate functions are available not only on the default pins but also on other specific pins onto which they are remappable. This has the advantage of making board design and port usage much more flexible. For details refer to Table 5: Pin definitions; it shows the list of remappable alternate functions and the pins onto which they can be remapped. See the STM32F10xxx reference manual for software considerations.
2.3.25
ADCs (analog-to-digital converters)
Two 12-bit analog-to-digital converters are embedded into STM32F105xx and STM32F107xx connectivity line devices and each ADC shares up to 16 external channels, performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow:
Simultaneous sample and hold Interleaved sample and hold Single shunt
The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the standard timers (TIMx) and the advanced-control timer (TIM1) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers.
2.3.26
DAC (digital-to-analog converter)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. This dual digital Interface supports the following features:
two DAC converters: one for each output channel 8-bit or 12-bit monotonic output left or right data alignment in 12-bit mode synchronized update capability noise-wave generation triangular-wave generation dual DAC channel independent or simultaneous conversions DMA capability for each channel external triggers for conversion input voltage reference VREF+
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Description
STM32F105xx, STM32F107xx Eight DAC trigger inputs are used in the STM32F105xx and STM32F107xx connectivity line family. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels.
2.3.27
Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value.
2.3.28
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
2.3.29
Embedded Trace MacrocellTM
The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F10xxx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools.
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STM32F105xx, STM32F107xx
Pinouts and pin description
3
Figure 2.
1
Pinouts and pin description
STM32F105xxx and STM32F107xxx connectivity line BGA100 ballout top view
2 3 4 5 6 7 8 9 10
A
PC14PC13OSC32_IN TAMPER-RTC
PE2
PB9
PB7
PB4
PB3
PA15
PA14
PA13
B
PC15OSC32_OUT
VBAT
PE3
PB8
PB6
PD5
PD2
PC11
PC10
PA12
C
OSC_IN
VSS_5
PE4
PE1
PB5
PD6
PD3
PC12
PA9
PA11
D
OSC_OUT
VDD_5
PE5
PE0
BOOT0
PD7
PD4
PD0
PA8
PA10
E
NRST
PC2
PE6
VSS_4
VSS_3
VSS_2
VSS_1
PD1
PC9
PC7
F
PC0
PC1
PC3
VDD_4
VDD_3
VDD_2
VDD_1
NC
PC8
PC6
G
VSSA
PA0-WKUP
PA4
PC4
PB2
PE10
PE14
PB15
PD11
PD15
H
VREF
PA1
PA5
PC5
PE7
PE11
PE15
PB14
PD10
PD14
J
VREF+
PA2
PA6
PB0
PE8
PE12
PB10
PB13
PD9
PD13
K
VDDA
PA3
PA7
PB1
PE9
PE13
PB11
PB12
PD8
PD12
AI16001c
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Pinouts and pin description Figure 3.
STM32F105xx, STM32F107xx
STM32F105xxx and STM32F107xxx connectivity line LQFP100 pinout
VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14
PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP PA1 PA2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
LQFP100
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VDD_2 VSS_2 NC PA 13 PA 12 PA 11 PA 10 PA 9 PA 8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12
PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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STM32F105xx, STM32F107xx Figure 4.
Pinouts and pin description
STM32F105xxx and STM32F107xxx connectivity line LQFP64 pinout
VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14
VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0 OSC_IN PD1 OSC_OUT NRST PC0 PC1 PC2 PC3 V SSA V DDA PA0-WKUP PA1 PA2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12
PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1
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Pinouts and pin description Table 5.
Pins LQFP100 BGA100 LQFP64 Pin name Type(1)
STM32F105xx, STM32F107xx
Pin definitions
I / O Level(2) Alternate functions(4) Main function(3) (after reset) PE2 PE3 PE4 PE5 PE6 VBAT PC13(6) PC14(6) PC15(6) VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA WKUP/USART2_CTS(7) ADC12_IN0/TIM2_CH1_ETR TIM5_CH1/ ETH_MII_CRS_WKUP USART2_RTS(7)/ ADC12_IN1/ TIM5_CH2 /TIM2_CH2(7)/ ETH_MII_RX_CLK/ ETH_RMII_REF_CLK ADC12_IN10 ADC12_IN11/ ETH_MII_MDC/ ETH_RMII_MDC ADC12_IN12/ ETH_MII_TXD2 ADC12_IN13/ ETH_MII_TX_CLK TAMPER-RTC OSC32_IN OSC32_OUT
Default TRACECK TRACED0 TRACED1 TRACED2 TRACED3
Remap
A3 B3 C3 D3 E3 B2 A2 A1 B1 C2 D2 C1 D1 E1 F1 F2
1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PE2 PE3 PE4 PE5 PE6 VBAT
I/O I/O I/O I/O I/O S
FT FT FT FT FT
PC13-TAMPERI/O RTC(5) PC14OSC32_IN(5) I/O
PC15I/O OSC32_OUT(5) VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA S S I O I/O I/O I/O I/O I/O S S S S
E2 10 17 F3 11 18 G1 12 19 H1 J1 20 21
K1 13 22
G2 14 23
PA0-WKUP
I/O
PA0
H2 15 24
PA1
I/O
PA1
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STM32F105xx, STM32F107xx Table 5.
Pins LQFP100 BGA100 LQFP64 Pin name Type(1)
Pinouts and pin description
Pin definitions (continued)
I / O Level(2) Alternate functions(4) Main function(3) (after reset)
Default USART2_TX(7)/ TIM5_CH3/ADC12_IN2/ TIM2_CH3 (7)/ ETH_MII_MDIO/ ETH_RMII_MDIO USART2_RX(7)/ TIM5_CH4/ADC12_IN3 / TIM2_CH4(7)/ ETH_MII_COL
Remap
J2
16 25
PA2
I/O
PA2
K2 17 26 E4 18 27 F4 19 28 G3 20 29 H3 21 30 J3 22 31
PA3 VSS_4 VDD_4 PA4 PA5 PA6
I/O S S I/O I/O I/O
PA3 VSS_4 VDD_4 PA4 PA5 PA6
SPI1_NSS(7)/DAC_OUT1 / USART2_CK(7) / ADC12_IN4 SPI1_SCK(7) / DAC_OUT2 / ADC12_IN5 SPI1_MISO(7)/ADC12_IN6 / TIM3_CH1(7) SPI1_MOSI(7)/ADC12_IN7 / TIM3_CH2(7)/ ETH_MII_RX_DV(8)/ ETH_RMII_CRS_DV ADC12_IN14/ ETH_MII_RXD0(8)/ ETH_RMII_RXD0 ADC12_IN15/ ETH_MII_RXD1(8)/ ETH_RMII_RXD1 ADC12_IN8/TIM3_CH3/ ETH_MII_RXD2(8) ADC12_IN9/TIM3_CH4(7)/ ETH_MII_RXD3(8)
SPI3_NSS/I2S3_WS
TIM1_BKIN
K3 23 32
PA7
I/O
PA7
TIM1_CH1N
G4 24 33
PC4
I/O
PC4
H4 25 34
PC5
I/O
PC5
J4
26 35
PB0 PB1 PB2 PE7 PE8 PE9 VSS_7 VDD_7 PE10 PE11 PE12
I/O I/O I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT
PB0 PB1 PB2/BOOT1 PE7 PE8 PE9
TIM1_CH2N TIM1_CH3N
K4 27 36 G5 28 37 H5 J5 K5 G6 H6 J6 38 39 40 41 42 43
TIM1_ETR TIM1_CH1N TIM1_CH1
PE10 PE11 PE12
TIM1_CH2N TIM1_CH2 TIM1_CH3N
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Pinouts and pin description Table 5.
Pins LQFP100 BGA100 LQFP64 Pin name Type(1)
STM32F105xx, STM32F107xx
Pin definitions (continued)
I / O Level(2) Alternate functions(4) Main function(3) (after reset) PE13 PE14 PE15 PB10 I2C2_SCL(8)/USART3_TX(7)/ ETH_MII_RX_ER I2C2_SDA(8)/USART3_RX(7)/ ETH_MII_TX_EN/ ETH_RMII_TX_EN
Default
Remap TIM1_CH3 TIM1_CH4 TIM1_BKIN TIM2_CH3
K6 G7 H7 J7
-
44 45 46
PE13 PE14 PE15 PB10
I/O FT I/O FT I/O FT I/O FT
29 47
K7 30 48 E7 31 49 F7 32 50
PB11 VSS_1 VDD_1
I/O FT S S
PB11 VSS_1 VDD_1
TIM2_CH4
K8 33 51
PB12
I/O FT
PB12
SPI2_NSS(8)/I2S2_WS(8)/ I2C2_SMBA(8) / USART3_CK(7)/ TIM1_BKIN(7) / CAN2_RX/ ETH_MII_TXD0/ ETH_RMII_TXD0 SPI2_SCK(8) / I2S2_CK(8) / USART3_CTS(7)/ TIM1_CH1N/CAN2_TX/ ETH_MII_TXD1/ ETH_RMII_TXD1 SPI2_MISO(8) / TIM1_CH2N / USART3_RTS(7) SPI2_MOSI(8) / I2S2_SD(8) / TIM1_CH3N(7) USART3_TX/ ETH_MII_RX_DV/ ETH_RMII_CRS_DV USART3_RX/ ETH_MII_RXD0/ ETH_RMII_RXD0 USART3_CK/ ETH_MII_RXD1/ ETH_RMII_RXD1 USART3_CTS/ ETH_MII_RXD2 TIM4_CH1 / USART3_RTS/ ETH_MII_RXD3 TIM4_CH2 TIM4_CH3
J8
34 52
PB13
I/O FT
PB13
H8 35 53 G8 36 54
PB14 PB15
I/O FT I/O FT
PB14 PB15
K9
-
55
PD8
I/O F T
PD8
J9
-
56
PD9
I/O F T
PD9
H9
-
57
PD10
I/O FT
PD10
G9
-
58
PD11
I/O FT
PD11
K10 J10 H10
-
59 60 61
PD12 PD13 PD14
I/O FT I/O FT I/O FT
PD12 PD13 PD14
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STM32F105xx, STM32F107xx Table 5.
Pins LQFP100 BGA100 LQFP64 Pin name Type(1)
Pinouts and pin description
Pin definitions (continued)
I / O Level(2) Alternate functions(4) Main function(3) (after reset) PD15 PC6 PC7 PC8 PC9 PA8 PA9 PA10 PA11 PA12 USART1_CK/OTG_FS_SOF / TIM1_CH1(8)/MCO USART1_TX(7)/ TIM1_CH2(7)/ OTG_FS_VBUS USART1_RX(7)/ TIM1_CH3(7)/OTG_FS_ID USART1_CTS / CAN1_RX / TIM1_CH4(7)/OTG_FS_DM USART1_RTS / OTG_FS_DP / CAN1_TX(7) / TIM1_ETR(7) PA13 I2S2_MCK/ I2S3_MCK
Default
Remap TIM4_CH4 TIM3_CH1 TIM3_CH2 TIM3_CH3 TIM3_CH4
G10
-
62
PD15 PC6 PC7 PC8 PC9 PA8 PA9 PA10 PA11 PA12 PA13
I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT
F10 37 63 E10 38 64 F9 39 65 E9 40 66 D9 41 67 C9 42 68 D10 43 69 C10 44 70 B10 45 71 A10 46 72 F8 73
I/O FT JTMS-SWDIO Not connected
E6 47 74 F6 48 75 A9 49 76 A8 50 77 B9 51 78 B8 52 79 C8 53 80 D8 E8 5 6 81 82
VSS_2 VDD_2 PA14 PA15 PC10 PC11 PC12 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
S S
VSS_2 VDD_2 PA14 SPI3_NSS / I2S3_WS UART4_TX UART4_RX UART5_TX TIM2_CH1_ETR / PA15 SPI1_NSS USART3_TX/ SPI3_SCK/I2S3_CK USART3_RX/ SPI3_MISO USART3_CK/ SPI3_MOSI/I2S3_SD CAN1_RX CAN1_TX TIM3_ETR / UART5_RX USART2_CTS USART2_RTS USART2_TX USART2_RX USART2_CK
I/O FT JTCK-SWCLK I/O FT I/O FT I/O FT I/O FT I/O FT JTDI PC10 PC11 PC12 OSC_IN(9)
(9)
I/O FT OSC_OUT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT PD2 PD3 PD4 PD5 PD6 PD7
B7 54 83 C7 D7 B6 C6 D6 84 85 86 87 88
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Pinouts and pin description Table 5.
Pins LQFP100 BGA100 LQFP64 Pin name Type(1)
STM32F105xx, STM32F107xx
Pin definitions (continued)
I / O Level(2) Alternate functions(4) Main function(3) (after reset)
Default
Remap PB3 / TRACESWO/ TIM2_CH2 / SPI1_SCK PB4 / TIM3_CH1/ SPI1_MISO
A7 55 89 A6 56 90
PB3 PB4
I/O FT I/O FT
JTDO NJTRST
SPI3_SCK / I2S3_CK SPI3_MISO
C5 57 91 B5 58 92 A5 59 93 D5 60 94 B4 61 95 A4 62 96 D4 C4 97 98
PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS_3 VDD_3
I/O I/O FT I/O FT I I/O FT I/O FT I/O FT I/O FT S S
PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS_3 VDD_3
I2C1_SMBA / SPI3_MOSI / TIM3_CH2/SPI1_MOSI/ ETH_MII_PPS_OUT / I2S3_SD CAN2_RX ETH_RMII_PPS_OUT I2C1_SCL(7)/TIM4_CH1(7) I2C1_SDA(7)/TIM4_CH2(7) USART1_TX/CAN2_TX USART1_RX
TIM4_CH3(7)/ ETH_MII_TXD3 TIM4_CH4(7) TIM4_ETR
I2C1_SCL/CAN1_RX I2C1_SDA / CAN1_TX
E5 63 99 F5 64 100
1. I = input, O = output, S = supply, HiZ = high impedance. 2. FT = 5 V tolerant. All I/Os are VDD capable. 3. Function availability depends on the chosen device. 4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 5. PC13, PC14 and PC15 are supplied through the power switch, and so their use in output mode is limited: they can be used only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time. 6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 7. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 8. SPI2/I2S2 and I2C2 are not available when the Ethernet is being used. 9. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 and BGA100 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.
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Memory mapping
4
Memory mapping
The memory map is shown in Figure 5. Figure 5. Memory map
Reserved USB OTG FS Reserved Ethernet Reserved CRC Reserved AHB Flash interface Reserved RCC Reserved DMA2 DMA1 Reserved USART1 Reserved SPI1 TIM1 ADC2 ADC1 Reserved Por t E Por t D Por t C Por t B Por t A EXTI AFIO Reserved DAC PWR BKP bxCAN2 bxCAN1 Reserved I2C2 I2C1 UART5 UART4 USART3 USART2 Reserved SPI3/I2S3 0x5000 0400 - 0x5FFF FFFF 0x5000 0000 - 0x5003 FFFF 0x4003 0000 - 0x4FFF FFFF 0x4002 8000 - 0x4002 9FFF 0x4002 3400 - 0x4002 7FFF 0x4002 3000 - 0x4002 33FF 0x4002 2400 - 0x4002 2FFF 0x4002 2000 - 0x4002 23FF 0x4002 1400 - 0x4002 1FFF 0x4002 1000 - 0x4002 13FF 0x4002 0800 - 0x4002 0FFF 0x4002 0400 - 0x4002 07FF 0x4002 0000 - 0x4002 03FF 0x4001 3C00 - 0x4001 FFFF 0x4001 3800 - 0x4001 3BFF 0x4001 3400 - 0x4001 37FF 0x4001 3000 - 0x4001 33FF 0x4001 2C00 - 0x4001 2FFF 0x4001 2800 - 0x4001 2BFF 0x4001 2400 - 0x4001 27FF 0x4001 1C00 - 0x4001 23FF 0x4001 1800 - 0x4001 1BFF 0x4001 1400 - 0x4001 17FF 0x4001 1000 - 0x4001 13FF 0x4001 0C00 - 0x4001 0FFF 0x4001 0800 - 0x4001 0BFF 0x4001 0400 - 0x4001 07FF 0x4001 0000 - 0x4001 3FFF 0x4000 7800 - 0x4000 FFFF 0x4000 7400 - 0x4000 77FF 0x4000 7000 - 0x4000 73FF 0x4000 6C00 - 0x4000 6FFF 0x4000 6800 - 0x4000 6BFF 0x4000 6400 - 0x4000 67FF 0x4000 5C00 - 0x4000 63FF 0x4000 5800 - 0x4000 5BFF 0x4000 5400 - 0x4000 57FF 0x4000 5000 - 0x4000 53FF 0x4000 4C00 - 0x4000 4FFF 0x4000 4800 - 0x4000 4BFF 0x4000 4400 - 0x4000 47FF 0x4000 4000 - 0x4000 43FF 0x4000 3C00 - 0x4000 3FFF 0x4000 3800 - 0x4000 3BFF 0x4000 3400 - 0x4000 37FF 0x4000 3000 - 0x4000 33FF 0x4000 2C00 - 0x4000 2FFF 0x4000 2800 - 0x4000 2BFF 0x4000 1800 - 0x4000 27FF 0x4000 1400 - 0x4000 17FF 0x4000 1000 - 0x4000 13FF 0x4000 0C00 - 0x4000 0FFF 0x4000 0800 - 0x4000 0BFF 0x4000 0400 - 0x4000 07FF 0x4000 0000 - 0x4000 03FF
0xFFFF FFFF
0xE000 0000 0xDFFF FFFF
512-Mbyte block 7 Cor tex-M3's internal peripherals 512-Mbyte block 6 Not used
APB2
0xC000 0000 0xBFFF FFFF 512-Mbyte block 5 Not used 0xB000 0000 0xAFFF FFFF 512-Mbyte block 4 Not used
0x8000 0000 0x7FFF FFFF 512-Mbyte block 3 Not used 0x6000 0000 0x5FFF FFFF 512-Mbyte block 2 Peripherals 0x4000 0000 0x3FFF FFFF 512-Mbyte block 1 SRAM 0x2000 0000 0x1FFF FFFF 512-Mbyte block 0 Code 0x0000 0000 Reser ved SRAM (aliased by bit-banding) Option bytes System memory Reser ved Flash Reser ved Aliased to Flash or system memor y depending on BOOT pins
APB1
SPI2/I2S2 Reserved IWDG WWDG RTC Reserved TIM7 TIM6 TIM5 TIM4 TIM3 TIM2
0x3FFF FFFF 0x2001 0000 0x2000 FFFF 0x2000 0000 0x1FFF F800 - 0x1FFF FFFF 0x1FFF B000 - 0x1FFF F7FF 0x1FFF AFFF 0x0804 0000 0x0803 FFFF 0x0800 0000 0x07FF FFFF 0x0004 0000 0x0003 FFFF 0x0000 0000
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Electrical characteristics
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5
5.1
Electrical characteristics
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
5.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3).
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.3 V (for the 2 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2).
5.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
5.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 6.
5.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 7. Figure 6. Pin loading conditions Figure 7. Pin input voltage
STM32F10xxx pin C = 50 pF
VIN
STM32F10xxx pin
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Electrical characteristics
5.1.6
Power supply scheme
Figure 8. Power supply scheme
VBAT
1. 8-3. 6V
Po wer swi tch
Backup circuitry (OSC32K,RTC, Wake-up logic Backup registers)
O UT
Level shifter
GP I/Os
IN
IO Logic Kernel logic (CPU, Digital & Memories)
VDD
VDD 1/2/3/4/5 VSS
Regulator
5 × 100 nF + 1 × 4.7 F
VDD VREF
1/2/3/4/5
VDDA VREF+ VREFVSSA
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10 nF + 1 F
10 nF + 1 F
ADC
An alo g: RCs, PLL, ...
Caution:
In Figure 8, the 4.7 F capacitor must be connected to VDD3.
5.1.7
Current consumption measurement
Figure 9. Current consumption measurement scheme
IDD_VBAT VBAT
IDD VDD
VDDA
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Electrical characteristics
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5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 6: Voltage characteristics, Table 7: Current characteristics, and Table 8: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 6.
Symbol VDDVSS VIN |VDDx| |VSSX VSS| VESD(HBM)
Voltage characteristics
Ratings External main supply voltage (including VDDA and VDD)(1) Input voltage on five volt tolerant pin(2) Input voltage on any other pin(2) Variations between different VDD power pins Variations between all the different ground pins Electrostatic discharge voltage (human body model) Min 0.3 VSS 0.3 VSS 0.3 Max 4.0 +5.5 VDD+0.3 50 mV 50 see Section 5.3.11: Absolute maximum ratings (electrical sensitivity) V Unit
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded (see Table 7: Current characteristics). This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN> VINmax while a negative injection is induced by VIN < VSS.
Table 7.
Symbol IVDD IVSS IIO
Current characteristics
Ratings Total current into VDD/VDDA power lines (source)(1) Total current out of VSS ground lines (sink)(1) Max. 150 150 25 25 mA Injected current on NRST pin 5 5 5 25 Unit
Output current sunk by any I/O and control pin Output current source by any I/Os and control pin
IINJ(PIN) (2)(3) IINJ(PIN)(2)
Injected current on HSE OSC_IN and LSE OSC_IN pins Injected current on any other pin(4)
Total injected current (sum of all I/O and control pins)(4)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. 3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.16: 12-bit ADC characteristics. 4. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with IINJ(PIN) maximum current injection on four I/O port pins of the device.
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STM32F105xx, STM32F107xx Table 8. Thermal characteristics
Ratings Storage temperature range Maximum junction temperature
Electrical characteristics
Symbol TSTG TJ
Value 65 to +150 150
Unit C C
5.3
5.3.1
Operating conditions
General operating conditions
Table 9.
Symbol fHCLK fPCLK1 fPCLK2 VDD
General operating conditions
Parameter Internal AHB clock frequency Internal APB1 clock frequency Internal APB2 clock frequency Standard operating voltage Analog operating voltage (ADC not used) Analog operating voltage (ADC used) Backup operating voltage LFBGA100 Power dissipation at TA = 85 C for suffix 6 or TA = 105 C for LQFP100 suffix 7(3) LQFP64 Power dissipation at TA = 85 C LQFP100 for suffix 6 or TA = 105 C for LQFP64 suffix 7(4) Ambient temperature for 6 suffix version Maximum power dissipation Low power dissipation
(5)
Conditions
Min 0 0 0 2 2
Max 72 36 72 3.6 3.6
Unit
MHz
V
VDDA
(1)
Must be the same potential as VDD(2)
V 2.4 1.8 3.6 3.6 500 434 444 434 mW 444 40 40 40 40 40 40 85 C 105 105 C 125 105 C 125 mW V
VBAT
PD
PD
TA Ambient temperature for 7 suffix version TJ Junction temperature range 7 suffix version
1. When the ADC is used, refer to Table 51: ADC characteristics. 2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and operation. 3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax. 4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax. 5. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax.
Maximum power dissipation Low power dissipation 6 suffix version
(5)
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Electrical characteristics
STM32F105xx, STM32F107xx
5.3.2
Operating conditions at power-up / power-down
Subject to general operating conditions for TA. Table 10.
Symbol tVDD
Operating conditions at power-up / power-down
Parameter VDD rise time rate VDD fall time rate Conditions Min 0 20 Max Unit s/V
5.3.3
Embedded reset and power control block characteristics
The parameters given in Table 11 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 11.
Symbol
Embedded reset and power control block characteristics
Parameter Conditions PLS[2:0]=000 (rising edge) PLS[2:0]=000 (falling edge) PLS[2:0]=001 (rising edge) PLS[2:0]=001 (falling edge) PLS[2:0]=010 (rising edge) PLS[2:0]=010 (falling edge) PLS[2:0]=011 (rising edge) Min 2.1 2 2.19 2.09 2.28 2.18 2.38 2.28 2.47 2.37 2.57 2.47 2.66 2.56 2.76 2.66 Typ 2.18 2.08 2.28 2.18 2.38 2.28 2.48 2.38 2.58 2.48 2.68 2.58 2.78 2.68 2.88 2.78 100 Falling edge Rising edge 1.8(1) 1.84 1.88 1.92 40 1 2.5 4.5 1.96 2.0 Max 2.26 2.16 2.37 2.27 2.48 2.38 2.58 2.48 2.69 2.59 2.79 2.69 2.9 2.8 3 2.9 Unit V V V V V V V V V V V V V V V V mV V V mV ms
VPVD
Programmable voltage detector level selection
PLS[2:0]=011 (falling edge) PLS[2:0]=100 (rising edge) PLS[2:0]=100 (falling edge) PLS[2:0]=101 (rising edge) PLS[2:0]=101 (falling edge) PLS[2:0]=110 (rising edge) PLS[2:0]=110 (falling edge) PLS[2:0]=111 (rising edge) PLS[2:0]=111 (falling edge)
VPVDhyst(2) VPOR/PDR VPDRhyst
(2) (2)
PVD hysteresis Power on/power down reset threshold PDR hysteresis Reset temporization
TRSTTEMPO
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value. 2. Guaranteed by design, not tested in production.
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Electrical characteristics
5.3.4
Embedded reference voltage
The parameters given in Table 12 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 12.
Symbol VREFINT
Embedded internal reference voltage
Parameter Internal reference voltage Conditions 40 C < TA < +105 C 40 C < TA < +85 C Min 1.16 1.16 Typ 1.20 1.20 5.1 Max 1.26 1.24 17.1(2) Unit V V s
ADC sampling time when TS_vrefint(1) reading the internal reference voltage Internal reference voltage VRERINT(2) spread over the temperature range TCoeff(2) Temperature coefficient VDD = 3 V 10 mV
10 100
mV ppm/C
1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production.
5.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 9: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code.
Maximum current consumption
The MCU is placed under the following conditions:
All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except when explicitly mentioned The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above) Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK
The parameters given in Table 13, Table 14 and Table 15 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9.
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Electrical characteristics Table 13.
STM32F105xx, STM32F107xx
Maximum current consumption in Run mode, code with data processing running from Flash
Max(1) Parameter Conditions fHCLK TA = 85 C 72 MHz 48 MHz External clock(2), all peripherals enabled 36 MHz 24 MHz 16 MHz 68 49 38.7 27.3 20.2 10.2 32.7 25 20.3 14.8 11.2 6.6 TA = 105 C 68.4 49.2 38.9 27.9 20.5 10.8 mA 72 MHz 48 MHz External clock(3), all 36 MHz peripherals disabled 24 MHz 16 MHz 8 MHz 32.9 25.2 20.6 15.1 11.7 7.2 Unit
Symbol
IDD
Supply current in Run mode
8 MHz
1. Based on characterization, not tested in production. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Table 14.
Maximum current consumption in Run mode, code with data processing running from RAM
Max(1) Parameter Conditions fHCLK 72 MHz 48 MHz External clock(2), all peripherals enabled 36 MHz 24 MHz 16 MHz Unit TA = 85 C 65.5 45.4 35.5 25.2 18 10.5 31.4 27.8 17.6 13.1 10.2 6.1 TA = 105 C 66 46 36.1 25.6 18.5 11 31.9 28.2 18.3 13.8 10.9 7.8 mA
Symbol
IDD
Supply current in Run mode
8 MHz 72 MHz 48 MHz External clock(3), all 36 MHz peripherals disabled 24 MHz 16 MHz 8 MHz
1. Based on characterization, tested in production at VDD max, fHCLK max.. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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STM32F105xx, STM32F107xx Table 15.
Symbol
Electrical characteristics
Maximum current consumption in Sleep mode, code running from Flash or RAM
Max(1) Parameter Conditions fHCLK 72 MHz 48 MHz External clock(2), all peripherals enabled 36 MHz 24 MHz 16 MHz Unit TA = 85 C 48.4 33.9 26.7 19.3 14.2 8.7 10.1 8.3 7.5 6.6 6 2.5 TA = 105 C 49 34.4 27.2 19.8 14.8 9.1 10.6 8.75 8 7.1 6.5 3 mA
IDD
Supply current in Sleep mode
8 MHz 72 MHz 48 MHz External clock(3), all peripherals disabled 36 MHz 24 MHz 16 MHz 8 MHz
1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Table 16.
Symbol
Typical and maximum current consumptions in Stop and Standby modes
Typ(1) Parameter Conditions Max VDD/VBAT VDD/VBAT VDD/VBAT TA = TA = Unit = 2.0 V = 2.4 V = 3.3 V 85 C 105 C
Regulator in Run mode, low-speed and high-speed internal RC oscillators and high-speed oscillator Supply current OFF (no independent watchdog) in Stop mode Regulator in Low Power mode, lowspeed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) Low-speed internal RC oscillator and independent watchdog ON Supply current Low-speed internal RC oscillator in Standby ON, independent watchdog OFF mode Low-speed internal RC oscillator and independent watchdog OFF, lowspeed oscillator and RTC OFF Backup IDD_VBAT domain supply Low-speed oscillator and RTC ON current
1. Typical values are measured at TA = 25 C. 2. Based on characterization, not tested in production.
32
33
600
1300
25
26
590
1280
IDD
3 2.8
3.8 3.6
5(2)
6.5(2)
A
1.9
2.1
1.1
1.2
1.4
2.1(2)
2.3(2)
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Electrical characteristics
STM32F105xx, STM32F107xx
Figure 10. Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values
2.5
Consumption (A)
2 1.5 1 0.5 0 40 C 25 C 70 C 85 C 105 C Temperature (C)
1.8 V 2V 2.4 V 3.3 V 3.6 V
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Figure 11. Typical current consumption in Stop mode with regulator in Run mode versus temperature at different VDD values
900.00 800.00 700.00
Cons umpt ion (A)
600.00 500.00 3.6 V 400.00 300.00 200.00 100.00 0.00 40 C 25 C 85 C 105 C
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3.3 V 3V 2.7 V 2.4 V
Temperature (C)
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Electrical characteristics
Figure 12. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at different VDD values
900.00 800.00
Consumption (A)
700.00 600.00 500.00 3.6 V 400.00 300.00 200.00 100.00 0.00 40 C 25 C 85 C 105 C
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3.3 V 3V 2.7 V 2.4 V
Temperature (C)
Figure 13. Typical current consumption in Standby mode versus temperature at different VDD values
4.50 4.00 3.50
Consumption (A)
3.00 2.50 2.00 1.50 1.00 0.50 0.00 40 C 25 C 85 C 105 C
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3.6 V 3.3 V 3V 2.7 V 2.4 V
Temperature (C)
Typical current consumption
The MCU is placed under the following conditions:
All I/O pins are in input mode with a static value at VDD or VSS (no load). All peripherals are disabled except if it is explicitly mentioned. The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above). Ambient temperature and VDD supply voltage conditions summarized in Table 9. Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling)
When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK = fPCLK2/4
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Electrical characteristics Table 17.
STM32F105xx, STM32F107xx
Typical current consumption in Run mode, code with data processing running from Flash
Typ(1) Parameter Conditions fHCLK Unit
Symbol
All peripherals All peripherals disabled enabled(2) 47.3 32 24.6 16.8 11.8 5.9 3.7 2.5 1.8 1.5 1.3 23.9 16.1 11.1 5.6 3.1 1.8 1.16 0.8 0.6 28.3 19.6 15.4 10.6 7.4 3.7 2.9 2 1.53 1.3 1.2 14.8 9.7 6.7 3.8 2.1 1.3 0.9 0.67 0.5
72 MHz 48 MHz 36 MHz 24 MHz 16 MHz External clock(3) 8 MHz 4 MHz 2 MHz 1 MHz IDD Supply current in Run mode 500 kHz 125 kHz 36 MHz 24 MHz Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 125 kHz
1. Typical values are measures at TA = 25 C, VDD = 3.3 V.
mA
mA
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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STM32F105xx, STM32F107xx Table 18.
Electrical characteristics
Typical current consumption in Sleep mode, code running from Flash or RAM
Typ(1) Conditions fHCLK Unit
Symbol Parameter
All peripherals All peripherals enabled(2) disabled 28.2 19 14.7 10.1 6.7 3.2 2.3 1.7 1.5 1.3 1.2 13.7 9.3 6.3 2.7 1.6 1 0.8 0.6 0.5 6 4.2 3.4 2.5 2 1.3 1.2 1.16 1.1 1.05
72 MHz 48 MHz 36 MHz 24 MHz 16 MHz External clock(3) 8 MHz 4 MHz 2 MHz 1 MHz IDD Supply current in Sleep mode 500 kHz 125 kHz 36 MHz 24 MHz 16 MHz Running on high 8 MHz speed internal RC (HSI), AHB prescaler 4 MHz used to reduce the 2 MHz frequency 1 MHz 500 kHz 125 kHz
1. Typical values are measures at TA = 25 C, VDD = 3.3 V.
mA 1.05 2.6 1.8 1.3 0.6 0.5 0.46 0.44 0.43 0.42
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 19. The MCU is placed under the following conditions:
all I/O pins are in input mode with a static value at VDD or VSS (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption with all peripherals clocked off with one peripheral clocked on (with only the clock applied)
ambient operating temperature and VDD supply voltage conditions summarized in Table 6
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Electrical characteristics Table 19. Peripheral current consumption(1) Peripheral AHB
ETH_MAC OTG_FS TIM2 TIM3 TIM4 TIM5 TIM6 TIM7 SPI2 USART2 APB1 USART3 UART4 UART5 I2C1 I2C2 CAN1 CAN2 DAC GPIO A GPIO B GPIO C GPIO D GPIO E APB2 ADC1
(2)
STM32F105xx, STM32F107xx
Typical consumption at 25 C
5.2 7.7 1.5 1.5 1.5 1.5 0.6 0.3 0.2
Unit
mA 0.5 0.5 0.5 0.5 0.5 0.5 0.8 0.8 0.4 0.5 0.5 0.5 0.5 0.5 mA 2.1 2.0 1.7 0.4 0.9
ADC2(2) TIM1 SPI1 USART1
1. fHCLK = 72 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral. 2. Specific conditions for ADC: fHCLK = 56 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/4, ADON bit in the ADC_CR2 register is set to 1.
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Electrical characteristics
5.3.6
External clock source characteristics
High-speed external user clock generated from an external source
The characteristics given in Table 20 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 9. Table 20.
Symbol fHSE_ext VHSEH VHSEL tw(HSE) tw(HSE) tr(HSE) tf(HSE) Cin(HSE)
High-speed external user clock characteristics
Parameter External user clock source frequency(1) OSC_IN input pin high level voltage OSC_IN input pin low level voltage OSC_IN high or low time(1) OSC_IN rise or fall time(1) OSC_IN input capacitance(1) 45 VSS VIN VDD 5 55 1 Conditions Min 1 0.7VDD VSS 16 ns 20 pF % A Typ 8 Max 50 VDD 0.3VDD Unit MHz
V
DuCy(HSE) Duty cycle IL OSC_IN Input leakage current
1. Guaranteed by design, not tested in production.
Low-speed external user clock generated from an external source
The characteristics given in Table 21 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 9. Table 21.
Symbol fLSE_ext VLSEH VLSEL tw(LSE) tw(LSE) tr(LSE) tf(LSE) Cin(LSE)
Low-speed external user clock characteristics
Parameter User External clock source frequency(1) OSC32_IN input pin high level voltage OSC32_IN input pin low level voltage OSC32_IN high or low time(1) OSC32_IN rise or fall time(1) 5 30 VSS VIN VDD 70 1 0.7VDD VSS 450 ns 50 pF % A Conditions Mi n Typ 32.768 Max 1000 VDD V 0.3VDD Unit kHz
OSC32_IN input capacitance(1)
DuCy(LSE) Duty cycle IL OSC32_IN Input leakage current
1. Guaranteed by design, not tested in production.
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Figure 14. High-speed external clock source AC timing diagram
VHSEH 90% VHSEL 10% tr(HSE) THSE tf(HSE) tW(HSE) tW(HSE) t
External clock source
fHSE_ext OSC _I N
IL STM32F10xxx ai14127b
Figure 15. Low-speed external clock source AC timing diagram
VLSEH 90% VLSEL 10% tr(LSE) TLSE tf(LSE) tW(LSE) tW(LSE) t
External clock source
fLSE_ext
OSC32_I N
IL STM32F10xxx ai14140c
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 3 to 25 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 22. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
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STM32F105xx, STM32F107xx Table 22.
Symbol fOSC_IN RF C
Electrical characteristics
HSE 3-25 MHz oscillator characteristics(1) (2)
Parameter Oscillator frequency Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) HSE driving current Oscillator transconductance Star tup time RS = 30 VDD = 3.3 V, VIN = VSS with 30 pF load Star tup VDD is stabilized 25 2 Conditions Mi n 3 200 30 Typ Max 25 Unit MHz k pF
i2 gm tSU(HSE(4)
1
mA mA/V ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization, not tested in production. 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 16). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. Figure 16. Typical application with an 8 MHz crystal
Resonator with integrated capacitors CL1 OSC_IN 8 MH z resonator CL2 REXT(1) OSC_OU T RF Bias controlled gain STM32F10xxx ai14128b fH S E
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 23. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
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resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 23.
Symbol RF C(2) I2 gm tSU(LSE)(4)
LSE oscillator characteristics (fLSE = 32.768 kHz) (1)
Parameter Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) LSE driving current Oscillator Transconductance star tup time VDD is stabilized RS = 30 k VDD = 3.3 V, VIN = VSS 5 3 Conditions Min Typ 5 15 1.4 Max Unit M pF A A/V s
1. Based on characterization, not tested in production. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for ST microcontrollers". 3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details 4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer
Note:
For CL1 and CL2 it is recommended to use high-quality external ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator (see Figure 17). CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF, then CL1 = CL2 = 8 pF. Figure 17. Typical application with a 32.768 kHz crystal
Caution:
Resonator with integrated capacitors CL1 OSC32_IN 32.768 KH z resonator CL2 RF OSC32_OU T Bias controlled gain STM32F10xxx fLSE
ai14129b
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5.3.7
Internal clock source characteristics
The parameters given in Table 24 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9.
High-speed internal (HSI) RC oscillator
Table 24.
Symbol f HSI
HSI oscillator characteristics (1)
Parameter Frequency User-trimmed with the RCC_CR register(2) Conditions Min Typ 8 1(3) 2 1.5 1.3 1.1 1 80 2.5 2.2 2 1.8 2 100 Max Unit MHz % % % % % s A
ACCHSI
Accuracy of the HSI oscillator Factorycalibrated(4)
TA = 40 to 105 C TA = 10 to 85 C TA = 0 to 70 C TA = 25 C
tsu(HSI)(4) IDD(HSI)(4)
HSI oscillator startup time HSI oscillator power consumption
1. VDD = 3.3 V, TA = 40 to 105 C unless otherwise specified. 2. Refer to application note AN2868 "STM32F10xxx internal RC oscillator (HSI) calibration" available from the ST website www.st.com. 3. Guaranteed by design, not tested in production. 4. Based on characterization, not tested in production.
Low-speed internal (LSI) RC oscillator
Table 25.
Symbol fLSI(2) tsu(LSI)
(3)
LSI oscillator characteristics (1)
Parameter Frequency LSI oscillator startup time LSI oscillator power consumption 0.65 Min 30 Typ 40 Max 60 85 1.2 Unit kHz s A
IDD(LSI)(3)
1. VDD = 3 V, TA = 40 to 105 C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production.
Wakeup time from low-power mode
The wakeup times given in Table 26 is measured on a wakeup phase with a 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode:
Stop or Standby mode: the clock source is the RC oscillator Sleep mode: the clock source is the clock that was set before entering Sleep mode.
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All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 26. Low-power mode wakeup timings
Parameter Wakeup from Sleep mode Wakeup from Stop mode (regulator in run mode) Wakeup from Stop mode (regulator in low power mode) Wakeup from Standby mode Typ 1.8 3.6 s 5.4 50 s Unit s
Symbol tWUSLEEP(1) tWUSTOP(1) tWUSTDBY(1)
1. The wakeup times are measured from the wakeup event to the point in which the user application code reads the first instruction.
5.3.8
PLL, PLL2 and PLL3 characteristics
The parameters given in Table 27 and Table 28 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 9. Table 27.
Symbol PLL input clock(2) fPLL_IN fPLL_OUT fVCO_OUT tLOCK Jitter Pulse width at high level PLL multiplier output clock PLL VCO output PLL lock time Cycle-to-cycle jitter
PLL characteristics
Parameter Min(1) 3 30 18 36 72 144 350 300 Max(1) 12 Unit MHz ns MHz MHz s ps
1. Based on characterization, not tested in production. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT.
Table 28.
Symbol
PLL2 and PLL3 characteristics
Parameter PLL input clock
(2)
Min(1) 3 30 40 80
Max(1) 5
Unit MHz ns
fPLL_IN fPLL_OUT fVCO_OUT tLOCK Jitter
Pulse width at high level PLL multiplier output clock PLL VCO output PLL lock time Cycle-to-cycle jitter
74 148 350 400
MHz MHz s ps
1. Based on characterization, not tested in production. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT.
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5.3.9
Memory characteristics
Flash memory
The characteristics are given at TA = 40 to 105 C unless otherwise specified. Table 29.
Symbol tprog t ERASE tME
Flash memory characteristics
Parameter Conditions Min(1) 40 20 20 Typ 52.5 Max(1) 70 40 40 20 Unit s ms ms mA
16-bit programming time TA40 to +105 C Page (1 KB) erase time Mass erase time TA 40 to +105 C TA 40 to +105 C Read mode fHCLK = 72 MHz with 2 wait states, VDD = 3.3 V
IDD
Supply current
Write / Erase modes fHCLK = 72 MHz, VDD = 3.3 V Power-down mode / Halt, VDD = 3.0 to 3.6 V
5 50 2 3.6
mA A V
Vprog
Programming voltage
1. Guaranteed by design, not tested in production.
Table 30.
Symbol
Flash memory endurance and data retention
Value Parameter Conditions TA = 40 to +85 C (6 suffix versions) TA = 40 to +105 C (7 suffix versions) 1 kcycle(2) at TA = 85 C
(2)
Min(1) 10 30 10 20
Unit Typ Max kcycles
N END
Endurance
tRET
Data retention
1 kcycle 10
at TA = 105 C at TA = 55 C
Years
kcycles(2)
1. Based on characterization, not tested in production. 2. Cycling performed over the whole temperature range.
5.3.10
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
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Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in Table 31. They are based on the EMS levels and classes defined in application note AN1709. Table 31.
Symbol
EMS characteristics
Parameter Conditions Level/ Class 2B
VFESD
VDD 3.3 V, LQFP100, TA = +25 C, Voltage limits to be applied on any I/O pin to fHCLK = 75 MHz, conforms to induce a functional disturbance IEC 61000-4-2 Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD3.3 V, LQFP100, TA = +25 C, fHCLK = 75 MHz, conforms to IEC 61000-4-2
VEFTB
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as:
Corrupted program counter Unexpected reset Critical Data corruption (control registers...)
Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
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Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. Table 32.
Symbol
EMI characteristics
Parameter Conditions Monitored frequency band 0.1 to 30 MHz Max vs. [fHSE/fHCLK] Unit 8/48 MHz 9 26 25 4 8/72 MHz 9 13 31 4 dBV
SEMI
Peak level
VDD 3.3 V, TA 25 C, LQFP100 package compliant with IEC61967-2
30 to 130 MHz 130 MHz to 1GHz SAE EMI Level
5.3.11
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 33.
Symbol VESD(HBM) VESD(CDM)
ESD absolute maximum ratings
Ratings Electrostatic discharge voltage (human body model) Electrostatic discharge voltage (charge device model) Conditions TA +25 C conforming to JESD22-A114 TA +25 C conforming to JESD22-C101 Class Maximum value(1) 2 II 2000 V 500 Unit
1. Based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up performance:
A supply overvoltage is applied to each power supply pin A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 34.
Symbol LU
Electrical sensitivities
Parameter Static latch-up class Conditions TA +105 C conforming to JESD78A Class II level A
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5.3.12
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 35 are derived from tests performed under the conditions summarized in Table 9. All I/Os are CMOS and TTL compliant.
Table 35.
Symbol
I/O static characteristics
Parameter Conditions Min 0.5 0.5 0.41 (VDD2) +1.3 0.42 (VDD2) +1 200 5% VDD(3) VSS VIN VDD Standard I/Os VIN= 5 V, I/O FT 1 A 3 30 8 VIN VDD 30 8 40 11 40 11 5 50 15 50 15 pF k k Typ Max 0.28 (VDD2) +0.8 0.32 (VDD2) +0.75 V VDD+0.5 5.5 mV mV Unit
Standard I/O input low level voltage VIL I/O FT(1) input low level voltage Standard I/O input high level voltage VIH I/O FT(1) input high level voltage Standard IO Schmitt trigger voltage hysteresis(2) IO FT Schmitt trigger voltage hysteresis(2) Input leakage current (4)
Vhys
Ilkg
RPU
All pins except for Weak pull-up PA10 equivalent resistor(5) PA10 All pins except for Weak pull-down PA10 equivalent resistor(5) PA10 I/O pin capacitance
VIN VSS
RPD CIO
1. FT = 5V tolerant. To sustain a voltage higher than VDD+0.5 the internal pull-up/pull-down resistors must be disabled. 2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production. 3. With a minimum of 100 mV. 4. Leakage could be higher than max. if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order).
All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 18 and Figure 19 for standard I/Os, and in Figure 20 and Figure 21 for 5 V tolerant I/Os.
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STM32F105xx, STM32F107xx Figure 18. Standard I/O input characteristics - CMOS port
Electrical characteristics
Figure 19. Standard I/O input characteristics - TTL port
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Electrical characteristics Figure 20. 5 V tolerant I/O input characteristics - CMOS port
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Figure 21. 5 V tolerant I/O input characteristics - TTL port
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Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/-20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2:
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 7). The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 7).
Output voltage levels
Unless otherwise specified, the parameters given in Table 36 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. All I/Os are CMOS and TTL compliant. Table 36.
Symbol VOL(1) VOH(2) VOL (1) VOH (2) VOL(1)(3) VOH(2)(3) VOL(1)(3) VOH(2)(3)
Output voltage characteristics
Parameter Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time Conditions TTL port IIO = +8 mA 2.7 V < VDD < 3.6 V CMOS port IIO =+ 8mA 2.7 V < VDD < 3.6 V Min Max 0.4 V VDD0.4 0.4 V 2.4 1.3 V VDD1.3 0.4 V VDD0.4 Unit
IIO = +20 mA 2.7 V < VDD < 3.6 V
IIO = +6 mA 2 V < VDD < 2.7 V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 3. Based on characterization data, not tested in production.
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Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 22 and Table 37, respectively. Unless otherwise specified, the parameters given in Table 37 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 37. I/O AC characteristics(1)
Parameter Conditions Min Max 2 125(3) CL = 50 pF, VDD = 2 V to 3.6 V 125(3) 10 25(3) CL = 50 pF, VDD = 2 V to 3.6 V 25(3) CL = 30 pF, VDD = 2.7 V to 3.6 V Fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V CL = 30 pF, VDD = 2.7 V to 3.6 V 11 tf(IO)out Output high to low level fall time CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V CL = 30 pF, VDD = 2.7 V to 3.6 V tr(IO)out Output low to high level rise time Pulse width of external signals detected by the EXTI controller CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V 50 30 20 5(3) 8(3) 12(3) 5(3) 8(3) 12(3) ns MHz MHz MHz ns MHz ns Unit MHz
MODEx[1:0] Symbol bit value(1)
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 10 tf(IO)out tr(IO)out Output high to low level fall time Output low to high level rise time
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 01 tf(IO)out tr(IO)out Output high to low level fall time Output low to high level rise time
-
tEXTIpw
10
ns
1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure 22. 3. Guaranteed by design, not tested in production.
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STM32F105xx, STM32F107xx Figure 22. I/O AC characteristics definition
Electrical characteristics
90% 5 0% 1 0% E XT ERNA L O UTP UT O N 50pF tr ( I O ) o u t
10% 50% 90% tr ( I O) o u t T
Maxi mum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF
ai14131
5.3.13
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 35). Unless otherwise specified, the parameters given in Table 38 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 38.
Symbol VIL(NRST)(1) VIH(NRST)(1) Vhys(NRST) RPU VF(NRST)
(1)
NRST pin characteristics
Parameter NRST Input low level voltage NRST Input high level voltage NRST Schmitt trigger voltage hysteresis Weak pull-up equivalent resistor(2) NRST Input filtered pulse VDD > 2.7 V 300 VIN VSS 30 Conditions Mi n 0.5 2 200 40 50 100 Typ Ma x 0.8 V VDD+0.5 mV k ns ns Unit
VNF(NRST)(1) NRST Input not filtered pulse
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order).
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Electrical characteristics Figure 23. Recommended NRST pin protection
STM32F105xx, STM32F107xx
External reset circuit(1) NRST(2)
VDD RPU Filter Internal reset
0.1 F
STM32F10x
ai14132d
2. The reset network protects the device against parasitic resets. 3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 38. Otherwise the reset will not be taken into account by the device.
5.3.14
TIM timer characteristics
The parameters given in Table 39 are guaranteed by design. Refer to Section 5.3.12: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 39.
Symbol tres(TIM)
TIMx(1) characteristics
Parameter Timer resolution time fTIMxCLK = 72 MHz Timer external clock frequency on CH1 to CH4 f TIMxCLK = 72 MHz Timer resolution 16-bit counter clock period 1 when internal clock is fTIMxCLK = 72 MHz 0.0139 selected 13.9 0 0 fTIMxCLK/2 36 16 65536 910 65536 × 65536 Conditions Min 1 Max Unit tTIMxCLK ns MHz MHz bit tTIMxCLK s tTIMxCLK s
fEXT ResTIM tCOUNTER
tMAX_COUNT Maximum possible count
fTIMxCLK = 72 MHz
59.6
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4 and TIM5 timers.
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5.3.15
Communications interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Table 40 are derived from tests performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 9. The STM32F105xx and STM32F107xx I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 40. Refer also to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 40.
Symbol tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) tsu(STO) tw(STO:STA) Cb
I2C characteristics
Standard mode I2C(1) Parameter Min SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time Star t condition hold time Repeated Start condition setup time Stop condition setup time Stop to Start condition time (bus free) Capacitive load for each bus line 4.0 4.7 4.0 4.7 400 4.7 4.0 250 0(3) 1000 300 0.6 s 0.6 0.6 1.3 400 s s pF Max Mi n 1.3 s 0.6 100 0(4) 20 + 0.1Cb 900(3) 300 300 ns Max Fast mode I2C(1)(2) Unit
1. Guaranteed by design, not tested in production. 2. fPCLK1 must be higher than 2 MHz to achieve standard mode I2C frequencies. It must be higher than 4 MHz to achieve the fast mode I2C frequencies and it must be a mulitple of 10 MHz in order to reach I2C fast mode maximum clock 400 kHz. 3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.
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Figure 24. I2C bus AC waveforms and measurement circuit
VDD 4 .7 k I²C bus VDD 4 .7 k
100 100
STM32F10x
SDA SCL
Star t repeated Star t tsu(STA) SD A tf(SDA) th(STA) SCL tw(SCLH) tr(SCL) tf(SCL) tsu(STO)
ai14133d
Star t
tr(SDA) tw(SCLL)
tsu(SDA) th(SDA) Stop
tsu(STO:STA)
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Table 41.
SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V)(1)(2)
I2C_CCR value fSCL (kHz) RP = 4.7 k 400 300 200 100 50 20 0x801E 0x8028 0x803C 0x00B4 0x0168 0x0384
2
1. RP = External pull-up resistance, fSCL = I C speed, 2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the tolerance on the achieved speed 2%. These variations depend on the accuracy of the external components used to design the application.
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I2S - SPI interface characteristics
Unless otherwise specified, the parameters given in Table 42 for SPI or in Table 43 for I2S are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 9. Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 42.
Symbol f SCK 1/tc(SCK) tr(SCK) tf(SCK) DuCy(SCK) tsu(NSS) th(NSS) tw(SCKH) tw(SCKL) tsu(MI) tsu(SI) th(MI) th(SI) ta(SO) tv(SO) tv(MO) th(SO) th(MO) Data output access time Data output valid time Data output valid time Data output hold time Master mode (after enable edge) 10 Data input hold time Slave mode Slave mode, fPCLK = 20 MHz Slave mode (after enable edge) Master mode (after enable edge) Slave mode (after enable edge) 32 5 3*tPCLK 34 8
SPI characteristics
Parameter SPI clock frequency Slave mode SPI clock rise and fall time SPI slave input clock duty cycle NSS setup time NSS hold time SCK high and low time Capacitive load: C = 30 pF Slave mode Slave mode Slave mode Master mode, fPCLK = 36 MHz, presc = 4 Master mode Data input setup time Slave mode Master mode 5 5 ns 30 4 tPCLK 2 tPCLK 50 4 60 18 8 70 ns % Conditions Master mode Min Max 18 MHz Unit
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Electrical characteristics Figure 25. SPI timing diagram - slave mode and CPHA = 0
STM32F105xx, STM32F107xx
NSS input tc(SCK) tSU(NSS) SCK Input CP HA= 0 CP OL=0 CP HA= 0 CP OL=1 ta(SO) M IS O OU T P U T tsu(SI) MOS I I N PU T M SB IN th(SI)
ai14134c
th(NSS)
tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) L SB OU T
tv(SO) MS B O U T
th(SO) BI T6 OU T
tdis(SO)
B I T1 IN
L SB IN
Figure 26. SPI timing diagram - slave mode and CPHA = 1(1)
NSS input tSU(NSS)
SCK Input
tc(SCK)
th(NSS)
CP HA=1 CP OL=0 CP HA=1 CP OL=1
tw(SCKH) tw(SCKL) tr(SCK) tf(SCK)
ta(SO) M IS O OU T P U T tsu(SI) MOS I I N PU T M SB IN
tv(SO) MS B O U T th(SI)
th(SO) BI T6 OU T
tdis(SO) L SB OU T
B I T1 IN
L SB IN
ai14135
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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STM32F105xx, STM32F107xx Figure 27. SPI timing diagram - master mode(1)
High NSS input tc(SCK)
SCK Input
Electrical characteristics
CP HA= 0 CP OL=0 CP HA= 0 CP OL=1
SCK Input
CP HA=1 CP OL=0 CP HA=1 CP OL=1 tsu(MI) M IS O INP U T MOS I OUTU T tw(SCKH) tw(SCKL) MS BIN th(MI) M SB OUT tv(MO) B I T1 OUT th(MO)
ai14136
tr(SCK) tf(SCK) BI T6 IN L SB IN
L SB OUT
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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Electrical characteristics Table 43.
Symbol fCK 1/tc(CK) t r(CK) tf(CK) tw(CKH)(1) tw(CKL)(1) tv(WS) (1) th(WS)
(1)
STM32F105xx, STM32F107xx
I2S characteristics
Parameter I2S clock frequency Conditions Master data: 16 bits, audio freq = 48 K Slave I2S clock rise and fall time I2S clock high time I S clock low time WS valid time WS hold time
2
Min 1.52 0
Max 1.54
Unit
MHz 6.5 8 317 333 3 320 336 ns
capacitive load CL = 50 pF Master fPCLK = 16 MHz, audio freq = 48 K Master mode I2S2 Master mode I2S3 I2S2 0 4 9 0 30 I2S2 Master receiver I2S3 10 3 8 2 4 2 4 23 33 29 27 8
0
tsu(WS) (1) th(WS)
(1)
WS setup time WS hold time I2S slave input clock duty cycle
Slave mode I2S3 Slave mode Slave mode
DuCy(SCK) tsu(SD_MR) (1)
70
%
Data input setup time tsu(SD_SR) (1) th(SD_MR)(1) Data input hold time th(SD_SR) (1)
(1)(3)
I2S2 Slave receiver I2S3 I2S2 Master receiver I2S3 I2S2 Slave receiver I2S3 Data output valid time Slave transmitter (after enable edge) Slave transmitter (after enable edge) Master transmitter (after enable edge) Master transmitter (after enable edge) I2S2 I2S3 I2S2 I2S3 I2S2 I2S3 I2S2 I2S3
ns
tv(SD_ST)
th(SD_ST) (1) tv(SD_MT) (1) th(SD_MT) (1)
Data output hold time
5 2 11 4
Data output valid time
Data output hold time
1. Based on design simulation and/or characterization results, not tested in production.
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STM32F105xx, STM32F107xx Figure 28. I2S slave timing diagram (Philips protocol)(1)
tc(CK) CK Input CP OL = 0
Electrical characteristics
CP OL = 1 tw(CKH) WS input tsu(WS) SDtransmit LSB transmit(2) tsu(SD_SR) SDreceive LSB receive(2) MSB receive MSB transmit tv(SD_ST) Bitn transmit th(SD_SR) Bitn receive LSB receive th(SD_ST) LSB transmit tw(CKL) th(WS)
ai14881b
1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.
Figure 29. I2S master timing diagram (Philips protocol)(1)
tf(CK)
tr(CK)
tc(CK) CK output CP OL = 0 tw(CKH) CP OL = 1 tv(WS) WS output tv(SD_MT) SDtransmit LSB transmit(2) tsu(SD_MR) SDreceive LSB receive(2) MSB receive MSB transmit Bitn transmit th(SD_MR) Bitn receive LSB receive th(SD_MT) LSB transmit tw(CKL) th(WS)
ai14884b
1. Based on characterization, not tested in production. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.
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Electrical characteristics
STM32F105xx, STM32F107xx
USB OTG FS characteristics
The USB OTG interface is USB-IF certified (Full-Speed). Table 44. USB OTG FS startup time
Parameter USB OTG FS transceiver startup time Max 1 Unit s
Symbol tSTARTUP(1)
1. Guaranteed by design, not tested in production.
Table 45.
Symbol
USB OTG FS DC electrical characteristics
Parameter USB OTG FS operating voltage I(USBDP, USBDM) Includes VDI range Conditions Min.(1) Typ. Max.(1) Unit 3.0(2) 0.2 0.8 1.3 RL of 1.5 k to 3.6 V(4) RL of 15 k to VSS(4) 2.8 17 VIN = VDD 0.65 VIN = VSS VIN = VSS 1.5 0.25 1.1 1.8 0.37 2.0 2.1 0.55 k 21 2.5 2.0 0.3 V 3.6 24 V 3.6 V
VDD Input levels
VDI(3) Differential input sensitivity VCM(3) VSE(3) Differential common mode range Single ended receiver threshold Static output level low Static output level high Pull-down resistance on PA11, PA12
Output levels
VOL VOH
RPD
Pull-down resistance on PA9 Pull-up resistance on PA12
RPU
Pull-up resistance on PA9
1. All the voltages are measured from the local ground potential. 2. The STM32F105xx and STM32F107xx USB OTG FS functionality is ensured down to 2.7 V but not the full USB OTG FS electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 3. Guaranteed by design, not tested in production. 4. RL is the load connected on the USB OTG FS drivers
Figure 30. USB OTG FS timings: definition of data signal rise and fall time
Crossover points Di fferen tial data lines V RS C VS S tf tr
ai14137
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Table 46. USB OTG FS electrical characteristics(1) Driver characteristics Symbol tr tf trfm VCRS Parameter Rise time(2) Fall time(2) Rise/ fall time matching Output signal crossover voltage Conditions CL = 50 pF CL = 50 pF tr/tf
Electrical characteristics
Min 4 4 90 1.3
Max 20 20 110 2.0
Unit ns ns % V
1. Guaranteed by design, not tested in production. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0).
Ethernet characteristics
Table 47 showns the Ethernet operating voltage. Table 47. Ethernet DC electrical characteristics
Parameter VDD Ethernet operating voltage Min.(1) 3.0 Max.(1) 3.6 Unit V
Symbol Input level
1. All the voltages are measured from the local ground potential.
Table 48 gives the list of Ethernet MAC signals for the SMI (station management interface) and Figure 31 shows the corresponding timing diagram. Figure 31. Ethernet SMI timing diagram
tMDC ETH_MDC td(MDIO) ETH_MDIO(O) tsu(MDIO) ETH_MDIO(I) th(MDIO)
ai15666c
Table 48.
Symbol t MDC td(MDIO) th(MDIO)
Dynamic characteristics: Ethernet MAC signals for SMI
Rating MDC cycle time (1.71 MHz, AHB = 72 MHz) MDIO write data valid time Min 583 13.5 35 0 Typ 583.5 14.5 Max 584 15.5 Unit ns ns ns ns
tsu(MDIO) Read data setup time Read data hold time
Table 49 gives the list of Ethernet MAC signals for the RMII and Figure 32 shows the corresponding timing diagram.
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Electrical characteristics Figure 32. Ethernet RMII timing diagram
RMII_REF_CLK td(TXEN) td(TXD) RMII_TX_EN RMII_TXD[1:0] tsu(RXD) tsu(CRS) RMII_RXD[1:0] RMII_CRS_DV tih(RXD) tih(CRS)
STM32F105xx, STM32F107xx
ai15667
Table 49.
Symbol tsu(RXD) tih(RXD) tsu(DV) tih(DV) td(TXEN) td(TXD)
Dynamic characteristics: Ethernet MAC signals for RMII
Rating Receive data setup time Receive data hold time Carrier sense set-up time Carrier sense hold time Transmit enable valid delay time Transmit data valid delay time Min 4 2 4 2 8 7 10 10 16 16 Typ Max Unit ns ns ns ns ns ns
Table 50 gives the list of Ethernet MAC signals for MII and Figure 32 shows the corresponding timing diagram. Figure 33. Ethernet MII timing diagram
MII_RX_CLK tsu(RXD) tsu(ER) tsu(DV) tih(RXD) tih(ER) tih(DV)
MII_RXD[3:0] MII_RX_DV MII_RX_ER
MII_TX_CLK td(TXEN) td(TXD) MII_TX_EN MII_TXD[3:0]
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STM32F105xx, STM32F107xx Table 50.
Symbol tsu(RXD) tih(RXD) tsu(DV) tih(DV) tsu(ER) tih(ER) td(TXEN) td(TXD)
Electrical characteristics
Dynamic characteristics: Ethernet MAC signals for MII
Rating Receive data setup time Receive data hold time Data valid setup time Data valid hold time Error setup time Error hold time Transmit enable valid delay time Transmit data valid delay time Min 10 10 10 10 10 10 14 13 16 16 18 20 Typ Max Unit ns ns ns ns ns ns ns ns
CAN (controller area network) interface
Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (CANTX and CANRX).
5.3.16
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 51 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 9.
Note: Table 51.
Symbol VDDA VREF+ IVREF f ADC fS(2)
It is recommended to perform a calibration after each power-up. ADC characteristics
Parameter Power supply Positive reference voltage Current on the VREF input pin ADC clock frequency Sampling rate fADC = 14 MHz 0.6 0.05 Conditions Min 2.4 2.4 160(1) Typ Max 3.6 VDDA 220(1) 14 1 823 17 0 (VSSA or VREFtied to ground) See Equation 1 and Table 52 for details VREF+ 50 1 8 fADC = 14 MHz 5.9 83 Unit V V A MHz MHz kHz 1/fADC V k k pF s 1/fADC
fTRIG(2) External trigger frequency VAIN Conversion voltage range(3)
RAIN(2) External input impedance RADC(2) Sampling switch resistance CADC(2) tCAL(2) Internal sample and hold capacitor Calibration time
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Electrical characteristics Table 51.
Symbol tlat(2) tlatr(2) tS(2) tSTAB(2) tCONV(2)
STM32F105xx, STM32F107xx
ADC characteristics (continued)
Parameter Conditions fADC = 14 MHz Min Typ Max 0.214 3 (4) fADC = 14 MHz 0.143 2 (4) fADC = 14 MHz 0.107 1.5 0 fADC = 14 MHz 1 0 17.1 239.5 1 18 Unit s 1/fADC s 1/fADC s 1/fADC s s 1/fADC
Injection trigger conversion latency
Regular trigger conversion latency
Sampling time Power-up time Total conversion time (including sampling time)
14 to 252 (tS for sampling +12.5 for successive approximation)
1. Based on characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 51.
Equation 1: RAIN max formula TS R AIN ------------------------------------------------------------- R A D C N+2 f A D C C A D C ln 2
The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 52.
RAIN max for fADC = 14 MHz(1)
Ts (cycles) tS (s) 0.11 0.54 0.96 2.04 2.96 3.96 5.11 17.1 0.4 5.9 11.4 25.2 37.2 50 NA NA RAIN max (k)
1.5 7.5 13.5 28.5 41.5 55.5 71.5 239.5
1. Based on characterization, not tested in production.
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STM32F105xx, STM32F107xx Table 53.
Symbol ET EO EG ED EL
Electrical characteristics
ADC accuracy - limited test conditions(1)
Parameter Total unadjusted error Offset error Gain error Differential linearity error Integral linearity error Test conditions fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 k, VDDA = 3 V to 3.6 V TA = 25 C Measurements made after ADC calibration Typ 1.3 1 0.5 0.7 0.8 Max(2) 2 1.5 1.5 1 1.5 LSB Unit
1. ADC DC accuracy values are measured after internal calibration. 2. Based on characterization, not tested in production.
Table 54.
Symbol ET EO EG ED EL
ADC accuracy(1) (2)
Parameter Total unadjusted error Offset error Gain error Differential linearity error Integral linearity error fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 k, VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration Test conditions Typ 2 1.5 1.5 1 1.5 Max(3) 5 2.5 3 2 3 LSB Unit
1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 3. Based on characterization, not tested in production.
Note:
ADC accuracy vs. negative injection current: Injecting a negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not affect the ADC accuracy.
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Electrical characteristics Figure 34. ADC accuracy characteristics
V V [1LSBIDEAL = REF+ (or DDA depending on package)] 4096 4096
EG 4095 4094 4093 (2) ET 7 6 5 4 3 2 1 0 1 VSSA 2 3 4 1 LSBIDEAL EO EL ED (3) (1)
STM32F105xx, STM32F107xx
(1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line
ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.
5
6
7
4093 4094 4095 4096 VDDA
ai14395b
Figure 35. Typical connection diagram using the ADC
VDD VT 0. 6 V AI Nx VT 0. 6 V IL1 A STM32F10xxx Sample and hold ADC conver ter RADC(1) 12-bit conver ter CADC(1)
RA IN(1)
VAIN Cparasitic
ai14139d
1. Refer to Table 51 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
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Electrical characteristics
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 36 or Figure 37, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 36. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32F10xxx
V REF+ (See note 1)
1 F // 10 nF
V DDA
1 F // 10 nF V SSA/V REF(See note 1)
ai14380c
1. VREF+ and VREF inputs are available only on 100-pin packages.
Figure 37. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32F10xxx
VREF+/VDDA (See note 1)
1 F // 10 nF
VREF/VSSA (See note 1)
ai14381c
1. VREF+ and VREF inputs are available only on 100-pin packages.
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Electrical characteristics
STM32F105xx, STM32F107xx
5.3.17
Table 55.
Symbol VDDA VREF+ VSSA RLOAD RO(1)
(1)
DAC electrical specifications
DAC characteristics
Parameter Analog supply voltage Reference supply voltage Ground Resistive load with buffer ON Impedance output with buffer OFF Min 2.4 2.4 0 5 Typ Max 3.6 3.6 0 Unit V V V k k When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 M Maximum capacitive load at DAC_OUT pin (when the buffer is ON). It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x155) to (0xEAB) at VREF+ = 2.4 V It gives the maximum output excursion of the DAC. VREF+ 1LSB V With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs With no load, middle code (0x800) on the inputs With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs Given for the DAC in 10-bit configuration. Given for the DAC in 12-bit configuration. Given for the DAC in 10-bit configuration. Given for the DAC in 12-bit configuration. VREF+ must always be below VDDA Comments
15
CLOAD(1)
Capacitive load
50
pF
DAC_OUT Lower DAC_OUT voltage min(1) with buffer ON DAC_OUT Higher DAC_OUT voltage with buffer ON max(1) DAC_OUT Lower DAC_OUT voltage min(1) with buffer OFF DAC_OUT Higher DAC_OUT voltage with buffer OFF max(1) IDDVREF+ DAC DC current consumption in quiescent mode (Standby mode)
0.2
V
VDDA 0.2 0.5
V mV
220
A
380 IDDA DAC DC current consumption in quiescent mode (Standby mode)
A
480
A
DNL(2)
Differential non linearity Difference between two consecutive code-1LSB) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023)
0.5
LSB
2 1
LSB LSB
INL(2)
4
LSB
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STM32F105xx, STM32F107xx Table 55.
Symbol
Electrical characteristics
DAC characteristics (continued)
Parameter Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) Min Typ Max 10 3 12 0.5 Unit mV LSB LSB % Comments Given for the DAC in 12-bit configuration Given for the DAC in 10-bit at VREF+ = 3.6 V Given for the DAC in 12-bit at VREF+ = 3.6 V Given for the DAC in 12bit configuration
Offset(2)
Gain error(2)
Gain error
Settling time (full scale: for a 10-bit input code transition (2) between the lowest and the tSETTLING highest input codes when DAC_OUT reaches final value 1LSB Update rate(2) Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB)
3
4
s
CLOAD 50 pF, RLOAD 5 k
1
MS/s
CLOAD 50 pF, RLOAD 5 k CLOAD 50 pF, RLOAD 5 k input code between lowest and highest possible ones. No RLOAD, CLOAD = 50 pF
Wakeup time from off state tWAKEUP(2) (Setting the ENx bit in the DAC Control register) PSRR+ (1) Power supply rejection ratio (to VDDA) (static DC measurement
6.5
10
s
67
40
dB
1. Guaranteed by design, not tested in production. 2. Guaranteed by characterization, not tested in production.
Figure 38. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC Buffer(1) R LOAD 12-bit digital to analog converter DACx_OUT
C LOAD
ai17157
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.
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Electrical characteristics
STM32F105xx, STM32F107xx
5.3.18
Temperature sensor characteristics
Table 56.
Symbol TL(1)
TS characteristics
Parameter VSENSE linearity with temperature 4.0 1.34 4 Min Typ Max Unit C mV/C V s s
1
4.3 1.43
2
4.6 1.52 10 17.1
Avg_Slope(1) Average slope V25(1) tSTART(2) TS_temp(3)(2) Voltage at 25 C Star tup time ADC sampling time when reading the temperature
1. Based on characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. Shortest sampling time can be determined in the application by multiple iterations.
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Package characteristics
6
6.1
Package characteristics
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
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Package characteristics
STM32F105xx, STM32F107xx
Figure 39. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package out line
Table 57.
LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data
mm inches(1) Max 1.700 0.270 1.085 0.30 0.80 0.45 9.85 0.50 10.00 7.20 9.85 10.00 7.20 0.80 1.40 0.12 0.15 0.08 100 10.15 0.0153 0.55 10.15 0.0007 0.0153 0.0008 0.0155 0.0111 0.0155 0.0111 0.0012 0.0022 0.0002 0.0002 0.0001 0.0157 0.0004 0.0017 0.0005 0.0012 0.0009 0.0157 Min Typ Max 0.0026
Dim. Min A A1 A2 A3 A4 b D D1 E E1 e F ddd eee fff N (number of balls) Typ
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
Figure 40. Recommended PCB design rules (0.80/0.75 mm pitch BGA)
0.37 mm 0.52 mm typ. (depends on solder Dsm mask registration tolerance Solder paste 0.37 mm aperture diameter Non solder mask defined pads are recommended 4 to 6 mils screen print
Dpad Dsm
Dpad
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Package characteristics
STM32F105xx, STM32F107xx Figure 42. Recommended footprint(1)(2)
Figure 41. LQFP100, 100-pin low-profile quad flat package outline(1)
0.25 mm 0.10 inch GAGE PLANE k D D1 D3
75 76 51
75
51
L L1 C
76
0.5
50
0.3
50
16.7
14.3
b E3 E1 E
100
26 1.2
1
100 26 25
25 12.3
Pin 1 1 identification e
ccc
C
16.7
A1 A2 A SEATING PLANE C
1L_ME
ai14906
1. Drawing is not to scale. 2. Dimensions are in millimeters.
Table 58.
Symbol
LQPF100 100-pin low-profile quad flat package mechanical data
millimeters Typ Mi n Max 1.60 0.05 1.40 0.22 1.35 0.17 0.09 16.00 14.00 12.00 16.00 14.00 12.00 0.50 0.60 1.00 3.5 0 0.08 7 0.45 0.75 15.80 13.80 16.20 14.20 15.80 13.80 0.15 1.45 0.27 0.20 16.20 14.20 0.6299 0.5512 0.4724 0.6299 0.5512 0.4724 0.0197 0.0236 0.0394 3.5 0 0.0031 7 0.0177 0.0295 0.622 0.5433 0.6378 0.5591 0.0551 0.0087 0.002 0.0531 0.0067 0.0035 0.622 0.5433 Typ inches(1) Min Max 0.063 0.0059 0.0571 0.0106 0.0079 0.6378 0.5591
A A1 A2 b c D D1 D3 E E1 E3 e L L1 k ccc
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics Figure 44. Recommended footprint(1)(2)
Figure 43. LQFP64 64 pin low-profile quad flat package outline(1)
A A2
48
33 0.3
A1
49
0.5
32
E
E1
b
12.7
10.3
e
10.3 64 17 1.2 1 16 7.8 12.7
ai14398b
D1 D L1 L
c
ai14909
1. Drawing is not to scale. 2. Dimensions are in millimeters.
Table 59.
Dim.
LQFP64 64 pin low-profile quad flat package mechanical data
mm Min Typ Max 1.60 0.05 1.35 0.17 0.09 12.00 10.00 12.00 10.00 0.50 0 0.45 3.5 0.60 1.00 Number of pins 7 0.75 0 0.0177 1.40 0.22 0.15 1.45 0.27 0.20 0.0020 0.0531 0.0067 0.0035 0.4724 0.3937 0.4724 0.3937 0.0197 3.5 0.0236 0.0394 7 0.0295 0.0551 0.0087 Min inches(1) Typ Max 0.0630 0.0059 0.0571 0.0106 0.0079
A A1 A2 b c D D1 E E1 e L L1 N
64
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
STM32F105xx, STM32F107xx
6.2
Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in Table 9: General operating conditions on page 35. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max × JA) Where:
TA max is the maximum ambient temperature in C, JA is the package junction-to-ambient thermal resistance, in C/W, PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max = (VOL × IOL) + ((VDD VOH) × IOH),
PI/O max represents the maximum power dissipation on output pins where: taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 60.
Symbol
Package thermal characteristics
Parameter Thermal resistance junction-ambient LQFP100 - 14 × 14 mm / 0.5 mm pitch Thermal resistance junction-ambient LQFP64 - 10 × 10 mm / 0.5 mm pitch Thermal resistance junction-ambient LFBGA100 - 10 × 10 mm / 0.8 mm pitch Value 46 C/W 45 40 46 45 C/W Unit
JA
JA
Thermal resistance junction-ambient LQFP100 - 14 × 14 mm / 0.5 mm pitch Thermal resistance junction-ambient LQFP64 - 10 × 10 mm / 0.5 mm pitch
6.2.1
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org.
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6.2.2
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 61: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. As applications do not commonly use the STM32F103xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. The following examples show how to calculate the temperature range needed for a given application.
Example 1: High-performance application
Assuming the following application conditions: Maximum ambient temperature TAmax = 82 C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA × 3.5 V= 175 mW PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW: PDmax = 175 + 272 = 447 mW Thus: PDmax = 447 mW Using the values obtained in Table 60 TJmax is calculated as follows: For LQFP100, 46 C/W TJmax = 82 C + (46 C/W × 447 mW) = 82 C + 20.6 C = 102.6 C This is within the range of the suffix 6 version parts (40 < TJ < 105 C). In this case, parts must be ordered at least with the temperature range suffix 6 (see Table 61: Ordering information scheme).
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature TJ remains within the specified range. Assuming the following application conditions: Maximum ambient temperature TAmax = 115 C (measured according to JESD51-2), IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V PINTmax = 20 mA × 3.5 V= 70 mW PIOmax = 20 × 8 mA × 0.4 V = 64 mW This gives: PINTmax = 70 mW and PIOmax = 64 mW: PDmax = 70 + 64 = 134 mW Thus: PDmax = 134 mW
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STM32F105xx, STM32F107xx
Using the values obtained in Table 60 TJmax is calculated as follows: For LQFP100, 46 C/W TJmax = 115 C + (46 C/W × 134 mW) = 115 C + 6.2 C = 121.2 C This is within the range of the suffix 7 version parts (40 < TJ < 125 C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Table 61: Ordering information scheme). Figure 45. LQFP100 PD max vs. TA
700 600
PD (mW)
500 400 300 200 100 0 65 75 85 95 105 115 125 135 Suf f ix 6 Suf f ix 7
TA (C)
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Part numbering
7
Part numbering
Table 61.
Example: Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 105 = connectivity, USB OTG FS 107= connectivity, USB OTG FS & Ethernet Pin count R = 64 pins V = 100 pins Flash memory size 8 = 64 Kbytes of Flash memory B = 128 Kbytes of Flash memory C = 256 Kbytes of Flash memory Package H = BGA T = LQFP Temperature range 6 = Industrial temperature range, 40 to 85 C. 7 = Industrial temperature range, 40 to 105 C. Options xxx = programmed parts TR = tape and real
Ordering information scheme
STM32 F 105 R C T 6 xxx
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office.
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Application block diagrams
STM32F105xx, STM32F107xx
Appendix A
A.1
Application block diagrams
USB OTG FS interface solutions
STM32F105xx/STM32F107xx OTG PHY USB Full-speed transceiver USB OTG Full-speed core DP USB Micro-B connector DM
To host
Figure 46. USB OTG FS device mode
HNP V BUS VSS
DP DM VBUS VSS
ID
SRP VDD
5 V to VDD Regulator(1)
ai15653b
1. Use a regulator if you want to build a bus-powered device.
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STM32F105xx, STM32F107xx Figure 47. Host connection
STM32F105xx/STM32F107xx OTG PHY USB full-speed/ low-speed transceiver USB OTG Full-speed core
Application block diagrams
DP USB Std-A connector DM
HNP V BUS VSS
ID
SRP
VDD(2)
GPIO GPIO + IRQ
Current-limited power distribution 5 V switch OVRCR STMPS2141STR(1) flag EN
ai15654b
1. STMPS2141STR needed only if the application has to support bus-powered devices.
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Application block diagrams Figure 48. OTG connection (any protocol)
STM32F105xx/STM32F107xx OTG PHY
STM32F105xx, STM32F107xx
DM ID
USB OTG Full-speed core
HNP V BUS VSS
ID
SRP
VDD
GPIO GPIO + IRQ
Current-limited power distribution 5 V switch OVRCR STMPS2141STR(1) flag EN
ai15655b
1. STMPS2141STR needed only if the application has to support bus-powered devices.
A.2
Ethernet interface solutions
Figure 49. MII mode using a 25 MHz crystal
STM32F107xx
MCU
MII_TX_CLK MII_TX_EN MII_TXD[3:0] MII_CRS MII_COL MII_RX_CLK MII_RXD[3:0] MII_RX_DV MII_RX_ER MDIO MDC PPS_OUT(2)
XTAL 25 MHz
Ethernet MAC 10/100
Ethernet PHY 10/100
MII = 15 pins MII + MDC = 17 pins
HCLK(1)
IEEE1588 PTP Timer input trigger Timestamp TIM2 comparator
OSC
PLL
HCLK PHY_CLK 25 MHz XT1
ai15656
1. HCLK must be greater than 25 MHz. 2. Pulse per second when using IEEE1588 PTP, optional signal.
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USB Micro-AB connector
USB full-speed/ low-speed transceiver
DP
STM32F105xx, STM32F107xx Figure 50. RMII with a 50 MHz oscillator
STM32F107xx
MCU
Application block diagrams
Ethernet PHY 10/100
RMII_TX_EN RMII_TXD[1:0] RMII_RXD[1:0] RMII_CRX_DV RMII_REF_CLK MDIO MDC RMII = 7 pins RMII + MDC = 9 pins
Ethernet MAC 10/100
HCLK(1)
IEEE1588 PTP Timer input trigger Timestamp TIM2 comparator
/2 or /20 2.5 or 25 MHz synchronous 50 MHz OSC 50 MHz PLL HCLK
PHY_CLK
50 MHz
XT1
50 MHz
ai15657
1. HCLK must be greater than 25 MHz.
Figure 51. RMII with a 25 MHz crystal and PHY with PLL
STM32F107xx
MCU Ethernet PHY 10/100
RMII_TX_EN RMII_TXD[1:0] RMII_RXD[1:0] RMII_CRX_DV RMII_REF_CLK IEEE1588 PTP Timer input trigger Timestamp TIM2 comparator MDIO MDC RMII = 7 pins REF_CLK RMII + MDC = 9 pins
Ethernet MAC 10/100
HCLK(1)
/2 or /20 2.5 or 25 MHz synchronous 50 MHz
XTAL 25 MHz
OSC
PLL
HCLK PHY_CLK 25 MHz XT1
PLL
ai15658
1. HCLK must be greater than 25 MHz.
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Application block diagrams Figure 52. RMII with a 25 MHz crystal
STM32F107xx
MCU
STM32F105xx, STM32F107xx
Ethernet PHY 10/100
RMII_TX_EN RMII_TXD[1:0] RMII_RXD[1:0] RMII_CRX_DV RMII_REF_CLK MDIO MDC RMII = 7 pins 50 MHz RMII + MDC = 9 pins
Ethernet MAC 10/100
HCLK IEEE1588 PTP 50 MHz Timer input trigger Time stamp TIM2 comparator
XTAL 25 MHz
50 MHz OSC PLLS XT1/XT2 NS DP83848(1)
ai15659b
1. The NS DP83848 is recommended as the input jitter requirement of this PHY. It is compliant with the output jitter specification of the MCU.
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Application block diagrams
A.3
Complete audio player solutions
Two solutions are offered, illustrated in Figure 53 and Figure 54. Figure 53 shows storage media to audio DAC/amplifier streaming using a software Codec. This solution implements an audio crystal to provide audio class I2S accuracy on the master clock (0.5% error maximum, see the Serial peripheral interface section in the reference manual for details). Figure 53. Complete audio player solution 1
STM32F105/STM32F107 XTAL 14.7456 MHz Cortex-M3 core 72 MHz Program memory GPIO File System Audio CODEC User application SPI
ai15660
SPI
LCD touch screen Control buttons DAC + Audio ampli
USB Mass-storage device
OTG (host mode) + PHY
I2S
MMC/ SDCard
Figure 54 shows storage media to audio Codec/amplifier streaming with SOF synchronization of input/output audio streaming using a hardware Codec. Figure 54. Complete audio player solution 2
STM32F105/STM32F107 XTAL 14.7456 MHz Cortex-M3 core 72 MHz Program memory GPIO USB Mass-storage device SOF File System SPI LCD touch screen Control buttons
OTG + PHY
I2S
MMC/ SDCard
User application SPI SOF synchronization of input/output audio streaming
ai15661
Audio CODEC
Audio ampli
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Application block diagrams
STM32F105xx, STM32F107xx
A.4
USB OTG FS interface + Ethernet/I2S interface solutions
With the clock tree implemented on the STM32F107xx, only one crystal is required to work with both the USB (host/device/OTG) and the Ethernet (MII/RMII) interfaces. Figure 55 illustrate the solution. Figure 55. USB OTG FS + Ethernet solution
STM32F107 MCU Div by 5 PLL2MUL x8
25 MHz XTAL
OSC
Up to 72 MHz
SYSCLK
PLLVCO (2 xPLLCLK Div by 5 Sel PLL3MUL x10 Up to 50 MHz Sel I2S 2% accuracy PLLMUL x9 Div by 3 OTG 48 MHz USB PHY
Ethernet PHY
MCO
With the clock tree implemented on the STM32F107xx, only one crystal is required to work with both the USB (host/device/OTG) and the I2S (Audio) interfaces. Figure 56 illustrate the solution. Figure 56. USB OTG FS + I2S (Audio) solution
14.7456 MHz XTAL OSC STM32F105 /STM32F107MCU Div by 4 PLL2MUL x8
Up to 71.88 MHz
SYSCLK
PLLVCO (2 xPLLCLK Div by 4 Sel PLLMUL x6.5 Div by 3 OTG 47.9232 MHz 0.16% accuracy USB PHY
Ethernet PHY
MCO PLL3MUL x20
PLL3VCO (2 xPLL3CLK Up to 147.456 MHz
MCLK I2S SCLK
Less than 0.5% accuracy on MCLK and SCLK
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Application
Application block diagrams
PLL configurations
Crystal value in PREDIV2 P LL2MUL MHz (XT1) 25 25 25 /5 /5 /5 PLL2ON x8 PLL2ON x8 PLL2ON x8 PLL2ON x12 PLL2OFF P LL2OFF PLL2ON x12 PLL2ON x12 PLLSRC PREDIV1 PLLMUL USB I2Sn MCO (main prescaler clock PLL3MUL clock (PLLVCO output) input output) NA /3 /3 PLL3ON x10 PLL3ON x10 PLL3ON x10 PLL3ON x20 PLL3OFF PLL3OFF PLL3ON x20 PLL3ON x20 NA NA PLL PLL3 VCO Out NA PLL PLL3 VCO Out PLL3 VCO out XT1 (MII) PLL3 (RMII) XT1 (MII) PLL3 (RMII) XT1 (MII) PLL3 (RMII) NA ETH PHY must use its own crystal NA NA
Ethernet only Ethernet + OTG Ethernet + OTG + basic audio
PLL 2 PLL 2 PLL 2
/5 /5 /5
PLLON x9 PLLON x9 PLLON x9
Ethernet + OTG + Audio class 14.7456 I2S(1) OTG only OTG + basic audio OTG + Audio class I2S(1) 8 8
/4
PLL 2
/4
PLLON x6.5 PLLON x9 PLLON x9 PLLON x6.5 PLLON x6.5
/3
NA NA
XT1 XT1
/1 /1
/3 /3
14.7456
/4
PLL 2
/4
/3
NA
Audio class I2S 14.7456 only(1)
/4
PLL 2
/4
NA
NA
1. SYSCLK is set to be at 72 MHz except in this case where SYSCLK is at 71.88 MHz.
Table 63 give the IDD run mode values that correspond to the conditions specified in Table 62.
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Application block diagrams Table 63.
Symbol
STM32F105xx, STM32F107xx
Applicative current consumption in Run mode, code with data processing running from Flash
parameter Conditions(1) Typ(2) Max(2) 85 C External clock, all peripherals enabled except ethernet, HSE = 8 MHz, fHCLK = 72 MHz, no MCO External clock, all peripherals enabled except ethernet, HSE = 14.74 MHz, fHCLK = 72 MHz, no MCO External clock, all peripherals enabled except OTG, HSE = 25 MHz, fHCLK = 72 MHz, MCO = 25 MHz External clock, all peripherals enabled, Supply current HSE = 25 MHz, f HCLK = 72 MHz, MCO in run mode = 25 MHz External clock, all peripherals enabled, HSE = 25 MHz, fHCLK = 72 MHz, MCO = 50 MHz External clock, all peripherals enabled, HSE = 50 MHz(3), fHCLK = 72 MHz, no MCO External clock, only OTG enabled, HSE = 8 MHz, fHCLK = 48 MHz, no MCO External clock, only ethernet enabled, HSE = 25 MHz, fHCLK = 25 MHz, MCO = 25 MHz 105 C Unit
57
63
64
60.5
67
68
53
60.7
61
IDD
60.5
65.5
66
mA
64
69.7
70
62.5
67.5
68
26.7
None
None
14.3
None
None
1. VDD = 3.3 V. 2. Based on characterization, not tested in production. 3. External oscillator.
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Revision history
Table 64.
Date 18-Dec-2008
Document revision history
Revision 1 Initial release. I/O information clarified on page 1. Figure 4: STM32F105xxx and STM32F107xxx connectivity line BGA100 ballout top view corrected. Section 2.3.8: Boot modes updated. PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default column to Remap column, plus small additional changes in Table 5: Pin definitions. Consumption values modified in Section 5.3.5: Supply current characteristics. Note modified in Table 13: Maximum current consumption in Run mode, code with data processing running from Flash and Table 15: Maximum current consumption in Sleep mode, code running from Flash or RAM. Table 20: High-speed external user clock characteristics and Table 21: Low-speed external user clock characteristics modified. Table 27: PLL characteristics modified and Table 28: PLL2 and PLL3 characteristics added. Changes
20-Feb-2009
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Revision history Table 64.
Date
STM32F105xx, STM32F107xx Document revision history (continued)
Revision Changes Section 2.3.8: Boot modes and Section 2.3.20: Ethernet MAC interface with dedicated DMA and IEEE 1588 support updated. Section 2.3.24: Remap capability added. Figure 1: STM32F105xx and STM32F107xx connectivity line block diagram and Figure 5: Memory map updated. In Table 5: Pin definitions: I2S3_WS, I2S3_CK and I2S3_SD default alternate functions added small changes in signal names Note 6 modified ETH_MII_PPS_OUT and ETH_RMII_PPS_OUT replaced by ETH_PPS_OUT ETH_MII_MDIO and ETH_RMII_MDIO replaced by ETH_MDIO ETH_MII_MDC and ETH_RMII_MDC replaced by ETH_MDC Figures: Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals enabled and Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals disabled removed. Table 13: Maximum current consumption in Run mode, code with data processing running from Flash, Table 14: Maximum current consumption in Run mode, code with data processing running from RAM and Table 15: Maximum current consumption in Sleep mode, code running from Flash or RAM are to be determined. Figure 12 and Figure 13 show typical curves. PLL1 renamed to PLL. IDD supply current in Stop mode modified in Table 16: Typical and maximum current consumptions in Stop and Standby modes. Figure 11: Typical current consumption in Stop mode with regulator in Run mode versus temperature at different VDD values, Figure 13: Typical current consumption in Standby mode versus temperature at different VDD values and Figure 13: Typical current consumption in Standby mode versus temperature at different VDD values updated. Table 17: Typical current consumption in Run mode, code with data processing running from Flash, Table 18: Typical current consumption in Sleep mode, code running from Flash or RAM and Table 19: Peripheral current consumption updated. fHSE_ext modified in Table 20: High-speed external user clock characteristics. Min PLL input clock (fPLL_IN), fPLL_OUT min and fPLL_VCO min modified in Table 27: PLL characteristics. ACCHSI max values modified in Table 24: HSI oscillator characteristics. Table 31: EMS characteristics and Table 32: EMI characteristics updated. Table 42: SPI characteristics updated. Modified: Figure 28: I2S slave timing diagram (Philips protocol)(1), Figure 29: I2S master timing diagram (Philips protocol)(1) and Figure 31: Ethernet SMI timing diagram. BGA100 package removed. Section 6.2: Thermal characteristics added. Small text changes.
19-Jun-2009
3
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Date
Revision history
Document revision history (continued)
Revision Changes Document status promoted from Preliminary data to full datasheet. Number of DACs corrected in Table 3: STM32F105xx and STM32F107xx family versus STM32F103xx family. Note 5 added in Table 5: Pin definitions. VRERINT and TCoeff added to Table 12: Embedded internal reference voltage. Values added to Table 13: Maximum current consumption in Run mode, code with data processing running from Flash, Table 14: Maximum current consumption in Run mode, code with data processing running from RAM and Table 15: Maximum current consumption in Sleep mode, code running from Flash or RAM. Typical IDD_VBAT value added in Table 16: Typical and maximum current consumptions in Stop and Standby modes. Figure 10: Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values added. Values modified in Table 17: Typical current consumption in Run mode, code with data processing running from Flash and Table 18: Typical current consumption in Sleep mode, code running from Flash or RAM. fHSE_ext min modified in Table 20: High-speed external user clock characteristics. CL1 and CL2 replaced by C in Table 22: HSE 3-25 MHz oscillator characteristics and Table 23: LSE oscillator characteristics (fLSE = 32.768 kHz), notes modified and moved below the tables. Note 1 modified below Figure 16: Typical application with an 8 MHz crystal. Conditions removed from Table 26: Low-power mode wakeup timings. Standards modified in Section 5.3.10: EMC characteristics on page 51, conditions modified in Table 31: EMS characteristics. Jitter maximum values added to Table 27: PLL characteristics and Table 28: PLL2 and PLL3 characteristics. RPU and RPD modified in Table 35: I/O static characteristics. Condition added for VNF(NRST) parameter in Table 38: NRST pin characteristics. Note removed and RPD, RPU values added in Table 45: USB OTG FS DC electrical characteristics. Table 47: Ethernet DC electrical characteristics added. Parameter values added to Table 48: Dynamic characteristics: Ethernet MAC signals for SMI, Table 49: Dynamic characteristics: Ethernet MAC signals for RMII and Table 50: Dynamic characteristics: Ethernet MAC signals for MII. CADC and RAIN parameters modified in Table 51: ADC characteristics. RAIN max values modified in Table 52: RAIN max for fADC = 14 MHz. Table 55: DAC characteristics modified. Figure 38: 12-bit buffered /non-buffered DAC added. Table 63: Applicative current consumption in Run mode, code with data processing running from Flash added. Small text changes.
14-Sep-2009
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Revision history Table 64.
Date
STM32F105xx, STM32F107xx Document revision history (continued)
Revision Changes Added BGA package. Table 5: Pin definitions: ETH_RMII_RXD0 and ETH_RMII_RXD1 added in remap column for PD9 and PD10, respectively. Note added to ETH_MII_RX_DV, ETH_MII_RXD0, ETH_MII_RXD1, ETH_MII_RXD2 and ETH_MII_RXD3 Updated Table 35: I/O static characteristics on page 54 Added Figure 18: Standard I/O input characteristics - CMOS port to Figure 21: 5 V tolerant I/O input characteristics - TTL port Updated Table 42: SPI characteristics on page 63. Updated Table 43: I2S characteristics on page 66. Updated Table 47: Ethernet DC electrical characteristics on page 69. Updated Table 48: Dynamic characteristics: Ethernet MAC signals for SMI on page 69. Updated Table 49: Dynamic characteristics: Ethernet MAC signals for RMII on page 70 Updated Figure 55: USB OTG FS + Ethernet solution on page 94. Updated Figure 56: USB OTG FS + I2S (Audio) solution on page 94
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