ST6208C/ST6209C ST6210C/ST6220C
8-BIT MCUs WITH A/D CONVERTER, TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET
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M e m o ri e s 1K, 2K or 4K bytes Program memory (OTP, EPROM, FASTROM or ROM) with read-out protection 64 bytes RAM Clock, Reset and Supply Management Enhanced reset system Low Voltage Detector (LVD) for Safe Reset Clock sources: crystal/ceramic resonator or RC network, external clock, backup oscillator (LFAO) Oscillator Safeguard (OSG) 2 Power Saving Modes: Wait and Stop Interrupt Management 4 interrupt vectors plus NMI and RESET 12 external interrupt lines (on 2 vectors) 12 I/O Ports 12 multifunctional bidirectional I/O lines 8 alternate function lines 4 high sink outputs (20mA) 2 Timers Configurable watchdog timer 8-bit timer/counter with a 7-bit prescaler Analog Peripheral 8-bit ADC with 4 or 8 input channels (except on ST6208C)
PDIP20
S O 20
SSOP20
CDIP 20W
(See Section 11.5 for Ordering Information)
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Instruction Set 8-bit data manipulation 40 basic instructions 9 addressing modes Bit manipulation Development Tools Full hardware/software development package
Device Summary
Features Program memory - bytes RAM - bytes Operating Supply Analog Inputs Clock Frequency Operating Temperature Packages S T62T08C(OTP)/ ST62T09C(OTP) / S T62T10C( OTP )/ S T62T20C( OTP ) ST62E20C (EP ROM) ST6208C( ROM) ST6209C (ROM) S T62 10C (ROM) S T6 220C(ROM ) ST62P08C(FASTROM) ST62P 09C(FAS TROM ) S T62P 10C(FAS TROM) ST62P 20C(FAS TROM )
1K
2K 64 3.0V to 6V
4K
4
8MHz Max -40C to +125C PDIP20/SO20/SSOP20
8
CDIP20W
Rev. 3.3
October 2003 1/104
1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 MEMORY MAPS, PROGRAMMING MODES AND OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . 9 3.1 MEMORY AND REGISTER MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1.3 Readout Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1.4 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1.5 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1.6 Data ROM Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 PROGR AMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.2 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 INTRODU CTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 4.3 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5 CLOCKS, SUPPLY AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1 CLOC K SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Oscillator Safeguard (OSG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 Low Frequency Auxiliary Oscillator (LFAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 5.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 RESET Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.4 W atchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.5 LVD Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 5.6 5.7 5.8 5.9 20 21 22 22 23 24 24 25 26 26 27
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
INTERRUPT RULES AND PRIORITY MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . 28 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 NON MASKABLE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 EXTERNAL INTERRUPTS (I/O PORTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.9.1 Notes on using External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.10 INTERRUPT HANDLING PROCEDURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.10.1 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.11 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 . 32 ... 6.1 INTRODU CTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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6.2 6.3 6.4 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 STOP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 NOTES RELATED TO WAIT AND STOP MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.4.1 Exit from Wait and Stop Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.4.2 Recommended MCU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.1 INTRODU CTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.2.1 Digital Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.2.2 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.2.3 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.2.4 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.2.5 Instructions NOT to be used to access Port Data registers (SET, RES, INC and DEC) 39 7.2.6 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.3 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.4 7.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.1 WATCHD OG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.4 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 8-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8. 2. 1 8. 2. 2 8. 2. 3 8. 2. 4 8. 2. 5 8. 2. 6 8. 2. 7 8.3 A/D 8. 3. 1 8. 3. 2 8. 3. 3 8. 3. 4 8. 3. 5 8. 3. 6 8. 3. 7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counter/Prescaler Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 42 43 43 44 44 45 46 46 46 47 48 50 50 51 52 52 52 53 54 55 55 55
9 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
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9.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.1.1 Minimum and Maximum Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2 Typical Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.3 Typical Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.4 Loading Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.5 Pin Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 62 62 62 62 63 63 63 63 64
10.3.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.3.2 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . 65 10.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.4.1 RU N Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.2 W AIT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.3 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.4 Supply and Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.5 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 CLOC K AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.4 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.5 Oscillator Safeguard (OSG) and Low Frequency Auxiliary Oscillator (LFAO) . . . . . 10.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 67 70 71 71 72 72 72 73 74 75 76
10.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10.6.2 EPROM Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 10.7.1 Functional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7.2 Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7.3 ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 78 80 81
10.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 10.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 10.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 10.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 10.9.2 NMI Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 10.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.10.1W atchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.10.28-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.11 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 11 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 87 88 90 90
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Table of Contents
11.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.5 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.6 TRANSFER OF CUSTOMER CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.6.1 FASTROM version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.6.2 ROM VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 12 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 13 ST6 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 14 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 15 TO GET MORE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
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1 INTRODUCTION
The ST6208C, 09C, 10C and 20C devices are low cost members of the ST62xx 8-bit HCMOS family of microcontrollers, which is targeted at low to medium complexity applications. All ST62xx devices are based on a building block approach: a common core is surrounded by a number of on-chip peripherals. The ST62E20C is the erasable EPROM version of the ST62T08C, T09C, T10C and T20C devices, which may be used during the development phase for the ST62T08C, T09C, T10C and T20C target devices, as well as the respective ST6208C, 09C, 10C and 20C ROM devices. OTP and EPROM devices are functionally identical. OTP devices offer all the advantages of user programmability at low cost, which make them the ideal choice in a wide range of applications where frequent code changes, multiple code versions or last minute programmability are required. The ROM based versions offer the same functionality, selecting the options defined in the programFigure 1. Block Diagram
8-BIT * A/D CONVERTER INTERRUPTS PORT B P:ROGRAM MEMORY (1K, 2K or 4K Bytes) DATA ROM USER SELECTABLE DATA RAM 64 Bytes TIMER TIMER PB0..PB7 / Ain*
mable option bytes of the OTP/EPROM versions in the ROM option list (See Section 11.6 on page 96) . The ST62P08C/P09C/P10C/P20C are the Factory Advanced Service Technique ROM (FASTROM) versions of ST62T08C, T09C, T10C and T20C OTP devices. They offer the same functionality as OTP devices, but they do not have to be programmed by the customer (See Section 11 on page 90). These compact low-cost devices feature a Timer comprising an 8-bit counter with a 7-bit programmable prescaler, an 8-bit A/D Converter with up to 8 analog inputs (depending on device) and a Digital Watchdog timer, making them well suited for a wide range of automotive, appliance and industrial applications. For easy reference, all parametric data are located in Section 11 on page 90.
VPP NMI
PORT A
PA0..PA3 (20mA Sink)
PC STACK LEVEL 1 STACK LEVEL 2 STACK LEVEL 3 STACK LEVEL 4 STACK LEVEL 5 STACK LEVEL 6 POWER SUPPLY
WATCHDOG TIMER
8-BIT CORE
OSCILLATOR
RESET
VDD VSS
OSCin OSCout
RESET
* Depending on device. Please refer to I/O Port section.
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2 PIN DESCRIPTION
Figure 2. 20-Pin Package Pinout
V DD TIMER OSCin OSCout NMI VPP RESET Ain*/PB7 Ain*/PB6 Ain*/PB5
itX associated interrupt vector * Depending on device. Please refer to I/O Port section.
1 2 3 4 5 6 7 8 9 it 2 10
20 19 it 1 1 8 17 16 15 14 it 2 1 3 12 11
VSS PA0/20mA Sink PA1/20mA Sink PA2/20mA Sink PA3/20mA Sink PB0/Ain* PB1/Ain* PB2/Ain* PB3/Ain* PB4/Ain*
Table 1. Device Pin Description
Type Pin n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 VDD
TIMER
Pin Name
Main Function (after Reset) Main power supply Timer input or output External clock input or resonator oscillator inverter input
Alternate Function
S I/O I O I
OSCin OSCout NMI VPP RESET PB7/Ain* PB6/Ain* PB5/Ain* PB4/Ain* PB3/Ain* PB2/Ain* PB1/Ain* PB0/Ain* PA3/ 20mA Sink PA2/ 20mA Sink PA1/ 20mA Sink
Resonator oscillator inverter output or resistor input for RC oscillator Non maskable interrupt (falling edge sensitive) Must be held at Vss for normal operation, if a 12.5V level is applied to the pin during the reset phase, the device enters EPROM programming mode.
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Top priority non maskable interrupt (active low) Pin B7 (IPU) Pin B6 (IPU) Pin B5 (IPU) Pin B4 (IPU) Pin B3 (IPU) Pin B2 (IPU) Pin B1 (IPU) Pin B0 (IPU) Pin A3 (IPU) Pin A2 (IPU) Pin A1 (IPU) Analog input Analog input Analog input Analog input Analog input Analog input Analog input Analog input
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Type
Pin n 19 20
Pin Name PA0/ 20mA Sink VSS
Main Function (after Reset) Pin A0 (IPU) Ground
Alternate Function
I/O S
Legend / Abbreviations for Table 1: * Depending on device. Please refer to Section 7 "I/O PORTS" on page 37. I = input, O = output, S = supply, IPU = input with pull-up The input with pull-up configuration (reset state) is valid as long as the user software does not change it. Refer to Section 7 "I/O PORTS" on page 37 for more details on the software configuration of the I/O ports.
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3 MEMORY MAPS, PROGRAMMING MODES AND OPTION BYTES
3.1 MEMORY AND REGISTER MAPS 3.1.1 Introduction The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in these three memory spaces is described in the following paragraphs. Figure 3. Memory Addressing Diagram Briefly, Program space contains user program code in OTP and user vectors; Data space contains user data in RAM and in OTP, and Stack space accommodates six levels of stack for subroutine and interrupt service routine nesting.
PROGRAM SPACE 000h 000h
DATA SPACE
RESERVED
03Fh 040h PROGRAM MEMORY (see Figure 4 on page 10) DATA ROM WINDOW 07Fh 080h 081h 082h 083h 084h 0BFh 0C0h 0FF0h INTERRUPT & RESET VECTORS 0FFFh 0FFh X REGISTER Y REGISTER V REGISTER W REGISTER RAM HARDWARE CONTROL REGISTERS (see Table 2) ACCUMULATOR
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MEMORY MAP (Cont'd) Figure 4. Program Memory Map
ST6208C, 09C
0000h 0000h
ST6210C
0000h
ST6220C
RESERVED*
07Fh 080h
NOT IMPLEMENTED
NOT IMPLEMENTED
07FFh 0800h
RESERVED*
087Fh 0880h 0AFF h 0B00h 0B9Fh 0BA0h
RESERVED*
USER PROGRAM MEMORY 3872 BYTES USER PROGRAM MEMORY 1824 BYTES
USER PROGRAM MEMORY 1024 BYTES
0F9Fh 0FA0h 0 FE Fh 0FF0h 0FF7h 0FF8h 0 FFB h 0FFCh 0FFDh 0 FFE h 0 FFFh 0F9Fh 0F A0h 0FEF h 0FF0h 0FF7h 0FF8h 0 FFB h 0FFCh 0FFDh 0 FFE h 0F FFh
RESERVED* INTERRUPT VECTORS RESERVED* NMI VECTOR USER RESET VECTOR
RESERVED* INTERRUPT VECTORS RESERVED* NMI VECTOR USER RESET VECTOR
0F9Fh 0FA0h 0FEFh 0FF0h 0FF7h 0FF8h 0FFBh 0F FCh 0F FDh 0FFEh 0FFFh
RESERVED* INTERRUPT VECTORS RESERVED* NMI VECTOR USER RESET VECTOR
(*) Reserved areas should be filled with 0FFh
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MEMORY MAP (Cont'd) 3.1.2 Program Space Program Space comprises the instructions to be executed, the data required for immediate addressing mode instructions, the reserved factory test area and the user vectors. Program Space is addressed via the 12-bit Program Counter register (PC register). Thus, the MCU is capable of addressing 4K bytes of memory directly. 3.1.3 Readout Protection The Program Memory in OTP, EPROM or ROM devices can be protected against external readout of memory by setting the Readout Protection bit in the option bytes (Section 3.3 on page 16). In the EPROM parts, Readout Protection option can be desactivated only by U.V. erasure that also results in the whole EPROM context being erased. Note: Once the Readout Protection is activated, it is no longer possible, even for STMicroelectronics, to gain access to the OTP or ROM contents. Returned parts can therefore not be accepted if the Readout Protection bit is set. 3.1.4 Data Space Data Space accommodates all the data necessary for processing the user program. This space comprises the RAM resource, the processor core and peripheral registers, as well as read-only data
such as constants and look-up tables in OTP/ E P R OM . 3.1.4.1 Data ROM All read-only data is physically stored in program memory, which also accommodates the Program Space. The program memory consequently contains the program code to be executed, as well as the constants and look-up tables required by the application. The Data Space locations in which the different constants and look-up tables are addressed by the processor core may be thought of as a 64-byte window through which it is possible to access the read-only data stored in OTP/EPROM. 3.1.4.2 Data RAM The data space includes the user RAM area, the accumulator (A), the indirect registers (X), (Y), the short direct registers (V), (W), the I/O port registers, the peripheral data and control registers, the interrupt option register and the Data ROM Window register (DRWR register). 3.1.5 Stack Space Stack space consists of six 12-bit registers which are used to stack subroutine and interrupt return addresses, as well as the current program counter contents.
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MEMORY MAP (Cont'd) Table 2. Hardware Register Map
Address 080h to 083h 0C0h 0C1h 0C2h 0C3h 0C4h 0C5h 0C6h 0C7h 0C8h 0C9h 0CAh 0CBh 0CCh 0CDh 0CEh 0CFh 0D0h 0D1h 0D2h 0D3h 0D4h 0D5h to 0D7h 0D8h 0D9h to 0FEh 0FFh CPU A Watchdog Timer WDGR ADC 4) ADR ADCR PSCR TCR TSCR I/O Ports ORA 2) ORB 2) CPU ROM IOR DRWR I/O Ports DDRA 2) DDRB 2) Block CPU I/O Ports Register Label X,Y,V,W DRA 1) 2) 3) DRB 1) 2) 3) Register Name X,Y index registers V,W short direct registers Port A Data Register Port B Data Register Reserved (2 Bytes) Port A Direction Register Port B Direction Register Reserved (2 Bytes) Interrupt Option Register Data ROM Window register Reserved (2 Bytes) Port A Option Register Port B Option Register Reserved (2 bytes) A/D Converter Data Register A/D Converter Control Register Timer 1 Prescaler Register Timer 1 Downcounter Register Timer 1 Status Control Register Reserved (3 Bytes) Watchdog Register Reserved (38 Bytes) Accumulator xxh R/W 0FEh R/W xxh 40h 7Fh 0FFh 00h Read-only Ro/Wo R/W R/W R/W 00h 00h R/W R/W xxh xxh Write-only Write-only 00h 00h R/W R/W Reset Status xxh 00h 00h Remarks R/W R/W R/W
Timer1
Legend: x = undefined, R/W = Read/Write, Ro = Read-only Bit(s) in the register, Wo = Write-only Bit(s) in the register. Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always be kept at their reset value. 3. Do not use single-bit instructions (SET, RES...) on Port Data Registers if any pin of the port is configured in input mode (refer to Section 7 "I/O PORTS" on page 37 for more details) 4. Depending on device. See device summary on page 1.
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MEMORY MAP (Cont'd) 3.1.6 Data ROM Window The Data read-only memory window is located from address 0040h to address 007Fh in Data space. It allows direct reading of 64 consecutive bytes located anywhere in program memory, between address 0000h and 0FFFh. There are 64 blocks of 64 bytes in a 4K device: Block 0 is related to the address range 0000h to 003Fh. Block 1 is related to the address range 0040h to 007Fh. and so on... All the program memory can therefore be used to store either instructions or read-only data. The Data ROM window can be moved in steps of 64 bytes along the program memory by writing the appropriate code in the Data ROM Window Register (DRWR). Figure 5. Data ROM Window
PROGRAM 0000h SPACE 000h DATA SPACE
3.1.6.1 Data ROM Window Register (DRWR) The DRWR can be addressed like any RAM location in the Data Space. This register is used to select the 64-byte block of program memory to be read in the Data ROM window (from address 40h to address 7Fh in Data space). The DRWR register is not cleared on reset, therefore it must be written to before accessing the Data read-only memory window area for the first time. Address: 0C9h -- W rite Only Reset Value = xxh (undefined)
7 0 DRWR5 DRWR4 DRWR3 DRWR2 DRWR1 DRWR0
Bits 7:6 = Reserved, must be cleared. Bit 5:0 = DRWR[5:0] Data read-only memory Window Register Bits. These are the Data read-only memory Window bits that correspond to the upper bits of the data read-only memory space. Caution: This register is undefined on reset, it is write-only, therefore do not read it nor access it using Read-Modify-Write instructions (SET, RES, INC and DEC).
040h DATA ROM 64-BYTE ROM 07Fh WINDOW
0FFFh
0FFh
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MEMORY MAP (Cont'd) 3.1.6.2 Data ROM Window memory addressing In cases where some data (look-up tables for example) are stored in program memory, reading these data requires the use of the Data ROM window mechanism. To do this: 1. The DRWR register has to be loaded with the 64-byte block number where the data are located (in program memory). This number also gives the start address of the block. 2. Then, the offset address of the byte in the Data ROM Window (corresponding to the offset in the 64-byte block in program memory) has to be loaded in a register (A, X,...). When the above two steps are completed, the data can be read. To understand how to determine the DRWR and the content of the register, please refer to the example shown in Figure 6. In any case the calculaFigure 6. Data ROM Window Memory Addressing
tion is automatically handled by the ST6 development tools. Please refer to the user manual of the correspoding tool. 3.1.6.3 Recommendations Care is required when handling the DRWR register as it is write only. For this reason, the DRWR contents should not be changed while executing an interrupt service routine, as the service routine cannot save and then restore the register's previous contents. If it is impossible to avoid writing to the DRWR during the interrupt service routine, an image of the register must be saved in a RAM location, and each time the program writes to the DRWR , it must also write to the image register. The image register must be written first so that, if an interrupt occurs between the two instructions, the DRWR is not affected.
DATA SPACE PROGRAM SPACE 0000h 000h
040h OFFSET 2 1h
DATA
061h 07Fh
0400h OFFSET 0421h 64 bytes DATA 10h DRWR
0FFh
07FFh DATA address in Program memory : 421h DRWR content : 421h / 3Fh (64) = 10H data is located in 64-bytes window number 10h 64-byte window start address : 10h x 3Fh = 400h Register (A, X,...)content : Offset = (421h - 400h) + 40h ( Data ROM Window start address in data space) = 61h
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3.2 PROGRAMMING MODES 3.2.1 Program Memory EPROM/OTP programming mode is set by a +12.5V voltage applied to the TEST/VPP pin. The programming flow of the ST62T08C,T09C,T10C, T20C and E20C is described in the User Manual of the EPROM Programming Board. Table 3. ST6208C/09C Program Memory Map
Device Address 0000h-0B9Fh 0BA0h-0F9Fh 0FA0h-0FEFh 0FF0h-0FF7h 0FF8h-0FFBh 0FFCh-0FFDh 0FFEh-0FFFh Description Reserved User ROM Reserved Interrupt Vectors Reserved NMI Interrupt Vector Reset Vector
Table 4. ST6210C Program Memory Map
Device Address 0000h-087Fh 0880h-0F9Fh 0FA0h-0FEFh 0FF0h-0FF7h 0FF8h-0FFBh 0FFCh-0FFDh 0FFEh-0FFFh Description Reserved User ROM Reserved Interrupt Vectors Reserved NMI Interrupt Vector Reset Vector
STMicroelectronics (please refer to Section 12 on page 99). 3.2.2 EPROM Erasing The EPROM devices can be erased by exposure to Ultra Violet light. The characteristics of the MCU are such that erasure begins when the memory is exposed to light with a wave lengths shorter than approximately 4000Å. It should be noted that sunlight and some types of fluorescent lamps have wavelengths in the range 3000-4000Å. It is thus recommended that the window of the MCU packages be covered by an opaque label to prevent unintentional erasure problems when testing the application in such an environment. The recommended erasure procedure is exposure to short wave ultraviolet light which have a wavelength 2537Å. The integrated dose (i.e. U.V. intensity x exposure time) for erasure should be a minimum of 30W-sec/cm2. The erasure time with this dosage is approximately 30 to 40 minutes using an ultraviolet lamp with 12000W/cm2 power rating. The EPROM device should be placed within 2.5cm (1inch) of the lamp tubes during erasure.
Table 5. ST6220C Program Memory Map
Device Address 0000h-007Fh 0080h-0F9Fh 0FA0h-0FEFh 0FF0h-0FF7h 0FF8h-0FFBh 0FFCh-0FFDh 0FFEh-0FFFh Description Reserved User ROM Reserved Interrupt Vectors Reserved NMI Interrupt Vector Reset Vector
Note: OTP/EPROM devices can be programmed with the development tools available from
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3.3 OPTION BYTES Each device is available for production in user programmable versions (OTP) as well as in factory coded versions (ROM). OTP devices are shipped to customers with a default content (00h), while ROM factory coded parts contain the code supplied by the customer. This implies that OTP devices have to be configured by the customer using the Option Bytes while the ROM devices are factory-configured. The two option bytes allow the hardware configuration of the microcontroller to be selected. The option bytes have no address in the memory map and can be accessed only in programming mode (for example using a standard ST6 programming tool). In masked ROM devices, the option bytes are fixed in hardware by the ROM code (see Section 11.6.2 "ROM VERSION" on page 98). It is therefore impossible to read the option bytes. The option bytes can be only programmed once. It is not possible to change the selected options after they have been programmed. In order to reach the power consumption value indicated in Section 10.4, the option byte must be programmed to its default value. Otherwise, an over-consumption will occur. MSB OPTION BYTE Bits 15:10 = Reserved, must be always cleared. Bit 9 = EXTCNTL External STOP MODE control. 0: EXTCNTL mode not available. STOP mode is not available with the watchdog active. 1: EXTCNTL mode available. STOP mode is available with the watchdog active by setting NMI pin to one. Bit 8 = LVD Low Voltage Detector on/off. This option bit enable or disable the Low Voltage Detector (LVD) feature. 0: Low Voltage Detector disabled 1: Low Voltage Detector enabled
MSB OPTION BYTE 15 Reserved Default Value X X X X X X EXT CTL X 8 LVD X 7 PRONMI TIM OSC Res. Res. TECT PULL PULL X X X X X X WD ACT X
LSB OPTION BYTE Bit 7 = PROTECT Readout Protection. This option bit enables or disables external access to the internal program memory. 0: Program memory not read-out protected 1: Program memory read-out protected Bit 6 = OSC Oscillator selection. This option bit selects the main oscillator type. 0: Quartz crystal, ceramic resonator or external clock 1: RC network Bit 5 = Reserved, must be always cleared. Bit 4 = Reserved, must be always set. Bit 3 = NMI PULL NMI Pull-Up on/off. This option bit enables or disables the internal pullup on the NMI pin. 0: Pull-up disabled 1: Pull-up enabled Bit 2 = TIM PULL TIMER Pull-Up on/off. This option bit enables or disables the internal pullup on the TIMER pin. 0: Pull-up disabled 1: Pull-up enabled Bit 1 = WDACT Hardware or software watchdog. This option bit selects the watchdog type. 0: Software (watchdog to be enabled by software) 1: Hardware (watchdog always enabled) Bit 0 = OSGEN Oscillator Safeguard on/off. This option bit enables or disables the oscillator Safeguard (OSG) feature. 0: Oscillator Safeguard disabled 1: Oscillator Safeguard enabled
LSB OPTION BYTE 0 OSG EN X
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4 CENTRAL PROCESSING UNIT
4.1 INTRODUCTION The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought of as an independent central processor communicating with on-chip I/O, Memory and Peripherals via internal address, data, and control bus es . 4.2 MAIN FEATURES
s s s s s s s
40 basic instructions 9 main addressing modes Two 8-bit index registers Two 8-bit short direct registers Low power modes Maskable hardware interrupts 6-level hardware stack
4.3 CPU REGISTERS The ST6 Family CPU core features six registers and three pairs of flags available to the programmer. These are described in the following paragraphs. Accumulator (A). The accumulator is an 8-bit general purpose register used in all arithmetic calculations, logical operations, and data manipulaFigure 7. CPU Registers
7 RESET VALUE = xxh 7 RESET VALUE = xxh 7 RESET VALUE = xxh 7 0 0 0 0
tions. The accumulator can be addressed in Data Space as a RAM location at address FFh. Thus the ST6 can manipulate the accumulator just like any other register in Data Space. Index Registers (X, Y). These two registers are used in Indirect addressing mode as pointers to memory locations in Data Space. They can also be accessed in Direct, Short Direct, or Bit Direct addressing modes. They are mapped in Data Space at addresses 80h (X) and 81h (Y) and can be accessed like any other memory location. Short Direct Registers (V, W). These two registers are used in Short Direct addressing mode. This means that the data stored in V or W can be accessed with a one-byte instruction (four CPU cycles). V and W can also be accessed using Direct and Bit Direct addressing modes. They are mapped in Data Space at addresses 82h (V) and 83h (W) and can be accessed like any other memory location. Note: The X and Y registers can also be used as Short Direct registers in the same way as V and W. Program Counter (PC). The program counter is a 12-bit register which contains the address of the next instruction to be executed by the core. This ROM location may be an opcode, an operand, or the address of an operand.
ACCUMULATOR SIX LEVEL STACK X INDEX REGISTER NORMAL FLAGS Y INDEX REGISTER INTERRUPT FLAGS V SHORT INDIRECT REGISTER RESET VALUE = xxh 7 0 W SHORT INDIRECT REGISTER RESET VALUE = xxh 11 0 x = Undefined value NMI FLAGS CI ZI CN ZN
CNMI ZNMI
PROGRAM COUNTER RESET VALUE = RESET VECTOR @ 0FFEh-0FFFh
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CPU REGISTERS (Cont'd) The 12-bit length allows the direct addressing of 4096 bytes in Program Space. However, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the Program ROM Page register. The PC value is incremented after reading the address of the current instruction. To execute relative jumps, the PC and the offset are shifted through the ALU, where they are added; the result is then shifted back into the PC. The program counter can be changed in the following ways: JP (Jump) instruction PC = Jump address CALL instruction PC = Call address Relative Branch InstructionPC = PC +/- offset Interrupt PC = Interrupt vector Reset PC = Reset vector RET & RETI instructions PC = Pop (stack) Normal instruction PC = PC + 1 Flags (C, Z). The ST6 CPU includes three pairs of flags (Carry and Zero), each pair being associated with one of the three normal modes of operation: Normal mode, Interrupt mode and Non Maskable Interrupt mode. Each pair consists of a CARRY flag and a ZERO flag. One pair (CN, ZN) is used during Normal operation, another pair is used during Interrupt mode (CI, ZI), and a third pair is used in the Non Maskable Interrupt mode (CNMI, ZNMI). The ST6 CPU uses the pair of flags associated with the current mode: as soon as an interrupt (or a Non Maskable Interrupt) is generated, the ST6 CPU uses the Interrupt flags (or the NMI flags) instead of the Normal flags. When the RETI instruction is executed, the previously used set of flags is restored. It should be noted that each flag set can only be addressed in its own context (Non Maskable Interrupt, Normal Interrupt or Main routine). The flags are not cleared during context switching and thus retain their status. C : Carry flag. This bit is set when a carry or a borrow occurs during arithmetic operations; otherwise it is cleared. The Carry flag is also set to the value of the bit tested in a bit test instruction; it also participates in the rotate left instruction. 0: No carry has occured 1: A carry has occured
Z : Zero flag This flag is set if the result of the last arithmetic or logical operation was equal to zero; otherwise it is cleared. 0: The result of the last operation is different from zero 1: The result of the last operation is zero Switching between the three sets of flags is performed automatically when an NMI, an interrupt or a RETI instruction occurs. As NMI mode is automatically selected after the reset of the MCU, the ST6 core uses the NMI flags first. Stack. The ST6 CPU includes a true LIFO (Last In First Out) hardware stack which eliminates the need for a stack pointer. The stack consists of six separate 12-bit RAM locations that do not belong to the data space RAM area. When a subroutine call (or interrupt request) occurs, the contents of each level are shifted into the next level down, while the content of the PC is shifted into the first level (the original contents of the sixth stack level are lost). When a subroutine or interrupt return occurs (RET or RETI instructions), the first level register is shifted back into the PC and the value of each level is popped back into the previous level. Figure 8. Stack manipulation
PROGRAM COUNTER
ON RETURN FROM INTERRUPT, OR SUBROUTINE
LEVEL 1 LEVEL 2 LEVEL 3 LEVEL 4 LEVEL 5 LEVEL 6
ON INTERRUPT, OR SUBROUTINE CALL
Since the accumulator, in common with all other data space registers, is not stored in this stack, management of these registers should be performed within the subroutine. Caution: The stack will remain in its "deepest" position if more than 6 nested calls or interrupts are executed, and consequently the last return address will be lost. It will also remain in its highest position if the stack is empty and a RET or RETI is executed. In this case the next instruction will be executed.
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5 CLOCKS, SUPPLY AND RESET
5.1 CLOCK SYSTEM The main oscillator of the MCU can be driven by any of these clock sources: external clock signal external AT-cut parallel-resonant crystal external ceramic resonator external RC network (RNET). In addition, an on-chip Low Frequency Auxiliary Oscillator (LFAO) is available as a back-up clock system or to reduce power consumption. An optional Oscillator Safeguard (OSG) filters spikes from the oscillator lines, and switches to the LFAO backup oscillator in the event of main oscillator failure. It also automatically limits the internal clock frequency (fINT) as a function of VDD, in order to guarantee correct operation. These functions are illustrated in Figure 10, and Figure 11. Figure 9. Clock Circuit Block Diagram
OSCILLATOR SAFEGUARD (OSG) SPI fOSC OSG filtering : 13 CORE 8-BIT TIMER 0 MAI N OSCILLATOR 1 ADC LFAO OSCOFF BIT * (ADCR REGISTER) :1 :3 8-BIT ARTIMER 8-BIT ARTIMER Oscillator Divider fINT : 12 WATCHDOG *
Table 6 illustrates various possible oscillator configurations using an external crystal or ceramic resonator, an external clock input, an external resistor (RNET), or the lowest cost solution using only the LFAO. For more details on configuring the clock options, refer to the Option Bytes section of this document. The internal MCU clock frequency (fINT) is divided by 12 to drive the Timer, the Watchdog timer and the A/D converter, by 13 to drive the CPU core and the SPI and by 1 or 3 to drive the ARTIMER, as shown in Figure 9. With an 8 MHz oscillator, the fastest CPU cycle is therefore 1.625s. A CPU cycle is the smallest unit of time needed to execute any operation (for instance, to increment the Program Counter). An instruction may require two, four, or five CPU cycles for execution.
OSG ENABLE OPTION BIT (See OPTION BYTE SECTION) * Depending on device. See device summary on page 1.
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RC Network Option1)
CLOCK SYSTEM (Cont'd) 5.1.1 Main Oscillator The oscillator configuration is specified by selecting the appropriate option in the option bytes (refer to the Option Bytes section of this document). When the CRYSTAL/RESONATOR option is selected, it must be used with a quartz crystal, a ceramic resonator or an external signal provided on the OSCin pin. When the RC NETWORK option is selected, the system clock is generated by an external resistor (the capacitor is implemented internally). The main oscillator can be turned off (when the OSG ENABLED option is selected) by setting the OSCOFF bit of the ADC Control Register (not available on some devices). This will automatically start the Low Frequency Auxiliary Oscillator (LFAO). The main oscillator can be turned off by resetting the OSCOFF bit of the A/D Converter Control Register or by resetting the MCU. When the main oscillator starts there is a delay made up of the oscillator start-up delay period plus the duration of the software instruction at a clock frequency fLFAO. Caution: It should be noted that when the RC network option is selected, the accuracy of the frequency is about 20% so it may not be suitable for some applications (For more details, please refer to the Electrical Characteristics Section).
Table 6. Oscillator Configurations
Hardware Configuration Crystal/Resonator Option1) External Clock ST6 OSCin OSCout NC EXTERNAL CLOCK Crystal/Resonator Clock 2) ST6 OSCin OSCout
Crystal/Resonator Option1)
CL 1
LOAD CAPACITORS 3) RC Network
ST6
CL2
OSCin NC
OSCout
R NET
OSG Enabled Option1)
LFAO
ST6
OSCin
OSCout NC
Notes: 1. To select the options shown in column 1 of the above table, refer to the Option Byte section. 2.This schematic are given for guidance only and are subject to the schematics given by the crystal or ceramic resonator manufacturer. 3. For more details, please refer to the Electrical Characteristics Section.
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CLOCK SYSTEM (Cont'd) 5.1.2 Oscillator Safeguard (OSG) The Oscillator Safeguard (OSG) feature is a means of dramatically improving the operational integrity of the MCU. It is available when the OSG ENABLED option is selected in the option byte (refer to the Option Bytes section of this document). The OSG acts as a filter whose cross-over frequency is device dependent and provides three basic functions: Filtering spikes on the oscillator lines which would result in driving the CPU at excessive frequencies Management of the Low Frequency Auxiliary Oscillator (LFAO), (useable as low cost internal clock source, backup clock in case of main oscillator failure or for low power consumption) Automatically limiting the fINT clock frequency as a function of supply voltage, to ensure correct operation even if the power supply drops. 5.1.2.1 Spike Filtering Spikes on the oscillator lines result in an effectively increased internal clock frequency. In the absence of an OSG circuit, this may lead to an over frequency for a given power supply voltage. The OSG filters out such spikes (as illustrated in Figure 10). In all cases, when the OSG is active, the max-
imum internal clock frequency, fINT, is limited to fOSG, which is supply voltage dependent. 5.1.2.2 Management of Supply Voltage Variations Over-frequency, at a given power supply level, is seen by the OSG as spikes; it therefore filters out some cycles in order that the internal clock frequency of the device is kept within the range the particular device can stand (depending on VDD), and below fOSG: the maximum authorised frequency with OSG enabled. 5.1.2.3 LFAO Management When the OSG is enabled, the Low Frequency Auxiliary Oscillator can be used (see Section 5.1.3). Note: The OSG should be used wherever possible as it provides maximum security for the application. It should be noted however, that it can increase power consumption and reduce the maximum operating frequency to fOSG (see Electrical Characteristics section). Caution: Care has to be taken when using the OSG, as the internal frequency is defined between a minimum and a maximum value and may vary depending on both VDD and temperature. For precise timing measurements, it is not recommended to use the OSG.
Figure 10. OSG Filtering Function
fOSC>fOSG fOSC fOSG fOSC
fINT
Figure 11. LFAO Oscillator Function
MAIN OSCILLATOR STOPS fOSC fLFAO fINT MAIN OSCILLATOR RESTARTS
INTERNAL CLOCK DRIVEN BY LFAO
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CLOCK SYSTEM (Cont'd) 5.1.3 Low Frequency Auxiliary Oscillator (LFAO) The Low Frequency Auxiliary Oscillator has three main purposes. Firstly, it can be used to reduce power consumption in non timing critical routines. Secondly, it offers a fully integrated system clock, without any external components. Lastly, it acts as a backup oscillator in case of main oscillator failure. This oscillator is available when the OSG ENABLED option is selected in the option byte (refer to the Option Bytes section of this document). In this case, it automatically starts one of its periods after the first missing edge of the main oscillator, whatever the reason for the failure (main oscillator defective, no clock circuitry provided, main oscillator sw itched off...). See Figure 11. User code, normal interrupts, WAIT and STOP instructions, are processed as normal, at the reduced fLFAO frequency. The A/D converter accuracy is decreased, since the internal frequency is below 1.2 MHz. At power on, until the main oscillator starts, the reset delay counter is driven by the LFAO. If the main oscillator starts before the 2048 cycle delay has elapsed, it takes over.
The Low Frequency Auxiliary Oscillator is automatically switched off as soon as the main oscillator starts. 5.1.4 Register Description ADC CONTROL REGISTER (ADCR) Address: 0D1h -- Read/Write Reset value: 0100 0000 (40h)
7 ADCR ADCR ADCR ADCR ADCR 7 6 5 4 3 OSC OFF 0 ADCR ADCR 1 0
Bit 7:3, 1:0 = ADCR[7:3], ADCR[1:0] ADC Control Register. These bits are used to control the A/D converter (if available on the device) otherwise they are not us ed. Bit 2 = OSCOFF Main Oscillator Off. 0: Main oscillator enabled 1: Main oscillator disabled Note: The OSG must be enabled using the OSGEN option in the Option Byte, otherwise the OSCOFF setting has no effect.
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5.2 LOW VOLTAGE DETECTOR (LVD) The on-chip Low Voltage Detector is enabled by setting a bit in the option bytes (refer to the Option Bytes section of this document). The LVD allows the device to be used without any external RESET circuitry. In this case, the RESET pin should be left unconnected. If the LVD is not used, an external circuit is mandatory to ensure correct Power On Reset operation, see figure in the Reset section. For more details, please refer to the application note AN669. The LVD generates a static Reset when the supply voltage is below a reference value. This means that it secures the power-up as well as the powerdown keeping the ST6 in reset. The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). Figure 12. Low Voltage Detector Reset
VDD Vhyst VIT+ VIT-
The LVD Reset circuitry generates a reset when VDD is below: VIT+ when VDD is rising VIT- when VDD is falling The LVD function is illustrated in Figure 12. If the LVD is enabled, the MCU can be in only one of two states: Over the input threshold voltage, it is running under full software control Below the input threshold voltage, it is in static safe reset In these conditions, secure operation is guaranteed without the need for external reset hardware. During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices.
RESET
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5.3 RESET 5.3.1 Introduction The MCU can be reset in three ways: s A low pulse input on the RESET pin s Internal Watchdog reset s Internal Low Voltage Detector (LVD) reset 5.3.2 RESET Sequence The basic RESET sequence consists of 3 main phas es : s Internal (watchdog or LVD) or external Reset event s A delay of 2048 clock (fI NT) cycles s RESET vector fetch The reset delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. Figure 13. RESET Sequence VDD
VIT+ VIT-
The RESET vector fetch phase duration is 2 clock cycles. When a reset occurs: The stack is cleared The PC is loaded with the address of the Reset vector. It is located in program ROM starting at address 0FFEh. A jump to the beginning of the user program must be coded at this address. The interrupt flag is automatically set, so that the CPU is in Non Maskable Interrupt mode. This prevents the initialization routine from being interrupted. The initialization routine should therefore be terminated by a RETI instruction, in order to go back to normal mode.
WATCHDOG RESET WATCHDOG UNDERFLOW
LVD RESET
RESET PIN
INTERNAL RESET
RUN
RUN
RUN
RUN
RESET
RESET
RESET 2048 CLOCK CYCLE (fINT) DELAY
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RESET (Cont'd) 5.3.3 RESET Pin The RESET pin may be connected to a device on the application board in order to reset the MCU if required. The RESET pin may be pulled low in RUN, WAIT or STOP mode. This input can be used to reset the internal state of the MCU and ensure it starts-up correctly. The pin, which is connected to an internal pull-up, is active low and features a Schmitt trigger input. A delay (2048 clock cycles) added to the external signal ensures that even short pulses on the RESET pin are accepted as valid, provided VDD has completed its rising phase and that the oscillator is running correctly (normal RUN or WAIT modes). The MCU is kept in the Reset state as long as the RESET pin is held low. Figure 14. Reset Block Diagram
If the RESET pin is grounded while the MCU is in RUN or WAIT modes, processing of the user program is stopped (RUN mode only), the I/O ports are configured as inputs with pull-up resistors and the main oscillator is restarted. When the level on the RESET pin then goes high, the initialization sequence is executed at the end of the internal delay period. If the RESET pin is grounded while the MCU is in STOP mode, the oscillator starts up and all the I/O ports are configured as inputs with pull-up resistors. When the RESET pin level then goes high, the initialization sequence is executed at the end of the internal delay period. A simple external RESET circuitry is shown in Figure 15. For more details, please refer to the application note AN669.
RPU
RESET RESD1) WATCHDOG RESET LVD RESET
1) Resistive ESD protection.
COUNTER
VDD
2048 clock cycles
fINT
INTERNAL RESET
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RESET (Cont'd) 5.3.4 Watchdog Reset The MCU provides a Watchdog timer function in order to be able to recover from software hangups. If the Watchdog register is not refreshed before an end-of-count condition is reached, a Watchdog reset is generated. After a Watchdog reset, the MCU restarts in the same way as if a Reset was generated by the RESET pin. Note: When a watchdog reset occurs, the RESET pin is tied low for very short time period, to flag the reset phase. This time is not long enough to reset external circuits. For more details refer to the Watchdog Timer chapter. 5.3.5 LVD Reset Two different RESET sequences caused by the internal LVD circuitry can be distinguished: s Powe r-O n RESET s Vol tage Drop RESET During an LVD reset, the RESET pin is pulled low when VDD
Figure 16. Reset Processing
RESET 2048 CLOCK CYCLE DELAY INTERNAL RESET
NMI MASK SET INT LATCH CLEARED (IF PRESENT)
SELECT NMI MODE FLAGS
PUT FFEh ON ADDRESS BUS
YES
IS RESET STILL PRESENT? NO LOAD PC FROM RESET LOCATIONS FFEh/FFFh
V DD R
VDD
FETCH INSTRUCTION
RESET C Typical: R = 10K C = 10nF ST62xx R > 4.7 K
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5.4 INTERRUPTS The ST6 core may be interrupted by four maskable interrupt sources, in addition to a Non Maskable Interrupt (NMI) source. The interrupt processing flowchart is shown in Figure 18. Maskable interrupts must be enabled by setting the GEN bit in the IOR register. However, even if they are disabled (GEN bit = 0), interrupt events are latched and may be processed as soon as the GEN bit is set. Each source is associated with a specific Interrupt Vector, located in Program space (see Table 8). In the vector location, the user must write a Jump inFigure 17. Interrupts Block Diagram
VD D
struction to the associated interrupt service routine. When an interrupt source generates an interrupt request, the PC register is loaded with the address of the interrupt vector, which then causes a Jump to the relevant interrupt service routine, thus servicing the interrupt. Interrupt are triggered by events either on external pins, or from the on-chip peripherals. Several events can be ORed on the same interrupt vector. On-chip peripherals have flag registers to determine which event triggered the interrupt.
NMI
LAT CH CLEARED BY H/W AT START OF VECTOR #0 ROUTINE
VECTOR #0
PA0...PA3
I/O PORT REGISTER "INPUT WITH INTERRUPT" CONFIGURATION
LATCH 0 VECTOR #1 CLEARED BY H/W AT START OF VECTOR #1 ROUTINE
1
LES BIT EXIT FROM STOP/WAIT
(IOR REGISTER)
PB0...PB7
I/O PORT REGISTER "INPUT WITH INTERRUPT" CONFIGURATION
LATCH
VECTOR #2
ESB BIT (IOR REGISTER) CLEARED BY H/W AT START OF VECTOR #2 ROUTINE TMZ BIT ETI BIT VECTOR #3
TIMER
(TSCR REGISTER) EAI BIT EOC BIT GEN BIT (IOR REGISTER) VECTOR #4
A/D CONVERTER *
(ADCR REGISTER)
* Depending on device. See device summary on page 1.
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5.5 INTERRUPT MANA GEMENT
s
RULES
AND
PRIORITY
5.7 NON MASKABLE INTERRUPT This interrupt is triggered when a falling edge occurs on the NMI pin regardless of the state of the GEN bit in the IOR register. An interrupt request on NMI vector #0 is latched by a flip flop which is automatically reset by the core at the beginning of the NMI service routine. 5.8 PERIPHERAL INTERRUPTS Different peripheral interrupt flags in the peripheral control registers are able to cause an interrupt when they are active if both: The GEN bit of the IOR register is set The corresponding enable bit is set in the peripheral control register. Peripheral interrupts are linked to vectors #3 and #4. Interrupt requests are flagged by a bit in their corresponding control register. This means that a request cannot be lost, because the flag bit must be cleared by user software.
s
s
A Reset can interrupt the NMI and peripheral interrupt routines The Non Maskable Interrupt request has the highest priority and can interrupt any peripheral interrupt routine at any time but cannot interrupt another NMI interrupt. No peripheral interrupt can interrupt another. If more than one interrupt request is pending, these are processed by the processor core according to their priority level: vector #1 has the highest priority while vector #4 the lowest. The priority of each interrupt source is fixed by hardware (see Interrupt Mapping table).
5.6 INTERRUPTS AND LOW POWER MODES All interrupts cause the processor to exit from WAIT mode. Only the external and some specific interrupts from the on-chip peripherals cause the processor to exit from STOP mode (refer to the "Exit from STOP" column in the Interrupt Mapping Table).
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5.9 EXTERNAL INTERRUPTS (I/O Ports) External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the GEN bit is set. These interrupts allow the processor to exit from STOP mode. The external interrupt polarity is selected through the IOR register. External interrupts are linked to vectors #1 and # 2. Interrupt requests on vector #1 can be configured either as edge or level-sensitive using the LES bit in the IOR Register. Interrupt requests from vector #2 are always edge sensitive. The edge polarity can be configured using the ESB bit in the IOR Register. In edge-sensitive mode, a latch is set when a edge occurs on the interrupt source line and is cleared when the associated interrupt routine is started. So, an interrupt request can be stored until completion of the currently executing interrupt routine, before being processed. If several interrupt requests occurs before completion of the current interrupt routine, only the first request is stored. Storing of interrupt requests is not possible in level sensitive mode. To be taken into account, the low level must be present on the interrupt pin when the MCU samples the line after instruction execution. 5.9.1 Notes on using External Interrupts ESB bit Spurious Interrupt on Vector #2 If a pin associated with interrupt vector #2 is configured as interrupt with pull-up, whenever vector #2 is configured to be rising edge sensitive (by setting the ESB bit in the IOR register), an interrupt is latched although a rising edge may not have occured on the associated pin. This is due to the vector #2 circuitry.The workaround is to discard this first interrupt request in the routine (using a flag for example). Masking of One Interrupt by Another on Vector #2. When two or more port pins (associated with interrupt vector #2) are configured together as input with interrupt (falling edge sensitive), as long as one pin is stuck at '0', the other pin can never generate an interrupt even if an active edge occurs at this pin. The same thing occurs when one pin is stuck at '1' and interrupt vector #2 is configured as rising edge sensitive. To avoid this the first pin must input a signal that goes back up to '1' right after the falling edge. Otherwise, in the interrupt routine for the first pin, deactivate the "input with interrupt" mode using the port control registers (DDR, OR, DR). An active edge on another pin can then be latched. I/O port Configuration Spurious Interrupt on Vector #2 If a pin associated with interrupt vector #2 is in `input with pull-up' state, a `0' level is present on the pin and the ESB bit = 0, when the I/O pin is configured as interrupt with pull-up by writing to the DDRx, ORx and DRx register bits, an interrupt is latched although a falling edge may not have occurred on the associated pin. In the opposite case, if the pin is in interrupt with pull-up state , a 0 level is present on the pin and the ESB bit =1, when the I/O port is configured as input with pull-up by writing to the DDRx, ORx and DRx bits, an interrupt is latched although a rising edge may not have occurred on the associated pin.
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5.10 INTERRUPT HANDLING PROCEDURE The interrupt procedure is very similar to a call procedure, in fact the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event, the user cannot know the context and the time at which it occurred. As a result, the user should save all Data space registers which may be used within the interrupt routines. The following list summarizes the interrupt procedure: When an interrupt request occurs, the following actions are performed by the MCU automatically: The core switches from the normal flags to the interrupt flags (or the NMI flags). The PC contents are stored in the top level of the stack. The normal interrupt lines are inhibited (NMI still active). The internal latch (if any) is cleared. The associated interrupt vector is loaded in the PC. When an interrupt request occurs, the following actions must be performed by the user software: User selected registers have to be saved within the interrupt service routine (normally on a software stack). The source of the interrupt must be determined by polling the interrupt flags (if more than one source is associated with the same vector). The RETI (RETurn from Interrupt) instruction must end the interrupt service routine. After the RETI instruction is executed, the MCU returns to the main routine. Caution: When a maskable interrupt occurs while the ST6 core is in NORMAL mode and during the execution of an "ldi IOR, 00h" instruction (disabling all maskable interrupts): if the interrupt request occurs during the first 3 cycles of the "ldi" instruction (which is a 4-cycle instruction) the core will switch to interrupt mode BUT the flags CN and ZN will NOT switch to the interrupt pair CI and ZI. 5.10.1 Interrupt Response Time This is defined as the time between the moment when the Program Counter is loaded with the interrupt vector and when the program has jump to the interrupt subroutine and is ready to execute the code. It depends on when the interrupt occurs while the core is processing an instruction. Figure 18. Interrupt Processing Flow Chart
INST RUCTION
FETCH INST RUCTION
EXECUTE INST RUCTION
LOAD PC FROM INTERRUPT VECTOR
WAS THE INSTRUCTION A RETI ? YES YES IS THE CORE ALREADY IN NORMAL MODE?
NO C LE A R INTERNAL LATCH *)
DISABLE MASKABLE INTERRUPT
NO ENABLE MASKABLE INTERRUPTS PUSH THE PC INTO THE STACK
SELECT NORMAL FLAGS
SELECT INTERRUPT FLAGS
" P OP " THE STACKED PC
NO
IS THERE AN AN INTERRUPT REQUEST AND INTERRUPT MASK?
YES
*)
If a latch is present on the interrupt source line
Table 7. Interrupt Response Time
Minimum Maximum 6 CPU cycles 11 CPU cycles
One CPU cycle is 13 external clock cycles thus 11 CPU cycles = 11 x (13 /8M) = 17.875 s with an 8 MHz external quartz.
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5.11 REGISTER DESCRIPTION INTERRUPT OPTION REGISTER (IOR) Address: 0C8h -- Write Only Reset status: 00h
7 LES ESB GEN 0 -
1: Low level sensitive mode is selected for interrupt vector #1 Bit 5 = ESB Edge Selection bit. 0: Falling edge mode on interrupt vector #2 1: Rising edge mode on interrupt vector #2 Bit 4 = GEN Global Enable Interrupt. 0: Disable all maskable interrupts 1: Enable all maskable interrupts Note: When the GEN bit is cleared, the NMI interrupt is active but cannot be used to exit from STOP or WAIT modes. Bits 3:0 = Reserved, must be cleared.
Caution: This register is write-only and cannot be accessed by single-bit operations (SET, RES, DEC ,...). Bit 7 =Reserved, must be cleared. Bit 6 = LES Level/Edge Selection bit. 0: Falling edge sensitive mode is selected for interrupt vector #1 Table 8. Interrupt Mapping
Vector number Vector #0 Source Block RESET NMI Description Reset Non Maskable Interrupt NOT USED Vector #1 Vector #2 Vector #3 Vector #4 Port A Port B TIMER ADC* Ext. Interrupt Port A Ext. Interrupt Port B Timer underflow End Of Conversion
Register Label N/A N/A
Flag N/A N/A
Exit from STOP yes yes
Vector Address FFEh-FFFh FFCh-FFDh FFAh-FFBh FF8h-FF9h FF6h-FF7h FF4h-FF5h FF2h-FF3h FF0h-FF1h
Priority Order Highest Priority
N/A N/A TSCR ADCR
N/A N/A TMZ EOC
yes yes yes no
Lowest Priority
* Depending on device. See device summary on page 1.
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6 POWER SAVING MODES
6.1 INTRODUCTION To give a large measure of flexibility to the application in terms of power consumption, two main power saving modes are implemented in the ST6 (see Figure 19). In addition, the Low Frequency Auxiliary Oscillator (LFAO) can be used instead of the main oscillator to reduce power consumption in RUN and WAIT modes. After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency. From Run mode, the different power saving modes may be selected by calling the specific ST6 software instruction or for the LFAO by setting the relevant register bit. For more information on the LFAO, please refer to the Clock chapter. Figure 19. Power Saving Mode Transitions
High RUN LFAO WAIT
STOP Low POWER CONSUMPTION
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6.2 WAIT MODE The MCU goes into WAIT mode as soon as the WAIT instruction is executed. This has the following effects: Program execution is stopped, the microcontroller software can be considered as being in a "frozen" state. RAM contents and peripheral registers are preserved as long as the power supply voltage is higher than the RAM retention voltage. The oscillator is kept running to provide a clock to the peripherals; they are still active. WAIT mode can be used when the user wants to reduce the MCU power consumption during idle periods, while not losing track of time or the ability to monitor external events. WAIT mode places the MCU in a low power consumption mode by stopping the CPU. The active oscillator (main oscillator or LFAO) is kept running in order to provide a clock signal to the peripherals. If the power consumption has to be further reduced, the Low Frequency Auxiliary Oscillator (LFAO) can be used in place of the main oscillator, if its operating frequency is lower. If required, the LFAO must be switched on before entering WAIT mode. Exit from Wait mode The MCU remains in WAIT mode until one of the following events occurs: RESET (Watchdog, LVD or RESET pin) A peripheral interrupt (timer, ADC,...), An external interrupt (I/O port, NMI) The Program Counter then branches to the starting address of the interrupt or RESET service routine. Refer to Figure 20. See also Section 6.4.1. Figure 20. WAIT Mode Flowchart
OSCILLATOR WAIT INSTRUCTION Clock to CPU On No
Clock to PERIPHERALS Yes
N RESET N INTERRUPT Y
Y
OSCILLATOR Clock to CPU
Restart Yes
Clock to PERIPHERALS Yes
2048 CLOCK CYCLE DELAY
OSCILLATOR
On
Clock to PERIPHERALS Yes Clock to CPU Yes
FETCH RESET VECTOR OR SERVICE INTERRUPT
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6.3 STOP MODE STOP mode is the lowest power consumption mode of the MCU (see Figure 22). The MCU goes into STOP mode as soon as the STOP instruction is executed. This has the following effects: Program execution is stopped, the microcontroller can be considered as being "frozen". The contents of RAM and the peripheral registers are kept safely as long as the power supply voltage is higher than the RAM retention voltage. The oscillator is stopped, so peripherals cannot work except the those that can be driven by an external clock. Exit from STOP Mode The MCU remains in STOP mode until one of the following events occurs: RESET (Watchdog, LVD or RESET pin) A peripheral interrupt (assuming this peripheral can be driven by an external clock) An external interrupt (I/O port, NMI) In all cases a delay of 2048 clock cycles (fINT) is generated to make sure the oscillator has started properly. The Program Counter then points to the starting address of the interrupt or RESET service routine (see Figure 21). STOP Mode and Watchdog When the Watchdog is active (hardware or software activation), the STOP instruction is disabled and a WAIT instruction will be executed in its place unless the EXCTNL option bit is set to 1 in the option bytes and a a high level is present on the NMI pin. In this case, the STOP instruction will be executed and the Watchdog will be frozen. Figure 21. STOP Mode Timing Overview
RUN STOP 2048 CLOCK CYCLE DELAY RUN
STOP INSTRUCTION
RESET OR INTERRUPT
FETCH VECTOR
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STOP MODE (Cont'd) Figure 22. STOP Mode Flowchart
STOP INSTRUCTION ENABLE
WATCHDOG DISABLE
EXCTNL VALUE 1) 0
1
0
LEVEL ON NMI PIN
1
OSCILLATOR Clock to PERIPHERALS2) Clock to CPU
Off No No
N
OSCILLATOR Clock to CPU On No
RESET N INTERRUPT 3) Y Y
OSCILLATOR Clock to CPU Restart Yes
Clock to PERIPHERALS Yes
Clock to PERIPHERALS Yes
N
Y RESET
2048 CLOCK CYCLE DELAY
N INTERRUPT
Y
OSCILLATOR Clock to CPU
On Yes
Clock to PERIPHERALS Yes
FETCH RESET VECTOR OR SERVICE INTERRUPT
Notes: 1. EXCTNL is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from STOP mode (such as external interrupt). Refer to the Interrupt Mapping table for more details.
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6.4 NOTES RELATED TO WAIT AND STOP MODES 6.4.1 Exit from Wait and Stop Modes 6.4.1.1 NMI Interrupt It should be noted that when the GEN bit in the IOR register is low (interrupts disabled), the NMI interrupt is active but cannot cause a wake up from STOP/WAIT modes. 6.4.1.2 Restart Sequence When the MCU exits from WAIT or STOP mode, it should be noted that the restart sequence depends on the original state of the MCU (normal, interrupt or non-maskable interrupt mode) prior to entering WAIT or STOP mode, as well as on the interrupt type. Normal Mode. If the MCU was in the main routine when the WAIT or STOP instruction was executed, exit from Stop or Wait mode will occur as soon as an interrupt occurs; the related interrupt routine is executed and, on completion, the instruction which follows the STOP or WAIT instruction is then executed, providing no other interrupts are pendi ng. Non Maskable Interrupt Mode. If the STOP or WAIT instruction has been executed during execution of the non-maskable interrupt routine, the MCU exits from Stop or Wait mode as soon as an interrupt occurs: the instruction which follows the STOP or WAIT instruction is executed, and the MCU remains in non-maskable interrupt mode, even if another interrupt has been generated. Normal Interrupt Mode. If the MCU was in interrupt mode before the STOP or WAIT instruction was executed, it exits from STOP or WAIT mode as soon as an interrupt occurs. Nevertheless, two cases must be considered: If the interrupt is a normal one, the interrupt routine in which the WAIT or STOP mode was entered will be completed, starting with the execution of the instruction which follows the STOP or the WAIT instruction, and the MCU is still in interrupt mode. At the end of this routine pending interrupts will be serviced according to their priority. In the event of a non-maskable interrupt, the non-maskable interrupt service routine is processed first, then the routine in which the WAIT or STOP mode was entered will be completed by executing the instruction following the STOP or WAIT instruction. The MCU remains in normal interrupt mode. 6.4.2 Recommended MCU Configuration For lowest power consumption during RUN or WAIT modes, the user software must configure the MCU as follows: Configure unused I/Os as output push-pull low mode Place all peripherals in their power down modes before entering STOP mode Select the Low Frequency Auxiliary Oscillator (provided this runs at a lower frequency than the main oscillator). The WAIT and STOP instructions are not executed if an enabled interrupt request is pending.
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7 I/O PORTS
7.1 INTRODUCTION Each I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without pull-up and interrupt generation), digital output (open drain, push-pull) or analog input (when available). The I/O pins can be used in either standard or alternate function mode. Standard I/O mode is used for: Transfer of data through digital inputs and outputs (on specific pins): External interrupt generation Alternate function mode is used for: Alternate signal input/output for the on-chip peripherals The generic I/O block diagram is shown in Figure 23. 7.2 FUNCTIONAL DESCRIPTION Each port is associated with 3 registers located in Data space: Data Register (DR) Data Direction Register (DDR) Option Register (OR) Each I/O pin may be programmed using the corresponding register bits in the DDR, DR and OR registers: bit x corresponding to pin x of the port. Table 9 illustrates the various port configurations which can be selected by user software. During MCU initialization, all I/O registers are cleared and the input mode with pull-up and no interrupt generation is selected for all the pins, thus avoiding pin conflicts. 7.2.1 Digital Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the DR and OR registers, see Table 9. External Interrupt Function All input lines can be individually connected by software to the interrupt system by programming the OR and DR registers accordingly. The interrupt trigger modes (falling edge, rising edge and low level) can be configured by software for each port as described in the Interrupt section. 7.2.2 Analog Inputs Some pins can be configured as analog inputs by programming the OR and DR registers accordingly, see Table 9. These analog inputs are connected to the on-chip 8-bit Analog to Digital Converter. Caution: ONLY ONE pin should be programmed as an analog input at any time, since by selecting more than one input simultaneously their pins will be effectively shorted. 7.2.3 Output Modes The output configuration is selected by setting the corresponding DDR register bit. In this case, writing to the DR register applies this digital value to the I/O pin through the latch. Then, reading the DR register returns the previously stored value. Tw o different output modes can be selected by software through the OR register: push-pull and open-drain. DR register value and output pin status:
DR 0 1 Push-pull VSS VDD Open-drain VSS Floating
Note: The open drain setting is not a true open drain. This means it has the same structure as the push-pull setting but the P-buffer is deactivated. To avoid damaging the device, please respect the VOUT absolute maximum rating described in the Electrical Characteristics section. 7.2.4 Alternate Functions When an on-chip peripheral is configured to use a pin, the alternate function (timer input/output...) is not systematically selected but has to be configured through the DDR, OR and DR registers. Refer to the chapter describing the peripheral for more details.
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I/O PORTS (Cont'd) Figure 23. I/O Port Block Diagram
PULL-UP
RESET
VDD VDD
DATA DIRECTION REGISTER
VDD
Pxx I/O Pin DATA REGISTER S T6 INTERNAL B US OPTION REGISTER P-BUFFER
N-BUFFER CLAMPING DIODES
CMOS TO INTERRUPT TO ADC * SCHMITT TRIGGER
* Depending on device. See device summary on page 1.
Table 9. I/O Port Configurations
DDR 0 0 0 0 1 1 OR 0 0 1 1 0 1 DR 0 1 0 1 x x Mode Input Input Input Input Output Output With pull-up, no interrupt No pull-up, no interrupt With pull-up and with interrupt Analog input (when available) Open-drain output (20mA sink when available) Push-pull output (20mA sink when available) Option
Note: x = Don't care
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I/O PORTS (Cont'd) 7.2.5 Instructions NOT to be used to access Port Data registers (SET, RES, INC and DEC) DO NOT USE READ-MODIFY-WRITE INSTRUCTIONS (SET, RES, INC and DEC) ON PORT DATA REGISTERS IF ANY PIN OF THE PORT IS CONFIGURED IN INPUT MODE. These instructions make an implicit read and write back of the entire register. In port input mode, however, the data register reads from the input pins directly, and not from the data register latches. Since data register information in input mode is used to set the characteristics of the input pin (interrupt, pull-up, analog input), these may be unintentionally reprogrammed depending on the state of the input pins. As a general rule, it is better to only use single bit instructions on data registers when the whole (8bit) port is in output mode. In the case of inputs or of mixed inputs and outputs, it is advisable to keep a copy of the data register in RAM. Single bit instructions may then be used on the RAM copy, after which the whole copy register can be written to the port data register: SET bit, datacopy LD a, datacopy LD DRA, a 7.2.6 Recommendations 1. Safe I/O State Switching Sequence Switching the I/O ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. The recommended safe transitions are illustrated in Figure 24 The Interrupt Pull-up to Input Analog transition (and vice-vesra) is potentially risky and should be avoided when changing the I/O operating mode.
2. Handling Unused Port Bits On ports that have less than 8 external pins connec t ed: Leave the unbonded pins in reset state and do not change their configuration. Do not use instructions that act on a whole port register (INC, DEC, or read operations). Unavailable bits must be masked by software (AND instruction). Thus, when a read operation performed on an incomplete port is followed by a comparison, use a mask. 3. High Impedance Input On any CMOS device, it is not recommended to connect high impedance on input pins. The choice of these impedance has to be done with respect to the maximum leakage current defined in the datasheet. The risk is to be close or out of specification on the input levels applied to the device. 7.3 LOW POWER MODES The WAIT and STOP instructions allow the ST62xx to be used in situations where low power consumption is needed. The lowest power consumption is achieved by configuring I/Os in output push-pull low mode.
Mode WAIT STOP Description No effect on I/O ports. External interrupts cause the device to exit from WAIT mode. No effect on I/O ports. External interrupts cause the device to exit from STOP mode.
7.4 INTERRUPTS The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR, DR and OR registers (see Table 9) and the GEN-bit in the IOR register is set.
Input Analog Input
Figure 24. Diagram showing Safe I/O State Transitions Interrupt 010* pull-up
Input pull-up (Reset state) Output Open Drain Output Push-pull
011
000
001
100
101
Output Open Drain Output Push-pull
110
111
Note *. xxx = DDR, OR, DR Bits respectively
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I/O PORTS (Cont'd) Table 10. I/O Port Option Selections
MODE AVAILABLE ON(1) SCHEMATIC
Input PA0-PA3 PB0-PB7 DDRx 0 ORx 0 Reset state Digital Input Input with pull up DDRx 0 ORx 0 Input with pull up with interrupt DDRx 0 Analog Input ORx 1 DRx 0 PB0-PB3 (ST6210C/20C only) DRx 1 PB4-PB7 (All devices, except ST6208C) PB0-PB7 PA0-PA3 PB0-PB7 DRx 0 PA0-PA3 PB0-PB7 DRx 1
V DD
V DD
Data in Interrupt
V DD
V DD
Data in Interrupt
V DD
VDD
Data in Interrupt
Analog Input
V DD
ADC
DDRx 0
ORx 1
Open drain output (5mA)
V DD
P-buffer disconnected
Open drain output (20 mA) PA0-PA3 Digital output DDRx 1 ORx 0 DRx 0/1 PB0-PB7
Data out
Push-pull output (5mA)
V DD
Push-pull output (20 mA) PA0-PA3 DDRx 1 ORx 1 DRx 0/1 Data out
Note 1. Provided the correct configuration has been selected (see Table 9).
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I/O PORTS (Cont'd) 7.5 REGISTER DESCRIPTION DATA REGISTER (DR) Port x Data Register DRx with x = A or B. Address DRA: 0C0h - Read / Write Address DRB: 0C1h - Read / Write Reset Value: 0000 0000 (00h)
7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bits 7:0 = DD[7:0] Data direction register bits. The DDR register gives the input/output direction configuration of the pins. Each bit is set and cleared by software. 0: Input mode 1: Output mode
Bits 7:0 = D[7:0] Data register bits. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input). Caution: In input mode, modifying this register will modify the I/O port configuration (see Table 9). Do not use the Single bit instructions on I/O port data registers. See (Section 7.2.5). DATA DIRECTION REGISTER (DDR) Port x Data Direction Register DDRx with x = A or B. Address DDRA: 0C4h - Read / Write Address DDRB: 0C5h - Read / Write Reset Value: 0000 0000 (00h)
7 DD7 DD6 DD5 DD4 DD3 DD2 DD1 0 DD0
OPTION REGISTER (OR) Port x Option Register ORx with x = A or B. Address ORA: 0CCh - Read/Write Address ORB: 0CDh - Read/Write Reset Value: 0000 0000 (00h)
7 O7 O6 O5 O4 O3 O2 O1 0 O0
Bits 7:0 = O[7:0] Option register bits. The OR register allows to distinguish in output mode if the push-pull or open drain configuration is selected. Output mode: 0: Open drain output(with P-Buffer deactivated) 1: Push-pull Output Input mode: See Table 9. Each bit is set and cleared by software. Caution: Modifying this register, will also modify the I/O port configuration in input mode. (see Table 9).
Table 11. I/O Port Register Map and Reset Values
Address (Hex.) Register Label 7 0 MSB MSB MSB 6 0 5 0 4 0 3 0 2 0 1 0 0 0 LSB LSB LSB
Reset Value of all I/O port registers 0C0h 0C1h 0C4h 0C5h 0CCh 0CDh DRA DRB DDRA DDRB ORA ORB
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8 ON-CHIP PERIPHERALS
8.1 WATCHDOG TIMER (WDG) 8.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter's contents before the SR bit becomes cleared. Figure 25. Watchdog Block Diagram 8.1.2 Main Features s Pro gramm abl e timer (64 steps of 3072 clock cycles) s Software reset s Reset (if watchdog activated) when the SR bit reaches zero s Hardware or software watchdog activation selectable by option bit (Refer to the option bytes section)
RESET
WATCHDOG REGISTER (WDGR) T0 T1 T2 T3 T4 T5 SR C
bit 7
7-BIT DOWNCOUNTER
bi t 0
fint /12
CLOCK DIVIDER ÷ 256
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WATC HDOG TIMER (Cont'd) 8.1.3 Functional Description The watchdog activation is selected through an option in the option bytes: HARDWARE Watchdog option After reset, the watchdog is permanently active, the C bit in the WDGR is forced high and the user can not change it. However, this bit can be read equally as 0 or 1. SOFTWARE Watchdog option After reset, the watchdog is deactivated. The function is activated by setting C bit in the WDGR register. Once activated, it cannot be deactivated. The counter value stored in the WDGR register (bits SR:T0), is decremented every 3072 clock cycles. The length of the timeout period can be programmed by the user in 64 steps of 3072 clock cycles. If the watchdog is activated (by setting the C bit) and when the SR bit is cleared, the watchdog initiates a reset cycle pulling the reset pin low for typically 500ns. The application program must write in the WDGR register at regular intervals during normal operation to prevent an MCU reset. The value to be stored in the WDGR register must be between FEh and 02h (see Table 12). To run the watchdog function the following conditions must be true: The C bit is set (watchdog activated) The SR bit is set to prevent generating an immediate reset The T[5:0] bits contain the number of decrements which represent the time delay before the watchdog produces a reset. Table 12. Watchdog Timing (fOSC = 8 MHz)
WDGR Register initial value FEh 02h WDG timeout period (ms) 24.576 0.384
mode availability (refer to the description of the WDACT and EXTCNTL bits on the Option Bytes). When STOP mode is not required, hardware activation without EXTERNAL STOP MODE CONTR OL should be preferred, as it provides maximum security, especially during power-on. When STOP mode is required, hardware activation and EXTERNAL STOP MODE CONTROL should be chosen. NMI should be high by default, to allow STOP mode to be entered when the MCU is idle. The NMI pin can be connected to an I/O line (see Figure 26) to allow its state to be controlled by software. The I/O line can then be used to keep NMI low while Watchdog protection is required, or to avoid noise or key bounce. When no more processing is required, the I/O line is released and the device placed in STOP mode for lowest power consumption. Figure 26. A typical circuit making use of the EXERNA L STOP MODE CONTROL feature
S W I TC H NM I
I/O
VR02002
Max. Min.
8.1.3.1 Software Reset The SR bit can be used to generate a software reset by clearing the SR bit while the C bit is set. 8.1.4 Recommendations 1. The Watchdog plays an important supporting role in the high noise immunity of ST62xx devices, and should be used wherever possible. Watchdog related options should be selected on the basis of a trade-off between application security and STOP
2. When software activation is selected (WDACT bit in Option byte) and the Watchdog is not activated, the downcounter may be used as a simple 7bit timer (remember that the bits are in reverse order). The software activation option should be chosen only when the Watchdog counter is to be used as a timer. To ensure the Watchdog has not been unexpectedly activated, the following instructions should be executed: jrr 0, WDGR, #+3 ; If C=0,jump to next ldi WDGR, 0FDH ; SR=0 -> reset next :
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WATC HDOG TIMER (Cont'd) These instructions test the C bit and reset the MCU (i.e. disable the Watchdog) if the bit is set (i.e. if the Watchdog is active), thus disabling the Wat c hdog. For more information on the use of the watchdog, please read application note AN1015.
Note: This note applies only when the watchdog is used as a standard timer. It is recommended to read the counter twice, as it may sometimes return an invalid value if the read is performed while the counter is decremented (counter bits in transient state). To validate the return value, both values read must be equal. The counter decrements every 384 s at 8 MHz fOSC.
8.1.5 Low Power Modes Mode WAIT STOP Description No effect on Watchdog.
Behaviour depends on the EXTCNTL option in the Option bytes: 1. Watchdog disabled: The MCU will enter Stop mode if a STOP instruction is executed. 2. Watchdog enabled and EXTCNTL option disabled: If a STOP instruction is encountered, it is interpreted as a WAIT. 3. Watchdog and EXTCNTL option enabled: If a STOP instruction is encountered when the NMI pin is low, it is interpreted as a WAIT. If, however, the STOP instruction is encountered when the NMI pin is high, the Watchdog counter is frozen and the CPU enters STOP mode. When the MCU exits STOP mode (i.e. when an interrupt is generated), the Watchdog resumes its activity.
8.1.6 Interrupts None.
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WATC HDOG TIMER (Cont'd) 8.1.7 Register Description WATC HDOG REGISTER (WDGR) Address: 0D8h - Read / Write Reset Value: 1111 1110 (FE h)
7 T0 T1 T2 T3 T4 T5 SR 0 C
Bits 7:2 = T[5:0] Downcounter bits Caution: These bits are reversed and shifted with respect to the physical counter: bit-7 (T0) is the LSB of the Watchdog downcounter and bit-2 (T5) is the MSB. Bit 1 = SR: Software Reset bit Software can generate a reset by clearing this bit while the C bit is set. When C = 0 (Watchdog deactivated) the SR bit is the MSB of the 7-bit timer. 0: Generate (write) 1: No software reset generated, MSB of 7-bit timer
Bit 0 = C Watchdog Control bit. If the hardware option is selected (WDACT bit in Option byte), this bit is forced high and cannot be changed by the user (the Watchdog is always active). When the software option is selected (WDACT bit in Option byte), the Watchdog function is activated by setting the C bit, and cannot then be deactivated (except by resetting the M CU). When C is kept cleared the counter can be used as a 7-bit timer. 0: Watchdog deactivated 1: Watchdog activated
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8.2 8-BIT TIMER 8.2.1 Introduction The 8-Bit Timer on-chip peripheral is a free running downcounter based on an 8-bit downcounter with a 7-bit programmable prescaler, giving a maximum count of 215. The peripheral may be configured in three different operating modes. 8.2.2 Main Features s Tim e-out downcounting mode with up to 15-bit ac c ur ac y s External counter clock source (valid also in STOP mode) s In terrupt capability on counter underflow s Output signal generation s External pulse length measurement s Eve nt counter The timer can be used in WAIT and STOP modes to wake up the MCU.
Figure 27. Timer Block Diagram
TIMER PIN 7 fINT/12 TC R TCR7 REGISTER TC R 6 T CR5 TCR4 TCR3 TCR2 TCR1 TCR0 8-BIT DOWN COUNTER 0 fCOUNTER
fEXT 7 TMZ E TI TOUT
LA TCH
0 DOUT PSI PS2 PS1 PS0 TSCR REGISTER
INTERRUPT
fPRESCALER
RELO AD
7
PSCR REGISTER
0
PSCR7 PSCR6 PSCR5 PSCR4 PSCR3 PSCR2 PSCR1 PSCR0 /128 /64 /32 /16 /8 /4 /2 /1
PROGRAMM ABLE PRESCALER
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8-BIT TIMER (Cont'd) 8.2.3 Counter/Prescaler Description Prescaler The prescaler input can be the internal frequency fINT divided by 12 or an external clock applied to the TIMER pin. The prescaler decrements on the rising edge, depending on the division factor programmed by the PS[2:0] bits in the TSCR register. The state of the 7-bit prescaler can be read in the PSCR register. When the prescaler reaches 0, it is automatically reloaded with 7Fh. Counter The free running 8-bit downcounter is fed by the output of the programmable prescaler, and is decremented on every rising edge of the fCOUNTER clock signal coming from the prescaler. It is possible to read or write the contents of the counter on the fly, by reading or writing the timer counter register (TCR). When the downcounter reaches 0, it is automatically reloaded with the value 0FFh. Counter Clock and Prescaler The counter clock frequency is given by: fCOUNTER = fPRESCALER / 2PS[2:0] where fPRESCALER can be: fINT/12 fEXT (input on TIMER pin) fINT/12 gated by TIMER pin The timer input clock feeds the 7-bit programmable prescaler. The prescaler output can be programmed by selecting one of the 8 available prescaler taps using the PS[2:0] bits in the Status/Control Register (TSCR). Thus the division factor of the prescaler can be set to 2n (where n equals 0, to 7). See Figure 27. The clock input is enabled by the PSI (Prescaler Initialize) bit in the TSCR register. When PSI is reset, the counter is frozen and the prescaler is loaded with the value 7Fh. When PSI is set, the pres-
caler and the counter run at the rate of the selected clock source. Counter and Prescaler Initialization After RESET, the counter and the prescaler are initialized to 0FFh and 7Fh respectively. The 7-bit prescaler can be initialized to 7Fh by clearing the PSI bit. Direct write access to the prescaler is also possible when PSI =1. Then, any value between 0 and 7Fh can be loaded into it. The 8-bit counter can be initialized separately by writing to the TCR register. 8.2.3.1 8-bit Counting and Interrupt Capability on Counter Underflow Whatever the division factor defined for the prescaler, the Timer Counter works as an 8-bit downcounter. The input clock frequency is user selectable using the PS[2:0] bits. When the downcounter decrements to zero, the TMZ (Timer Zero) bit in the TSCR is set. If the ETI (Enable Timer Interrupt) bit in the TSCR is also set, an interrupt request is generated. The Timer interrupt can be used to exit the MCU from WAIT or STOP mode. The TCR can be written at any time by software to define a time period ending with an underflow event, and therefore manage delay or timer functions. TMZ is set when the downcounter reaches zero; however, it may also be set by writing 00h in the TC R register or by setting bit 7 of the TSCR register. The TMZ bit must be cleared by user software when servicing the timer interrupt to avoid undesired interrupts when leaving the interrupt service routine. Note: A write to the TCR register will predominate over the 8-bit counter decrement to 00h function, i.e. if a write and a TCR register decrement to 00h occur simultaneously, the write will take precedence, and the TMZ bit is not set until the 8-bit counter underflows again.
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8-BIT TIMER (Cont'd) 8.2.4 Functional Description There are three operating modes, which are selected by the TOUT and DOUT bits (see TSCR register). These three modes correspond to the two clocks which can be connected to the 7-bit prescaler (fINT ÷ 12 or TIMER pin signal), and to the output mode. The settings for the different operating modes are summarized Table 13. Table 13. Timer Operating Modes
TOUT DOUT 0 0 1 1 0 1 0 1 Timer Function Event Counter (input) Gated input (input) Output "0" (output) Output "1" (output) Application External counter clock source External Pulse length measurement Output signal generation
the DDR, OR and DR registers. For more details, please refer to the I/O Ports section. Figure 28. fTIMER Clock in Gated Mode
fINT/12 fPRESCALER
TI ME R
fEXT
Figure 29. Gated Mode Operation
COUNTER VALUE xx1 VALUE 1
xx2
VALUE 2
TIMER PIN PULSE LENGTH 1
8.2.4.1 Gated Mode (TOUT = "0", DOUT = "1") In this mode, the prescaler is decremented by the Timer clock input, but only when the signal on the TIMER pin is held high (fINT/12 gated by TIMER pin). See Figure 28 and Figure 29. This mode is selected by clearing the TOUT bit in the TSCR register (i.e. as input) and setting the DOUT bit. Note: In this mode, if the TIMER pin is multiplexed, the corresponding port control bits have to be set in input with pull-up configuration through
TIMER CLOCK
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8-BIT TIMER (Cont'd) 8.2.4.2 Event Counter Mode (TOUT = "0", DOUT = "0") In this mode, the TIMER pin is the input clock of the Timer prescaler which is decremented on every rising edge of the input clock (allowing event count). See Figure 30 and Figure 31. This mode is selected by clearing the TOUT bit in the TSCR register (i.e. as input) and clearing the DOUT bit. Note: In this mode, if the TIMER pin is multiplexed, the corresponding port control bits have to be set in input with pull-up configuration. Figure 30. fTIMER Clock in Event Counter Mode
bit transition is used to latch the DOUT bit in the TSCR and, if the TOUT bit is set, DOUT is transferred to the TIMER pin. This operating mode allows external signal generation on the TIMER pin. See Figure 33. This mode is selected by setting the TOUT bit in the TSCR register (i.e. as output) and setting the DOU T bit to output a high level or clearing the DOU T bit to output a low level. Note: As soon as the TOUT bit is set, The timer pin is configured as output push-pull regardless of the corresponding I/O port control registers setting (if the TIMER pin is multiplexed). Figure 32. Output Mode Control
TI ME R
fPRESCALER
TI ME R
LATCH
Figure 31. Event Counter Mode Operation
COUNTER VALUE XX1 VALUE 1 TMZ TOUT DOUT
Figure 33. Output Mode Operation
Counter
XX2 TIMER PIN VALUE 2
FFh
TIMER PIN
8.2.4.3 Output Mode (TOUT = "1", DOUT = "data out") In Output mode, the TIMER pin is connected to the DOUT latch, hence the Timer prescaler is clocked by the prescaler clock input (fINT/12). See Figure 32. The user can select the prescaler division ratio using the PS[2:0] bits in the TSCR register. When TCR decrements to zero, it sets the TMZ bit in the TSCR. The TMZ bit can be tested under program control to perform a timer function whenever it goes high and has to be cleared by the user. The low-to-high TMZ
1
At each zero event DOUT has to be copied to the TIMER pin
1st downcount: Default output value is 0
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8-BIT TIMER (Cont'd) 8.2.5 Low Power Modes
Mode WAIT Description No effect on timer. Timer interrupt events cause the device to exit from WAIT mode. Timer registers are frozen except in Event Counter mode (with external clock on TIMER pin).
8.2.6 Interrupts
Interrupt Event Timer Zero Event Event Flag TMZ Enable Bit ETI Exit from Wait Yes Exit from Stop Yes
STOP
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8-BIT TIMER (Cont'd) 8.2.7 Register Description PRESCALER COUNTER REGISTER (PSCR) Address: 0D2h - Read/Write Reset Value: 0111 1111 (7Fh)
7 0
ETI=0 the timer interrupt is disabled. If ETI=1 and TMZ=1 an interrupt request is generated. 0: Interrupt disabled (reset state) 1: Interrupt enabled Bit 5 = TOUT Timer Output Control. When low, this bit selects the input mode for the TIMER pin. When high the output mode is selected. 0: Input mode (reset state) 1: Output mode, the TIMER pin is configured as push-pull output Bit 4 = DOUT Data Output. Data sent to the timer output when TMZ is set high (output mode only). Input mode selection (input mode only). Bit 3 = PSI: Prescaler Initialize bit. Used to initialize the prescaler and inhibit its counting. When PSI="0" the prescaler is set to 7Fh and the counter is inhibited. When PSI="1" the prescaler is enabled to count downwards. As long as PSE="1" both counter and prescaler are not running 0: Counting disabled 1: Counting enabled Bits 1:0 = PS[2:0] Prescaler Mux. Select. These bits select the division ratio of the prescaler register. Table 14. Prescaler Division Factors
PS2 0 0 0 0 1 1 1 1 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 Divided by 1 2 4 8 16 32 64 128
PSCR PSCR PSCR PSCR PSCR PSCR PSCR PSCR 7 6 5 4 3 2 1 0
Bit 7 = PSCR7: Not used, always read as "0". Bits 6:0 = PSCR[6:0] Prescaler LSB. TIMER COUNTER REGISTER (TCR) Address: 0D3h - Read / Write Reset Value: 1111 1111 (FFh)
7 T CR7 TCR6 TCR5 TCR4 TCR3 TCR2 T CR1 0 TCR0
Bits 7:0 = TCR[7:0] Timer counter bits. TIMER STATUS CONTROL REGISTER (TSCR) Address: 0D4h - Read/Write Reset Value: 0000 0000 (00h)
7 TM Z E TI TOUT DOUT PSI PS2 PS1 0 PS0
Bit 7 = TMZ Timer Zero bit. A low-to-high transition indicates that the timer count register has underflowed. It means that the TCR value has changed from 00h to FFh. This bit must be cleared by user software. 0: Counter has not underflowed 1: Counter underflow occurred Bit 6 = ETI Enable Timer Interrupt. When set, enables the timer interrupt request. If
Table 15. 8-Bit Timer Register Map and Reset Values
Address (Hex.) 0D2h 0D3h 0D4h Register Label PSCR Reset Value TCR Reset Value TSCR Reset Value 7 PSCR7 0 TCR7 1 TMZ 0 6 PSCR6 1 TCR6 1 ETI 0 5 PSCR5 1 TCR5 1 TOUT 0 4 PSCR4 1 TCR4 1 DOUT 0 3 PSCR3 1 TCR3 1 PSI 0 2 PSCR2 1 TCR2 1 PS2 0 1 PSCR1 1 TCR1 1 PS1 0 0 PSCR0 1 TCR0 1 PS0 0
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8.3 A/D CONVERTER (ADC) 8.3.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 8-bit, successive approximation converter. This peripheral has multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from different sources. The result of the conversion is stored in a 8-bit Data Register. The A/D converter is controlled through a Control Register. 8.3.2 Main Features s 8-bit conversion s Mu lti plexed analog input channels s Linea r successive approximation s Data register (DR) which contains the results s End of Conversion flag s On/Off bit (to reduce consumption) s Typical conversion time 70 s (with an 8 MHz crystal) The block diagram is shown in Figure 34.
Figure 34. ADC Block Diagram
fINT
DIV 12
fADC
AD OSC AD AD EAI EOC STA PDS CR3 OFF CR1 CR0
ADCR
AIN0 AIN1 PORT MUX AINx
I/O PORT
ANALOG TO DIGITAL CONVERTER
DDRx ORx DRx
ADR ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
Note: ADC not present on some devices. See device summary on page 1.
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A/D CONVERTER (Cont'd) 8.3.3 Functional Description 8.3.3.1 Analog Power Supply The high and low level reference voltage pins are internally connected to the VDD and VSS pins. Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. 8.3.3.2 Digital A/D Conversion Result The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (VAIN) is greater than or equal to VDDA (high-level voltage reference) then the conversion result in the DR register is FFh (full scale) without overflow indication. If input voltage (VAIN) is lower than or equal to VSSA (low-level voltage reference) then the conversion result in the DR register is 00h. The A/D converter is linear and the digital result of the conversion is stored in the ADR register. The accuracy of the conversion is described in the parametric section. RAIN is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage |
