M48Z02 M48Z12
5V, 16Kbit (2Kb x 8) ZEROPOWER SRAM
Features
Integrated, ultra low power SRAM and powerfail control circuit Unlimited WRITE cycles READ cycle time equals WRITE cycle time Automatic power-fail chip deselect and WRITE protection WRITE protect voltages (VPFD = Power-fail deselect voltage): M48Z02: VCC = 4.75 to 5.5V; 4.5V VPFD 4.75V M48Z12: VCC = 4.5 to 5.5V; 4.2V VPFD 4.5V Self-contained battery in the CAPHATTM DIP package Pin and function compatible with JEDEC standard 2K x 8 SRAMs RoHS compliant Lead-free second level interconnect
24 1
PCDIP24 (PC) battery CAPHATTM
November 2007
Rev 5
1/20
www.st.com 1
Contents
M48Z02, M48Z12
Contents
1 2 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 2.3 2.4 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 4 5 6 7
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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M48Z02, M48Z12
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Read mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PCDIP24 24-pin plastic DIP, battery CAPHATTM, package mechanical data . . . . . . . . . 17 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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List of figures
M48Z02, M48Z12
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Read mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write enable controlled, write AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip enable controlled, write AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Checking the BOK flag status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PCDIP24 24-pin plastic DIP, battery CAPHATTM, package outline . . . . . . . . . . . . . . . . . 17
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M48Z02, M48Z12
Summary
1
Summary
The M48Z02/12 ZEROPOWER RAM is a 2K x 8 non-volatile static RAM which is pin and functional compatible with the DS1220. A special 24-pin, 600mil DIP CAPHATTM package houses the M48Z02/12 silicon with a long life lithium button cell to form a highly integrated battery backed-up memory solution. The M48Z02/12 button cell has sufficient capacity and storage life to maintain data functionality for an accumulated time period of at least 10 years in the absence of power over commercial operating temperature range. The M48Z02/12 is a non-volatile pin and function equivalent to any JEDEC standard 2K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. Figure 1. Logic diagram
VCC
11 A0-A10
8 DQ0-DQ7
W E G
M48Z02 M48Z12
VSS
AI01186
Table 1.
A0-A10 DQ0-DQ7 E G W VCC VSS
Signal names
Address inputs Data inputs / outputs Chip enable Output enable WRITE enable Supply voltage Ground
5/20
Summary Figure 2. DIP connections
A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 M48Z02 6 M48Z12 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A8 A9 W G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
M48Z02, M48Z12
AI01187
Figure 3.
Block diagram
A0-A10
LITHIUM CELL VOLTAGE SENSE AND SWITCHING CIRCUITRY
POWER
2K x 8 SRAM ARRAY
DQ0-DQ7
VPFD
E W G
VCC
VSS
AI01255
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M48Z02, M48Z12
Operation modes
2
Operation modes
The M48Z02/12 also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below approximately 3V, the control circuitry connects the battery which maintains data operation until valid power returns. Table 2.
Mode Deselect WRITE READ READ Deselect Deselect VSO to VPFD VSO (min)(1)
(1)
Operating modes
VCC E VIH 4.75 to 5.5V or 4.5 to 5.5V VIL VIL VIL X X G X X VIL VIH X X W X VIL VIH VIH X X DQ0DQ7 High Z DIN DOUT High Z High Z High Z Power Standby Active Active Active CMOS standby Battery back-up mode
1. See Table 10 on page 16 for details.
Note:
X = VIH or VIL; VSO = Battery back-up switchover voltage.
2.1
Read mode
The M48Z02/12 is in the READ Mode whenever W (WRITE Enable) is high and E (Chip Enable) is low. The device architecture allows ripple-through access of data from eight of 16,384 locations in the static storage array. Thus, the unique address specified by the 11 Address Inputs defines which one of the 2,048 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the Chip Enable Access time (tELQV) or Output Enable Access time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access.
7/20
Operation modes Figure 4. Read mode AC waveforms
tAVAV A0-A10 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 VALID tGHQZ VALID
M48Z02, M48Z12
tAXQX tEHQZ
AI01330
Note: Table 3.
WRITE Enable (W) = High. Read mode AC characteristics
M48Z02/M48Z12
Symbol
Parameter(1)
70 Min Max
150 Min 150 70 70 35 150 150 75 10 5 25 25 35 35 5 5 Max
200 Min 200 200 200 80 10 5 40 40 Max
Unit
tAVAV tAVQV tELQV tGLQV tELQX tGLQX tEHQZ tGHQZ tAXQX
READ cycle time Address valid to output valid Chip enable low to output valid Output enable low to output valid Chip enable low to output transition Output enable low to output transition Chip enable high to output Hi-Z Output enable high to output Hi-Z Address transition to output transition
70
ns ns ns ns ns ns ns ns ns
5 5
10
1. Valid for ambient operating temperature: TA = 0 to 70C or 40 to 85C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
2.2
Write mode
The M48Z02/12 is in the WRITE Mode whenever W and E are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls.
8/20
M48Z02, M48Z12 Figure 5. Write enable controlled, write AC waveform
tAVAV A0-A10 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
Operation modes
tWHAX
tWHQX
AI01331
Figure 6.
Chip enable controlled, write AC waveforms
tAVAV A0-A10 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI01332B
tELEH
tEHAX
9/20
Operation modes Table 4. Write mode AC characteristics
M48Z02/M48Z12 Symbol Parameter(1)(1) Min tAVAV tAVWL tAVEL tWLWH t ELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ tAVWH tAVEH tWHQX WRITE cycle time Address valid to WRITE enable low Address valid to chip enable 1 low WRITE enable pulse width Chip enable low to chip enable 1 high WRITE enable high to address transition Chip enable high to address transition Input valid to WRITE enable high Input valid to Chip enable high WRITE enable high to input transition Chip enable high to input transition WRITE enable low to output Hi-Z Address valid to WRITE enable high Address valid to chip enable high WRITE enable high to output transition 60 60 5 70 0 0 50 55 0 0 30 30 5 5 25 120 120 10 70 Max 150 Min 150 0 0 90 90 10 10 40 40 5 5 50 Max
M48Z02, M48Z12
200 Min 200 0 0 120 120 10 10 60 60 5 5 60 140 140 10 Max
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1. Valid for ambient operating temperature: TA = 0 to 70C or 40 to 85C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
2.3
Data retention mode
With valid VCC applied, the M48Z02/12 operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs become high impedance, and all inputs are treated as "don't care."
Note:
A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48Z02/12 may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. The power switching circuit connects external VCC to the RAM and disconnects the battery when VCC rises above VSO. As VCC rises, the battery voltage is checked. If the voltage is too low, an internal Battery Not OK (BOK) flag will be set. The BOK flag can be checked after power up. If the BOK flag is set, the first WRITE attempted will be blocked. The flag is automatically cleared after the first WRITE, and normal RAM operation resumes. Figure 7 on page 11 illustrates how a BOK check routine could be structured. For more information on a Battery Storage Life refer to the Application Note AN1012.
10/20
M48Z02, M48Z12 Figure 7. Checking the BOK flag status
POWER-UP
Operation modes
READ DATA AT ANY ADDRESS
WRITE DATA COMPLEMENT BACK TO SAME ADDRESS
READ DATA AT SAME ADDRESS AGAIN
IS DATA COMPLEMENT OF FIRST READ? (BATTERY OK) YES
NO (BATTERY LOW)
NOTIFY SYSTEM OF LOW BATTERY (DATA MAY BE CORRUPTED)
WRITE ORIGINAL DATA BACK TO SAME ADDRESS
CONTINUE
AI00607
2.4
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (as shown in Figure 8 on page 12) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, STMicroelectronics recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount.
11/20
Operation modes Figure 8. Supply voltage protection
M48Z02, M48Z12
VCC VCC
0.1F
DEVICE
VSS
AI02169
12/20
M48Z02, M48Z12
Maximum rating
3
Maximum rating
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 5.
Symbol TA TSTG TSLD(1) VIO VCC IO PD
Absolute maximum ratings
Parameter Ambient operating temperature Storage temperature (VCC off, oscillator off) Lead solder temperature for 10 seconds Input or output voltages Supply voltage Output current Power dissipation Grade 1 Value 0 to 70 40 to 85 260 0.3 to 7 0.3 to 7 20 1 Unit C C C V V mA W
1. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds).
Caution:
Negative undershoots below 0.3V are not allowed on any pin while in the battery back-up mode.
13/20
DC and AC parameters
M48Z02, M48Z12
4
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in Table 6: Operating and AC measurement conditions. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 6. Operating and AC measurement conditions
Parameter Supply voltage (VCC) Ambient operating temperature (TA) Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages Grade 1 M48Z02 4.75 to 5.5 0 to 70 100 5 0 to 3 1.5 M48Z12 4.5 to 5.5 0 to 70 100 5 0 to 3 1.5 Unit V C pF ns V V
Note:
Output Hi-Z is defined as the point where data is no longer driven. Figure 9. AC testing load circuit
5V
1.8k DEVICE UNDER TEST 1k
OUT
CL = 100pF
CL includes JIG capacitance
AI01019
Table 7.
Symbol CIN CIO
(3)
Capacitance
Parameter(1)(2) Input capacitance Input / output capacitance Min Max 10 10 Unit pF pF
1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs deselected.
14/20
M48Z02, M48Z12 Table 8.
Symbol ILI ILO
(2)
DC and AC parameters
DC characteristics
Parameter Input leakage current Output leakage current Supply current Supply current (standby) TTL Supply current (standby) CMOS Input low voltage Input high voltage Output low voltage Output high voltage IOL = 2.1mA IOH = 1mA 2.4 Test condition(1) 0V VIN VCC 0V VOUT VCC Outputs open E = VIH E = VCC 0.2V 0.3 2.2 Min Max 1 1 80 3 3 0.8 VCC + 0.3 0.4 Unit A A mA mA mA V V V V
ICC ICC1 ICC2 VIL VIH VOL VOH
1. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. Outputs deselected.
Figure 10. Power down/up mode AC waveforms
VCC VPFD (max) VPFD (min) VSO tF tPD INPUTS
RECOGNIZED
tDR tFB tRB DON'T CARE
tR tREC
NOTE RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI00606
Note:
Inputs may or may not be recognized at this time. Caution should be taken to keep E high as VCC rises past VPFD (min). Some systems may perform inadvertent WRITE cycles after VCC rises above VPFD (min) but before normal system operations begin. Even though a power on reset is being applied to the processor, a reset condition may not occur until after the system is running.
15/20
DC and AC parameters Table 9.
Symbol tPD tF(2) tFB(3) tR tRB tREC
M48Z02, M48Z12 Power down/up AC characteristics
Parameter(1) E or W at VIH before power down VPFD (max) to VPFD (min) VCC fall time VPFD (min) to VSS VCC fall time VPFD (min) to VPFD (max) VCC rise time VSS to VPFD (min) VCC rise time E or W at VIH after power up Min 0 300 10 0 1 2 Max Unit s s s s s ms
1. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 10.
Symbol VPFD VSO tDR(3)
Power down/up trip points DC characteristics
Parameter(1)(2) Power-fail deselect voltage M48Z02 M48Z12 Min 4.5 4.2 Typ 4.6 4.3 3.0 10 Max 4.75 4.5 Unit V V V YEARS
Batter y back-up switchover voltage Expected data retention time
1. All voltages referenced to VSS. 2. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 3. At 25C, VCC = 0V.
16/20
M48Z02, M48Z12
Package mechanical data
5
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 11. PCDIP24 24-pin plastic DIP, battery CAPHATTM, package outline
A2 A
A1 B1 B e3 D
N
L eA
C
e1
E
1 PCDIP
Note:
Drawing is not to scale. Table 11. PCDIP24 24-pin plastic DIP, battery CAPHATTM, package mechanical data
mm Symb Typ A A1 A2 B B1 C D E e1 e3 eA L N Min 8.89 0.38 8.38 0.38 1.14 0.20 34.29 17.83 2.29 25.15 15.24 3.05 24 Max 9.65 0.76 8.89 0.53 1.78 0.31 34.80 18.34 2.79 30.73 16.00 3.81 Typ Min 0.350 0.015 0.330 0.015 0.045 0.008 1.350 0.702 0.090 0.990 0.600 0.120 24 Max 0.380 0.030 0.350 0.021 0.070 0.012 1.370 0.722 0.110 1.210 0.630 0.150 inches
17/20
Part numbering
M48Z02, M48Z12
6
Part numbering
Table 12.
Example:
Ordering information scheme
M48Z 02 70 PC 1
Device type M48Z
Supply voltage and write protect voltage 02 = VCC = 4.75 to 5.5V; VPFD = 4.5 to 4.75V 12 = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V
Speed 70 = 70ns (M48Z02/12) 150 = 150ns (M48Z02/12) 200 = 200ns (M48Z02/12)
Package PC = PCDIP24
Temperature range 1 = 0 to 70C
Shipping method blank = ECOPACK package, tubes
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST sales office nearest you.
18/20
M48Z02, M48Z12
Revision history
7
Revision history
Table 13.
Date May-1999 09-Jul-2001 17-Dec-2001 20-May-2002 01-Apr-2003 22-Apr-2003 12-Dec-2005
Document revision history
Revision 1.0 2.0 2.1 2.2 3.0 3.1 4.0 First issue Reformatted; temperature information added to tables (Table 5, 6, 7, 8, 3, 4, 9, 10); Figure updated (Figure 10) Remove references to "clock" in document Updated VCC noise and negative going transients text v2.2 template applied; test condition updated (Table 10) Fix error in ordering information (Table 12) Update template, Lead-free text, and remove references to `crystal' and footnote (Table 8, 12) Reformatted document; added lead-free second level interconnect information to cover page and Section 5: Package mechanical data; updated Table 5, 6, 8, 9, 10, 12. Changes
02-Nov-2007
5
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M48Z02, M48Z12
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