Obsolete Product Datasheets | Microcontrollers | 8-bit Microcontrollers | ST6 - 8-bit Microcontrollers

8-bit OTP/EPROM MCUs with A/D converter, 16-bit auto-reload timer, EEPROM, SPI and UART

Obsolete Product Datasheet

Format: (1858 kb)

Last Updated: 26/08/2008

Pages: 84

Untitled Document

Generic Part Number

Orderable Part Number

Status

ST6230B	ST6230BB6	Obsolete
	ST62T30BM6	Obsolete
	ST62T30BB6	Obsolete
	ST62T30BB3	Obsolete

Related Information

Option list

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(Unformatted textual content of the document used by search engines)

ST62T30B ST62E30B
8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, 16-BIT AUTO-RELOAD TIMER, EEPROM, SPI AND UART
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3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +125C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table capability in Program Memory Data Storage in Program Memory: User selectable size Data RAM: 192 bytes Data EEPROM: 128 bytes User Programmable Options 20 I/O pins, fully programmable as: Input with pull-up resistor Input without pull-up resistor Input with interrupt generation Open-drain or push-pull output Analog Input 4 I/O lines can sink up to 20mA to drive LEDs or TRIACs directly 8-bit Timer/Counter with 7-bit programmable prescaler 16-bit Auto-reload Timer with 7-bit programmable prescaler (AR Timer) Digital Watchdog 8-bit A/D Converter with 16 analog inputs 8-bit Synchronous Peripheral Interface (SPI) 8-bit Asynchronous Peripheral Interface (UA RT ) On-chip Clock oscillator can be driven by Quartz Crystal or Ceramic resonator Oscillator Safe Guard One external Non-Maskable Interrupt ST623x-EMU2 Emulation and Development System (connects to an MS-DOS PC via a parallel port).

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C D IP 2 8 W
(See end of Datasheet for Ordering Information)

DEVICE SUMMARY
DEVICE ST62T30B ST62E30B OTP
(Bytes)

7948

EPROM (Bytes) 7948

EEPROM (Bytes) 128 128

I/O Pins 20 20

Rev. 2.7
October 2003 1/84

Table of Contents

Document Page

ST62T30B / ST62E30B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3.4 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3.5 Data Window Register (DWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3.6 Da ta RAM/EEPROM Bank Register (DRBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.3.7 EEPROM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.4.1 Option Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.3 EEPROM Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.4 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 18 3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 Low Frequency Auxiliary Oscillator (LFAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.3 Oscillator Safe Guard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 W atchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.5 MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.1 Digital Watchdog Register (DWDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.3.2 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

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3.4.1 Interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 Interrupt Option Register (IOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 POW ER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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18 19 19 22 22 22 23 23 23 25

15 15 15 15 16 16

29 30 31 32 35 35 35 36 37 37

3.5.1 W AIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.3 Exit from WAIT and STOP Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 . . .. 4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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4.1.2 Safe I/O State Switching Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.3 ARTimer alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.4 SPI alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.5 UART alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.6 I/O Port Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.7 I/O Port Data Direction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.8 I/O Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.4 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 ARTIMER 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 CENTRAL COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 SIGNAL GENERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 TIMINGS MEASUREMENT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4 INTERRUPT CAPABILITIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.5 CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.6 16-BIT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

39 41 41 41 43 43 43 44 45 45 46 46 47 47 49 51 53 54 56 58

4.4.1 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.5 U. A. R. T. (UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER) . . . . . . . . . . . 60 4.5.1 PORTS INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.2 CLOCK GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.3 DATA TRANSMISSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.4 DATA RECEPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.5 INTERRUPT CAPABILITIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.6 REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.5 A/D CONVERTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.6 TIMER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.7 SPI CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.8 ARTIMER16 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.2 .ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

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7.3 IMPORTANT NOTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

ST6230B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 1.2 ROM READOUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 1.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 1.3.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 1.3.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 2 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

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ST62T30B ST62E30B

1 GENERAL DESCRIPTION
1.1 INTRODUCTION The ST62T30B and ST62E30B devices are low cost members of the ST62xx 8-bit HCMOS family of microcontrollers, which is targeted at low to medium complexity applications. All ST62xx devices are based on a building block approach: a common core is surrounded by a number of on-chip peripherals. The ST62E30B is the erasable EPROM version of the ST62T30B device, which may be used to emulate the ST62T30B device, as well as the respective ST6230B ROM devices.

Figure 1. Block Diagram
PA0..PA1 / 20 mA Sink PA2/OVF / 20 mA Sink PA3/PWM/20 mA Sink PA4/Ain/CP1 PA5/Ain/CP2

TEST/V PP

8-BIT A/D CONVERTER TEST

PORT A

PORT B NMI INT ERRUPT DAT A ROM U SER SELECTABLE PROGRAM Memory 7948 bytes DATA RAM 192 Bytes PORT D PORT C

PB4..PB6/Ain

PC4..PC7/Ain

DATA EEPROM 128 Bytes

PC STACK LEVEL 1 STACK LEVEL 2 STACK LEVEL 3 STACK LEVEL 4 STACK LEVEL 5 STACK LEVEL 6 POWER SUPPLY

O

(VPP on EPROM/OTP versions only)

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AUTORELOAD TI ME R TIMER SPI (SERIAL PERIPHERAL INTERFACE) DIGITAL WATCHDOG T IMER

OSCILLAT OR

RESET

VDD VSS

OSCin OSCout

RESET VR01823F

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ST62 T30B ST62E30B

INTRODUCTION (Cont'd) OTP and EPROM devices are functionally identical. The ROM based versions offer the same functionality selecting as ROM options the options defined in the programmable option byte of the OTP/EPROM versions.OTP devices offer all the advantages of user programmability at low cost, which make them the ideal choice in a wide range of applications where frequent code changes, multiple code versions or last minute programmability are required. Figure 2. ST62T30B/E30B Pin Configuration These compact low-cost devices feature a Timer
VDD TIMER OSCin OSCout NMI Ain/PC7 Ain/PC6 Ain/PC5 Ain/PC4 TEST/VPP(1) RESET Ain/PB6 Ain/PB5 Ain/PB4
(1) V
PP

1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

VSS PA0 PA1 PA2/OVF PA3/PWM PA4/Ain/CP1 PA5/Ain/CP2 PD1/Ain/Scl PD2/Ain/Sin PD3/Ain/Sout PD4/Ain/RXD1 PD5/Ain/TXD1 PD6/Ain PD7/Ain

on EPROM/OTP only

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VR01804B

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1.2 PIN DESCRIPTIONS VDD and VSS. Power is supplied to the MCU via these two pins. VDD is the power connection and VSS is the ground connection. OSCin and OSCout. These pins are internally connected to the on-chip oscillator circuit. A quartz crystal, a ceramic resonator or an external clock signal can be connected between these two pins. The OSCin pin is the input pin, the OSCout pin is the output pin. RESET. The active-low RESET pin is used to restart the microcontroller. TEST/VPP. The TEST must be held at VSS for normal operation. If TEST pin is connected to a +12.5V level during the reset phase, the EPROM/OTP programming Mode is entered. NMI. The NMI pin provides the capability for asynchronous interruption, by applying an external non maskable interrupt to the MCU. The NMI input is falling edge sensitive with Schmitt trigger characteristics. The user can select as option the availability of an on-chip pull-up at this pin. PA0-PA5. These 6 lines are organised as one I/O port (A). Each line may be configured under software control as inputs with or without internal pullup resistors, interrupt generating inputs with pullup resistors, open-drain or push-pull outputs. PA2/OVF, PA3/PWM, PA4/CP1 and PA5/CP2 can be used respectively as overflow output pin, output compare pin, and as two input capture pins for the embedded 16-bit Auto-Reload Timer. In addition, PA4-PA5 can also be used as analog inputs for the A/D converter while PA0-PA3 can sink 20mA for direct LED or TRIAC drive. PB4-PB6. These 3 lines are organised as one I/O port (B). Each line may be configured under software control as inputs with or without internal pullup resistors, interrupt generating inputs with pullup resistors, open-drain or push-pull outputs, analog inputs for the A/D converter. PC4-PC7. These 4 lines are organised as one I/O port (C). Each line may be configured under software control as input with or without internal pullup resistor, interrupt generating input with pull-up resistor, analog input for the A/D converter, opendrain or push-pull output. PD1-PD7. These 7 lines are organised as one I/O port (portD). Each line may be configured under software control as input with or without internal pull-up resistor, interrupt generating input with pull-up resistor, analog input open-drain or pushpull output. In addition, the pins PD5/TXD1 and PD4/RXD1 can be used as UART output (PD5/TXD1) or UART input (PD4/RXD1). The pins PD3/Sout, PD2/Sin and PD1/SCL can also be used respectively as data out, data in and Clock pins for the on-chip SPI. TIMER. This is the TIMER 1 I/O pin. In input mode, it is connected to the prescaler and acts as external timer clock or as control gate for the internal timer clock. In output mode, the TIMER pin outputs the data bit when a time-out occurs.The user can select as option the availability of an on-chip pullup at this pin.

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1.3 MEMORY MAP 1.3.1 Introduction The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in these three memory spaces is described in the following paragraphs. Briefly, Program space contains user program code in Program memory and user vectors; Data space contains user data in RAM and in Program memory, and Stack space accommodates six levels of stack for subroutine and interrupt service routine nesting. 1.3.2 Program Space Program Space comprises the instructions to be executed, the data required for immediate addressing mode instructions, the reserved factory test area and the user vectors. Program Space is addressed via the 12-bit Program Counter register (PC register). Program Space is organised in four 2K pages. Three of them are addressed in the 000h-7FFh locations of the Program Space by the Program Counter and by writing the appropriate code in the Program ROM Page Register (PRPR register). A Figure 4. Memory Addressing Diagram
PROGRAM SPACE

common (STATIC) 2K page is available all the time for interrupt vectors and common subroutines, independently of the PRPR register content. This "STATIC" page is directly addressed in the 0800h-0FFFh by the MSB of the Program Counter register PC 11. Note this page can also be addressed in the 000-7FFh range. It is two different ways of addressing the same physical memory. Jump from a dynamic page to another dynamic page is achieved by jumping back to the static page, changing contents of PRPR and then jumping to the new dynamic page. Figure 3. 8Kbytes Program Space Addressing
ROM SPACE PC SPACE 000h Page 0 7FFh 800h FFFh Page 1 Static Page 0000h Page 1 Static Page Page 2 1FFFh

0000h

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DATA SPACE

000h RAM / EEPROM BANKING AREA 03Fh 040h DATA READ-ONLY MEMORY WINDOW 07Fh 080h 081h 082h 083h 084h 0C0h X REGISTER Y REGISTER V REGISTER W REGISTER RAM DATA READ-ONLY MEMORY WINDOW SELECT DATA RAM BANK SELECT ACCUMULATOR
VR01568

0-63

0FF0h INTERRUPT & RESET VECTORS 0FFFh 0FFh

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MEMORY MAP (Cont'd) Table 1. ST62E30B/T30B Program Memory Map
ROM Page Page 0 Device Address 0000h-007Fh 0080h-07FFh 0800h-0F9Fh 0FA0h-0FEFh 0FF0h-0FF7h 0FF8h-0FFBh 0FFCh-0FFDh 0FFEh-0FFFh 0000h-000Fh 0010h-07FFh 0000h-000Fh 0010h-07FFh Description Reserved User ROM User ROM Reserved Interrupt Vectors Reserved NMI Vector Reset Vector Reserved User ROM Reserved User ROM

Program ROM Page Register (PRPR) Address: CAh
7 -

--

Write Only
0 PRPR0 PRPR1

Page 1 "STATIC"

Bits 2-7= Not used. Bit 5-0 = PRPR1-PRPR0: Program ROM Select. These two bits select the corresponding page to be addressed in the lower part of the 4K program address space as specified in Table 2. This register is undefined on Reset. Neither read nor single bit instructions may be used to address this register. Table 2. 8Kbytes Program ROM Page Register Coding
PRPR1 PRPR0 X 0 PC bit 11 1 0 0 0 0 X 0 0 1 1

Page 2 Page 3

Note: OTP/EPROM devices can be programmed with the development tools available from STMicroelectronics (ST62E3X-EPB or ST623X-KIT). 1.3.2.1 Program ROM Page Register (PRPR) The PRPR register can be addressed like a RAM location in the Data Space at the address CAh; nevertheless it is a write only register that cannot be accessed with single-bit operations. This register is used to select the 2-Kbyte ROM bank of the Program Space that will be addressed. The number of the page has to be loaded in the PRPR register. Refer to the Program Space description for additional information concerning the use of this register. The PRPR register is not modified when an interrupt or a subroutine occurs.

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Care is required when handling the PRPR register as it is write only. For this reason, it is not allowed to change the PRPR contents while executing interrupt service routine, as the service routine cannot save and then restore its previous content. This operation may be necessary if common routines and interrupt service routines take more than 2K bytes; in this case it could be necessary to divide the interrupt service routine into a (minor) part in the static page (start and end) and to a second (major) part in one of the dynamic pages. If it is impossible to avoid the writing of this register in interrupt service routines, an image of this register must be saved in a RAM location, and each time the program writes to the PRPR it must write also to the image register. The image register must be written before PRPR, so if an interrupt occurs between the two instructions the PRPR is not affected.

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1.3.2.2 Program Memory Protection The Program Memory in OTP or EPROM devices can be protected against external readout of memory by selecting the READOUT PROTECTION option in the option byte. In the EPROM parts, READOUT PROTECTION option can be disactivated only by U.V. erasure that also results into the whole EPROM context eras ure. Note: Once the Readout Protection is activated, it is no longer possible, even for STMicroelectronics, to gain access to the Program memory contents. Returned parts with a protection set can therefore not be accepted.

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Memory Page

Static Page (Page 1) Page 1 (Static Page

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MEMORY MAP (Cont'd) 1.3.3 Data Space Data Space accommodates all the data necessary for processing the user program. This space comprises the RAM resource, the processor core and peripheral registers, as well as read-only data such as constants and look-up tables in Program memory. 1.3.3.1 Data ROM All read-only data is physically stored in program memory, which also accommodates the Program Space. The program memory consequently contains the program code to be executed, as well as the constants and look-up tables required by the application. The Data Space locations in which the different constants and look-up tables are addressed by the processor core may be thought of as a 64-byte window through which it is possible to access the read-only data stored in Program memory. 1.3.3.2 Data RAM/EEPROM In ST6230B and ST62E30B devices, the data space includes 60 bytes of RAM, the accumulator (A), the indirect registers (X), (Y), the short direct registers (V), (W), the I/O port registers, the peripheral data and control registers, the interrupt option register and the Data ROM Window register (DRW register). Additional RAM and EEPROM pages can also be addressed using banks of 64 bytes located between addresses 00h and 3Fh. 1.3.4 Stack Space

Table 4. ST62T30B/E30B Data Memory Space
DATA and EEPROM DATA ROM WINDOW AREA X REGISTER Y REGISTER V REGISTER W REGISTER DATA RAM PORT A DATA REGISTER PORT B DATA REGISTER PORT C DATA REGISTER PORT D DATA REGISTER PORT A DIRECTION REGISTER PORT B DIRECTION REGISTER PORT C DIRECTION REGISTER PORT D DIRECTION REGISTER INT ERRUPT OPTION REGISTER DATA ROM WINDOW REGISTER ROM BANK SELECT REGISTER RAM/EEPROM BANK SELECT REGISTER PORT A OPTION REGISTER PORT B OPTION REGISTER PORT C OPTION REGISTER PORT D OPTION REGISTER A/D DATA REGISTER A/D CONTROL REGISTER TIM ER 1 PRESCALER REGISTER TIMER 1 COUNTER REGISTER TIMER 1 STATUS/CONTROL REGISTER RESERVED UART DATA SHIFT REGISTER UART STATUS CONTROL REGISTER WATCHDOG REGISTER RESERVED I/O INTERRUPT POLARITY REGISTER OSCILLATOR CONTROL REGISTER SPI INTERRUPT DISABLE REGISTER SPI DATA REGISTER RESERVED EEPROM CONTROL REGISTER ARTIM16 COMPARE MASK REG. LOW BYTE MASK ARTIM16 2ND STATUS CONTROL REGISTER SCR2 ARTIM16 3RD STATUS CONTROL REGISTER SCR3 ARTIM16 4TH STATUS CONTROL REGISTER SCR4 ARTIM16 1ST STATUS CONTROL REGISTER SCR1 ARTIM16 RELOAD CAPTURE REG. HIGH BYTE RLCP ARTIM16 RELOAD CAPTURE REG. LOW BYTE RLCP ARTIM16 CAPTURE REGISTER HIGH BYTE CP ARTIM16 CAPTURE REGISTER LOW BYTE CP ARTIM16 COMPARE VALUE REGISTER HIGH BYTE CMP ARTIM 16 COMPARE VALUE REGISTER LOWBYTE CMP ARTIM 16 COMPARE MASK REG. HIGH BYTE MASK RESERVED 000h 03Fh 040h 07Fh 080h 081h 082h 083h 084h 0BFh 0C0h 0C1h 0C2h 0C3h 0C4h 0C5h 0C6h 0C7h 0C8h* 0C9h* 0CAh* 0CBh* 0CCh 0CDh 0CEh 0CFh 0D0h 0D1h 0D2h 0D3h 0D4h 0D5h 0D6h 0D7h 0D8h 0D9h 0DAh 0DBh 0DCh* 0DDh 0DEh 0DFh 0E0h 0E1h 0E2h 0E3h 0E8h 0E9h 0EAh 0EBh 0ECh 0EDh 0EEh 0EFh 0F0h 0FBh OFCh 0F Dh 0FEh O FFh

Stack space consists of six 12-bit registers which are used to stack subroutine and interrupt return addresses, as well as the current program counter contents. Table 3. Additional RAM/EEPROM Banks.
Device ST62T30B/E30B

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RAM

2 x 64 bytes

2 x 64 bytes

RESERVED ACCUMULATOR * WRITE ONLY REGISTER

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MEMORY MAP (Cont'd) 1.3.5 Data Window Register (DWR) The Data read-only memory window is located from address 0040h to address 007Fh in Data space. It allow s direct reading of 64 consecutive bytes located anywhere in program memory, between address 0000h and 1FFFh (top memory address depends on the specific device). All the program memory can therefore be used to store either instructions or read-only data. Indeed, the window can be moved in steps of 64 bytes along the program memory by writing the appropriate code in the Data Window Register (DWR). The DWR can be addressed like any RAM location in the Data Space, it is however a write-only register and therefore cannot be accessed using singlebit operations. This register is used to position the 64-byte read-only data window (from address 40h to address 7Fh of the Data space) in program memory in 64-byte steps. The effective address of the byte to be read as data in program memory is obtained by concatenating the 6 least significant bits of the register address given in the instruction (as least significant bits) and the content of the DWR register (as most significant bits), as illustrated in Figure 5 below. For instance, when addressing location 0040h of the Data Space, with 0 loaded in the DWR register, the physical location addressed in program memory is 00h. The DWR register is not cleared on reset, therefore it must be written to prior to the first access to the Data readonly memory window area.

Data Window Register (DWR) Address: 0C9h
7 -

--

W rite Only
0

DWR6 DWR5 DWR4 DWR3 DWR2 DWR1 DWR0

Bits 7 = Not used. Bit 6-0 = DWR5-DWR0: Data read-only memory Window Register Bits. These are the Data readonly memory Window bits that correspond to the upper bits of the data read-only memory space. Caution: This register is undefined on reset. Neither read nor single bit instructions may be used to address this register. Note: Care is required when handling the DWR register as it is write only. For this reason, the DWR contents should not be changed while executing an interrupt service routine, as the service routine cannot save and then restore the register's previous contents. If it is impossible to avoid writing to the DWR during the interrupt service routine, an image of the register must be saved in a RAM location, and each time the program writes to the DWR, it must also write to the image register. The image register must be written first so that, if an interrupt occurs between the two instructions, the DWR is not affected.

Figure 5. Data read-only memory Window Memory Addressing
D ATA ROM 13 12 6 11 5 10 4

WINDO W REGISTER 7 C ONTEN TS ( DW R)

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0 PR OGR AM SPACE ADDRESS RE AD 0 D ATA SPACE ADDRESS 40h-7Fh IN INSTRUCTION

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0 1 0 1 1 0 0 1 D ATA SPACE ADDRESS 59h

RO M AD DRESS:A 19h

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VR 0A157 3

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MEMORY MAP (Cont'd) 1.3.6 Data RAM/EEPROM Bank (DRBR) Address: CBh -- W rite only
7 DRBR4 DRBR3 -

Register

0 DRBR1 DRBR0

Bit 7-5 = These bits are not used Bit 4 - DRBR4. This bit, when set, selects RAM Page 2. Bit 3 - DRBR3. This bit, when set, selects RAM Page 1. Bit2. This bit is not used. Bit 1 - DRBR1. This bit, when set, selects EEPROM Page 1. Bit 0 - DRBR0. This bit, when set, selects EEPROM Page 0. The selection of the bank is made by programming the Data RAM Bank Switch register (DRBR register) located at address CBh of the Data Space according to Table 1. No more than one bank should be set at a time. The DRBR register can be addressed like a RAM Data Space at the address CBh; nevertheless it is a write only register that cannot be accessed with single-bit operations. This register is used to select the desired 64-byte RAM/EEPROM bank of the Data Space. The number of banks has to be loaded in the DRBR register and the instruction has to point to the selected location as if it was in bank 0 (from 00h address to 3Fh address).

This register is not cleared during the MCU initialization, therefore it must be written before the first access to the Data Space bank region. Refer to the Data Space description for additional information. The DRBR register is not modified when an interrupt or a subroutine occurs. Notes: Care is required when handling the DRBR register as it is write only. For this reason, it is not allowed to change the DRBR contents while executing interrupt service routine, as the service routine cannot save and then restore its previous content. If it is impossible to avoid the writing of this register in interrupt service routine, an image of this register must be saved in a RAM location, and each time the program writes to DRBR it must write also to the image register. The image register must be written first, so if an interrupt occurs between the two instructions the DRBR is not affected. In DRBR Register, only 1 bit must be set. Otherwise two or more pages are enabled in parallel, producing errors. Table 5. Data RAM Bank Register Set-up
DRBR 00 01 02 08

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ST62T30B/E30B None

EEPROM Page 0 EEPROM Page 1 RAM Page 1 RAM Page 2 Reserved

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MEMORY MAP (Cont'd) 1.3.7 EEPROM Description EEPROM memory is located in 64-byte pages in data space. This memory may be used by the user program for non-volatile data storage. Data space from 00h to 3Fh is paged as described in Table 6. EEPROM locations are accessed directly by addressing these paged sections of data space. The EEPROM does not require dedicated instructions for read or write access. Once selected via the Data RAM Bank Register, the active EEPROM page is controlled by the EEPROM Control Register (EECTL), which is described below. Bit E20FF of the EECTL register must be reset prior to any write or read access to the EEPROM. If no bank has been selected, or if E2OFF is set, any access is meaningless. Programming must be enabled by setting the E2ENA bit of the EECTL register. The E2BUSY bit of the EECTL register is set when the EEPROM is performing a programming cycle. Any access to the EEPROM when E2BUSY is set is meaningless. Provided E2OFF and E2BUSY are reset, an EEPROM location is read just like any other data location, also in terms of access time.

(PMODE). In BMODE, one byte is accessed at a time, while in PMODE up to 8 bytes in the same row are programmed simultaneously (with consequent speed and power consumption advantages, the latter being particularly important in battery powered circuits). General Notes: Data should be written directly to the intended address in EEPROM space. There is no buffer memory between data RAM and the EEPROM space. When the EEPROM is busy (E2BUSY = "1") EECTL cannot be accessed in write mode, it is only possible to read the status of E2BUSY. This implies that as long as the EEPROM is busy, it is not possible to change the status of the EEPROM Control Register. EECTL bits 4 and 5 are reserved and must never be set. Care is required when dealing with the EECTL register, as some bits are write only. For this reason, the EECTL contents must not be altered while executing an interrupt service routine. If it is impossible to avoid writing to this register within an interrupt service routine, an image of the register must be saved in a RAM location, and each time the program writes to EECTL it must also write to the image register. The image register must be written to first so that, if an interrupt occurs between the two instructions, the EECTL will not be affected.

Writing to the EEPROM may be carried out in two modes: Byte Mode (BMODE) and Parallel Mode

Table 6. Row Arrangement for Parallel Writing of EEPROM Locations

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Byte ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 ROW1 ROW0

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Dataspace addresses. Banks 0 and 1. 5 6 7 38h-3Fh 30h-37h 28h-2Fh 20h-27h 18h-1Fh 10h-17h 08h-0Fh 00h-07h

3

Up to 8 bytes in each row may be programmed simultaneously in Parallel Write mode. The number of available 64-byte banks (1 or 2) is device dependent.

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MEMORY MAP (Cont'd) Additional Notes on Parallel Mode: If the user wishes to perform parallel programming, the first step should be to set the E2PAR2 bit. From this time on, the EEPROM will be addressed in write mode, the ROW address will be latched and it will be possible to change it only at the end of the programming cycle, or by resetting E2PAR2 without programming the EEPROM. After the ROW address is latched, the MCU can only "see" the selected EEPROM row and any attempt to write or read other rows will produce errors. The EEPROM should not be read while E2PAR2 is set. As soon as the E2PAR2 bit is set, the 8 volatile ROW latches are cleared. From this moment on, the user can load data in all or in part of the ROW. Setting E2PAR1 will modify the EEPROM registers corresponding to the ROW latches accessed after E2PAR2. For example, if the software sets E2PAR2 and accesses the EEPROM by writing to addresses 18h, 1Ah and 1Bh, and then sets E2PAR1, these three registers will be modified simultaneously; the remaining bytes in the row will be unaffected. Note that E2PAR2 is internally reset at the end of the programming cycle. This implies that the user must set the E2PAR2 bit between two parallel programming cycles. Note that if the user tries to set E2PAR1 while E2PAR2 is not set, there will be no programming cycle and the E2PAR1 bit will be unaffected. Consequently, the E2PAR1 bit cannot be set if E2ENA is low. The E2PAR1 bit can be set by the user, only if the E2ENA and E2PAR2 bits are also set. EEPROM Control Register (EECTL) Address: DFh -- Read/Write Reset status: 00h
7 D7 E2OFF D5 D4 0 E2PAR1 E2PAR2 E2BUSY E2ENA

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Bit 7 = D7: Unused. Bit 6 = E2OFF: Stand-by Enable Bit. WRITE ONLY. If this bit is set the EEPROM is disabled (any access will be meaningless) and the power consumption of the EEPROM is reduced to its lowest value. Bit 5-4 = D5-D4: Reserved. MUST be kept reset. Bit 3 = E2PAR1: Parallel Start Bit. WRITE ONLY. Once in Parallel Mode, as soon as the user software sets the E2PAR1 bit, parallel writing of the 8 adjacent registers will start. This bit is internally reset at the end of the programming procedure. Note that less than 8 bytes can be written if required, the undefined bytes being unaffected by the parallel programming cycle; this is explained in greater detail in the Additional Notes on Parallel Mode overleaf. Bit 2 = E2PAR2: Parallel Mode En. Bit. WRITE ONLY. This bit must be set by the user program in order to perform parallel programming. If E2PAR2 is set and the parallel start bit (E2PAR1) is reset, up to 8 adjacent bytes can be written simultaneously. These 8 adjacent bytes are considered as a row, whose address lines A7, A6, A5, A4, A3 are fixed while A2, A1 and A0 are the changing bits, as illustrated in Table 6. E2PAR2 is automatically reset at the end of any parallel programming procedure. It can be reset by the user software before starting the programming procedure, thus leaving the EEPROM registers unchanged. Bit 1 = E2BUSY: EEPROM Busy Bit. READ ONLY. This bit is automatically set by the EEPROM control logic when the EEPROM is in programming mode. The user program should test it before any EEPROM read or write operation; any attempt to access the EEPROM while the busy bit is set will be aborted and the writing procedure in progress will be completed. Bit 0 = E2ENA: EEPROM Enable Bit. WRITE ONLY. This bit enables programming of the EEPROM cells. It must be set before any write to the EEPROM register. Any attempt to write to the EEPROM when E2ENA is low is meaningless and will not trigger a write cycle.

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1.4 PROGRAMMING MODES 1.4.1 Option Byte The Option Byte allows configuration capability to the MCUs. Option byte's content is automatically read, and the selected options enabled, when the chip reset is activated. It can only be accessed during the programming mode. This access is made either automatically (copy from a master device) or by selecting the OPTION BYTE PROGRAMMING mode of the programmer. The option byte is located in a non-user map. No address has to be specified. EPROM Code Option Byte
7 0 NMI TIM PORT WDACT OSGEN EXTCNTL PROTECT PULL PULL PULL

Bit 0 = OSGEN. This bit must be set high to enable the oscillator Safe Guard. When this bit is low, the OSG is disabled. The Option byte is written during programming either by using the PC menu (PC driven Mode) or automatically (stand-alone mode) 1.4.2 Program Memory EPROM/OTP programming mode is set by a +12.5V voltage applied to the TEST/VPP pin. The programming flow of the ST62T30B/E30B is described in the User Manual of the EPROM Programming Board. The MCUs can be programmed with the ST62E3xB EPROM programming tools available from STMicroelectronics. 1.4.3 EEPROM Data Memory EEPROM data pages are supplied in the virgin state FFh. Partial or total programming of EEPROM data memory can be performed either through the application software, or through an external programmer. Any STMicroelectronics tool used for the program memory (OTP/EPROM) can also be used to program the EEPROM data memory . 1.4.4 EPROM Erasing The EPROM of the windowed package of the MCUs may be erased by exposure to Ultra Violet light. The erasure characteristic of the MCUs is such that erasure begins when the memory is exposed to light with a wave lengths shorter than approximately 4000Å. It should be noted that sunlights and some types of fluorescent lamps have wavelengths in the range 3000-4000Å. It is thus recommended that the window of the MCUs packages be covered by an opaque label to prevent unintentional erasure problems when testing the application in such an environment. The recommended erasure procedure of the MCUs EPROM is the exposure to short wave ultraviolet light which have a wave-length 2537A. The integrated dose (i.e. U.V. intensity x exposure time) for erasure should be a minimum of 15Wsec/cm2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with 12000W/cm2 power rating. The ST62E30B should be placed within 2.5cm (1Inch) of the lamp tubes during erasure.

Bit 7. Reserved. Bit 6 = PORT PULL. This bit must be set high to have pull-up input state at reset on the I/O port. When this bit is low, I/O ports are in input without pull-up (high impedance) state at reset Bit 5 = EXTCNTL. This bit selects the External STOP Mode capability. When EXTCNTL is high, pin NMI controls if the STOP mode can be accessed when the watchdog is active. When EXTCNTL is low, the STOP instruction is processed as a WAIT as soon as the watchdog is active. Bit 4 = PROTECT. This bit allows the protection of the software contents against piracy. When the bit PROTECT is set high, readout of the OTP contents is prevented by hardware. No programming equipment is able to gain access to the user program. When this bit is low, the user program can be read.

Bit 3= NMI PULL. This bit must be set high to configure the NMI pin with a pull up resistor when it is low, no pull up is provided.

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Bit 2= TIM PULL. This bit must be set high to configure the TIMER pin with a pull up resistor. When it is low, no pull up is provided. Bit 1 = WDACT. This bit controls the watchdog activation. When it is high, hardware activation is selected. The software activation is selected when WDACT is low.

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2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought of as an independent central processor communicating with on-chip I/O, Memory and Peripherals via internal address, data, and control buses. In-core communication is arranged as shown in Figure 6; the controller being externally linked to both the Reset and Oscillator circuits, while the core is linked to the dedicated on-chip peripherals via the serial data bus and indirectly, for interrupt purposes, through the control registers. 2.2 CPU REGISTERS The ST6 Family CPU core features six registers and three pairs of flags available to the programmer. These are described in the following paragraphs. Accumulator (A). The accumulator is an 8-bit general purpose register used in all arithmetic calculations, logical operations, and data manipulations. The accumulator can be addressed in Data space as a RAM location at address FFh. Thus the ST6 can manipulate the accumulator just like any other register in Data space. Figure 6. ST6 Core Block Diagram
RESET OSCin

0,01 TO 8MHz

CONTROLLER

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ROM/EPROM

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Indirect Registers (X, Y). These two indirect registers are used as pointers to memory locations in Data space. They are used in the register-indirect addressing mode. These registers can be addressed in the data space as RAM locations at addresses 80h (X) and 81h (Y). They can also be accessed with the direct, short direct, or bit direct addressing modes. Accordingly, the ST6 instruction set can use the indirect registers as any other register of the data space. Short Direct Registers (V, W). These two registers are used to save a byte in short direct addressing mode. They can be addressed in Data space as RAM locations at addresses 82h (V) and 83h (W). They can also be accessed using the direct and bit direct addressing modes. Thus, the ST6 instruction set can use the short direct registers as any other register of the data space. Program Counter (PC). The program counter is a 12-bit register which contains the address of the next ROM location to be processed by the core. This ROM location may be an opcode, an operand, or the address of an operand. The 12-bit length allows the direct addressing of 4096 bytes in Program space.

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INTERRUPTS DATA SPACE

OPCODE

FLAG VALUES

CONTROL SIGNALS ADDRESS/READ LINE

D A TA RAM/EEPROM

ADDRESS 256 DECODER A-DATA B-DATA

DATA ROM/EPROM

DEDICAT IONS ACCUMULATOR

12

Program Counter and 6 LAYER STACK

FLAGS ALU RESULTS TO DATA SPACE (WRITE LINE) VR01811

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ST62T30B ST62E30B

bs O

CPU REGISTERS (Cont'd) However, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the Program Bank Switch register. The PC value is incremented after reading the address of the current instruction. To execute relative jumps, the PC and the offset are shifted through the ALU, where they are added; the result is then shifted back into the PC. The program counter can be changed in the following ways: - JP (Jump) instructionPC=Jump address - CALL instructionPC= Call address - Relative Branch Instruction.PC= PC +/- offset - Interrupt PC=Interrupt vector - Reset PC= Reset vector - RET & RETI instructionsPC= Pop (stack) - Normal instructionPC= PC + 1 Flags (C, Z). The ST6 CPU includes three pairs of flags (Carry and Zero), each pair being associated with one of the three normal modes of operation: Normal mode, Interrupt mode and Non Maskable Interrupt mode. Each pair consists of a CARRY flag and a ZERO flag. One pair (CN, ZN) is used during Normal operation, another pair is used during Interrupt mode (CI, ZI), and a third pair is used in the Non Maskable Interrupt mode (CNMI, ZNMI). The ST6 CPU uses the pair of flags associated with the current mode: as soon as an interrupt (or a Non Maskable Interrupt) is generated, the ST6 CPU uses the Interrupt flags (resp. the NMI flags) instead of the Normal flags. When the RETI instruction is executed, the previously used set of flags is restored. It should be noted that each flag set can only be addressed in its own context (Non Maskable Interrupt, Normal Interrupt or Main routine). The flags are not cleared during context sw itching and thus retain their status. The Carry flag is set when a carry or a borrow occurs during arithmetic operations; otherwise it is cleared. The Carry flag is also set to the value of the bit tested in a bit test instruction; it also participates in the rotate left instruction. The Zero flag is set if the result of the last arithmetic or logical operation was equal to zero; otherwise it is cleared. Switching between the three sets of flags is performed automatically when an NMI, an interrupt or a RETI instructions occurs. As the NMI mode is

automatically selected after the reset of the MCU, the ST6 core uses at first the NMI flags. Stack. The ST6 CPU includes a true LIFO hardware stack which eliminates the need for a stack pointer. The stack consists of six separate 12-bit RAM locations that do not belong to the data space RAM area. When a subroutine call (or interrupt request) occurs, the contents of each level are shifted into the next higher level, while the content of the PC is shifted into the first level (the original contents of the sixth stack level are lost). When a subroutine or interrupt return occurs (RET or RETI instructions), the first level register is shifted back into the PC and the value of each level is popped back into the previous level. Since the accumulator, in common with all other data space registers, is not stored in this stack, management of these registers should be performed within the subroutine. The stack will remain in its "deepest" position if more than 6 nested calls or interrupts are executed, and consequently the last return address will be lost. It will also remain in its highest position if the stack is empty and a RET or RETI is executed. In this case the next instruction will be executed. F l igure 7. ST6 CPU Programming Mode
INDEX REGISTER

let o

ro P e

du

ct

(s)

Ob -

so

te le
b7 b7 b7 b7 b7

ro P

uc d
b0 b0

s) t(

X R E G . P O IN T E R

Y R E G . P O IN T E R V REGISTER W REGISTER A C C U M U L A TO R

SHORT DIRECT ADDRESSING MODE b0 b0 b0 b0

b 11

PROGRAM COUNTER

SIX LEVELS STACK REGISTER

NORMAL FLAGS INTERRUPT FLAGS NMI FLAGS

C C C

Z Z Z VA000423

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ST62 T30B ST62E30B

3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES
3.1 CLOCK SYSTEM The MCU features a Main Oscillator which can be driven by an external clock, or used in conjunction with an AT-cut parallel resonant crystal or a suitable ceramic resonator. In addition, a Low Frequency Auxiliary Oscillator (LFAO) can be switched in for security reasons, to reduce power consumption, or to offer the benefits of a back-up clock system. The Oscillator Safeguard (OSG) option filters spikes from the oscillator lines, provides access to the LFAO to provide a backup oscillator in the event of main oscillator failure and also automatically limits the internal clock frequency (f INT) as a function of VDD, in order to guarantee correct operation. These functions are illustrated in Figure 9, Figure 10, Figure 11 and Figure 12. Figure 8 illustrates various possible oscillator configurations using an external crystal or ceramic resonator, an external clock input or the lowest cost solution using only the LFAO. C L1 an CL2 should have a capacitance in the range 12 to 22 pF for an oscillator frequency in the 4-8 MHz range. The internal MCU clock frequency (fINT) is divided by 12 to drive the Timer and the Watchdog timer, and by 13 to drive the CPU core, while the A/D converter is driven by fINT divided either by 6 or by 12 as may be seen in Figure 11. With an 8 MH z oscillator frequency, the fastest machine cycle is therefore 1.625s. A machine cycle is the smallest unit of time needed to execute any operation (for instance, to increment the Program Counter). An instruction may require two, four, or five machine cycles for execution. 3.1.1 Main Oscillator The main oscillator can be turned off (when the OSG ENABLED option is selected) by setting the OSCOFF bit of the OSCR Control Register. The Low Frequency Auxiliary Oscillator is automatically started. Figure 8. Oscillator Configurations

CRYSTAL/RESONATOR CLOCK

ST6xxx

OSCin

OSCout

C L1n

C L2

EXTERNAL CLOCK

bs O

let o

Pr e

od

ct u

(s)

so Ob -

te le

ro P
ST6xxx

uc d

s) t(

VA0016

OSCin

OSCout NC VA0015A

INTEGRATED CLOCK OSG ENABLED option

ST6xxx

OSCin

OSCout NC

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ST62T30B ST62E30B

CLOCK SYSTEM (Cont'd) Turning on the main oscillator is achieved by resetting the OSCOFF bit of the OSCR Register or by resetting the MCU. Restarting the main oscillator implies a delay comprising the oscillator start up delay period plus the duration of the software instruction at f LFAO clock frequency. 3.1.2 Low Frequency Auxiliary Oscillator (LFAO) The Low Frequency Auxiliary Oscillator has three main purposes. Firstly, it can be used to reduce power consumption in non timing critical routines. Secondly, it offers a fully integrated system clock, without any external components. Lastly, it acts as a safety oscillator in case of main oscillator failure. This oscillator is available when the OSG ENABLED option is selected. In this case, it automatically starts one of its periods after the first missing edge from the main oscillator, whatever the reason (main oscillator defective, no clock circuitry provided, main oscillator switched off...). User code, normal interrupts, WAIT and STOP instructions, are processed as normal, at the reduced fLFAO frequency. The A/D converter accuracy is decreased, since the internal frequency is below 1MHz. At power on, the Low Frequency Auxiliary Oscillator starts faster than the Main Oscillator. It therefore feeds the on-chip counter generating the POR delay until the Main Oscillator runs. The Low Frequency Auxiliary Oscillator is automatically switched off as soon as the main oscillator starts. OS C R Address: 0DBh -- Read/Write
7 -

bs O

Bit 7-1= These bits are not used and must be kept cleared after reset. Bit 0 = OSCOFF. Main oscillator turn-off. When low, this bit enables main oscillator to run. The main oscillator is switched off when OSCOFF is high.

let o

Pr e
-

du o
-

(s) ct
-

so Ob -

0 OSC OFF

3.1.3 Oscillator Safe Guard The Oscillator Safe Guard (OSG) affords drastically increased operational integrity in ST62xx devices. The OSG circuit provides three basic functions: it filters spikes from the oscillator lines which would result in over frequency to the ST62 CPU; it gives access to the Low Frequency Auxiliary Oscillator (LFAO), used to ensure minimum processing in case of main oscillator failure, to offer reduced power consumption or to provide a fixed frequency low cost oscillator; finally, it automatically limits the internal clock frequency as a function of supply voltage, in order to ensure correct operation even if the power supply should drop. The OSG is enabled or disabled by choosing the relevant OSG option. It may be viewed as a filter whose cross-over frequency is device dependent. Spikes on the oscillator lines result in an effectively increased internal clock frequency. In the absence of an OSG circuit, this may lead to an over frequency for a given power supply voltage. The OSG filters out such spikes (as illustrated in Figure 9). In all cases, when the OSG is active, the maximum internal clock frequency, fINT, is limited to fOSG, which is supply voltage dependent. This relationship is illustrated in Figure 12. When the OSG is enabled, the Low Frequency Auxiliary Oscillator may be accessed. This oscillator starts operating after the first missing edge of the main oscillator (see Figure 10). Over-frequency, at a given power supply level, is seen by the OSG as spikes; it therefore filters out some cycles in order that the internal clock frequency of the device is kept within the range the particular device can stand (depending on VDD), and below fOSG: the maximum authorised frequency with OSG enabled. Note. The OSG should be used wherever possible as it provides maximum safety. Care must be taken, however, as it can increase power consumption and reduce the maximum operating frequency to fOSG.

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ST62 T30B ST62E30B

CLOCK SYSTEM (Cont'd) Figure 9. OSG Filtering Principle

(1)

(2)

(3)

(4)

(1) Maximum Frequency for the device to work correctly (2) Actual Quartz Crystal Frequency at OSCin pin (3) Noise from OSCin (4) Resulting Internal Frequency

Figure 10. OSG Emergency Oscillator Principle

Main Oscillator

bs O

Emergency Oscillator

let o
Internal

Pr e

du o

(s) ct

so Ob -

te le

ro P

uc d

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VR001932

Frequency

VR001933

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ST62T30B ST62E30B

CLOCK SYSTEM (Cont'd) Figure 11. Clock Circuit Block Diagram
POR

: 13 OSG

Core TIMER 1

MAIN OSCILLATOR

M U X

fINT

: 12

Watchdog M U X ADC

:6 LFAO :1

ARTIMER 16

Main Oscillator off

Figure 12. Maximum Operating Frequency (fMAX) versus Supply Voltage (V DD)
Maximum FREQUENCY (MHz) 8 7 FUNCTIONALITY IS NOT GUARANTEED IN THIS AREA 6 5 4 3 2 1 4

O

Notes: 1. In this area, operation is guaranteed at the quartz crystal frequency. 2. When the OSG is disabled, operation in this area is guaranteed at the crystal frequency. When the OSG is enabled, operation in this area is guaranteed at a frequency of at least fOSG Min. 3. When the OSG is disabled, operation in this area is guaranteed at the quartz crystal frequency. When the OSG is enabled, access to this area is prevented. The internal frequency is kept a fOSG. 4. When the OSG is disabled, operation in this area is not guaranteed When the OSG is enabled, access to this area is prevented. The internal frequency is kept at fOSG.

bs

let o

Pr e
2.5

du o
3

(s) ct
3.5

so Ob 3 2 1 4 4.5

te le
fOSG

ro P

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s) t(

fOSG Min

5

5.5

6

SUPPLY VOLTAGE (VDD ) VR01807

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3.2 RESETS The MCU can be reset in three ways: by the external Reset input being pulled low; by Power-on Reset; by the digital Watchdog peripheral timing out. 3.2.1 RESET Input The RESET pin may be connected to a device of the application board in order to reset the MCU if required. The RESET pin may be pulled low in RUN, WAIT or STOP mode. This input can be used to reset the MCU internal state and ensure a correct start-up procedure. The pin is active low and features a Schmitt trigger input. The internal Reset signal is generated by adding a delay to the external signal. Therefore even short pulses on the RESET pin are acceptable, provided VDD has completed its rising phase and that the oscillator is running correctly (normal RUN or WAIT modes). The MCU is kept in the Reset state as long as the RESET pin is held low. If RESET activation occurs in the RUN or WAIT modes, processing of the user program is stopped (RUN mode only), the Inputs and Outputs are configured as inputs with pull-up resistors and the main Oscillator is restarted. When the level on the RESET pin then goes high, the initialization sequence is executed following expiry of the internal delay period. If RESET pin activation occurs in the STOP mode, the oscillator starts up and all Inputs and Outputs are configured as inputs with pull-up resistors. When the level of the RESET pin then goes high, the initialization sequence is executed following expiry of the internal delay period. 3.2.2 Power-on Reset The function of the POR circuit consists in waking up the MCU at an appropriate stage during the power-on sequence. At the beginning of this sequence, the MCU is configured in the Reset state: all I/O ports are configured as inputs with pull-up resistors and no instruction is executed. When the power supply voltage rises to a sufficient level, the oscillator starts to operate, whereupon an internal delay is initiated, in order to allow the oscillator to fully stabilize before executing the first instruction. The initialization sequence is executed immediately following the internal delay. The internal delay is generated by an on-chip counter. The internal reset line is released 2048 internal clock cycles after release of the external reset. Notes: To ensure correct start-up, the user should take care that the reset signal is not released before the VDD level is sufficient to allow MCU operation at the chosen frequency (see Recommended Operating Conditions). A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin. Figure 13. Reset and Interrupt Processing
RESET

NMI MASK SET INT LATCH CLEARED ( IF PRESENT )

bs O

let o

Pr e

du o

(s) ct

so Ob -

te le

SELECT NMI MODE FLAGS

ro P

uc d

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PUT FFEH ON ADDRESS BUS

YES

IS RESET STILL PRESENT?

NO LO AD PC FROM RESET LOCATIONS FFE/FFF

FETCH INSTRUCTION VA000427

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ST62T30B ST62E30B

RESETS (Cont'd) 3.2.3 Watchdog Reset The MCU provides a Watchdog timer function in order to ensure graceful recovery from software upsets. If the Watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will be activated. This, amongst other things, resets the watchdog counter. The MCU restarts just as though the Reset had been generated by the RESET pin, including the built-in stabilisation delay period. 3.2.4 Application Notes No external resistor is required between VDD and the Reset pin, thanks to the built-in pull-up device. The POR circuit operates dynamically, in that it triggers MCU initialization on detecting the rising edge of VDD. The typical threshold is in the region of 2 volts, but the actual value of the detected threshold depends on the way in which VDD rises. The POR circuit is NOT designed to supervise static, or slowly rising or falling VDD. 3.2.5 MCU Initialization Sequence When a reset occurs the stack is reset, the PC is loaded with the address of the Reset Vector (located in program ROM starting at address 0FFEh). A jump to the beginning of the user program must be coded at this address. Following a Reset, the Interrupt flag is automatically set, so that the CPU is in Non Maskable Interrupt mode; this prevents the Figure 15. Reset Block Diagram

initialisation routine from being interrupted. The initialisation routine should therefore be terminated by a RETI instruction, in order to revert to normal mode and enable interrupts. If no pending interrupt is present at the end of the initialisation routine, the MCU will continue by processing the instruction immediately following the RETI instruction. If, however, a pending interrupt is present, it will be serviced. Figure 14. Reset and Interrupt Processing
RESET

JP RESET VECTOR

JP: 2 BYTES/4 CYCLES

INITIALIZATION ROUTINE

O

bs

RESET

let o

Pr e

VDD

du o

(s) ct
fOSC

so Ob -

te le

RETI

ro P

uc d

s) t(
VA00181

RETI: 1 BYTE/2 CYCLES

CK

S T6 INTERNAL RESET COUNTER

300k

RESET 2.8k POWER ON RESET

RESET

WATCHDOG RESET

VA0200B

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ST62 T30B ST62E30B

RESETS (Cont'd) Table 7. Register Reset Status
Register Oscillator Control Register EEPROM Control Register Port Data Registers Port Direction Register Port Option Register Interrupt Option Register TIMER Status/Control AR AR AR AR TIMER Status/Control 1 Register TIMER Status/Control 2 Register TIMER Status/Control 3 Register TIMER Status/Control 4 Register Address(es) 0DBh 0DFh 0C0h to 0C2h 0C4h to 0C6h 0CCh to 0CEh 0C8h 0D4h 0E8h 0E1h 0E2h OE3h 0DCh to 0DDh 080H TO 083H 0FFh 084h to 0BFh 0CBh 0C9h 00h to 03Fh 0D0h 0DBh 0D9h OE0h-OEFh OEDh-OEEh 0D3h 0D2h 0D8h 0D1h Status Comment Main oscillator on EEPROM enabled I/O are Input with or without pull-up depending on PORT PULL option Interrupt disabled TIMER disabled

00h

AR TIMER stopped

SPI Registers X, Y, V, W, Register Accumulator Data RAM Data RAM Page REgister Data ROM Window Register EEPROM A/D Result Register AR TIMER Capture Register AR TIMER Reload/Capture Register ARTIMER Mask Registers ARTIMER Compare Registers TIMER Counter Register TIMER Prescaler Register Watchdog Counter Register A/D Control Register UART Control UART Data Register

SPI disabled

Undefined

bs O

let o

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du

ct

(s)

so Ob FFh 7Fh FEh 40h

te le

As written if programmed

ro P

uc d

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Max count loaded A/D in Stand-by UART disabled

OD7h OD6h

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ST62T30B ST62E30B

3.3 DIGITAL WATCHDOG The digital Watchdog consists of a reloadable downcounter timer which can be used to provide controlled recovery from software upsets. The Watchdog circuit generates a Reset when the downcounter reaches zero. User software can prevent this reset by reloading the counter, and should therefore be written so that the counter is regularly reloaded while the user program runs correctly. In the event of a software mishap (usually caused by externally generated interference), the user program will no longer behave in its usual fashion and the timer register will thus not be reloaded periodically. Consequently the timer will decrement down to 00h and reset the MCU. In order to maximise the effectiveness of the Watchdog function, user software must be written with this concept in mind. Watchdog behaviour is governed by two options, known as "WATCHDOG ACTIVATION" (i.e. HAR DWARE or SOFTWARE) and "EXTERNAL STOP MODE CONTROL" (see Table 8). In the SOFTWARE option, the Watchdog is disabled until bit C of the DWDR register has been set. When the Watchdog is disabled, low power Stop mode is available. Once activated, the Watchdog cannot be disabled, except by resetting the MCU. In the HARDWARE option, the Watchdog is permanently enabled. Since the oscillator will run continuously, low power mode is not available. The STOP instruction is interpreted as a WAIT instruction, and the Watchdog continues to countdown. However, when the EXTERNAL STOP MODE CON TROL option has been selected low power consumption may be achieved in Stop Mode. Execution of the STOP instruction is then governed by a secondary function associated with the NMI pin. If a STOP instruction is encountered when the NMI pin is low, it is interpreted as WAIT, as described above. If, however, the STOP instruction is encountered when the NMI pin is high, the Watchdog counter is frozen and the CPU enters STOP mode. When the MCU exits STOP mode (i.e. when an interrupt is generated), the Watchdog resumes its activity.

Table 8. Recommended Option Choices
Functions Required Stop Mode & Watchdog Stop Mode Watchdog

bs O

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Pr e

du o

(s) ct

so Ob -

Recommended Options "EXTERNAL STOP MODE" & "HARDWARE WATCHDOG" "SOFTWARE WATCHDOG" "HARDWARE WATCHDOG"

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ST62 T30B ST62E30B

DIGITAL WATCHDOG (Cont'd) The Watchdog is associated with a Data space register (Digital WatchDog Register, DWDR, location 0D8h) which is described in greater detail in Section 3.3.1 Digital Watchdog Register (DWDR). This register is set to 0FEh on Reset: bit C is cleared to "0", which disables the Watchdog; the timer downcounter bits, T0 to T5, and the SR bit are all set to "1", thus selecting the longest Watchdog timer period. This time period can be set to the user's requirements by setting the appropriate value for bits T0 to T5 in the DWDR register. The SR bit must be set to "1", since it is this bit which generates the Reset signal when it changes to "0"; clearing this bit would generate an immediate Reset. It should be noted that the order of the bits in the DWDR register is inverted with respect to the associated bits in the down counter: bit 7 of the DWDR register corresponds, in fact, to T0 and bit 2 to T5. The user should bear in mind the fact that these bits are inverted and shifted with respect to the physical counter bits when writing to this register. The relationship between the DWDR register bits and the physical implementation of the Watchdog timer downcounter is illustrated in Figure 16. Only the 6 most significant bits may be used to define the time period, since it is bit 6 which triggers the Reset when it changes to "0". This offers the user a choice of 64 timed periods ranging from 3,072 to 196,608 clock cycles (with an oscillator frequency of 8MHz, this is equivalent to timer periods ranging from 384 s to 24.576ms).

Figure 16. Watchdog Counter Control

D0 D1 WATCHDOG COUNTER D2 D3 D4 D5 D6

C SR RESET T5 T4 T3

WATCHDOG CONTROL REGISTER

bs O

let o

Pr e

du o

(s) ct

so Ob -

te le
D7

ro P

uc d
T2 T1 T0

s) t(

÷ 28

OSC ÷12
VR02068A

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ST62T30B ST62E30B

DIGITAL WATCHDOG (Cont'd) 3.3.1 Digital Watchdog Register (DWDR) Address: 0D8h -- Read/Write Reset status: 1111 1110 b
7 T0 T1 T2 T3 T4 T5 SR 0 C

Bit 0 = C: Watchdog Control bit If the hardware option is selected, this bit is forced high and the user cannot change it (the Watchdog is always active). When the software option is selected, the Watchdog function is activated by setting bit C to 1, and cannot then be disabled (save by resetting the MCU). When C is kept low the counter can be used as a 7-bit timer. This bit is cleared to "0" on Reset. Bit 1 = SR: Software Reset bit This bit triggers a Reset when cleared. When C = "0" (Watchdog disabled) it is the MSB of the 7-bit timer. This bit is set to "1" on Reset. Bits 2-7 = T5-T0: Downcounter bits It should be noted that the register bits are reversed and shifted with respect to the physical counter: bit-7 (T0) is the LSB of the Watchdog downcounter and bit-2 (T5) is the MSB. These bits are set to "1" on Reset.

bs O

let o

Pr e

du o

(s) ct

so Ob -

3.3.2 Application Notes The Watchdog plays an important supporting role in the high noise immunity of ST62xx devices, and should be used wherever possible. Watchdog related options should be selected on the basis of a trade-off between application security and STOP mode availability. When STOP mode is not required, hardware activation without EXTERNAL STOP MODE CONTR OL should be preferred, as it provides maximum security, especially during power-on. When STOP mode is required, hardware activation and EXTERNAL STOP MODE CONTROL should be chosen. NMI should be high by default, to allow STOP mode to be entered when the MCU is idle. The NMI pin can be connected to an I/O line (see Figure 17) to allow its state to be controlled by software. The I/O line can then be used to keep NMI low while Watchdog protection is required, or to avoid noise or key bounce. When no more processing is required, the I/O line is released and the device placed in STOP mode for lowest power consumption. When software activation is selected and the Watchdog is not activated, the downcounter may be used as a simple 7-bit timer (remember that the bits are in reverse order). The software activation option should be chosen only when the Watchdog counter is to be used as a timer. To ensure the Watchdog has not been unexpectedly activated, the following instructions should be executed within the first 27 instructions: jrr 0, WD, #+3 ldi WD, 0FDH

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ST62 T30B ST62E30B

DIGITAL WATCHDOG (Cont'd) These instructions test the C bit and Reset the MCU (i.e. disable the Watchdog) if the bit is set (i.e. if the Watchdog is active), thus disabling the Wat c hdog. In all modes, a minimum of 28 instructions are executed after activation, before the Watchdog can generate a Reset. Consequently, user software should load the watchdog counter within the first 27 instructions following Watchdog activation (software mode), or within the first 27 instructions executed following a Reset (hardware activation). It should be noted that when the GEN bit is low (interrupts disabled), the NMI interrupt is active but cannot cause a wake up from STOP/WAIT modes.

Figure 17. A typical circuit making use of the EXERNA L STOP MODE CONTROL feature

SWITCH NMI

I/O

Figure 18. Digital Watchdog Block Diagram

RE SE T

Q RS F F R S

bs O

let o

ro P e

DB 0

du

(s) ct
8

-2

7

DB1.7 L OAD SET

so Ob -

te le

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VR02002

-2 8 SE T

- 12

O SC ILLA TOR C LO CK

WRITE RE SE T DA TA BUS
VA00010

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ST62T30B ST62E30B

3.4 INTERRUPTS The CPU can manage four Maskable Interrupt sources, in addition to a Non Maskable Interrupt source (top priority interrupt). Each source is associated with a specific Interrupt Vector which contains a Jump instruction to the associated interrupt service routine. These vectors are located in Program space (see Table 9). When an interrupt source generates an interrupt request, and interrupt processing is enabled, the PC register is loaded with the address of the interrupt vector (i.e. of the Jump instruction), which then causes a Jump to the relevant interrupt service routine, thus servicing the interrupt. Interrupt sources are linked to events either on external pins, or on chip peripherals. Several events can be ORed on the same interrupt source, and relevant flags are available to determine which event triggered the interrupt. The Non Maskable Interrupt request has the highest priority and can interrupt any interrupt routine at any time; the other four interrupts cannot interrupt each other. If more than one interrupt request is pending, these are processed by the processor core according to their priority level: source #1 has the higher priority while source #4 the lower. The priority of each interrupt source is fixed. Table 9. Interrupt Vector Map
Interrupt Source Interrupt source #0 Interrupt source #1 Interrupt source #2 Interrupt source #3 Interrupt source #4 Priority 1 2 3 4 5

bs O

3.4.1 Interrupt request All interrupt sources but the Non Maskable Interrupt source can be disabled by setting accordingly the GEN bit of the Interrupt Option Register (IOR). This GEN bit also defines if an interrupt source, including the Non Maskable Interrupt source, can restart the MCU from STOP/WAIT modes. Interrupt request from the Non Maskable Interrupt source #0 is latched by a flip flop which is automat-

let o

Pr e

du o

Vector Address (FFCh-FFDh) (FF6h-FF7h) (FF4h-FF5h) (FF2h-FF3h) (FF0h-FF1h)

(s) ct

so Ob GEN ESB

ically reset by the core at the beginning of the nonmaskable interrupt service routine. Interrupt request from source #1 can be configured either as edge or level sensitive by setting accordingly the LES bit of the Interrupt Option Register (IOR). Interrupt request from source #2 are always edge sensitive. The edge polarity can be configured by setting accordingly the ESB bit of the Interrupt Option Register (IOR). Interrupt request from sources #3 & #4 are level sensitive. In edge sensitive mode, a latch is set when a edge occurs on the interrupt source line and is cleared when the associated interrupt routine is started. So, the occurrence of an interrupt can be stored, until completion of the running interrupt routine before being processed. If several interrupt requests occurs before completion of the running interrupt routine, only the first request is stored. Storage of interrupt requests is not available in level sensitive mode. To be taken into account, the low level must be present on the interrupt pin when the MCU samples the line after instruction execution. At the end of every instruction, the MCU tests the interrupt lines: if there is an interrupt request the next instruction is not executed and the appropriate interrupt service routine is executed instead.

te le

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Table 10. Interrupt Option Register Description
SET CLEARED SET CLEARED SET LES CLEARED OTHERS NOT USED Enable all interrupts Disable all interrupts Rising edge mode on interrupt source #2 Falling edge mode on interrupt source #2 Level-sensitive mode on interrupt source #1 Falling edge mode on interrupt source #1

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ST62 T30B ST62E30B

bs O

INTERRUPTS (Cont'd) 3.4.2 Interrupt Procedure The interrupt procedure is very similar to a call procedure, indeed the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event, the user cannot know the context and the time at which it occurred. As a result, the user should save all Data space registers which may be used within the interrupt routines. There are separate sets of processor flags for normal, interrupt and non-maskable interrupt modes, which are automatically switched and so do not need to be saved. The following list summarizes the interrupt procedure: MCU The interrupt is detected. The C and Z flags are replaced by the interrupt flags (or by the NMI flags). The PC contents are stored in the first level of the stack. The normal interrupt lines are inhibited (NMI still active). The first internal latch is cleared. The associated interrupt vector is loaded in the PC. WARNING: In some circumstances, when a maskable interrupt occurs while the ST6 core is in NORMAL mode and especially during the execution of an "ldi IOR, 00h" instruction (disabling all maskable interrupts): if the interrupt arrives during the first 3 cycles of the "ldi" instruction (which is a 4-cycle instruction) the core will switch to interrupt mode BUT the flags CN and ZN will NOT switch to the interrupt pair CI and ZI. User User selected registers are saved within the interrupt service routine (normally on a software stack). The source of the interrupt is found by polling the interrupt flags (if more than one source is associated with the same vector). The interrupt is serviced. Return from interrupt (RETI)

M CU Automatically the MCU switches back to the normal flag set (or the interrupt flag set) and pops the previous PC value from the stack. The interrupt routine usually begins by the identifying the device which generated the interrupt request (by polling). The user should save the registers which are used within the interrupt routine in a software stack. After the RETI instruction is executed, the MCU returns to the main routine.
Figure 19. Interrupt Processing Flow Chart
INST R U C T IO N

F E TCH INST R U C T ION

EXEC U T E INST R U C TION

WAS TH E INSTRUCTION A RETI ? YES

NO

let o

Pr e

du o

(s) ct

so Ob YE S

te le
?
NO

ro P

uc d

s) t(

L OA D PC FROM INTERRUPT VECTOR (F FC/F F D)

IS THE CORE ALREADY IN NORMAL MODE?

SET INT E R R U P T MASK

C LEAR INTERRUPT MASK

P U S H THE PC INTO THE STACK

S EL E C T PROGRAM FLAGS

S E L ECT INTERNAL MODE FLAG

" P OP " T HE STACKED PC

NO

?
Y ES

C H E C K IF THERE IS A N INTERRUPT REQUEST AND INTERRUPT MASK

V A 00 00 1 4

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INTERRUPTS (Cont'd) 3.4.3 Interrupt Option Register (IOR) The Interrupt Option Register (IOR) is used to enable/disable the individual interrupt sources and to select the operating mode of the external interrupt inputs. This register is write-only and cannot be accessed by single-bit operations. Address: 0C8h -- Write Only Reset status: 00h
7 LES ESB GEN 0 -

Bit 7, Bits 3-0 = Unused.

Bit 6 = LES: Level/Edge Selection bit. When this bit is set to one, the interrupt source #1 is level sensitive. When cleared to zero the edge sensitive mode for interrupt request is selected. Bit 5 = ESB: Edge Selection bit. The bit ESB selects the polarity of the interrupt source #2. Bit 4 = GEN: Global Enable Interrupt. When this bit is set to one, all interrupts are enabled. When this bit is cleared to zero all the interrupts (excluding NMI) are disabled. When the GEN bit is low, the NMI interrupt is active but cannot cause a wake up from STOP/WAIT m odes . This register is cleared on reset.

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IINTERRUPTS (Cont'd) 3.4.4 Interrupt sources Interrupt sources available on the ST62E30B/T30B are summarized in the Table 11 Table 11. Interrupt Requests and Mask Bits
Peripheral GENERAL TIMER A/D CONVERTER UART Register IOR TSCR1 ADCR UARTCR SCR1 SCR2 SCR3 SCR3 SCR3 SPI ORPA-DRPA ORPB-DRPB ORPC-DRPC ORPD-DRPD Address Register C8h D4h D1h D7h E8h E1h E2h E2h E2h DCh C0h-C4h C1h-C5h C2h-C6h C3h-C7h ETI EAI RXIEN TXIEN

with associated mask bit to enable/disable the interrupt request.

Mask bit GEN

Masked Interrupt Source

Interrupt source All source 4 source 4 source 4

All Interrupts, excluding NMI
TMZ: TIMER Overflow EOC: End of Conversion RXRDY: Byte received TXMT: Byte sent

ARTIMER

OVFIEN CP1IEN CP2IEN ZEROIEN CMPIEN ALL ORPAn-DRPAn ORPBn-DRPBn ORPCn-DRPCn ORPDn-DRPDn

OVFFLG: ARTIMER Overflow CP1FLG CP2FLG source 3 ZEROFLG: Compare to zero flag CMPFLG: Compare flag End of Transmission PAn pin PBn pin PCn pin PDn pin

SPI Port PAn Port PBn Port PCn Port PDn

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source 1

source 1 source 2 source 0 source 2

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IINTERRUPTS (Cont'd) Interrupt Polarity Register (IPR) Address: DAh
7 -

--

R ead/Write
0 PortD PortC PortA PortB

1 ; port C generates interrupt on rising edge. At reset, IPR is cleared and all port interrupts are not inverted (e.g. Port C generates interrupts on falling edges). Bit 7 - Bit 4 = Unused. Bit 3 = Port D Interrupt Polarity.

In conjunction with IOR register ESB bit, the polarity of I/O pins triggered interrupts can be selected by setting accordingly the Interrupt Polarity Register (IPR). If a bit in IPR is set to one the corresponding port interrupt is inverted (e.g. IPR bit 2 =

Bit 2 = Port C Interrupt Polarity. Bit 1= Port A Interrupt Polarity. Bit 0 = Port B Interrupt Polarity.

Tables 12. I/O Interrupts selections according to IPR, IOR programming
GEN 1 1 1 1 1 1 1 1 0 IPR3 0 0 0 0 1 1 1 1 X IPR0 0 0 1 1 0 0 1 1 X IOR5 0 1 0 1 0 1 0 1 X Port B occurrence falling edge rising edge rising edge falling edge falling edge rising edge rising edge falling edge Disabled Port D occurrence falling edge rising edge falling edge rising edge rising edge falling edge rising edge falling edge Disabled

GEN 1 1 1 1 0 IPR2 0 1

IPR1 0 0 1 1 X

IOR6

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du o

(s) ct

0 1 0 1 X

so Ob -

te le
falling edge low level rising edge high level Disabled

ro P

uc d

s) t(
2

Interrupt source

Port A occurrence

Interrupt source

1

Port C occurrence falling edge rising edge

Interrupt source 0

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INTERRUPTS (Cont'd) Figure 20. Interrupt Block Diagram
FROM REGISTER PORT A,B,C,D,E SINGLE BIT ENABLE PBE IPR Bit 2 VDD FF CLK Q CLR I0 Start IPR Bit 0 PORT A Bits PBE FF CLK Q CLR I1 Start 1 0 MUX INT #0 NMI (FFC,D))

PORT C Bits N MI

SPI

IOR bit 6 (LES)

IPR Bit 1 PORT B B it s PBE

IPR Bit 3 PORT D Bits PBE

bs O

let o

ro P e
RXRDY RXIEN

du

CP1FLG CP1IEN CP2FLG CP2IEN OVFLG OVFIEN CMPFLG CMPIEN ZEROFLG ZERO IEN

(s) ct

IOR bit 5 (ESB)

so Ob FF CLK Q CLR

te le

ro P

uc d

INT #1 (FF6,7)

s) t(
RESTART F ROM STOP/WAIT

INT #2 (FF4,5)

I2 Start

INT #3 (FF2,3)

TMZ ETI

EAI EOC

INT #4 (FF0,1)

TXMT TXIEN

IOR bit 4(GEN)

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3.5 POWER SAVING MODES The WAIT and STOP modes have been implemented in the ST62xx family of MCUs in order to reduce the product's electrical consumption during idle periods. These two power saving modes are described in the following paragraphs. 3.5.1 WAIT Mode The MCU goes into WAIT mode as soon as the WAIT instruction is executed. The microcontroller can be considered as being in a "software frozen" state where the core stops processing the program instructions, the RAM contents and peripheral registers are preserved as long as the power supply voltage is higher than the RAM retention voltage. In this mode the peripherals are still active. WAIT mode can be used when the user wants to reduce the MCU power consumption during idle periods, while not losing track of time or the capability of monitoring external events. The active oscillator is not stopped in order to provide a clock signal to the peripherals. Timer counting may be enabled as well as the Timer interrupt, before entering the WAIT mode: this allows the WAIT mode to be exited when a Timer interrupt occurs. The same applies to other peripherals which use the clock signal. If the WAIT mode is exited due to a Reset (either by activating the external pin or generated by the Watchdog), the MCU enters a normal reset procedure. If an interrupt is generated during WAIT mode, the MCU's behaviour depends on the state of the processor core prior to the WAIT instruction, but also on the kind of interrupt request which is generated. This is described in the following paragraphs. The processor core does not generate a delay following the occurrence of the interrupt, because the oscillator clock is still available and no stabilisation period is necessary. 3.5.2 STOP Mode If the Watchdog is disabled, STOP mode is available. When in STOP mode, the MCU is placed in the lowest power consumption mode. In this operating mode, the microcontroller can be considered as being "frozen", no instruction is executed, the oscillator is stopped, the RAM contents and peripheral registers are preserved as long as the power supply voltage is higher than the RAM retention voltage, and the ST62xx core waits for the occurrence of an external interrupt request or a Reset to exit the STOP state. If the STOP state is exited due to a Reset (by activating the external pin) the MCU will enter a normal reset procedure. Behaviour in response to interrupts depends on the state of the processor core prior to issuing the STOP instruction, and also on the kind of interrupt request that is generat ed. This case will be described in the following paragraphs. The processor core generates a delay after occurrence of the interrupt request, in order to wait for complete stabilisation of the oscillator, before executing the first instruction.

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POWER SAVING MODE (Cont'd) 3.5.3 Exit from WAIT and STOP Modes The following paragraphs describe how the MCU exits from WAIT and STOP modes, when an interrupt occurs (not a Reset). It should be noted that the restart sequence depends on the original state of the MCU (normal, interrupt or non-maskable interrupt mode) prior to entering WAIT or STOP mode, as well as on the interrupt type. Interrupts do not affect the oscillator selection. 3.5.3.1 Normal Mode If the MCU was in the main routine when the WAIT or STOP instruction was executed, exit from Stop or Wait mode will occur as soon as an interrupt occurs; the related interrupt routine is executed and, on completion, the instruction which follows the STOP or WAIT instruction is then executed, providing no other interrupts are pending. 3.5.3.2 Non Maskable Interrupt Mode If the STOP or WAIT instruction has been executed during execution of the non-maskable interrupt routine, the MCU exits from the Stop or Wait mode as soon as an interrupt occurs: the instruction which follows the STOP or WAIT instruction is executed, and the MCU remains in non-maskable interrupt mode, even if another interrupt has been generat ed. 3.5.3.3 Normal Interrupt Mode

tered will be completed, starting with the execution of the instruction which follows the STOP or the WAIT instruction, and the MCU is still in the interrupt mode. At the end of this routine pending interrupts will be serviced in accordance with their priority. In the event of a non-maskable interrupt, the non-maskable interrupt service routine is processed first, then the routine in which the WAIT or STOP mode was entered will be completed by executing the instruction following the STOP or W AIT instruction. The MCU remains in normal interrupt mode. Notes:

To achieve the lowest power consumption during RUN or WAIT modes, the user program must take care of: configuring unused I/Os as inputs without pull-up (these should be externally tied to well defined logic levels); placing all peripherals in their power down modes before entering STOP mode;
When the hardware activated Watchdog is selected, or when the software Watchdog is enabled, the STOP instruction is disabled and a WAIT instruction will be executed in its place. If all interrupt sources are disabled (GEN low), the MCU can only be restarted by a Reset. Although setting GEN low does not mask the NMI as an interrupt, it will stop it generating a wake-up signal. The WAIT and STOP instructions are not executed if an enabled interrupt request is pending.

If the MCU was in interrupt mode before the STOP or WAIT instruction was executed, it exits from STOP or WAIT mode as soon as an interrupt occurs. Nevertheless, two cases must be considered: If the interrupt is a normal one, the interrupt routine in which the WAIT or STOP mode was en-

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ST62T30B ST62E30B

4 ON-CHIP PERIPHERALS
4.1 I/O PORTS The MCU features Input/Output lines which may be individually programmed as any of the following input or output configurations: Input without pull-up or interrupt Input with pull-up and interrupt Input with pull-up, but without interrupt Analog input Push-pull output Open drain output The lines are organised as bytewise Ports. Each port is associated with 3 registers in Data space. Each bit of these registers is associated with a particular line (for instance, bits 0 of Port A Data, Direction and Option registers are associated with the PA0 line of Port A). The DATA registers (DRx), are used to read the voltage level values of the lines which have been configured as inputs, or to write the logic value of the signal to be output on the lines configured as outputs. The port data registers can be read to get the effective logic levels of the pins, but they can Figure 21. I/O Port Block Diagram
RESET SIN CONTROLS

be also written by user software, in conjunction with the related option registers, to select the different input mode options. Single-bit operations on I/O registers are possible but care is necessary because reading in input mode is done from I/O pins while writing will directly affect the Port data register causing an undesired change of the input configuration. The Data Direction registers (DDRx) allow the data direction (input or output) of each pin to be s et . The Option registers (ORx) are used to select the different port options available both in input and in output mode. All I/O registers can be read or written to just as any other RAM location in Data space, so no extra RAM cells are needed for port data storage and manipulation. During MCU initialization, all I/O registers are cleared and the input mode with pull-ups and no interrupt generation is selected for all the pins, thus avoiding pin conflicts.

SHIFT REGISTER

bs O

let o
SOUT

Pr e

du o

DATA DIRECTION REGISTER

(s) ct

so Ob -

te le

ro P
VDD

uc d

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VDD

INPUT /OUTPUT

DATA REGISTER

OPTION REGISTER

TO INTERRUPT TO ADC

VA00413

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I/O PORTS (Cont'd) 4.1.1 Operating Modes Each pin may be individually programmed as input or output with various configurations. This is achieved by writing the relevant bit in the Data (DR), Data Direction (DDR) and Option registers (OR). Table 13 illustrates the various port configurations which can be selected by user software. 4.1.1.1 Input Options Pull-up, High Impedance Option. All input lines can be individually programmed with or without an internal pull-up by programming the OR and DR registers accordingly. If the pull-up option is not selected, the input pin will be in the high-impedance state. Table 13. I/O Port Option Selection
DDR 0 0 0 0 1 1 OR 0 0 1 1 0 1 DR 0 1 0 1 X X Mode Input Input Input Input Output Output

4.1.1.2 Interrupt Options All input lines can be individually connected by software to the interrupt system by programming the OR and DR registers accordingly. The interrupt trigger modes (falling edge, rising edge and low level) can be configured by software as described in the Interrupt Chapter for each port. 4.1.1.3 Analog Input Options Some pins can be configured as analog inputs by programming the OR and DR registers accordingly. These analog inputs are connected to the onchip 8-bit Analog to Digital Converter. ONLY ONE pin should be programmed as an analog input at any time, since by selecting more than one input simultaneously their pins will be effectively shorted.

Option With pull-up, no interrupt No pull-up, no interrupt With pull-up and with interrupt Analog input (when available)

Open-drain output (20mA sink when available) Push-pull output (20mA sink when available)

Note: X = Don't care

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I/O PORTS (Cont'd) 4.1.2 Safe I/O State Switching Sequence Switching the I/O ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. The recommended safe transitions are illustrated in Figure 22. All other transitions are potentially risky and should be avoided when changing the I/O operating mode, as it is most likely that undesirable sideeffects will be experienced, such as spurious interrupt generation or two pins shorted together by the analog multiplexer. Single bit instructions (SET, RES, INC and DEC) should be used with great caution on Ports Data registers, since these instructions make an implicit read and write back of the entire register. In port input mode, however, the data register reads from the input pins directly, and not from the data register latches. Since data register information in input mode is used to set the characteristics of the input pin (interrupt, pull-up, analog input), these may be unintentionally reprogrammed depending on the state of the input pins. As a general rule, it is better to limit the use of single bit instructions on data registers to when the whole (8-bit) port is in output mode. In the case of inputs or of mixed inputs and

outputs, it is advisable to keep a copy of the data register in RAM. Single bit instructions may then be used on the RAM copy, after which the whole copy register can be written to the port data regist er : SET bit, datacopy LD a, datacopy LD DRA, a Warning: Care must also be taken to not use instructions that act on a whole port register (INC, DEC, or read operations) when all 8 bits are not available on the device. Unavailable bits must be masked by software (AND instruction). The WAIT and STOP instructions allow the ST62xx to be used in situations where low power consumption is needed. The lowest power consumption is achieved by configuring I/Os in input mode with well-defined logic levels. The user must take care not to switch outputs with heavy loads during the conversion of one of the analog inputs in order to avoid any disturbance to the conversion.

Figure 22. Diagram showing Safe I/O State Transitions Interrupt pull-up I nput pull-up (Reset state) Output Open Drain Output P us h-pul l

010*

Note *. xxx = DDR, OR, DR Bits respectively

bs O

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ro P e

uc d

(s) t
000 100 110

so Ob -

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ro P
I nput A nal og I nput

uc d

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011

001

101

Output Open Drain Output P us h-pul l

111

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ST62 T30B ST62E30B

I/O PORTS (Cont'd) Table 14. I/O Port configuration for the ST62T30B/E30B
MODE AVAILABLE ON(1) SCHEMATIC

Input (Reset state if PORT PULL option disabled)

PA0-PA5 PB4-PB6 PC4-PC7 PD1-PD7

Data in Interrupt

Input with pull up (Reset state if PORT PULL option enabled)

PA0-PA5 PB4-PB6 PC4-PC7 PD1-PD7

Input with pull up with interrupt

PA0-PA5 PB4-PB6 PC4-PC7 PD1-PD7

Analog Input

PA4-PA5 PB4-PB6 PC4-PC7 PD1-PD7

Open drain output 5mA

bs O

Open drain output 20mA Push-pull output 5mA

let o

Pr e

PA4-PA5 PB4-PB6 PC4-PC7 PD1-PD7 PA0-PA3

du o

(s) ct

so Ob -

te le

ro P
ADC

uc d

s) t(
Data in Data in

Interrupt

Interrupt

Data out

PA4-PA5 PB4-PB6 PC4-PC7 PD1-PD7 PA0-PA3

Data out

Push-pull output 20mA

VR01992A

Note 1. Provided the correct configuration has been selected.

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ST62T30B ST62E30B

I/O PORTS (Cont'd) 4.1.3 ARTimer alternate functions As long as PWMEN (resp. OVFEN) bit is kept low, the PA3/PWM (resp. PA2/OVF) pin is used as standard I/O pin and therefore can be configured in any mode through the DDR and OR registers. If PWMEN (resp. OVFEN) bit is set, PA3/PWM (resp. PA2/OVF) pin must be configured as output through the DDR and OR registers to be used as PW M (OVF) output of the ARTimer16. All output modes are available. PA4/CP1 or PA5/CP2 pins must be configured as input through DDR register to allow CP1 or CP2 triggered input capture of the ARTimer16. All input modes are available and I/O's can be read independently of the ARTimer at any time. As long as RLDSEL2, RLDSEL1 bits do not enable CP1 or CP2 triggered capture, PA4/CP1 and PA5/CP2 are standard I/O's configurable through DDR and OR registers. 4.1.4 SPI alternate functions PD2/Sin and PD1/Scl pins must be configured as input through the DDR and OR registers to be

used as data in and data clock (Slave mode) for the SPI. All input modes are available and I/O's can be read independently of the SPI at any time. PD3/Sout must be configured in open drain output mode to be used as data out for the SPI. In output mode, the value present on the pin is the port data register content only if PD3 is defined as push pull output, while serial transmission is possible only in open drain mode. 4.1.5 UART alternate functions PD4/RXD1 pin must be configured as input through the DDR and OR registers to be used as reception line for the UART. All input modes are available and PD4 can be read independently of the UART at any time. PD5/TXD1 pin must be configured as output through the DDR and OR registers to be used as transmission line for the UART. Value present on the pin in output mode is the Data register content as long as no transmission is active.

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I/O PORTS (Cont'd) Figure 23. Peripheral Interface Configuration of SPI, UART and AR Timer16
VDD PID R XD PD4/RXD1 DR

UART
IARTOE PID PD5/TXD1 MU X 0 1 DR TX D

PID PP/OD OPR PD3/Sout 1 MU X 0 DR OUT PID IN PD2/Sin DR

PD1/Scl

DR

PA3/PWM

bs O

let o

PA4/CP1

Pr e

du o

ct

(s)

so Ob PID MUX 1 0 DR PID

te le
PW M

SYNCHRONOUS SERIAL I/O

ro P

uc d

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CLOCK

PWMEN

PID

C P1 DR

ARTIMER 16
PID C P2

PA5/CP2

DR

OVFEN PID PA2/OVF MU X 1 0 OVF DR VR01661D

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I/O PORTS (Cont'd) 4.1.6 I/O Port Option Registers ORA/B/C/D (CCh PA, CDh PB, CEh PC, CFh PD) Read/Write
7 Px7 Px6 Px5 Px4 Px3 Px2 Px1 0 Px0

4.1.8 I/O Port Data Registers DRA/B/C/D (C0h PA, C1h PB, C2h PC, C3h PD) Read/Write
7 Px7 Px6 Px5 Px4 Px3 Px2 Px1 0 Px0

Bit 7-0 = Px7 - Px0: Port A, B, C, and D Option Register bits. 4.1.7 I/O Port Data Direction Registers DDRA/B /C/D (C4h PA, C5h PB, C6h PC, C7h PD) Read/Write
7 Px7 Px6 Px5 Px4 Px3 Px2 Px1 0 Px0

Bit 7-0 = Px7 - Px0: Port A, B, C, and D Data Registers bits.

Bit 7-0 = Px7 - Px0: Port A, B, C, and D Data Direction Registers bits.

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4.2 TIMER The MCU features an on-chip Timer peripheral, consisting of an 8-bit counter with a 7-bit programmable prescaler, giving a maximum count of 2 15. The peripheral may be configured in three different operating modes. Figure 24 shows the Timer Block Diagram. The external TIMER pin is available to the user. The content of the 8-bit counter can be read/written in the Timer/Counter register, TCR, while the state of the 7-bit prescaler can be read in the PSC register. The control logic device is managed in the TSCR register as described in the following paragraphs. The 8-bit counter is decremented by the output (rising edge) coming from the 7-bit prescaler and can be loaded and read under program control. When it decrements to zero then the TMZ (Timer Zero) bit in the TSCR is set to "1". If the ETI (Enable Timer Interrupt) bit in the TSCR is also set to "1", an interrupt request is generated as described in the Interrupt Chapter. The Timer interrupt can be used to exit the MCU from WAIT mode. The prescaler input can be the internal frequency fINT divided by 12 or an external clock applied to the TIMER pin. The prescaler decrements on the rising edge. Depending on the division factor programmed by PS2, PS1 and PS0 bits in the TSCR. The clock input of the timer/counter register is multiplexed to different sources. For division factor 1, the clock input of the prescaler is also that of timer/counter; for factor 2, bit 0 of the prescaler register is connected to the clock input of TCR. This bit changes its state at half the frequency of the prescaler input clock. For factor 4, bit 1 of the PSC is connected to the clock input of TCR, and so forth. The prescaler initialize bit, PSI, in the TSCR register must be set to "1" to allow the prescaler (and hence the counter) to start. If it is cleared to "0", all the prescaler bits are set to "1" and the counter is inhibited from counting. The prescaler can be loaded with any value between 0 and 7Fh, if bit PSI is set to "1". The prescaler tap is selected by means of the PS2/PS1/PS0 bits in the control register. Figure 25 illustrates the Timer's working principle.

Figure 24. Timer Block Diagram

8 6 5 4 3 2 1 0

PSC

TIMER

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let o

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fOSC

ct u

(s)

SELECT 1 OF 7

so Ob DATABUS 8 8 8-BIT COUNTER 3

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b5 b4

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8
b3 b2 b1 b0

STATUS/CONTROL REGISTER
T M Z ET I TO UT DO UT P SI P S2 P S1 P S0

INTERRUPT LINE SYNCHRONI ZATION LOGIC LATCH

:12

VA00009

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ST62T30B ST62E30B

TIMER (Cont'd) 4.2.1 Timer Operating Modes There are three operating modes, which are selected by the TOUT and DOUT bits (see TSCR register). These three modes correspond to the two clocks which can be connected to the 7-bit prescaler (fINT ÷ 12 or TIMER pin signal), and to the output mode. 4.2.1.1 Gated Mode (TOUT = "0", DOUT = "1") In this mode the prescaler is decremented by the Timer clock input (f INT ÷ 12), but ONLY when the signal on the TIMER pin is held high (allowing pulse width measurement). This mode is selected by clearing the TOUT bit in the TSCR register to "0" (i.e. as input) and setting the DOUT bit to "1". 4.2.1.2 Event Counter Mode (TOUT = "0", DOUT = "0") In this mode, the TIMER pin is the input clock of the prescaler which is decremented on the rising edge. 4.2.1.3 Output Mode (TOUT = "1", DOUT = data out) The TIMER pin is connected to the DOUT latch, hence the Timer prescaler is clocked by the prescaler clock input (fINT ÷ 12). Figure 25. Timer Working Principle

The user can select the desired prescaler division ratio through the PS2, PS1, PS0 bits. When the TC R count reaches 0, it sets the TMZ bit in the TSCR. The TMZ bit can be tested under program control to perform a timer function whenever it goes high. The low-to-high TMZ bit transition is used to latch the DOUT bit of the TSCR and transfer it to the TIMER pin. This operating mode allows external signal generation on the TIMER pin. Table 15. Timer Operating Modes
TOUT 0 0 1 1 DOUT 0 1 0 1 Timer Pin Input Input Output Output Timer Function Event Counter Gated Input Output "0" Output "1"

4.2.2 Timer Interrupt When the counter register decrements to zero with the ETI (Enable Timer Interrupt) bit set to one, an interrupt request is generated as described in the Interrupt Chapter. When the counter decrements to zero, the TMZ bit in the TSCR register is set to one.

CL O CK

BIT0

BIT1

0

1

O

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let o

Pr e
BIT0

du o
BIT1

2

(s) ct
BIT2 BIT2

7-BIT PRESCALER BIT3

so Ob -

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BIT4

BIT5

BIT6

4 3 8-1 MULTIPLEXER

5

6

7

PS 0 PS 1 PS 2

BIT3

BIT4

BIT5

BIT6

BIT7

8-B IT COUNTER
VA00186

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TIMER (Cont'd) 4.2.3 Application Notes TMZ is set when the counter reaches zero; however, it may also be set by writing 00h in the TCR register or by setting bit 7 of the TSCR register. The TMZ bit must be cleared by user software when servicing the timer interrupt to avoid undesired interrupts when leaving the interrupt service routine. After reset, the 8-bit counter register is loaded with 0FFh, while the 7-bit prescaler is loaded with 07Fh, and the TSCR register is cleared. This means that the Timer is stopped (PSI="0") and the timer interrupt is disabled. If the Timer is programmed in output mode, the DOUT bit is transferred to the TIMER pin when TMZ is set to one (by software or due to counter decrement). When TMZ is high, the latch is transparent and DOUT is copied to the timer pin. When TMZ goes low, DOUT is latched. A write to the TCR register will predominate over the 8-bit counter decrement to 00h function, i.e. if a write and a TCR register decrement to 00h occur simultaneously, the write will take precedence, and the TMZ bit is not set until the 8-bit counter reaches 00h again. The values of the TCR and the PSC registers can be read accurately at any time. 4.2.4 Timer Registers Timer Status Control Register (TSCR) Address: 0D4h -- Read/Write
7 TMZ E TI TOUT DOUT PSI PS2 PS1 0

Bit 4 = DOUT: Data Output Data sent to the timer output when TMZ is set high (output mode only). Input mode selection (input mode only). Bit 3 = PSI: Prescaler Initialize Bit Used to initialize the prescaler and inhibit its counting. When PSI="0" the prescaler is set to 7Fh and the counter is inhibited. When PSI="1" the prescaler is enabled to count downwards. As long as PSI="0" both counter and prescaler are not running. Bit 2, 1, 0 = PS2, PS1, PS0: Prescaler Mux. Select. These bits select the division ratio of the prescaler register. Table 16. Prescaler Division Factors
PS2 0 0 0 0 1 1 1 1 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1

bs O

Bit 7 = TMZ: Timer Zero bit A low-to-high transition indicates that the timer count register has decrement to zero. This bit must be cleared by user software before starting a new count. Bit 6 = ETI: Enable Timer Interrupt When set, enables the timer interrupt request. If ETI=0 the timer interrupt is disabled. If ETI=1 and TMZ=1 an interrupt request is generated. Bit 5 = TOUT: Timers Output Control When low, this bit selects the input mode for the TIMER pin. When high the output mode is selected.

let o

od Pr e

ct u

(s)

PS0

so Ob 7 D7 D6

te le
D5

ro P

uc d

s) t(

Divided by 1 2 4 8 16 32 64 128

Timer Counter Register TCR Address: 0D3h -- Read/Write
0 D4 D3 D2 D1 D0

Bit 7-0 = D7-D0: Counter Bits. Prescaler Register PSC Address: 0D2h -- Read/Write
7 D7 D6 D5 D4 D3 D2 D1 0 D0

Bit 7 = D7: Always read as "0". Bit 6-0 = D6-D0: Prescaler Bits.

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4.3 ARTIMER 16 The ARTIMER16 is a timer module based on a 16 bit downcounter with Reload, Capture and Compare features to manage timing requirements. Two outputs provide PWM and Overflow (OVF) output signals each with programmable polarity, and two inputs CP1 and CP2 control start-up, capture and/or reload operations on the central counter. The ARTIMER16 includes four 16-bit registers CMP,RLCP,MASK and CP for the Reload, Capture and compare functions, four 8-bit status/control registers and the associated control logic.The 16-bit registers are accessed from the 8-bit internal bus. The full 16-bit word is written in two bytes, the high byte first and then the low byte. The high byte is stored in an intermediate register and is written to the target 16-bit register at the same Figure 26. ARTIMER16 Block Diagram time as the write to the low byte. This high byte will remain constant if further writes are made to the low bytes, until the high byte is changed. Full Read/Write access is available to all registers except where mentioned. The ARTIMER16 may be placed into the reset mode by resetting RUNRES to 0 in order to achieve lower consumption. The contents of RLCP, CP, MASK and CMP are not affected, nor is the previous run mode of the timer changed. If RUNRES is subsequently set to 1, the timer restarts in the same RUN mode as previously set if no changes are made to the timer status registers. Finally, interrupt capabilities are associated to the Reload, Capture and Compare features.

8 SCR1 8 SCR2 8 8-Bit MCU DATA BUS 16-Bit DATA BUS SCR3 4 SCR4

16 CMP

16-Bit

PSC

16

BUS INTERFACE

8

bs O

let o
INT

Pr e

du o
16

(s) ct
16 16

Ob RLCP 16-Bit CP

MASK

so

16-Bit

te le

Compare

ro P

uc d

fINT

s) t(
PWM

Compare-to-0 16-Bit

OVF

COUNTER

CP1

CONTROL LOGIC

CP2

VR02014

4.3.1 CENTRAL COUNTER The core of the 16 bit Auto-Reload Timer is a 16-

bit synchronous downcounter which accepts the MCU internal clock through a prescaler with a programmable ratio (1/1, 1/4, 1/16).

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ST62 T30B ST62E30B

The maximum time for downcounting is therefore 216 x Psc x Tclk where Psc is the prescaler ratio, and Tclk the period of the main oscillator. This down counter is stopped and its content kept cleared as long as RUNRES bit is cleared. 4.3.1.1 Reload functions The 16-bit down counter can be reloaded 3 different ways: At a zero overflow occurrence with the bit RELOAD cleared: The counter is reloaded to FFFFh. At a zero overflow occurrence with the bit RELOAD set: The counter is reloaded with the value programmed in the RLCP register. For each overflow, the transition between 0000h and the reload value (RLCP or FFFFh) is flagged through the OVFFLG bit. At an external event on pin CP1 or CP2 with the bit RELOAD set: The counter is reloaded with the value programmed in the RLCP register. As a consequence, the time between a timer reload and a zero overflow occurrence depends on the value in RLCP when RELOAD bit is set. This time is equal to (RLCP+1) x Psc x Tclk when RELOAD bit is set, while it is 216 x Psc x Tclk when RELOAD bit is cleared. 4.3.1.2 Compare functions The value in the counter CT is continuously compared to 0000h and to the value programmed into

the Compare Register CMP. The comparison range to 0000h and CMP is defined by using the MASK register to select which bits are used, therefore the comparisons performed are: ? MASK&CT = MASK&CMP. ? MASK&CT = 0000h