ST90158 - ST90135
8/16-BIT MCU FAMILY WITH UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM
Register File based 8/16 bit Core Architecture with RUN, WFI, SLOW and HALT modes s Internal Memory: EPROM/OTP/ROM 24/32/48/64K bytes ROMless version available RAM 768/1K/1.5K/2K bytes s M axim um External Memory: 64K bytes s 2 24 general purpose registers available as RAM, accumulators or index pointers (register file) s 6 7 fully programmable I/O bits s F ully Programmable PLL Clock Generator, with Frequency Multiplication and low frequency, low cost external crystal s M ini mu m 8-bit Instruction Cycle time: 83ns - (@ 24 MHz internal clock frequency) s M ini mu m 16-bit Instruction Cycle time: 250ns (@ 24 MHz internal clock frequency) s 8 external and 1 Non-Maskable Interrupts s DM A Controller and Programmable Interrupt Handler s Sin gle Master Serial Peripheral Interface with I2C capability s T wo 16-bit Timers with 8-bit Prescaler, one usable as a Watchdog Timer (software and h ar d w a r e ) s T hree (ST90158) or two (ST90135) 16-bit Multifunction Timers, each with an 8 bit prescaler, 12 operating modes and DMA capabilities s 8 channel 8-bit Analog to Digital Converter, with Automatic voltage monitoring capabilities and external reference inputs DEVICE SUMMARY
s
TQFP80
PQFP80
s
s s s
s
s
Two (ST90158) or one (ST90135) Serial Communication Interfaces with asynchronous, synchronous and DMA capabilities Rich Instruction Set with 14 Addressing modes Division-by-Zero trap generation Versatile IDE (Integrated development Environment) including Assembler, Linker, Ccompiler, Archiver, Source Level Debugger Hardware tools; Real Time Emulator, EPROM Programming Board Gang Programmer and Real Time Operating System available from Third parties
Features Program Memory RAM Operating Supply CPU Frequency Peripherals Operating Temperature Packages
ST90135M5 24K ROM 768
ST90135M6 32K ROM 1K
ST90158M7 48K ROM 1.5K
ST90158M9 64K ROM 2K
ST90R158 ROMless 2K
ST90T158 64K OTP
2.7V to 3.3V or 4.5V to 5.5V Up to 16MHz (for 2.7V to 3.3V) or Up to 24MHz (for 4.5V to 5.5V) Watchdog Timer, Two MultifuncWatchdog Timer, Three Multifunction Timers, Two SCI, One SPI, tion Timers, One SCI, One SPI, ADC, 16-bit timer ADC, 16-bit Timer -40C to 85C TQFP80 (4.5V to 5.5V and 2.7V to 3.3V) / PQFP80 (4.5V to 5.5V)
Rev. 3.3
January 2001 1/199
9
Table of Contents
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.1 ST9 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.2 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.3 System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.4 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.5 Multifunction Timers (MFT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.6 Standard Timer (STIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.7 Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.8 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.9 Serial Communications Controllers (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.10 Analog/Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 I/O PORT PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 DEVICE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.1 CORE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2 MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.1 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.2 Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3 SYSTEM REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.1 Central Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.2 Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.3 Register Pointing Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.4 Paged Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3.5 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3.6 Stack Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.4 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.5 MEMORY MANAGEMENT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.6 ADDRESS SPACE EXTENSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.6.1 Addressing 16-Kbyte Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.6.2 Addressing 64-Kbyte Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.7 MMU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.7.1 DPR[3:0]: Data Page Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.7.2 CSR: Code Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.7.3 ISR: Interrupt Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.7.4 DMASR : DMA Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.8 MMU USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.8.1 Normal Program Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.8.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.8.3 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3 REGISTER AND MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.1 MEMORY CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.2 EPROM PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.4 ST90158/135 REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 . 48 ... 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.2 INTERRUPT VECTORING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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4.2.1 Divide by Zero trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.2.2 Segment Paging During Interrupt Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.3 INTERRUPT PRIORITY LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.4 PRIORITY LEVEL ARBITRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.4.1 Priority level 7 (Lowest) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.4.2 Maximum depth of nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.4.3 Simultaneous Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.4.4 Dynamic Priority Level Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.5 ARBITRATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.5.1 Concurrent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.5.2 Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.7 TOP LEVEL INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.8 ON-CHIP PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.9 INTERRUPT RESPONSE TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.10 INTERRUPT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5 ON-CHIP DIRECT MEMORY ACCESS (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.2 DMA PRIORITY LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3 DMA TRANSACTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.4 DMA CYCLE TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.5 SWAP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.6 DMA REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6 RESET AND CLOCK CONTROL UNIT (RCCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.2 CLOCK CONTROL UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.2.1 Clock Control Unit Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3 CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.3.1 PLL Clock Multiplier Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3.2 CPU Clock Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3.3 Peripheral Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3.5 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.4 CLOCK CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.5 OSC ILLATOR CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.6 RESET/STOP MANAGER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.6.1 RESET Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7 EXTERNAL MEMORY INTERFACE (EXTMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.2 EXTERNAL MEMORY SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.2.1 AS: Address Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.2.2 DS: Data Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.2.3 DS2: Data Strobe 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.2.4 RW : Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.2.5 BREQ, BACK: Bus Request, Bus Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.2.6 PORT 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.2.7 PORT 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
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7.2.8 WAIT: External Memory Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.2 SPECIFIC PORT CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.3 POR T CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.4 INPUT/OUTPU T BIT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8.5 ALTER NATE FUNCTION ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.5.1 Pin Declared as I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.5.2 Pin Declared as an Alternate Function Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.5.3 Pin Declared as an Alternate Function Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.6 I/O STATUS AFTER WFI, HALT AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.1 TIMER/W ATCHDOG (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 9.1.3 Watchdog Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.1.4 WD T Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 9.1.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 9.2 STANDARD TIMER (STIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 9.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 9.2.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 9.2.3 Interrupt Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 9.2.4 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 9.2.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 9.3 MULTIFUNCTION TIMER (MFT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 9.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 9.3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.3.3 Input Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9.3.4 Output Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.3.5 Interrupt and DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.3.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9.4 STANDARD TIMER (STIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9.4.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.4.3 Interrupt Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.4.4 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.4.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.5.2 Device-Specific Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.5.4 Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 9.5.5 Working With Other Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.5.6 I2C-bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.5.7 S-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 9.5.8 IM-bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 9.5.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
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Table of Contents
9.6 MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) . . . . . . . . . . . . 9.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6.4 SCI-M Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6.5 Serial Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6.6 Clocks And Serial Transmission Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6.7 SCI -M Initialization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6.8 Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6.9 Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6.10 Interrupts and DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6.11 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.7 MIRROR REGISTER (MR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.7.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.7.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8 EIGHT-CH ANNEL ANALOG TO DIGITAL CONVERTER (A/D) . . . . . . . . . . . . . . . . . . . 9.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 144 144 145 146 149 152 152 154 154 155 158 169 1 69 169 169 169 170 170 171 173 174 178 195 195 197
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1 GENERAL DESCRIPTION
1.1 INTRODUCTION The ST90158 and ST90135 microcontrollers are developed and manufactured by STMicroelectronics using a proprietary n-well CMOS process. Their performance derives from the use of a flexible 256-register programming model for ultra-fast context switching and real-time event response. The intelligent on-chip peripherals offload the ST9 core from I/O and data management processing tasks allowing critical application tasks to get the maximum use of core resources. The new-generation ST9 MCU devices now also support low power consumption and low voltage operation for power-efficient and low-cost embedded systems. 1.1.1 ST9 Core The advanced Core consists of the Central Processing Unit (CPU), the Register File, the Interrupt and DMA controller, and the Memory Management Unit (MMU). The MMU allows addressing of up to 4 Megabytes of program and data mapped into a single linear space. Four independent buses are controlled by the Core: a 16-bit memory bus, an 8-bit register data bus, an 8-bit register address bus and a 6-bit interrupt/DMA bus which connects the interrupt and DMA controllers in the on-chip peripherals with the core. This multiple bus architecture makes the ST9 family devices highly efficient for accessing on and offchip memory and fast exchange of data with the on-chip peripherals. The general-purpose registers can be used as accumulators, index registers, or address pointers. Adjacent register pairs make up 16-bit registers for addressing or 16-bit processing. Although the ST9 has an 8-bit ALU, the chip handles 16-bit operations, including arithmetic, loads/stores, and memory/register and memory/memory exchanges. 1.1.2 Power Saving Modes To optimize performance versus power consumption, a range of operating modes can be dynamically selected. Run Mode. This is the full speed execution mode with CPU and peripherals running at the maximum clock speed delivered by the Phase Locked Loop (PLL) of the Clock Control Unit (CCU). Slow Mode. Power consumption can be significantly reduced by running the CPU and the peripherals at reduced clock speed using the CPU Prescaler and CCU Clock Divider (PLL not used) or by using the CK_AF external clock. Wait For Interrupt Mode. The Wait For Interrupt (WFI) instruction suspends program execution until an interrupt request is acknowledged. During WFI, the CPU clock is halted while the peripheral and interrupt controller keep running at a frequency programmable via the CCU. Halt Mode. When executing the HALT instruction, and if the Watchdog is not enabled, the CPU and its peripherals stop operating and the status of the machine remains frozen (the clock is also stopped). A reset is necessary to exit from Halt m ode. 1.1.3 System Clock A programmable PLL Clock Generator allows standard 3 to 5 MHz crystals to be used to obtain a large range of internal frequencies up to 16 MHz or 24 MHz, depending on device. 1.1.4 I/O Ports The I/O lines are grouped into up to nine 8-bit I/O Ports and can be configured on a bit basis to provide timing, status signals, an address/data bus for interfacing to external memory, timer inputs and outputs, analog inputs, external interrupts and serial or parallel I/O.
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1.1.5 Multifunction Timers (MFT) Each multifunction timer has a 16-bit Up/Down counter supported by two 16-bit Compare registers and two 16-bit input capture registers. Timing resolution can be programmed using an 8-bit prescaler. Multibyte transfers between the peripheral and memory are supported by two DMA channels. 1.1.6 Standard Timer (STIM) The Standard Timer includes a programmable 16bit down counter and an associated 8-bit prescaler with Single and Continuous counting modes. 1.1.7 Watchdog Timer (WDT) The Watchdog timer can be used to monitor system integrity. When enabled, it generates a reset after a timeout period unless the counter is refreshed by the application software. For additional
security, watchdog function can be enabled by hardware using a specific pin. 1.1.8 Serial Peripheral Interface (SPI) The SPI bus is used to communicate with external devices via the SPI, I²C, IMBus or SBus communication standards. The SPI uses one or two lines for serial data and a synchronous clock signal. 1.1.9 Serial Communications Controllers (SCI) Each SCI provides a synchronous or asynchronous serial I/O port using two DMA channels. Baud rates and data formats are programmable. 1.1.10 Analog/Digital Converter (ADC) The ADCs provide up to 8 analog inputs with onchip sample and hold. The analog watchdog generates an interrupt when the input voltage moves out of a preset threshold.
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ST90 158 - GENERAL DESCRIPTION
Figure 1. ST90158 Block Diagram
ADDRESS DATA
Port0 EPROM/ ROM/OTP up to 64 Kbytes
P0[7:0]
ADDRESS
Port1
P1[7:0] P0[7:0] P1[7:0] P2[6:0] P4[7:0] P5[7:3], P5.1 P6[6:0] P7[7:0] P8[7:0] P9[7:4], P9[2:0]
RAM up to 2 Kbytes
Fully Prog.
256 bytes Register File 8/16 bits CPU Interrupt Management ST9 CORE
MEMORY BUS
AS WAIT NMI R/W DS
I/Os
STIM
STOUT
INT0-7
OSCIN OSCOUT RESET INTCLK CKAF
SPI I2C/IM Bus
SDI SDO SCK
REGISTER BUSES
RCCU
WDIN WDOUT HW0SW1 T0OUTA T0OUTB T0INA T0INB T1OUTA T1OUTB T1INA T1INB T3OUTA T3OUTB T3INA T3INB
WATCHDOG
A/D Converter with analog watchdog
EXTRG AIN[7:0] TX0CKIN RX0CKIN S0IN DCD0 S0OUT CLK0OUT RTS0 TX1CKIN RX1CKIN S1IN DCD1 S1OUT CLK1OUT RTS1
MFT0
SCI0
MFT1 SCI1 MFT3
All alternate functions (Italic characters) are mapped on Port2 through Port9
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ST90158 - GENERAL DESCRIPTION
Figure 2. ST90135 Block Diagram
ADDRESS D A TA
ROM up to 32 Kbytes
Port0
P0[7:0]
ADDRESS
Port1 RAM up to 1 Kbyte
Fully Prog.
P1[7:0] P0[7:0] P1[7:0] P2[6:0] P4[7:0] P5[7:3], P5.1 P6[6:0] P7[7:0] P8[7:0] P9[7:4], P9[2:0]
256 bytes Register File 8/16 bits CPU Interrupt Management ST9 CORE
MEMORY BUS
AS WA IT N MI R/W DS
I/Os
STIM
STOUT
INT0-7
OSCIN OSCOUT RESET INTCLK CKAF
SPI I2C/IM Bus
SDI SDO SCK
REGISTER BUSES
RCCU
WDIN WDOUT HW0SW1 T1OUTA T1OUTB T1INA T1INB T3OUTA T3OUTB T3INA T3INB
WATCHDOG
A/D Converter with analog watchdog SCI0
EXTRG AIN[7:0] TX0CKIN RX0CKIN S0IN DCD0 S0OUT CLK0OUT RTS0
MFT1
MFT3
All alternate functions (Italic characters) are mapped on Port2 through Port9
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ST90 158 - GENERAL DESCRIPTION
1.2 PIN DESCRIPTION RESET: Reset (input, active low). The ST9 is initialised by the Reset signal. With the deactivation of RESET, program execution begins from the memory location pointed to by the vector contained in memory locations 00h and 01h. AS: Address Strobe (output, active low, 3-state). Address Strobe is pulsed low once at the beginning of each memory cycle. The rising edge of AS indicates that address, Read/Write (R/W), and Data Memory signals are valid for memory transfers. Under program control, AS can be placed in a high-impedance state along with Port 0, Port 1 and Data Strobe (DS). AS is active after reset on Romless device. DS: Data Strobe (output, active low, 3-state). Data Strobe provides the timing for data movement to or from Port 0 for each memory transfer. During a write cycle, data out is valid at the leading edge of DS. During a read cycle, Data In must be valid prior to the trailing edge of DS. When the ST90158 accesses on-chip memory, DS is held high during the whole memory cycle. It can be placed in a high impedance state along with Port 0, Port 1 and AS. DS is active after reset on Romless device. R/W: Read/Write (output, 3-state). Read/Write determines the direction of data transfer for external memory transactions. R/W is low when writing to external memory, and high for all other transactions. It can be placed in high impedance state along with Port 0, Port 1, AS and DS. R/W is not active after reset on Romless device. OSCIN, OSCOUT: Oscillator (input and output). These pins connect a parallel-resonant crystal (3 to 5 MHz), or an external source to the on-chip clock oscillator and buffer. OSCIN is the input of the oscillator inverter and internal clock generator; OSCOUT is the output of the oscillator inverter. HW0_SW 1: When connected to VDD through a 1K pull-up resistor, the software watchdog option is selected. When connected to VSS through a 1K pull-down resistor, the hardware watchdog option is selected. VPP: Programming voltage for EPROM/OTP devices. Must be connected to VSS in user mode through a 10 Kohm resistor. AVDD: Analog VDD of the Analog to Digital Converter. AVSS: Analog VSS of the Analog to Digital Converter. VDD: Main Power Supply Voltage. VSS: Digital Circuit Ground. P0[7:0], P1[7:0]: (Input/Output, TTL or CMOS compatible). 16 lines grouped into I/O ports providing the external memory interface for addressing 64Kbytes of external memory. P0[7:0], P1[7:0], P2[6:0], P4[7:0], P5[7:3], P5.1, P6[6:0], P7[7:0], P8[7:0], P9[7:4], P9[2:0]: I/O Port Lines (Input/Output, TTL or CMOS compatible). I/O lines grouped into I/O ports of 8 bits, bit programmable under program control as general purpose I/O or as alternate functions.
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PIN DESCRIPTION (Cont'd) Figure 3. 80-Pin TQFP Pin-out
AD6/P0.6 VSS AD7/P0.7 VD D AS DS VP P * P4.0 P4.1 INTCLK/P4.2 ST OUT/P4.3 WDOUT/INT0/P4.4 INT4/P4.5 T0OUTB/INT5/P4.6 T0OUTA/P4.7 P2.0 P2.1 P2.2 P2.3 P2.4
80 1
P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 P6.6 P6.5/RW P6.4 P6.3 P6.2 P6.1 P6.0 P1.7/A15 P1.6/A14 P1.5/A13 P1.4/A12 P1.3/A11 P1.2/A10 P1.1/A9 61 60
ST90158/ST90135
20 21
41 40
P1.0/A8 RESET OSCIN VS S OSCOUT P5.1/SDI HW0SW1 P5.3 P5.4/T1OUTA/DCD0 P5.5/T1OUT1/RTS0 P5.6/T3OUTA/DCD1 P5.7/T3OUTB/RTS1/CKAF VD D P8.0/T3INA P8.1/T1INB P8.2/INT1/T1OUTA P8.3/INT3/T1OUTB P8.4/T1INA/WAIT/WDOUT P8.5/T3INB P8.6/INT7/T3OUTA
P2.5 P2.6 S1OUT/P9.0 T0OUTB/S1IN/P9.1 TX1CKIN/CLK1OUT/P9.2 S0OUT/RX1CKIN/P9.4 S0IN/P9.5 INT2/SCK/P9.6 INT 6/SDO/P9.7 AIN0/RX0CKIN/WDIN/EXTRG/P7.0 AIN1/T0INB/P7.1 AIN2/CLK0OUT/TX0CKIN/P7.2 AIN3/T0INA/P7.3 AIN4/P7.4 AIN5/P7.5 AIN6/P7.6 AIN7/P7.7 AVD D AVSS NMI/T3OUTB/P8.7
*EPROM or OTP devices only
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ST90 158 - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont'd) Figure 4. 80-Pin PQFP Pin-Out
P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 P6.6 P6.5/RW P6.4 P6.3 P6.2 P6.1 P6.0 P1.7/A15 P1.6/A14 P1.5/A13 P1.4/A12 P1.3/A11 AD4/P0.4 AD5/P0.5 AD6/P0.6 VSS AD7/P0.7 VD D AS DS VPP* P4.0 P4.1 INTCLK/P4.2 STOUT/P4.3 INT0/WDOUT/P4.4 INT4/P4.5 INT5/T0OUTB/P4.6 T0OUTA/P4.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 1 80 64
ST90158/ST90135
24
40
P1.2/A10 P1.1/A9 P1.0/A8 RESET OSCIN VSS OSCOUT P5.1/SDI HW0SW1 P5.3 P5.4/T1OUTA/DCD0 P5.5/T1OUTB/RTS0 P5.6/T3OUTA/DCD1 P5.7/T3OUTB/RTS1/CK_AF VDD P8.0/T3INA P8.1/T1INB P8.2/T1OUTA/INT1 P8.3/T1OUTB/INT3 P8.4/T1INA/WAIT/WDOUT P8.5/T3INB P8.6/INT7/T3OUTA P8.7/NMI/T3OUTB AVSS
S1OUT/P9.0 T0OUTB/S1IN/P9.1 TX1CKIN/CLK1OUT/P9.2 S0OUT/RX1CKIN/P9.4 S0IN/P9.5 INT2/SCK/P9.6 INT6/SDO/P9.7 AIN0/RX0CKIN/WDIN/EXTRG/P7.0 AIN1/T0INB/P7.1 AIN2/CLK0OUT/TX0CKIN/P7.2 AIN3/T0INA/P7.3 AIN4/P7.4 AIN5/P7.5 AIN6/P7.6 AIN7/P7.7 A VD D 12/199
*EPROM or OTP devices only
9
ST90158 - GENERAL DESCRIPTION
1.3 I/O PORT PINS All the ports of the device can be programmed as Input/Output or in Input mode, compatible with TTL or CMOS levels (except where Schmitt Trigger is present). Each bit can be programmed individually (Refer to the I/O ports chapter). TTL/CMOS Input For all those port bits where no input schmitt trigger is implemented, it is always possible to program the input level as TTL or CMOS compatible by programming the relevant PxC2.n control bit. Refer to the section titled "Input/Output Bit Configuration" in the I/O Ports Chapter . Table 1. I/O Port Characteristics
Port 0 Port 1 Port 2 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Input TTL/CMOS TTL/CMOS TTL/CMOS Schmitt trigger Schmitt trigger TTL/CMOS Schmitt trigger Schmitt trigger Schmitt trigger Output Push-Pull/OD Push-Pull/OD Push-Pull/OD Push-Pull/OD Push-Pull/OD Push-Pull/OD Push-Pull/OD Push-Pull/OD Push-Pull/OD Weak Pull-Up Yes Yes No Yes Yes No Yes Yes Yes Reset State Bidirectional WPU Bidirectional WPU Bidirectional Bidirectional WPU Bidirectional WPU Bidirectional Bidirectional WPU Bidirectional WPU Bidirectional WPU
Push-Pull/OD Output The output buffer can be programmed as pushpull or open-drain: attention must be paid to the fact that the open-drain option corresponds only to a disabling of P-channel MOS transistor of the buffer itself: it is still present and physically connected to the pin. Consequently it is not possible to increase the output voltage on the pin over VDD+0.3 Volt, to avoid direct junction biasing.
Legend: WPU = Weak Pull-Up, OD = Open Drain
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I/O PORT PINS (Cont'd) How to Configure the I/O ports To configure the I/O ports, use the information in Table 1, Table 2 and the Port Bit Configuration Table (Table 19) in the I/O Ports Chapter (See page 91 ) . Input Note = the hardware characteristics fixed for each port line in Table 1. If Input note = TTL/CMOS, either TTL or CMOS input level can be selected by software. If Input note = Schmitt trigger, selecting CMOS or TTL input by software has no effect, the input will always be Schmitt Trigger. Alternate Functions (AF) = More than one AF cannot be assigned to an I/O pin at the same time. All alternate functions are mapped on Port 2 through Port 9. An alternate function can be selected as follows. AF Inputs: AF is selected implicitly by enabling the corresponding peripheral. Exception to this are A/D inputs which must be explicitly selected as AF by software. AF Outputs or Bidirectional Lines: In the case of Outputs or I/Os, AF is selected explicitly by software. Example 1: SCI data input AF: S0IN, Port: P9.5, Port Style: Input Schmitt Trigger. Write the port configuration bits: P 9 C 2 . 5 =1 P 9 C 1 . 5 =0 P 9 C 0 . 5 =1 Enable the SCI peripheral by software as described in the SCI chapter. Example 2: SCI data output AF: S0OUT, Port: P9.4 Output push-pull (configured by software). Write the port configuration bits: P9C2.4=0 P 9 C 1 . 4 =1 P 9 C 0 . 4 =1 Example 3: ADC data input AF: AIN0, Port : P7.0, Input Note: does not apply to ADC Write the port configuration bits: P7C2.0=1 P 7 C 1 . 0 =1 P 7 C 0 . 0 =1 Example 4: External Memory I/O AF: AD0, Port : P0.0 Write the port configuration bits: P0C2.0=0 P 0 C 1 . 0 =1 P 0 C 0 . 0 =1
Table 2. I/O Port Description and Alternate Functions
Pin No. PQFP TQFP Alternate Functions
Port Name
General Purpose I/O
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 All ports useable for general purpose I/O (input, output or bidirectional)
75 77 AD0 76 78 AD1 77 79 AD2 78 80 AD3 79 80 1 3 1 2 3 5 AD4 AD5 AD6 AD7
I/O Address/Data bit 0 mux I/O Address/Data bit 1 mux I/O Address/Data bit 2 mux I/O Address/Data bit 3 mux I/O Address/Data bit 4 mux I/O Address/Data bit 5 mux I/O Address/Data bit 6 mux I/O Address/Data bit 7 mux I/O Address bit 8 I/O Address bit 9
60 62 A8 61 63 A9
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Port Name
P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 P5.1 P5.3 P5.4
62 64 A10 63 65 A11 64 66 A12 65 67 A13 66 68 A14 67 69 A15 16 18 17 19 18 20 19 21 20 22 21 23 22 24 8 9 10 All ports useable 11 for general purpose I/O (input, output or bidirec- 12 tional) 13 10 11 12 INTCLK 13 STOUT 14 INT0 WDOUT
PQFP
TQFP
General Purpose I/O
Pin No. Alternate Functions
I/O Address bit 10 I/O Address bit 11 I/O Address bit 12 I/O Address bit 13 I/O Address bit 14 I/O Address bit 15 I/O I/O I/O I/O I/O I/O I/O I/O I/O O Internal main Clock O Standard Timer Output I External Interrupt 0
O Watchdog Timer output I I External interrupt 4 External Interrupt 5
15 INT4 INT5 T0OUTB
14 16
O MF Timer 0 Output B 1) O MF Timer 0 Output A 1) I I/O SPI Serial Data In
15 17 T0OUTA 55 57 SDI 53 55 52 54 T1OUTA DCD0 RTS0 T1OUTB T3OUTA DCD1 RTS1
O MF Timer 1 output A I SCI0 Data Carrier Detect
P5.5
51 53
O SCI0 Request to Send O MF Timer 1 output B O MF Timer 3 output A I SCI1 Data Carrier Detect 1) O SCI1 Request to Send 1) O MF Timer 3 output B I I/O External Clock Input
P5.6
50 52
P5.7
49 51 T3OUTB CK_AF
P6.0
68 70
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Port Name
P6.1 P6.2 P6.3 P6.4 P6.5 P6.6
69 71 70 72 71 73 72 74 73 75 R/W 74 76 AIN0
PQFP
TQFP
General Purpose I/O
Pin No. Alternate Functions
I/O I/O I/O I/O O Read/Write I/O I I I I I I I A/D Analog input 0 SCI0 Receive Clock input T/WD input A/D External Trigger A/D Analog input 1 MF Timer 0 input B 1) A/D Analog input 2
P7.0
30 32
RX0CKIN WDIN EXTRG
P7.1
31 33
AIN1 T0INB AIN2
P7.2
32 34 CLK0OUT O SCI0 Byte Sync Clock output TX0CKIN I I I I I I I I I I SCI0 Transmit Clock input A/D Analog input 3 MF Timer 0 input A 1) A/D Analog input 4 A/D Analog input 5 A/D Analog input 6 A/D Analog input 7 MF Timer 3 input A MF Timer 1 input B External interrupt 1
P7.3 P7.4 P7.5 P7.6 P7.7 P8.0 P8.1 P8.2
All ports useable 33 35 for general purpose I/O (input, 34 36 output or bidirec35 37 tional) 36 38
AIN3 T0INA AIN4 AIN5 AIN6
37 39 AIN7 47 49 T3INA 46 48 T1INB 45 47 INT1 T1OUTA INT3 T1OUTB T1INA
O MF Timer 1 output A I External interrupt 3
P8.3
44 46
O MF Timer 1 output B I I MF Timer 1 input A External Wait input
P8.4
43 45 WAIT WDOUT
O Watchdog Timer output I I MF Timer 3 input B External interrupt 7
P8.5 P8.6
42 44 T3INB 41 43 INT7 T3OUTA NMI T3OUTB
O MF Timer 3 output A I Non-Maskable Interrupt
P8.7
40 42
O MF Timer 3 output B
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Port Name
PQFP
TQFP
General Purpose I/O
Pin No. Alternate Functions
P9.0 P9.1
23 25 S1OUT 24 26 T0OUTB S1IN
O SCI1 Serial Output 1) O MF Timer 0 output B 1) I SCI1 Serial Input 1) SCI1 Transmit Clock input 1)
P9.2
25 27 All ports useable for general purpose I/O (input, 26 28 output or bidirectional) 27 29 28 30
CLK1OUT O SCI1 Byte Sync Clock output 1) TX1CKIN S0OUT I
P9.4 P9.5 P9.6
O SCI0 Serial Output
RX1CKIN O SCI1 Receive Clock input 1) S0IN INT2 SCK INT6 SDO I I SCI0 Serial Input External interrupt 2
O SPI Serial Clock I External interrupt 6
P9.7
29 31
O SPI Serial Data Out
Note 1) Not present on ST90135
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2 DEVICE ARCHITECTURE
2.1 CORE ARCHITECTURE The ST9 Core or Central Processing Unit (CPU) features a highly optimised instruction set, capable of handling bit, byte (8-bit) and word (16-bit) data, as well as BCD and Boolean formats; 14 addressing modes are available. Four independent buses are controlled by the Core: a 16-bit Memory bus, an 8-bit Register data bus, an 8-bit Register address bus and a 6-bit Interrupt/DMA bus which connects the interrupt and DMA controllers in the on-chip peripherals with the Core. This multiple bus architecture affords a high degree of pipelining and parallel operation, thus making the ST9 family devices highly efficient, both for numerical calculation, data handling and with regard to communication with on-chip peripheral resources. which hold data and control bits for the on-chip peripherals and I/Os. A single linear memory space accommodating both program and data. All of the physically separate memory areas, including the internal ROM, internal RAM and external memory are mapped in this common address space. The total addressable memory space of 4 Mbytes (limited by the size of on-chip memory and the number of external address pins) is arranged as 64 segments of 64 Kbytes. Each segment is further subdivided into four pages of 16 Kbytes, as illustrated in Figure 5. A Memory Management Unit uses a set of pointer registers to address a 22-bit memory field using 16-bit address-based instructions. 2.2.1 Register File The Register File consists of (see Figure 6): 2.2 MEMORY SPACES 224 general purpose registers (Group 0 to D, There are two separate memory spaces: registers R0 to R223) The Register File, which comprises 240 8-bit 6 system registers in the System Group (Group registers, arranged as 15 groups (Group 0 to E), E, registers R224 to R239) each containing sixteen 8-bit registers plus up to Up to 64 pages, depending on device configura64 pages of 16 registers mapped in Group F, tion, each containing up to 16 registers, mapped to Group F (R240 to R255), see Figure 7. Figure 5. Single Program and Data Memory Address Space
Address
3 FFFFFh 3F0000h 3 E FFFFh 3E0000h
Data 16K Pages
255 254 253 252 251 250 249 248 247
Code 64K Segments
63
62
up to 4 Mbytes
135 134 133 132
21FFFFh 210000h 20FFFFh
Reserved
33
02FFFF h 020000h 01FFFF h 010000h 00FFFF h 0 0 00h
11 10 9 8 7 6 5 4 3 2 1 0
2
1
0
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MEMORY SPACES (Cont'd) Figure 6. Register Groups
UP TO 64 PAGES
Figure 7. Page Pointer for Group F mapping
P AGE 63
255 240 F PA GE D REGISTERS 239 E S YS TE M REGISTERS 224 223 D C B A 9 8 7 6 5 4 3 2 1 0 0 15 0
P AG E 5 R2 5 5 P AGE 0
R2 4 0 R 234 224 GEN ER AL P UR PO SE RE G I ST ER S R 224 PA GE POINTER
VA00432
R0
VA00433
Figure 8. Addressing the Register File
RE GIS TER FILE 255 240 F PA GE D REGISTERS 239 E S YS TE M REGISTERS 224 223 D C B A 9 8 7 6 5 4 3 2 1 0 0 15 0
VR 000118
G RO U P D R1 9 5 (R 0C3h) R2 0 7
( 1100) (0011) G R O UP C
R 195 R1 9 2 G R O UP B
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MEMORY SPACES (Cont'd) 2.2.2 Register Addressing Register File registers, including Group F paged registers (but excluding Group D), may be addressed explicitly by means of a decimal, hexadecimal or binary address; thus R231, RE7h and R11100111b represent the same register (see Figure 8). Group D registers can only be addressed in Working Register mode. Note that an upper case "R" is used to denote this direct addressing mode. Working Registers Certain types of instruction require that registers be specified in the form "rx", where x is in the range 0 to 15: these are known as Working Registers. Note that a lower case "r" is used to denote this indirect addressing mode. Two addressing schemes are available: a single group of 16 working registers, or two separately mapped groups, each consisting of 8 working registers. These groups may be mapped starting at any 8 or 16 byte boundary in the register file by means of dedicated pointer registers. This technique is described in more detail in Section 2.3.3 Register Pointing Techniques, and illustrated in Figure 9 and in Figure 10. System Registers The 16 registers in Group E (R224 to R239) are System registers and may be addressed using any of the register addressing modes. These registers are described in greater detail in Section 2.3 SYSTEM REGISTERS. Paged Registers Up to 64 pages, each containing 16 registers, may be mapped to Group F. These are addressed using any register addressing mode, in conjunction with the Page Pointer register, R234, which is one of the System registers. This register selects the page to be mapped to Group F and, once set, does not need to be changed if two or more registers on the same page are to be addressed in succession.
Therefore if the Page Pointer, R234, is set to 5, the instructions: spp #5 ld R242, r4 will load the contents of working register r4 into the third register of page 5 (R242). These paged registers hold data and control information relating to the on-chip peripherals, each peripheral always being associated with the same pages and registers to ensure code compatibility between ST9 devices. The number of these registers therefore depends on the peripherals which are present in the specific ST9 family device. In other words, pages only exist if the relevant peripheral is present. Table 3. Register File Organization
Hex. Address F0-FF E0-EF D0-DF C0-CF B0-BF A0-AF 90-9F 80-8F 70-7F 60-6F 50-5F 40-4F 30-3F 20-2F 10-1F 00-0F Decimal Address 240-255 224-239 208-223 192-207 176-191 160-175 144-159 128-143 112-127 96-111 80-95 64-79 48-63 32-47 16-31 00-15 General Purpose Registers Function Paged Registers System Registers Register File Group Group F Group E Group D Group C Group B Group A Group 9 Group 8 Group 7 Group 6 Group 5 Group 4 Group 3 Group 2 Group 1 Group 0
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2.3 SYSTEM REGISTERS The System registers are listed in Table 4. They are used to perform all the important system settings. Their purpose is described in the following pages. Refer to the chapter dealing with I/O for a description of the PORT[5:0] Data registers. Table 4. System Registers (Group E)
R239 (EFh) R238 (EEh) R237 (EDh) R236 (ECh) R235 (EBh) R234 (EAh) R233 (E9h) R232 (E8h) R231 (E7h) R230 (E6h) R229 (E5h) R228 (E4h) R227 (E3h) R226 (E2h) R225 (E1h) R224 (E0h) SSPLR SSPHR USPLR USPHR MODE REGISTER PAGE POINTER REGISTER REGISTER POINTER 1 REGISTER POINTER 0 FLAG REGISTER CENTRAL INT. CNTL REG PORT5 DATA REG. PORT4 DATA REG. PORT3 DATA REG. PORT2 DATA REG. PORT1 DATA REG. PORT0 DATA REG.
Note: If an MFT is not included in the ST9 device, then this bit has no effect. Bit 6 = TLIP: Top Level Interrupt Pending. This bit is set by hardware when a Top Level Interrupt Request is recognized. This bit can also be set by software to simulate a Top Level Interrupt Request. 0: No Top Level Interrupt pending 1: Top Level Interrupt pending Bit 5 = TLI: Top Level Interrupt bit. 0: Top Level Interrupt is acknowledged depending on the TLNM bit in the NICR Register. 1: Top Level Interrupt is acknowledged depending on the IEN and TLNM bits in the NICR Register (described in the Interrupt chapter). Bit 4 = IEN: Interrupt Enable . This bit is cleared by interrupt acknowledgement, and set by interrupt return (iret). IEN is modified implicitly by iret, ei and di instructions or by an interrupt acknowledge cycle. It can also be explicitly written by the user, but only when no interrupt is pending. Therefore, the user should execute a di instruction (or guarantee by other means that no interrupt request can arrive) before any write operation to the CICR register. 0: Disable all interrupts except Top Level Interrupt. 1: Enable Interrupts Bit 3 = IAM: Interrupt Arbitration Mode. This bit is set and cleared by software to select the arbitration mode. 0: Concurrent Mode 1: Nested Mode. Bits 2:0 = CPL[2:0]: Current Priority Level. These three bits record the priority level of the routine currently running (i.e. the Current Priority Level, CPL). The highest priority level is represented by 000, and the lowest by 111. The CPL bits can be set by hardware or software and provide the reference according to which subsequent interrupts are either left pending or are allowed to interrupt the current interrupt service routine. When the current interrupt is replaced by one of a higher priority, the current priority value is automatically stored until required in the NICR register.
2.3.1 Central Interrupt Control Register Please refer to the "INTERRUPT" chapter for a detailed description of the ST9 interrupt philosophy. CEN TRAL INTERRUPT CONTROL REGISTER (CICR) R230 - Read/Write Register Group: E (System) Reset Value: 1000 0111 (87h)
7 GCEN TLIP TLI IEN IAM 0 CPL2 CPL1 CPL0
Bit 7 = GCEN: Global Counter Enable. This bit is the Global Counter Enable of the Multifunction Timers. The GCEN bit is ANDed with the CE bit in the TCR Register (only in devices featuring the MFT Multifunction Timer) in order to enable the Timers when both bits are set. This bit is set after the Reset cycle.
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SYSTEM REGISTERS (Cont'd) 2.3.2 Flag Register The Flag Register contains 8 flags which indicate the CPU status. During an interrupt, the flag register is automatically stored in the system stack area and recalled at the end of the interrupt service routine, thus returning the CPU to its original status. This occurs for all interrupts and, when operating in nested mode, up to seven versions of the flag register may be stored. FLAG REGISTER (FLAGR) R231- Read/Write Register Group: E (System) Reset value: 0000 0000 (00h)
7 C Z S V DA H 0 DP
decw), Test (tm, tmw, tcm, tcmw, btset). In most cases, the Zero flag is set when the contents of the register being used as an accumulator become zero, following one of the above operations. Bit 5 = S: Sign Flag. The Sign flag is affected by the same instructions as the Zero flag. The Sign flag is set when bit 7 (for a byte operation) or bit 15 (for a word operation) of the register used as an accumulator is one. Bit 4 = V: Overflow Flag. The Overflow flag is affected by the same instructions as the Zero and Sign flags. When set, the Overflow flag indicates that a two'scomplement number, in a result register, is in error, since it has exceeded the largest (or is less than the smallest), number that can be represented in two's-complement notation. Bit 3 = DA: Decimal Adjust Flag. The DA flag is used for BCD arithmetic. Since the algorithm for correcting BCD operations is different for addition and subtraction, this flag is used to specify which type of instruction was executed last, so that the subsequent Decimal Adjust (da) operation can perform its function correctly. The DA flag cannot normally be used as a test condition by the programmer. Bit 2 = H: Half Carry Flag. The H flag indicates a carry out of (or a borrow into) bit 3, as the result of adding or subtracting two 8-bit bytes, each representing two BCD digits. The H flag is used by the Decimal Adjust (da) instruction to convert the binary result of a previous addition or subtraction into the correct BCD result. Like the DA flag, this flag is not normally accessed by the user. Bit 1 = Reserved bit (must be 0). Bit 0 = DP: Data/Program Memory Flag. This bit indicates the memory area addressed. Its value is affected by the Set Data Memory (sdm) and Set Program Memory (spm) instructions. Refer to the Memory Management Unit for further details.
Bit 7 = C: Carry Flag. The carry flag is affected by: Addition (add, addw, adc, adcw), Subtraction (sub, subw, sbc, sbcw), Compare (cp, cpw), Shift Right Arithmetic (sra, sraw), Shift Left Arithmetic (sla, slaw), Swap Nibbles (swap), Rotate (rrc, rrcw, rlc, rlcw, ror, rol), Decimal Adjust (da), Multiply and Divide (mul, div, divws). When set, it generally indicates a carry out of the most significant bit position of the register being used as an accumulator (bit 7 for byte operations and bit 15 for word operations). The carry flag can be set by the Set Carry Flag (scf ) instruction, cleared by the Reset Carry Flag (rcf ) instruction, and complemented by the Complement Carry Flag (ccf) instruction. Bit 6 = Z: Zero Flag. The Zero flag is affected by: Addition (add, addw, adc, adcw), Subtraction (sub, subw, sbc, sbcw), Compare (cp, cpw), Shift Right Arithmetic (sra, sraw), Shift Left Arithmetic (sla, slaw), Swap Nibbles (swap), Rotate (rrc, rrcw, rlc, rlcw, ror, rol), Decimal Adjust (da), Multiply and Divide (mul, div, divws), Logical (and, andw, or, orw, xor, xorw, cpl), Increment and Decrement (inc, incw, dec,
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SYSTEM REGISTERS (Cont'd) If the bit is set, data is accessed using the Data Pointers (DPRs registers), otherwise it is pointed to by the Code Pointer (CSR register); therefore, the user initialization routine must include a Sdm instruction. Note that code is always pointed to by the Code Pointer (CSR). Note: In the current ST9 devices, the DP flag is only for compatibility with software developed for the first generation of ST9 devices. With the single memory addressing space, its use is now redundant. It must be kept to 1 with a Sdm instruction at the beginning of the program to ensure a normal use of the different memory pointers. 2.3.3 Register Pointing Techniques Two registers within the System register group, are used as pointers to the working registers. Register Pointer 0 (R232) may be used on its own as a single pointer to a 16-register working space, or in conjunction with Register Pointer 1 (R233), to point to two separate 8-register spaces. For the purpose of register pointing, the 16 register groups of the register file are subdivided into 32 8register blocks. The values specified with the Set Register Pointer instructions refer to the blocks to be pointed to in twin 8-register mode, or to the lower 8-register block location in single 16-register mode. The Set Register Pointer instructions srp, srp0 and srp1 automatically inform the CPU whether the Register File is to operate in single 16-register mode or in twin 8-register mode. The srp instruction selects the single 16-register group mode and
specifies the location of the lower 8-register block, while the srp0 and srp1 instructions automatically select the twin 8-register group mode and specify the locations of each 8-register block. There is no limitation on the order or position of these register groups, other than that they must start on an 8-register boundary in twin 8-register mode, or on a 16-register boundary in single 16register mode. The block number should always be an even number in single 16-register mode. The 16-register group will always start at the block whose number is the nearest even number equal to or lower than the block number specified in the srp instruction. Avoid using odd block numbers, since this can be confusing if twin mode is subsequently selected. Thus: srp #3 will be interpreted as srp #2 and will allow using R16 ..R31 as r0 .. r15. In single 16-register mode, the working registers are referred to as r0 to r15. In twin 8-register mode, registers r0 to r7 are in the block pointed to by RP0 (by means of the srp0 instruction), while registers r8 to r15 are in the block pointed to by RP1 (by means of the srp1 instruction). Caution: Group D registers can only be accessed as working registers using the Register Pointers, or by means of the Stack Pointers. They cannot be addressed explicitly in the form "Rxxx".
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SYSTEM REGISTERS (Cont'd) POINTER 0 REGISTER (RP0) R232 - Read/Write Register Group: E (System) Reset Value: xxxx xx00 (xxh)
7 RG4 RG3 RG2 RG1 RG0 RPS 0 0 0
POINTER 1 REGISTER (RP1) R233 - Read/Write Register Group: E (System) Reset Value: xxxx xx00 (xxh)
7 RG4 RG3 RG2 RG1 RG0 RPS 0 0 0
Bits 7:3 = RG[4:0]: Register Group number. These bits contain the number (in the range 0 to 31) of the register block specified in the srp0 or srp instructions. In single 16-register mode the number indicates the lower of the two 8-register blocks to which the 16 working registers are to be mapped, while in twin 8-register mode it indicates the 8-register block to which r0 to r7 are to be mapped. Bit 2 = RPS: Register Pointer Selector. This bit is set by the instructions srp0 and srp1 to indicate that the twin register pointing mode is selected. The bit is reset by the srp instruction to indicate that the single register pointing mode is selected. 0: Single register pointing mode 1: Twin register pointing mode Bits 1:0: Reserved. Forced by hardware to zero.
This register is only used in the twin register pointing mode. When using the single register pointing mode, or when using only one of the twin register groups, the RP1 register must be considered as RESERVED and may NOT be used as a general purpose register. Bits 7:3 = RG[4:0]: Register Group number. These bits contain the number (in the range 0 to 31) of the 8-register block specified in the srp1 instruction, to which r8 to r15 are to be mapped. Bit 2 = RPS: Register Pointer Selector. This bit is set by the srp0 and srp1 instructions to indicate that the twin register pointing mode is selected. The bit is reset by the srp instruction to indicate that the single register pointing mode is selected. 0: Single register pointing mode 1: Twin register pointing mode Bits 1:0: Reserved. Forced by hardware to zero.
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SYSTEM REGISTERS (Cont'd) Figure 9. Pointing to a single group of 16 registers
REGISTER GROUP REGISTER FI LE
Figure 10. Pointing to two groups of 8 registers
REGISTER GROUP REGISTER FI LE 31
BLOCK NUMBER
BLOCK NUMBER
31 F 30 29 E 28 points to: 27 D 26 25 25 addressed by BLOCK 7 9 9 4 8 7 7 3 6 5 5 2 4 r15 3 1 2 r0 1 0 0 addressed by BLOCK 2 1 GROUP 1 2 3 4 6 8 26 27 REGISTER POINTER 0 set by: 30 29
F
REGISTER POINTER 0 & REGISTER POINTER 1 set by:
srp #2
instruction
E 28
srp0 #2
& D
srp1 #7
instructions point to:
4 r15 GROUP 3 3 r8
2
1
r7 r0 GROUP 1 addressed by BLOCK 2
0 0
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SYSTEM REGISTERS (Cont'd) 2.3.4 Paged Registers Up to 64 pages, each containing 16 registers, may be mapped to Group F. These paged registers hold data and control information relating to the on-chip peripherals, each peripheral always being associated with the same pages and registers to ensure code compatibility between ST9 devices. The number of these registers depends on the peripherals present in the specific ST9 device. In other words, pages only exist if the relevant peripheral is present. The paged registers are addressed using the normal register addressing modes, in conjunction with the Page Pointer register, R234, which is one of the System registers. This register selects the page to be mapped to Group F and, once set, does not need to be changed if two or more registers on the same page are to be addressed in succession. Thus the instructions: spp #5 ld R242, r4 will load the contents of working register r4 into the third register of page 5 (R242). Warning: During an interrupt, the PPR register is not saved automatically in the stack. If needed, it should be saved/restored by the user within the interrupt routine. PAGE POINTER REGISTER (PPR) R234 - Read/Write Register Group: E (System) Reset value: xxxx xx00 (xxh)
7 PP5 PP4 PP3 PP2 PP1 PP0 0 0 0
Management of the clock frequency, Enabling of Bus request and Wait signals when interfacing to external memory. MODE REGISTER (MODER) R235 - Read/Write Register Group: E (System) Reset value: 1110 0000 (E0h)
7
SSP USP DIV2 PRS2 PRS1
0
PRS0 BRQEN HIMP
Bit 7 = SSP: System Stack Pointer. This bit selects an internal or external System Stack area. 0: External system stack area, in memory space. 1: Internal system stack area, in the Register File (reset state). Bit 6 = USP: User Stack Pointer. This bit selects an internal or external User Stack area. 0: External user stack area, in memory space. 1: Internal user stack area, in the Register File (reset state). Bit 5 = DIV2: OSCIN Clock Divided by 2. This bit controls the divide-by-2 circuit operating on OSCIN. 0: Clock divided by 1 1: Clock divided by 2 Bits 4:2 = PRS[2:0]: CPUCLK Prescaler. These bits load the prescaler division factor for the internal clock (INTCLK). The prescaler factor selects the internal clock frequency, which can be divided by a factor from 1 to 8. Refer to the Reset and Clock Control chapter for further information. Bit 1 = BRQEN: Bus Request Enable. 0: External Memory Bus Request disabled 1: External Memory Bus Request enabled on BREQ pin (where available). Note: Disregard this bit if BREQ pin is not available. Bit 0 = HIMP: High Impedance Enable. When any of Ports 0, 1, 2 or 6 depending on device configuration, are programmed as Address and Data lines to interface external Memory, these lines and the Memory interface control lines (AS, DS, R/W) can be forced into the High Impedance
Bits 7:2 = PP[5:0]: Page Pointer. These bits contain the number (in the range 0 to 63) of the page specified in the spp instruction. Once the page pointer has been set, there is no need to refresh it unless a different page is required. Bits 1:0: Reserved. Forced by hardware to 0. 2.3.5 Mode Register The Mode Register allows control of the following operating parameters: Selection of internal or external System and User Stack areas,
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SYSTEM REGISTERS (Cont'd) state by setting the HIMP bit. When this bit is reset, it has no effect. Setting the HIMP bit is recommended for noise reduction when only internal Memory is used. If Port 1 and/or 2 are declared as an address AND as an I/O port (for example: P10... P14 = Address, and P15... P17 = I/O), the HIMP bit has no effect on the I/O lines. 2.3.6 Stack Pointers Two separate, double-register stack pointers are available: the System Stack Pointer and the User Stack Pointer, both of which can address registers or memory. The stack pointers point to the "bottom" of the stacks which are filled using the push commands and emptied using the pop commands. The stack pointer is automatically pre-decremented when data is "pushed" in and post-incremented when data is "popped" out. The push and pop commands used to manage the System Stack may be addressed to the User Stack by adding the suffix "u". To use a stack instruction for a word, the suffix "w" is added. These suffixes may be combined. When bytes (or words) are "popped" out from a stack, the contents of the stack locations are unchanged until fresh data is loaded. Thus, when data is "popped" from a stack area, the stack contents remain unchanged. Note: Instructions such as: pushuw RR236 or pushw RR238, as well as the corresponding pop instructions (where R236 & R237, and R238 & R239 are themselves the user and system stack pointers respectively), must not be used, since the pointer values are themselves automatically changed by the push or pop instruction, thus corrupting their value. System Stack The System Stack is used for the temporary storage of system and/or control data, such as the Flag register and the Program counter. The following automatically push data onto the System Stack: Interrupts When entering an interrupt, the PC and the Flag Register are pushed onto the System Stack. If the ENC SR bit in the EMR2 register is set, then the
Code Segment Register is also pushed onto the System Stack. Subroutine Calls When a call instruction is executed, only the PC is pushed onto stack, whereas when a calls instruction (call segment) is executed, both the PC and the Code Segment Register are pushed onto the System Stack. Link Instruction The link or linku instructions create a C language stack frame of user-defined length in the System or User Stack. All of the above conditions are associated with their counterparts, such as return instructions, which pop the stored data items off the stack. User Stack The User Stack provides a totally user-controlled stacking area. The User Stack Pointer consists of two registers, R236 and R237, which are both used for addressing a stack in memory. When stacking in the Register File, the User Stack Pointer High Register, R236, becomes redundant but must be considered as reserved. Stack Pointers Both System and User stacks are pointed to by double-byte stack pointers. Stacks may be set up in RAM or in the Register File. Only the lower byte will be required if the stack is in the Register File. The upper byte must then be considered as reserved and must not be used as a general purpose register. The stack pointer registers are located in the System Group of the Register File, this is illustrated in Table 4. Stack Location Care is necessary when managing stacks as there is no limit to stack sizes apart from the bottom of any address space in which the stack is placed. Consequently programmers are advised to use a stack pointer value as high as possible, particularly when using the Register File as a stacking area. Group D is a good location for a stack in the Register File, since it is the highest available area. The stacks may be located anywhere in the first 14 groups of the Register File (internal stacks) or in RAM (external stacks). Note. Stacks must not be located in the Paged Register Group or in the System Register Group.
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SYSTEM REGISTERS (Cont'd) USER STACK POINTER HIGH REGISTER (USPHR) R236 - Read/Write Register Group: E (System) Reset value: undefined
7 USP15 USP14 USP13 USP12 USP11 USP10 USP9 0 USP8
SYSTEM STACK POINTER HIGH REGISTER (SSPHR) R238 - Read/Write Register Group: E (System) Reset value: undefined
7 SSP15 SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 0 SSP8
USER STACK POINTER LOW REGISTER (USPLR) R237 - Read/Write Register Group: E (System) Reset value: undefined
7 USP7 USP6 USP5 USP4 U SP3 USP2 USP1 0 USP0
SYSTEM STACK POINTER LOW REGISTER (SSPLR) R239 - Read/Write Register Group: E (System) Reset value: undefined
7 SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 0 SSP0
Figure 11. Internal Stack Mode
Figure 12. External Stack Mode
REGISTER FI LE STACK POINTER (LOW) F points to: F
REGISTER FI LE
STACK POINTER (LOW) & STACK POINTER (HIGH) point to: MEMORY
E STACK D
E
D
STACK 4 4
3
3
2
2
1
1
0
0
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2.4 MEMORY ORGANIZATION Code and data are accessed within the same linear address space. All of the physically separate memory areas, including the internal ROM, internal RAM and external memory are mapped in a common address space. The ST9 provides a total addressable memory space of 4 Mbytes. This address space is arranged as 64 segments of 64 Kbytes; each segment is again subdivided into four 16 Kbyte pages. The mapping of the various memory areas (internal RAM or ROM, external memory) differs from device to device. Each 64-Kbyte physical memory segment is mapped either internally or externally; if the memory is internal and smaller than 64 Kbytes, the remaining locations in the 64-Kbyte segment are not used (reserved). Refer to the Register and Memory Map Chapter for more details on the memory map.
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2.5 MEMORY MANAGEMENT UNIT The CPU Core includes a Memory Management Unit (MMU) which must be programmed to perform memory accesses (even if external memory is not used). The MMU is controlled by 7 registers and 2 bits (ENCSR and DPRREM) present in EMR2, which may be written and read by the user program. These registers are mapped within group F, Page 21 of the Register File. The 7 registers may be Figure 13. Page 21 Registers sub-divided into 2 main groups: a first group of four 8-bit registers (DPR[3:0]), and a second group of three 6-bit registers (CSR, ISR, and DMASR). The first group is used to extend the address during Data Memory access (DPR[3:0]). The second is used to manage Program and Data Memory accesses during Code execution (CSR), Interrupts Service Routines (ISR or CSR), and DMA transfers (DMASR or ISR).
Page 21 FFh FEh FDh FCh FBh FAh F9h F8h F7h F6h F5h F4h F3h F2h F1h F0h EMR2 EMR1 CSR DPR3 DPR2 DPR1 DPR0 DMASR ISR R255 R254 R253 R252 R251 R250 R249 R248 R247 R246 R245 R244 R243 R242 R241 R240 MMU EM MMU MMU SSPLR SSPHR USPLR USPHR MODER PPR RP1 RP0 FLAGR CICR P5DR P4DR P3DR P2DR P1DR P0DR SSPLR SSPHR USPLR USPHR MODER PPR RP1 RP0 FLAGR CICR P5DR P4DR DPR3 DPR2 DPR1 DPR0
Relocation of P[3:0] and DPR[3:0] Registers
DMASR ISR EMR2 EMR1 CSR DPR3 DPR2 1 DPR0
DMASR ISR EMR2 EMR1 CSR P3DR P2DR P1DR P0DR
Bit DPRREM=0 (default setting)
Bit DPRREM=1
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2.6 ADDRESS SPACE EXTENSION To manage 4 Mbytes of addressing space, it is necessary to have 22 address bits. The MMU adds 6 bits to the usual 16-bit address, thus translating a 16-bit virtual address into a 22-bit physical address. There are 2 different ways to do this depending on the memory involved and on the operation being performed. 2.6.1 Addressing 16-Kbyte Pages This extension mode is implicitly used to address Data memory space if no DMA is being performed. The Data memory space is divided into 4 pages of 16 Kbytes. Each one of the four 8-bit registers (DPR[3:0], Data Page Registers) selects a different 16-Kbyte page. The DPR registers allow access to the entire memory space which contains 256 pages of 16 Kbytes. Data paging is performed by extending the 14 LSB of the 16-bit address with the contents of a DPR register. The two MSBs of the 16-bit address are interpreted as the identification number of the DPR register to be used. Therefore, the DPR registers Figure 14. Addressing via DPR[3:0] are involved in the following virtual address ranges : D PR0: from 0000h to 3FFFh; D PR1: from 4000h to 7FFFh; D PR2: from 8000h to BFFFh; D PR3: from C000h to FFFFh. The contents of the selected DPR register specify one of the 256 possible data memory pages. This 8-bit data page number, in addition to the remaining 14-bit page offset address forms the physical 22-bit address (see Figure 14). A DPR register cannot be modified via an addressing mode that uses the same DPR register. For instance, the instruction "POPW DPR0" is legal only if the stack is kept either in the register file or in a memory location above 8000h, where DPR2 and DPR3 are used. Otherwise, since DPR0 and DPR1 are modified by the instruction, unpredictable behaviour could result.
MMU registers DPR0 DPR1 DPR2 DPR3
16-bit virtual address
00
01
10
11
2M
SB
8 bits
14 LSB
22-bit physical address
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ADDRESS SPACE EXTENSION (Cont'd) 2.6.2 Addressing 64-Kbyte Segments This extension mode is used to address Data memory space during a DMA and Program memory space during any code execution (normal code and interrupt routines). Three registers are used: CSR, ISR, and DMASR. The 6-bit contents of one of the registers CSR, ISR, or DMASR define one out of 64 Memory segments of 64 Kbytes within the 4 Mbytes address space. The register contents represent the 6 MSBs of the memory address, whereas the 16 LSBs of the address (intra-segment address) are given by the virtual 16-bit address (see Figure 15). 2.7 MMU REGISTERS The MMU uses 7 registers mapped into Group F, Page 21 of the Register File and 2 bits of the EMR2 register.
Most of these registers do not have a default value after reset. 2.7.1 DPR[3:0]: Data Page Registers The DPR[3:0] registers allow access to the entire 4 Mbyte memory space composed of 256 pages of 16 Kbytes. 2.7.1.1 Data Page Register Relocation If these registers are to be used frequently, they may be relocated in register group E, by programming bit 5 of the EMR2-R246 register in page 21. If this bit is set, the DPR[3:0] registers are located at R224-227 in place of the Port 0-3 Data Registers, which are re-mapped to the default DPR's locations: R240-243 page 21. Data Page Register relocation is illustrated in Figure 13.
Figure 15. Addressing via CSR, ISR, and DMASR
MMU registers CSR DMASR ISR
16-bit virtual address
1 1 2 Fetching program instruction Data Memory accessed in DMA Fetching interrupt instruction or DMA access to Program Memory
2
3
6 bits
3
22-bit physical address
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MMU REGISTERS (Cont'd) DATA PAGE REGISTER 0 (DPR0) R240 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R224 if EMR2.5 is set.
7 0
DATA PAGE REGISTER 2 (DPR2) R242 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R226 if EMR2.5 is set.
7 0
DPR0_7 DPR0_6 DPR0_5 DPR0_4 DPR0_3 DPR0_2 DPR0_1 DPR0_0
DPR2_7 DP R2_6 DPR2_5 DPR2_4 DPR2_3 DPR2_2 DPR2_1 DPR2_0
Bits 7:0 = DPR0_[7:0]: These bits define the 16Kbyte Data Memory page number. They are used as the most significant address bits (A21-14) to extend the address during a Data Memory access. The DPR0 register is used when addressing the virtual address range 0000h-3FFFh. DATA PAGE REGISTER 1 (DPR1) R241 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R225 if EMR2.5 is set.
7 0
Bits 7:0 = DPR2_[7:0]: These bits define the 16Kbyte Data memory page. They are used as the most significant address bits (A21-14) to extend the address during a Data memory access. The DPR2 register is involved when the virtual address is in the range 8000h-BFFFh. DATA PAGE REGISTER 3 (DPR3) R243 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R227 if EMR2.5 is set.
7 0
DPR1_7 DPR1_6 DPR1_5 DPR1_4 DPR1_3 DPR1_2 DPR1_1 DPR1_0
DPR3_7 DP R3_6 DPR3_5 DPR3_4 DPR3_3 DPR3_2 DPR3_1 DPR3_0
Bits 7:0 = DPR1_[7:0]: These bits define the 16Kbyte Data Memory page number. They are used as the most significant address bits (A21-14) to extend the address during a Data Memory access. The DPR1 register is used when addressing the virtual address range 4000h-7FFFh.
Bits 7:0 = DPR3_[7:0]: These bits define the 16Kbyte Data memory page. They are used as the most significant address bits (A21-14) to extend the address during a Data memory access. The DPR3 register is involved when the virtual address is in the range C000h-FFFFh.
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MMU REGISTERS (Cont'd) 2.7.2 CSR: Code Segment Register This register selects the 64-Kbyte code segment being used at run-time to access instructions. It can also be used to access data if the spm instruction has been executed (or ldpp, ldpd, lddp). Only the 6 LSBs of the CSR register are implemented, and bits 6 and 7 are reserved. The CSR register allows access to the entire memory space, divided into 64 segments of 64 Kbytes. To generate the 22-bit Program memory address, the contents of the CSR register is directly used as the 6 MSBs, and the 16-bit virtual address as the 16 LSBs. Note: The CSR register should only be read and not written for data operations (there are some exceptions which are documented in the following paragraph). It is, however, modified either directly by means of the jps and calls instructions, or indirectly via the stack, by means of the rets instruction. CODE SEGMENT REGISTER (CSR) R244 - Read/Write Register Page: 21 Reset value: 0000 0000 (00h)
7 0 0 CSR_5 CSR_4 CSR_3 CSR_2 CSR_1 0 CSR_0
ISR and ENCSR bit (EMR2 register) are also described in the chapter relating to Interrupts, please refer to this description for further details. Bits 7:6 = Reserved, keep in reset state. Bits 5:0 = ISR_[5:0]: These bits define the 64Kbyte memory segment (among 64) which contains the interrupt vector table and the code for interrupt service routines and DMA transfers (when the PS bit of the DAPR register is reset). These bits are used as the most significant address bits (A21-16). The ISR is used to extend the address space in two cases: Whenever an interrupt occurs: ISR points to the 64-Kbyte memory segment containing the interrupt vector table and the interrupt service routine code. See also the Interrupts chapter. During DMA transactions between the peripheral and memory when the PS bit of the DAPR register is reset : ISR points to the 64 K-byte Memory segment that will be involved in the DMA transaction. 2.7.4 DMASR: DMA Segment Register DMA SEGMENT REGISTER (DMASR) R249 - Read/Write Register Page: 21 Reset value: undefined
7 D MA SR_5 DMA SR_4 DMA SR_3 D MA SR_2 DMA SR_1 0 D MA SR_0
Bits 7:6 = Reserved, keep in reset state. Bits 5:0 = CSR_[5:0]: These bits define the 64Kbyte memory segment (among 64) which contains the code being executed. These bits are used as the most significant address bits (A21-16). 2.7.3 ISR: Interrupt Segment Register INTERRUPT SEGMENT REGISTER (ISR) R248 - Read/Write Register Page: 21 Reset value: undefined
7 0 0 0 ISR_5 ISR_4 ISR_3 ISR_2 ISR_1 ISR_0
0
0
Bits 7:6 = Reserved, keep in reset state. Bits 5:0 = DMASR_[5:0]: These bits define the 64Kbyte Memory segment (among 64) used when a DMA transaction is performed between the peripheral's data register and Memory, with the PS bit of the DAPR register set. These bits are used as the most significant address bits (A21-16). If the PS bit is reset, the ISR register is used to extend the addres s .
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MMU REGISTERS (Cont'd) Figure 16. Memory Addressing Scheme (example)
4M bytes
3FFFFFh
16K
294000h
DPR3 DPR2 DPR1 DPR0 16K 16K 20C000h 20 0 0h 1FFFFFh 240000h 23FFFFh
64K DMASR
040000h 03FFFFh 030000h 020000h
ISR CSR
64K 16K 64K
010000h 00C000h 0 0 00h
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2.8 MMU USAGE 2.8.1 Normal Program Execution Program memory is organized as a set of 64Kbyte segments. The program can span as many segments as needed, but a procedure cannot stretch across segment boundaries. jps, calls and rets instructions, which automatically modify the CSR, must be used to jump across segment boundaries. Writing to the CSR is forbidden during normal program execution because it is not synchronized with the opcode fetch. This could result in fetching the first byte of an instruction from one memory segment and the second byte from another. Writing to the CSR is allowed when it is not being used, i.e during an interrupt service routine if ENC SR is reset. Note that a routine must always be called in the same way, i.e. either always with call or always with calls, depending on whether the routine ends with ret or rets. This means that if the routine is written without prior knowledge of the location of other routines which call it, and all the program code does not fit into a single 64-Kbyte segment, then calls/rets should be used. In typical microcontroller applications, less than 64 Kbytes of RAM are used, so the four Data space pages are normally sufficient, and no change of DPR [3:0] is needed during Program execution. It may be useful however to map part of the ROM into the data space if it contains strings, tables, bit maps, etc. If there is to be frequent use of paging, the user can set bit 5 (DPRREM) in register R246 (EMR2) of Page 21. This swaps the location of registers DPR [3:0] with that of the data registers of Ports 03. In this way, DPR registers can be accessed without the need to save/set/restore the Page Pointer Register. Port registers are therefore moved to page 21. Applications that require a lot of paging typically use more than 64 Kbytes of external memory, and as ports 0, 1 and 2 are required to address it, their data registers are unused. 2.8.2 Interrupts The ISR register has been created so that the interrupt routines may be found by means of the same vector table even after a segment jump/call. When an interrupt occurs, the CPU behaves in one of 2 ways, depending on the value of the ENCSR bit in the EMR2 register (R246 on Page 21). If this bit is reset (default condition), the CPU works in original ST9 compatibility mode. For the duration of the interrupt service routine, the ISR is used instead of the CSR, and the interrupt stack frame is kept exactly as in the original ST9 (only the PC and flags are pushed). This avoids the need to save the CSR on the stack in the case of an interrupt, ensuring a fast interrupt response time. The drawback is that it is not possible for an interrupt service routine to perform segment calls/jps : these instructions would update the CSR, which, in this case, is not used (ISR is used instead). The code size of all interrupt service routines is thus limited to 64 Kbytes. If, instead, bit 6 of the EMR2 register is set, the ISR is used only to point to the interrupt vector table and to initialize the CSR at the beginning of the interrupt service routine: the old CSR is pushed onto the stack together with the PC and the flags, and then the CSR is loaded with the ISR. In this case, an iret will also restore the CSR from the stack. This approach lets interrupt service routines access the whole 4-Mbyte address space. The drawback is that the interrupt response time is slightly increased, because of the need to also save the CSR on the stack. Compatibility with the original ST9 is also lost in this case, because the interrupt stack frame is different; this difference, however, would not be noticeable for a vast majority of programs. Data memory mapping is independent of the value of bit 6 of the EMR2 register, and remains the same as for normal code execution: the stack is the same as that used by the main program, as in the ST9. If the interrupt service routine needs to access additional Data memory, it must save one (or more) of the DPRs, load it with the needed memory page and restore it before completion. 2.8.3 DMA Depending on the PS bit in the DAPR register (see DMA chapter) DMA uses either the ISR or the DMASR for memory accesses: this guarantees that a DMA will always find its memory segment(s), no matter what segment changes the application has performed. Unlike interrupts, DMA transactions cannot save/restore paging registers, so a dedicated segment register (DMASR) has been created. Having only one register of this kind means that all DMA accesses should be programmed in one of the two following segments: the one pointed to by the ISR (when the PS bit of the DAPR register is reset), and the one referenced by the DMASR (when the PS bit is set).
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3 REGISTER AND MEMORY MAP
3.1 MEMORY CONFIGURATION The Program memory space of the ST90135/158, 0/24/32/48/64/K bytes of directly addressable onchip memory, is fully available to the user. The first 256 memory locations from address 0 to FFh hold the Reset Vector, the Top-Level (Pseudo Non-Maskable) interrupt, the Divide by Zero Trap Routine vector and, optionally, the interrupt vector table for use with the on-chip peripherals and the external interrupt sources. Apart from this case no other part of the Program memory has a predetermined function except segment 21h which is reserved for use by STMicroelectronics. 3.2 EPROM PROGRAMMING The 65536 bytes of EPROM memory of the ST90E158 may be programmed by using the EPROM Programming Boards (EPB) available from STMicroelectronics or gang programmers available from third party. EPROM Erasing The EPROM of the windowed package of the ST90E158 may be erased by exposure to Ultra-Violet light. The erasure characteristic of the ST90E158 is such that erasure begins when the memory is exposed to light with a wave lengths shorter than approximately 4000Å. It should be noted that sunlight and some types of fluorescent lamps have wavelengths in the range 3000-4000Å. It is thus recommended that the window of the ST90E158 packages be covered by an opaque label to prevent unintentional erasure problems when testing the application in such an environment. The recommended erasure procedure of the EPROM is the exposure to short wave ultraviolet light which have a wave-length 2537Å. The integrated dose (i.e. U.V. intensity x exposure time) for erasure should be a minimum of 15W-sec/cm2. The erasure time with this dosage is approximately 30 minutes using an ultraviolet lamp with 12000mW /cm2 power rating. The ST90E158 should be placed within 2.5cm (1 inch) of the lamp tubes during erasure. Table 5. First 6 Bytes of Program Space
0 1 2 3 4 5 Address Address Address Address Address Address high of Power on Reset routine low of Power on Reset routine high of Divide by zero trap Subroutine low of Divide by zero trap Subroutine high of Top Level Interrupt routine low of Top Level Interrupt routine
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Figure 17. Interrupt Vector Table
REGISTER FILE F PAGE REGISTERS PROGRAM MEMORY USER ISR USER DIVIDE-BY-ZERO ISR USER MAIN PROGRAM INT . VECTOR REGISTER USER TOP LEVEL ISR R240 R239
0000F Fh ODD EVEN LO HI LO 0 0 04h HI LO 0 0 02h HI LO 0 0 00h HI TOP LEVEL INT. DIVIDE-BY-ZERO POWER-ON RESET ISR ADDRESS VECTOR TABLE
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3.3 MEMORY MAP Figure 18. Memory Map
3FFFFFh
External Memory
Upper Memory (usually RAM mapped in Segment 23h)
230000h 22FFFFh
Reserved
SEGMENTS 21h and 22h 128 Kbytes
Internal RAM 768 bytes 1 Kbytes 1.5 Kbytes 2 Kbytes
20FFFFh
210000h 20FFFFh
PAGE 83 - 16 Kbytes
20C000h 20BFFFh
PAGE 82 - 16 Kbytes
20FD00h 20FC00h 20FA00h 208000h 207FFFh
SEGMENT 20h 64 Kbytes
PAGE 81 - 16 Kbytes
204000h 203FFFh
PAGE 80 - 16 Kbytes
20 0 0h 1FFFFFh
20F800h
External Memory
Lower Memory (usually ROM/EPROM mapped in Segment 1)
010000h 00FFFFh
64 Kbytes 48 Kbytes 32 Kbytes
00FFFFh 00BFFFh 007FFFh 00FFFFh
PAGE 3 - 16 Kbytes
00C000h 00BFFFh
Internal ROM 24 Kbytes
Internal ROM/EPROM (external ROM on ROMless devices)
PAGE 2 - 16 Kbytes
008000h 007FFFh
SEGMENT 0 64 Kbytes
PAGE 1 - 16 Kbytes
004000h 003FFFh
0 0 00h
PAGE 0 - 16 Kbytes
0 0 00h
Note: The total amount of directly addressable external memory is 64 Kbytes.
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3.4 ST90158/135 REGISTER MAP The following pages contain a list of ST90158/135 registers, grouped by peripheral or function. Be very careful to correctly program both: The set of registers dedicated to a particular function or peripheral. Registers common to other functions. In particular, double-check that any registers with "undefined" reset values have been correctly initialised. Warning: Note that in the EIVR and each IVR register, all bits are significant. Take care when defining base vector addresses that entries in the Interrupt Vector table do not overlap.
Table 6. Common Registers
Function or Peripheral SCI, MFT ADC SPI, WDT, STIM I/O PORTS EXTERNAL INTERRUPT RCCU Common Registers CICR + NICR + DMA REGISTERS + I/O PORT REGISTERS CICR + NICR + I/O PORT REGISTERS CICR + NICR + EXTERNAL INTERRUPT REGISTERS + I/O PORT REGISTERS I/O PORT REGISTERS + MODER INTERRUPT REGISTERS + I/O PORT REGISTERS INTERRUPT REGISTERS + MODER
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Table 7. Group F Pages Resources available on the ST90158/ST90135 devices:
Register 0 R255 R254 SPI R253 R252 R251 R250 WDT R249 R248 MFT1 R247 R246 R245 R244 R243 R242 R241 R240 MR Res. PORT PORT 0 4 PORT PORT 1 5 MFT1 MFT3 Res. Res. PORT 2 WCR Res. Res. 2 3 8 9 10 11 Page 12 13 21 24 25 43 55 63
PORT 7 Res. Res. Res.
PORT 9
Res.
PORT 6
Res. MMU MFT MFT0 (*) MFT3 Res. EXT MI SCI0 SCI1 (*)
PORT 8
A/D
RCCU
EXT INT
Res. Res. Res. Res. MMU STIM Res. Res. RCCU RCCU
MFT0 (*)
(*) ST90158/ST90E158 only. Not present on ST90135.
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Table 8. Detailed Register Map
Page (Decimal) Block Reg. No. R230 R231 R232 R233 Core R234 R235 R236 N /A R237 R238 R239 R224 I/O Port 5:4,2:0 MR R225 R226 R228 R229 R241 R242 R243 INT R244 R245 R246 0 R247 R248 R249 WDT R250 R251 R252 SPI I/O Port 0 I/O 2 Port 1 I/O Port 2 R253 R254 R240 R241 R242 R244 R245 R246 R248 R249 R250 Register Name CICR FLAGR RP0 RP1 PPR MODER USPHR USPLR SSPHR SSPLR P0DR P1DR P2DR P4DR P5DR MIRROR EITR EIPR EIMR EIPLR EIVR NICR WDTHR WDTLR WDTPR WDTCR WCR SPIDR SPICR P0C0 P0C1 P0C2 P1C0 P1C1 P1C2 P2C0 P2C1 P2C2 Description Central Interrupt Control Register Flag Register Pointer 0 Register Pointer 1 Register Page Pointer Register Mode Register User Stack Pointer High Register User Stack Pointer Low Register System Stack Pointer High Reg. System Stack Pointer Low Reg. Port 0 Data Register Port 1 Data Register Port 2 Data Register Port 4 Data Register Port 5 Data Register Mirror register External Interrupt Trigger Register External Interrupt Pending Reg. External Interrupt Mask-bit Reg. External Interrupt Priority Level Reg. External Interrupt Vector Register Nested Interrupt Control Watchdog Timer High Register Watchdog Timer Low Register Watchdog Timer Prescaler Reg. Watchdog Timer Control Register Wait Control Register SPI Data Register SPI Control Register Port 0 Configuration Register 0 Port 0 Configuration Register 1 Port 0 Configuration Register 2 Port 1 Configuration Register 0 Port 1 Configuration Register 1 Port 1 Configuration Register 2 Port 2 Configuration Register 0 Port 2 Configuration Register 1 Port 2 Configuration Register 2 Reset Value Hex. 87 00 xx xx xx E0 xx xx xx xx FF FF FF FF FF 00 00 00 00 FF x6 00 FF FF FF 12 7F xx 00 00 00 00 00 00 00 FF 00 00
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Page (Decimal)
Block I/O Port 4 I/O Port 5
Reg. No. R240 R241 R242 R244 R245 R246 R248 R249 R250 R251 R252 R253 R254 R255
Register Name P4C0 P4C1 P4C2 P5C0 P5C1 P5C2 P6C0 P6C1 P6C2 P6DR P7C0 P7C1 P7C2 P7DR
Description Port 4 Configuration Register 0 Port 4 Configuration Register 1 Port 4 Configuration Register 2 Port 5 Configuration Register 0 Port 5 Configuration Register 1 Port 5 Configuration Register 2 Port 6 Configuration Register 0 Port 6 Configuration Register 1 Port 6 Configuration Register 2 Port 6 Data Register Port 7 Configuration Register 0 Port 7 Configuration Register 1 Port 7 Configuration Register 2 Port 7 Data Register
Reset Value Hex. FF 00 00 FF 00 00 FF 00 00 FF 00/FF 00/00 00/00 FF
3
I/O Port 6 I/O Port 7
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Page (Decimal)
Block
Reg. No. R240 R241 R242 R243 R244 R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 R255 R244 R245 R246 R247
Register Name REG0HR1 REG0LR1 REG1HR1 REG1LR1 CMP0HR1 CMP0LR1 CMP1HR1 CMP1LR1 TCR1 TMR1 ICR1 PRSR1 OACR1 OBCR1 FLAGR1 IDMR1 DCPR0 DAPR0 IVR0 IDCR0 IOCR DCPR1 DAPR1 IVR1 IDCR1 REG0HR0 REG0LR0 REG1HR0 REG1LR0 CMP0HR0 CMP0LR0 CMP1HR0 CMP1LR0 TCR0 TMR0 ICR0 PRSR0 OACR0 OBCR0 FLAGR0 IDMR0
Description Capture Load Register 0 High Capture Load Register 0 Low Capture Load Register 1 High Capture Load Register 1 Low Compare 0 Register High Compare 0 Register Low Compare 1 Register High Compare 1 Register Low Timer Control Register Timer Mode Register External Input Control Register Prescaler Register Output A Control Register Output B Control Register Flags Register Interrupt/DMA Mask Register DMA Counter Pointer Register DMA Address Pointer Register Interrupt Vector Register Interrupt/DMA Control Register I/O Connection Register DMA Counter Pointer Register DMA Address Pointer Register Interrupt Vector Register Interrupt/DMA Control Register Capture Load Register 0 High Capture Load Register 0 Low Capture Load Register 1 High Capture Load Register 1 Low Compare 0 Register High Compare 0 Register Low Compare 1 Register High Compare 1 Register Low Timer Control Register Timer Mode Register External Input Control Register Prescaler Register Output A Control Register Output B Control Register Flags Register Interrupt/DMA Mask Register
Reset Value Hex. xx xx xx xx 00 00 00 00 0x 00 0x 00 xx xx 00 00 xx xx xx C7 FC xx xx xx C7 xx xx xx xx 00 00 00 00 0x 00 0x 00 xx xx 00 00
8 MFT1
9
MFT0,1
R248 R240 R241 R242 R243 R240 R241 R242 R243 R244
MFT0 (*) 10
R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 R255
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Page (Decimal)
Block
Reg. No. R240
Register Name STH STL STP STC REG0HR1 REG0LR1 REG1HR1 REG1LR1 CMP0HR1 CMP0LR1 CMP1HR1 CMP1LR1 TCR1 TMR1 ICR1 PRSR1 OACR1 OBCR1 FLAGR1 IDMR1 DCPR0 DAPR0 IVR0 IDCR0 DPR0 DPR1 DPR2 DPR3 CSR ISR DMASR EMR1 EMR2
Description Counter High Byte Register Counter Low Byte Register Standard Timer Prescaler Register Standard Timer Control Register Capture Load Register 0 High Capture Load Register 0 Low Capture Load Register 1 High Capture Load Register 1 Low Compare 0 Register High Compare 0 Register Low Compare 1 Register High Compare 1 Register Low Timer Control Register Timer Mode Register External Input Control Register Prescaler Register Output A Control Register Output B Control Register Flags Register Interrupt/DMA Mask Register DMA Counter Pointer Register DMA Address Pointer Register Interrupt Vector Register Interrupt/DMA Control Register Data Page Register 0 Data Page Register 1 Data Page Register 2 Data Page Register 3 Code Segment Register Interrupt Segment Register DMA Segment Register External Memory Register 1 External Memory Register 2
Reset Value Hex. FF FF FF 14 xx xx xx xx 00 00 00 00 0x 00 0x 00 xx xx 00 00 xx xx xx C7 xx xx xx xx 00 xx xx 80 0F
11
STIM
R241 R242 R243 R240 R241 R242 R243 R244 R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 R255 R244 R245 R246 R247 R240 R241 R242
12 MFT3
13
MMU 21
R243 R244 R248 R249 R245 R246
EXTMI
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Page (Decimal)
Block
Reg. No. R240 R241 R242 R243 R244 R245 R246 R247
Register Name RDCPR0 RDAPR0 TDCPR0 TDAPR0 IVR0 ACR0 IMR0 ISR0 RXBR0 TXBR0 IDPR0 CHCR0 CCR0 BRGHR0 BRGLR0 SICR0 SOCR0 RDCPR1 RDAPR1 TDCPR1 TDAPR1 IVR1 ACR1 IMR1 ISR1 RXBR1 TXBR1 IDPR1 CHCR1 CCR1 BRGHR1 BRGLR1 SICR1 SOCR1 P8C0 P8C1 P8C2 P8DR P9C0 P9C1 P9C2 P9DR
Description Receiver DMA Transaction Counter Pointer Receiver DMA Source Address Pointer Transmitter DMA Transaction Counter Pointer Transmitter DMA Destination Address Pointer Interrupt Vector Register Address/Data Compare Register Interrupt Mask Register Interrupt Status Register Receive Buffer Register Transmitter Buffer Register Interrupt/DMA Priority Register Character Configuration Register Clock Configuration Register Baud Rate Generator High Reg. Baud Rate Generator Low Register Synchronous Input Control Synchronous Output Control Receiver DMA Transaction Counter Pointer Receiver DMA Source Address Pointer Transmitter DMA Transaction Counter Pointer Transmitter DMA Destination Address Pointer Interrupt Vector Register Address/Data Compare Register Interrupt Mask Register Interrupt Status Register Receive Buffer Register Transmitter Buffer Register Interrupt/DMA Priority Register Character Configuration Register Clock Configuration Register Baud Rate Generator High Reg. Baud Rate Generator Low Register Synchronous Input Control Synchronous Output Control Port 8 Configuration Register 0 Port 8 Configuration Register 1 Port 8 Configuration Register 2 Port 8 Data Register Port 9 Configuration Register 0 Port 9 Configuration Register 1 Port 9 Configuration Register 2 Port 9 Data Register
Reset Value Hex. xx xx xx xx xx xx x0 xx xx xx xx xx 00 xx xx 03 01 xx xx xx xx xx xx x0 xx xx xx xx xx 00 xx xx 03 01 00/03 00/00 00/00 FF 00/00 00/00 00/00 FF
24
SCI0
R248 R248 R249 R250 R251 R252 R253 R254 R255 R240 R241 R242 R243 R244 R245 R246 R247 R248 R248 R249 R250 R251 R252 R253 R254 R255 R248 R249 R250 R251 R252 R253 R254 R255
25
SCI1 (*)
I/O Port 8 43 I/O Port 9
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Page (Decimal)
Block
Reg. No. R240
Register Name CLKCTL CLK_FLAG PLLCONF D0R0 D1R0 D2R0 D3R0 D4R0 D5R0 D6R0 D7R0 LT6R0 LT7R0 UT6R0 UT7R0 CRR0 CLR0 ICR0 IVR0
Description Clock Control Register Clock Flag Register PLL Configuration Register Channel 0 Data Register Channel 1 Data Register Channel 2 Data Register Channel 3 Data Register Channel 4 Data Register Channel 5 Data Register Channel 6 Data Register Channel 7 Data Register Channel 6 Lower Threshold Reg. Channel 7 Lower Threshold Reg. Channel 6 Upper Threshold Reg. Channel 7 Upper Threshold Reg. Compare Result Register Control Logic Register Interrupt Control Register Interrupt Vector Register
Reset Value Hex. 00 48, 28 or 08 xx xx xx xx xx xx xx xx xx xx xx xx xx 0F 00 0F x2
55
RCCU
R242 R246 R240 R241 R242 R243 R244 R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 R255
63
AD0
(*) Not present on ST90135. Note: xx denotes a byte with an undefined value, however some of the bits may have defined values. Refer to register description for details.
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4 INTERRUPTS
4.1 INTRODUCTION The ST9 responds to peripheral and external events through its interrupt channels. Current program execution can be suspended to allow the ST9 to execute a specific response routine when such an event occurs, providing that interrupts have been enabled, and according to a priority mechanism. If an event generates a valid interrupt request, the current program status is saved and control passes to the appropriate Interrupt Service Routine. The ST9 CPU can receive requests from the following sources: On-chip peripherals External pins Top-Level Pseudo-non-maskable interrupt According to the on-chip peripheral features, an event occurrence can generate an Interrupt request which depends on the selected mode. Up to eight external interrupt channels, with programmable input trigger edge, are available. In addition, a dedicated interrupt channel, set to the Top-level priority, can be devoted either to the external NMI pin (where available) to provide a NonMaskable Interrupt, or to the Timer/Watchdog. Interrupt service routines are addressed through a vector table mapped in Memory. Figure 19. Interrupt Response
n
4.2 INTERRUPT VECTORING The ST9 implements an interrupt vectoring structure which allows the on-chip peripheral to identify the location of the first instruction of the Interrupt Service Routine automatically. When an interrupt request is acknowledged, the peripheral interrupt module provides, through its Interrupt Vector Register (IVR), a vector to point into the vector table of locations containing the start addresses of the Interrupt Service Routines (defined by the programmer). Each peripheral has a specific IVR mapped within its Register File pages. The Interrupt Vector table, containing the addresses of the Interrupt Service Routines, is located in the first 256 locations of Memory pointed to by the ISR register, thus allowing 8-bit vector addressing. For a description of the ISR register refer to the chapter describing the MMU. The user Power on Reset vector is stored in the first two physical bytes in memory, 0 0 00h and 0000 01h. The Top Level Interrupt vector is located at addresses 0004h and 0005h in the segment pointed to by the Interrupt Segment Register (ISR). With one Interrupt Vector register, it is possible to address several interrupt service routines; in fact, peripherals can share the same interrupt vector register among several interrupt channels. The most significant bits of the vector are user programmable to define the base vector address within the vector table, the least significant bits are controlled by the interrupt module, in hardware, to select the appropriate vector. Note: The first 256 locations of the memory segment pointed to by ISR can contain program code. 4.2.1 Divide by Zero trap The Divide by Zero trap vector is located at addresses 0002h and 0003h of each code segment; it should be noted that for each code segment a Divide by Zero service routine is required. Warning. Although the Divide by Zero Trap operates as an interrupt, the FLAG Register is not pushed onto the system Stack automatically. As a result it must be regarded as a subroutine, and the service routine must end with the RET instruction (not IRET ).
NORMAL PROGRAM FLOW
INTERRUPT SERVICE ROUTINE
INTERRUPT
CLEAR PENDING BIT
IRET INSTRUCTION
VR001833
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4.2.2 Segment Paging During Interrupt Routines The ENCSR bit in the EMR2 register can be used to select whether the CSR is saved or not when an interrupt occurs. For a description of the EMR2 register, refer to the External Memory Interface Chapter on page 87. ENC SR = 0 If ENCSR is reset, for the duration of the interrupt service routine, ISR is used instead of CSR and only the PC and Flags are pushed. This avoids saving the CSR on the stack in the event of an interrupt, thus ensuring a faster interrupt response time. It is not possible for an interrupt service routine to perform inter-segment calls or jumps: these instructions would update the CSR, which, in this case, is not used (ISR is used instead). The code segment size for all interrupt service routines is thus limited to 64K bytes. This mode ensures compatibiliy with the original ST9. ENC SR = 1 If ENCSR is set, ISR is only used to point to the interrupt vector table and to initialize the CSR at the beginning of the interrupt service routine: the old CSR is pushed onto the stack together with the PC and flags, and CSR is then loaded with the contents of ISR. In this case, iret will also restore CSR from the stack. This approach allows interrupt service routines to access the entire 4 Mbytes of address space. The drawback is that the interrupt response time is slightly increased, because of the need to also save CSR on the stack. Full compatibility with the original ST9 is lost in this case, because the interrupt stack frame is different .
ENCSR Bit 0 1 Pushed/Popped PC, FLAGR, PC, FLAGR Registers CSR Max. Code Size 64KB No limit for interrupt service routine Within 1 segment Across segments
4.3 INTERRUPT PRIORITY LEVELS The ST9 supports a fully programmable interrupt priority structure. Nine priority levels are available to define the channel priority relationships: The on-chip peripheral channels and the eight external interrupt sources can be programmed within eight priority levels. Each channel has a 3bit field, PRL (Priority Level), that defines its priority level in the range from 0 (highest priority) to 7 (lowest priority). The 9th level (Top Level Priority) is reserved for the Timer/Watchdog or the External Pseudo Non-Maskable Interrupt. An Interrupt service routine at this level cannot be interrupted in any arbitration mode. Its mask can be both maskable (TLI) or non-maskable (TLNM). 4.4 PRIORITY LEVEL ARBITRATION The 3 bits of CPL (Current Priority Level) in the Central Interrupt Control Register contain the priority of the currently running program (CPU priority). CPL is set to 7 (lowest priority) upon reset and can be modified during program execution either by software or automatically by hardware according to the selected Arbitration Mode. During every instruction, an arbitration phase takes place, during which, for every channel capable of generating an Interrupt, each priority level is compared to all the other requests (interrupts or DMA). If the highest priority request is an interrupt, its PRL value must be strictly lower (that is, higher priority) than the CPL value stored in the CICR register (R230) in order to be acknowledged. The Top Level Interrupt overrides every other priority. 4.4.1 Priority level 7 (Lowest) Interrupt requests at PRL level 7 cannot be acknowledged, as this PRL value (the lowest possible priority) cannot be strictly lower than the CPL value. This can be of use in a fully polled interrupt environment. 4.4.2 Maximum depth of nesting No more than 8 routines can be nested. If an interrupt routine at level N is being serviced, no other Interrupts located at level N can interrupt it. This guarantees a maximum number of 8 nested levels including the Top Level Interrupt request. 4.4.3 Simultaneous Interrupts If two or more requests occur at the same time and at the same priority level, an on-chip daisy chain, specific to every ST9 version, selects the channel
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with the highest position in the chain, as shown in Figure 9 Table 9. Daisy Chain Priority
Highest Position INTA0 INTA1 INTB0 INTB1 INTC0 INTC1 INTD0 INTD1 TIMER0 SCI0 SCI1 A/D TIMER3 TIMER1 INT0/WDT INT1 INT2/SPI INT3 INT4/STIM INT5 INT6/RCCU INT7
Lowest Position
4.4.4 Dynamic Priority Level Modification The main program and routines can be specifically prioritized. Since the CPL is represented by 3 bits in a read/write register, it is possible to modify dynamically the current priority value during program execution. This means that a critical section can have a higher priority with respect to other interrupt requests. Furthermore it is possible to prioritize even the Main Program execution by modifying the CPL during its execution. See Figure 20 Figure 20. Example of Dynamic priority level modification in Nested Mode
INTERRUPT 6 HAS PRIORITY LEVEL 6 Priority Level CPL is set to 7 4 by MAIN program ei INT6 MAIN CPL is set to 5 CPL6 > CPL5: 6 INT6 pending 7 5
INT 6 CPL=6 MAIN CPL=7
4.5 ARBITRATION MODES The ST9 provides two interrupt arbitration modes: Concurrent mode and Nested mode. Concurrent mode is the standard interrupt arbitration mode. Nested mode improves the effective interrupt response time when service routine nesting is required, depending on the request priority levels.
The IAM control bit in the CICR Register selects Concurrent Arbitration mode or Nested Arbitration M ode. 4.5.1 Concurrent Mode This mode is selected when the IAM bit is cleared (reset condition). The arbitration phase, performed during every instruction, selects the request with the highest priority level. The CPL value is not modified in this mode. Start of Interrupt Routine The interrupt cycle performs the following steps: All maskable interrupt requests are disabled by clearing CICR.IEN. The PC low byte is pushed onto system stack. The PC high byte is pushed onto system stack. If ENCSR is set, CSR is pushed onto system stack. The Flag register is pushed onto system stack. The PC is loaded with the 16-bit vector stored in the Vector Table, pointed to by the IVR. If ENCSR is set, CSR is loaded with ISR contents; otherwise ISR is used in place of CSR until iret instruction. End of Interrupt Routine The Interrupt Service Routine must be ended with the iret instruction. The iret instruction executes the following operations: The Flag register is popped from system stack. If ENCSR is set, CSR is popped from system stack. The PC high byte is popped from system stack. The PC low byte is popped from system stack. All unmasked Interrupts are enabled by setting the CICR.IEN bit. If ENCSR is reset, CSR is used instead of ISR. Normal program execution thus resumes at the interrupted instruction. All pending interrupts remain pending until the next ei instruction (even if it is executed during the interrupt service routine). Note: In Concurrent mode, the source priority level is only useful during the arbitration phase, where it is compared with all other priority levels and with the CPL. No trace is kept of its value during the ISR. If other requests are issued during the interrupt service routine, once the global CICR.IEN is re-enabled, they will be acknowledged regardless of the interrupt service routine's priority. This may cause undesirable interrupt response sequences.
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ARBITRATION MODES (Cont'd) Examples In the following two examples, three interrupt requests with different priority levels (2, 3 & 4) occur simultaneously during the interrupt 5 service routine.
Example 1 In the first example, (simplest case, Figure 21) the ei instruction is not used within the interrupt service routines. This means that no new interrupt can be serviced in the middle of the current one. The interrupt routines will thus be serviced one after another, in the order of their priority, until the main program eventually resumes.
Figure 21. Simple Example of a Sequence of Interrupt Requests with: - Concurrent mode selected and - IEN unchanged by the interrupt routines
0 Priority Level of Interrupt Request
INT ERRUPT 2 HAS PRIORITY LEVEL 2 INT ERRUPT 3 HAS PRIORITY LEVEL 3 INT ERRUPT 4 HAS PRIORITY LEVEL 4 INT ERRUPT 5 HAS PRIORITY LEVEL 5
1
2
INT 2 CPL = 7 INT 3 CPL = 7 INT 2 INT 3 INT 4 INT 5 ei CPL = 7 INT 4 CPL = 7
3
4
5
6 INT 5 7 MAIN CPL is set to 7 MAIN CPL = 7
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ARBITRATION MODES (Cont'd) Example 2 In the second example, (more complex, Figure 22), each interrupt service routine sets Interrupt Enable with the ei instruction at the beginning of the routine. Placed here, it minimizes response time for requests with a higher priority than the one being serviced. The level 2 interrupt routine (with the highest priority) will be acknowledged first, then, when the ei instruction is executed, it will be interrupted by the level 3 interrupt routine, which itself will be interrupted by the level 4 interrupt routine. When the level 4 interrupt routine is completed, the level 3 interrupt routine resumes and finally the level 2 interrupt routine. This results in the three interrupt serv-
ice routines being executed in the opposite order of their priority. It is therefore recommended to avoid inserting the ei instruction in the interrupt service routine in Concurrent mode. Use the ei instruction only in nested mode. WARN ING: If, in Concurrent Mode, interrupts are nested (by executing ei in an interrupt service routine), make sure that either ENCSR is set or CSR=ISR, otherwise the iret of the innermost interrupt will make the CPU use CSR instead of ISR before the outermost interrupt service routine is terminated, thus making the outermost routine fail.
Figure 22. Complex Example of a Sequence of Interrupt Requests with: - Concurrent mode selected - IEN set to 1 during interrupt service routine execution
0 Priority Level of Interrupt Request
INT ERRUPT 2 HAS PRIORITY LEVEL 2 INT ERRUPT 3 HAS PRIORITY LEVEL 3 INT ERRUPT 4 HAS PRIORITY LEVEL 4 INT ERRUPT 5 HAS PRIORITY LEVEL 5
1
2
INT 2 CPL = 7
INT 2 CPL = 7 INT 3 CPL = 7 ei INT 4 CPL = 7 INT 5 CPL = 7 INT 3 CPL = 7
3 INT 2 INT 3 INT 4 INT 5 ei 6 INT 5 7 MAIN CPL is set to 7 CPL = 7 ei
ei
4
5
ei
MAIN CPL = 7
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ARBITRATION MODES (Cont'd) 4.5.2 Nested Mode The difference between Nested mode and Concurrent mode, lies in the modification of the Current Priority Level (CPL) during interrupt processing. The arbitration phase is basically identical to Concurrent mode, however, once the request is acknowledged, the CPL is saved in the Nested Interrupt Control Register (NICR) by setting the NICR bit corresponding to the CPL value (i.e. if the CPL is 3, the bit 3 will be set). The CPL is then loaded with the priority of the request just acknowledged; the next arbitration cycle is thus performed with reference to the priority of the interrupt service routine currently being executed. Start of Interrupt Routine The interrupt cycle performs the following steps:
All maskable interrupt requests are disabled by clearing CICR.IEN. CPL is saved in the special NICR stack to hold the priority level of the suspended routine. Priority level of the acknowledged routine is stored in CPL, so that the next request priority will be compared with the one of the routine currently being serviced. The PC low byte is pushed onto system stack. The PC high byte is pushed onto system stack. If ENCSR is set, CSR is pushed onto system stack. The Flag register is pushed onto system stack. The PC is loaded with the 16-bit vector stored in the Vector Table, pointed to by the IVR. If ENCSR is set, CSR is loaded with ISR contents; otherwise ISR is used in place of CSR until iret instruction.
Figure 23. Simple Example of a Sequence of Interrupt Requests with: - Nested mode - IEN unchanged by the interrupt routines
Priority Level of Interrupt Request 0 INT 0 CPL=0 CPL6 > CPL3: INT6 pending
INTERRUPT 0 HAS PRIORITY LEVEL 0 INTERRUPT 2 HAS PRIORITY LEVEL 2 INTERRUPT 3 HAS PRIORITY LEVEL 3 INTERRUPT 4 HAS PRIORITY LEVEL 4 INTERRUPT 5 HAS PRIORITY LEVEL 5 INTERRUPT 6 HAS PRIORITY LEVEL 6
1 INT0 2 INT 2 CPL=2
INT6 INT 3 CPL=3
INT 2 CPL=2
3 INT2 INT3 INT4 INT 5 CPL=5
INT2 INT 4 CPL=4
4
5 ei 6 INT5 7
CPL2 < CPL4: Serviced next
INT 6 CPL=6 MAIN CPL=7
MAIN CPL is set to 7
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ARBITRATION MODES (Cont'd) End of Interrupt Routine The iret Interrupt Return instruction executes the following steps: The Flag register is popped from system stack. If ENCSR is set, CSR is popped from system stack. The PC high byte is popped from system stack. The PC low byte is popped from system stack. All unmasked Interrupts are enabled by setting the CICR.IEN bit. The priority level of the interrupted routine is popped from the special register (NICR) and copied into CPL.
If ENCSR is reset, CSR is used instead of ISR, unless the program returns to another nested routine. The suspended routine thus resumes at the interrupted instruction. Figure 23 contains a simple example, showing that if the ei instruction is not used in the interrupt service routines, nested and concurrent modes are equivalent. Figure 24 contains a more complex example showing how nested mode allows nested interrupt processing (enabled inside the interrupt service routinesi using the ei instruction) according to their priority level.
Figure 24. Complex Example of a Sequence of Interrupt Requests with: - Nested mode - IEN set to 1 during the interrupt routine execution
Priority Level of Interrupt Request 0
INTERRUPT 0 HAS PRIORITY LEVEL 0 INTERRUPT 2 HAS PRIORITY LEVEL 2
INT 0 CPL=0 CPL6 > CPL3: INT6 pending INT 2 CPL=2 INT 2 CPL=2
INTERRUPT 3 HAS PRIORITY LEVEL 3 INTERRUPT 4 HAS PRIORITY LEVEL 4 INTERRUPT 5 HAS PRIORITY LEVEL 5 INTERRUPT 6 HAS PRIORITY LEVEL 6
1 INT0 2 INT 2 CPL=2 ei INT2 INT3 INT4 INT 5 CPL=5 ei ei INT5 7 MAIN CPL is set to 7
INT6 INT 3 CPL=3 INT2
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