M41T00
Serial real-time clock
Not For New Design
Features
For new designs use M41T00S Counters for seconds, minutes, hours, day, month, years, and century 32 kHz crystal oscillator integrating load capacitance (12.5 pF) providing exceptional oscillator stability and high crystal series resistance operation Serial interface supports protocol) I 2C bus (100 kHz
8 1
SO8(M)
Ultra low battery supply current of 0.8 A (typ at 3 V) 2.0 to 5.5 V clock operating voltage Automatic switchover and deselect circuitry (for 3 V application select M41T00S datasheet) Software clock calibration to compensate crystal deviation due to temperature Automatic leap year compensation Operating temperature of -40 to 85 C
Description
The M41T00 is a low power serial real time clock with a built-in 32.768 kHz oscillator (external crystal controlled). Eight bytes of the RAM are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. Addresses and data are transferred serially via a two-line bidirectional bus. The built-in address register is incremented automatically after each WRITE or READ data byte. The M41T00 clock has a built-in power sense circuit which detects power failures and automatically switches to the battery supply during power failures. The energy needed to sustain the RAM and clock operations can be supplied from a small lithium coin cell. Typical data retention time is in excess of 5 years with a 50 mA/h 3 V lithium cell (see Section 2.10: Data retention mode for AC/DC characteristics). The M41T00 is supplied in 8-lead plastic small outline package.
May 2008
Rev 9
1/25
www.st.com 1
This is information on a product still in production but not recommended for new designs.
Contents
M41T00
Contents
1 2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 Wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Star t data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
M41T00 clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 3.2 3.3 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 5 6 7 8
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2/25
M41T00
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 RTC power down/up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 RTC power down/up trip points dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SO8 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . . 22 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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List of figures
M41T00
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SOIC connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Acknowledge sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Alternate READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 WRITE mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AC testing input/output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SO8 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . . 22
4/25
M41T00
Device overview
1
Device overview
Figure 1. Logic symbol
VCC VBAT
OSCI SCL M41T00
OSCO SDA FT/OUT
VSS
AI00530
Figure 2.
SOIC connection
M41T00 OSCI OSCO VBAT VSS 1 2 3 4 8 7 6 5
AI00531
VCC FT/OUT SCL SDA
Table 1.
OSCI OSCO FT/OUT SCL SDA VBAT
Pin description
Symbol Oscillator input Oscillator output Frequency test/output driver (open drain) Serial clock Serial data address input/output Battery supply voltage Ground Supply voltage Name and function
VSS VCC
5/25
Device overview Figure 3.
OSCI OSCILLATOR 32.768 kHz OSCO FT/OUT VCC VSS VBAT VOLTAGE SENSE and SWITCH CIRCUITRY DIVIDER MINUTES
M41T00
Block diagram
1 Hz SECONDS
CENTURY/HOURS CONTROL LOGIC DAY DATE MONTH
SCL
SERIAL BUS INTERFACE
YEAR ADDRESS REGISTER CONTROL
SDA
AI00603
6/25
M41T00
Device operation
2
Device operation
The M41T00 clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 8 bytes contained in the device can then be accessed sequentially in the following order: 1st byte: seconds register 2nd byte: minutes register 3rd byte: century/hours register 4th byte: day register 5th byte: date register 6th byte: month register 7th byte: years register 8th byte: control register The M41T00 clock continually monitors VCC for an out of tolerance condition. Should VCC fall below VSO, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out of tolerance system. When VCC falls below VSO, the device automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. Upon power-up, the device switches from battery to VCC at VSO and recognizes inputs.
2.1
Wire bus characteristics
This bus is intended for communication between different ICs. It consists of two lines: one bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined:
Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is High. Changes in the data line while the clock line is High will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
2.2
Bus not busy
Both data and clock lines remain high.
2.3
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the START condition.
7/25
Device operation
M41T00
2.4
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the STOP condition.
2.5
Data valid
The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition, a device that gives out a message is called "transmitter", the receiving device that gets the message is called "receiver". The device that controls the message is called "master". The devices that are controlled by the master are called "slaves".
2.6
Acknowledge
Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte. Also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case, the transmitter must leave the data line high to enable the master to generate the STOP condition.
8/25
M41T00 Figure 4. Serial bus data transfer sequence
Device operation
DATA LINE STABLE DATA VALID
CLOCK
DATA
START CONDITION
CHANGE OF DATA ALLOWED
STOP CONDITION
AI00587
Figure 5.
Acknowledge sequences
CLOCK PULSE FOR ACKNOWLEDGEMENT 1 2 8 9
START SCLK FROM MASTER
DATA OUTPUT BY TRANSMITTER
MSB
LSB
DATA OUTPUT BY RECEIVER
AI00601
Figure 6.
Bus timing requirements sequence
SDA tBUF tHD:STA tR SCL tHIGH P S tLOW tSU:DAT tHD:DAT tSU:STA SR P tSU:STO tF tHD:STA
AI00589
1. P = STOP and S = START
9/25
Device operation
M41T00
2.7
Characteristics
Table 2.
Symbol fSCL tLOW tHIGH tR tF tHD:STA tSU:STA
AC characteristics
Parameter(1) SCL clock frequency Clock low period Clock high period SDA and SCL rise time SDA and SCL fall time START condition hold time (after this period the first clock pulse is generated) START condition setup time (only relevant for a repeated start condition) 4 4.7 0 250 4.7 4.7 Min 0 4.7 4 1 300 Typ Max 100 Units kHz s s s ns s s ns ns s s
tHD:DAT(2) Data hold time tSU:DAT tSU:STO tBUF Data setup time STOP condition setup time Time the bus must be free before a new transmission can start
1. Valid for ambient operating temperature: TA = 40 to 85C; VCC = 2.0 to 5.5 V (except where noted). 2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of SCL.
2.8
READ mode
In this mode, the master reads the M41T00 slave after setting the slave address (see Figure 7). Following the WRITE mode control bit (R/W = 0) and the acknowledge bit, the word address An is written to the on-chip address pointer. Next the START condition and slave address are repeated, followed by the READ mode control bit (R/W = 1). At this point, the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. The address pointer is only incremented on reception of an acknowledge bit. The M41T00 slave transmitter will now place the data byte at address An+1 on the bus. The master receiver reads and acknowledges the new byte and the address pointer is incremented to An+2. This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter. An alternate READ mode may also be implemented, whereby the master reads the M41T00 slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer.
10/25
M41T00 Figure 7. Slave address location
R/W
Device operation
START
SLAVE ADDRESS
A
MSB
1
1
0
1
0
0
LSB 0
AI00602
Figure 8.
READ mode sequence
START START R/W R/W
BUS ACTIVITY: MASTER
SDA LINE
S
WORD ADDRESS (An)
ACK
S
DATA n
DATA n+1
ACK
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
SLAVE ADDRESS
STOP
DATA n+X
P
AI00899
Figure 9.
Alternate READ mode sequence
START STOP DATA n ACK ACK DATA n+1 ACK ACK DATA n+X P NO ACK
AI00895
BUS ACTIVITY: MASTER SDA LINE
S
BUS ACTIVITY: SLAVE ADDRESS
R/W
NO ACK
ACK
11/25
Device operation
M41T00
2.9
WRITE mode
In this mode the master transmitter transmits to the M41T00 slave receiver. Bus protocol is shown in Figure 10. Following the START condition and slave address, a logic '0' (R/W = 0) is placed on the bus and indicates to the addressed device that word address An will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the RAM on the reception of an acknowledge clock. The M41T00 slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address and again after it has received the word address and each data byte (see Figure 7).
Figure 10. WRITE mode sequences
START STOP
BUS ACTIVITY: MASTER
R/W
SDA LINE
S
WORD ADDRESS (An)
ACK ACK
DATA n
DATA n+1
DATA n+X
P
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
AI00591
2.10
Data retention mode
With valid VCC applied, the M41T00 can be accessed as described above with READ or WRITE cycles. Should the supply voltage decay, the M41T00 will automatically deselect, WRITE protecting itself when VCC falls (see Figure 11).
Figure 11. Power down/up mode AC waveforms
VCC VSO tPD SDA SCL DON'T CARE
AI00596
tREC
Table 3.
Symbol tPD trec
RTC power down/up ac characteristics
Parameter(1)(2) SCL and SDA at VIH before power down SCL and SDA at VIH after power up Min 0 10 Typ Max Unit ns s
1. Valid for ambient operating temperature: TA = -40 to 85C; VCC = 2.0 to 5.5 V (except where otherwise noted). 2. VCC fall time should not exceed 5 mV/s.
12/25
ACK
M41T00 Table 4.
Symbol VSO(4)
Device operation RTC power down/up trip points dc characteristics
Parameter(1)(2) Backup switchover voltage Min VBAT -0.80 Typ VBAT -0.50 Max(3) VBAT -0.30 Unit V
1. Valid for ambient operating temperature: TA = 40 to 85 C; VCC = 2.0 to 5.5 V (except where otherwise noted). 2. All voltages referenced to VSS. 3. In 3.3 V application, if initial battery voltage is > 3.4 V, it may be necessary to reduce battery voltage (i.e., through wave soldering the battery) in order to avoid inadvertent switchover/deselection for VCC -10 % operation. 4. Switchover and deselect point.
13/25
M41T00 clock operation
M41T00
3
M41T00 clock operation
The eight byte clock register (see Table 5) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Seconds, minutes, and hours are contained within the first three registers. Bits D6 and D7 of clock register 2 (century/hours register) contain the century enable bit (CEB) and the century bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0', CB will not toggle. Bits D0 through D2 of register 3 contain the day (day of week). Registers 4, 5 and 6 contain the date (day of month), month and years. The final register is the control register (this is described in the clock calibration section). Bit D7 of register 0 contains the STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts within one second.
Note:
In order to guarantee oscillator start-up after the initial power-up, set the ST bit to a '1,' then reset this bit to a '0.' This sequence enables a "kick start" circuit which aids the oscillator start-up during worst case conditions of voltage and temperature. The seven clock registers may be read one byte at a time, or in a sequential block. The control register (address location 7) may be accessed independently. Provision has been made to ensure that a clock update does not occur while any of the seven clock addresses are being read. If a clock address is being read, an update of the clock registers will be delayed by 250 ms to allow the read to be completed before the update occurs. This will prevent a transition of data during the read.
Note:
Note: This 250 ms delay affects only the clock register update and does not alter the actual clock time.
14/25
M41T00 Table 5.
Address D7 0 1 2 3 4 5 6 7 OUT ST X CEB(2) X X X CB X X X D6 D5 D4 D3 D2 D1 D0 10 seconds 10 minutes 10 hours X X X Seconds Minutes Hours Day Date Month Years Calibration
M41T00 clock operation Register map(1)
Data Function/range BCD format Seconds Minutes Centur y/hours Day Date Month Year Control 00-59 00-59 0-1/00-23 01-07 01-31 01-12 00-99
10 date X 10 M.
10 Years FT S
1. Keys: S = sign bit FT = frequency test bit ST = stop bit OUT = output level X = don't care CEB = century enable bit CB = century bit 2. When CEB is set to '1', CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century (dependent upon the initial value set).When CEB is set to '0', CB will not toggle.
3.1
Clock calibration
The M41T00 is driven by a quartz controlled oscillator with a nominal frequency of 32768 Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25C, which equates to about 1.53 minutes per month. With the calibration bits properly set, the accuracy of each M41T00 improves to better than 2 ppm at 25 C. The oscillation rate of any crystal changes with temperature (see Figure 12). Most clock chips compensate for crystal frequency and temperature shift error with cumbersome trim capacitors. The M41T00 design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 13. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five-bit calibration byte found in the control register. Adding counts speeds the clock up, subtracting counts slows the clock down. The calibration byte occupies the five lower order bits (D4-D0) in the control register (addr 7). This byte can be set to represent any value between 0 and 31 in binary form. Bit D5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on.
15/25
M41T00 clock operation
M41T00
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or 2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or 5.35 seconds per month which corresponds to a total range of +5.5 or 2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M41T00 may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accessed the calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of some test equipment. When the frequency test (FT) bit, the seventh-most significant bit in the control register, is set to a '1', and the oscillator is running at 32768 Hz, the FT/OUT pin of the device will toggle at 512 Hz. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a 10(XX00 1010b) to be loaded into the calibration byte for correction. Note that setting or changing the calibration byte does not affect the frequency test output frequency. Figure 12. Crystal accuracy across temperature
Frequency (ppm) 20 0 20 40 60 80 100 120 140 160 40 30 20 10 0 10 20 30 40 50 60 70 80 F = K x (T T )2 O F K = 0.036 ppm/C2 0.006 ppm/C2 TO = 25C 5C
Temperature C
AI00999b
16/25
M41T00 Figure 13. Clock calibration
NORMAL
M41T00 clock operation
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
3.2
Output driver pin
When the FT bit is not set, the FT/OUT pin becomes an output driver that reflects the contents of D7 of the control register. In other words, when D6 of address 7 is a zero and D7 of address 7 is a zero and then the FT/OUT pin will be driven low.
Note:
The FT/OUT pin is open drain which requires an external pull-up resistor.
3.3
Initial power-on defaults
Upon initial application of power to the device, the FT bit will be set to a '0' and the OUT bit will be set to a '1'. All other register bits will initially power on in a random state.
17/25
Maximum ratings
M41T00
4
Maximum ratings
Stressing the device above the rating listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 6.
Symbol TSTG TA VIO TSLD(1) VCC IO PD
Absolute maximum ratings
Parameter Storage temperature (VCC off, oscillator off) Ambient operating temperature Input or output voltages Lead solder temperature for 10 seconds Supply voltage Output current Power dissipation Value 55 to 125 -40 to 85 0.3 to 7 260 0.3 to 7 20 0.25 Unit C C V C V mA W
1. Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds).
Caution:
Negative undershoots below -0.3 V are not allowed on any pin while in the backup mode.
18/25
M41T00
DC and AC parameters
5
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 7. Operating and AC measurement conditions(1)
Parameter Supply voltage (VCC) Ambient operating temperature (TA) Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing reference voltages
1. Output Hi-Z is defined as the point where data is no longer driven.
M41T00 2.0 to 5.5 V -40 to 85 C 100 pF 5 ns 0.2 VCC to 0.8 VCC 0.3 VCC to 0.7 VCC
Figure 14. AC testing input/output waveform
0.8VCC
0.7VCC 0.3VCC
AI02568
0.2VCC
Table 8.
Symbol CIN
COUT(3)
Capacitance
Parameter (1)(2) Input capacitance (SCL) Output capacitance (SDA,FT/OUT) Low-pass filter input time constant (SDA and SCL) 250 Min Max 7 10 1000 Unit pF pF ns
tLP
1. Effective capacitance measured with power supply at 3.3 V; sampled only, not 100% tested 2. At 25C, f = 1 MHz 3. Output deselected.
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DC and AC parameters Table 9.
Symbol ILI ILO ICC1 ICC2 VIL VIH VOL
M41T00
DC characteristics
Parameter Input leakage current Output leakage current Supply current RTC supply current (standby) Input low voltage Input high voltage Output low voltage Output low voltage (open drain) IOL = 3.0 mA FT/OUT 2.5(3) TA = 25 C, VCC = 0 V oscillator ON, VBAT = 3 V 0.8 Test condition(1) 0 V = VIN = VCC 0 V = VOUT = VCC Switch frequency = 100 kHz SCL, SDA = VCC 0.3 V 0.3 0.7 VCC Min Typ Max 1 1 300 70 0.3VCC VCC + 0.5 0.4 5.5 3.5(4) 1 Unit A A A A V V V V V A
VBAT(2) IBAT
Battery supply voltage Battery supply current
1. Valid for ambient operating temperature: TA = 40 to 85 C; VCC = 2.0 to 5.5 V (except where otherwise noted). 2. STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equivalent)as the battery supply. 3. After switchover (VSO), VBAT(min) can be 2.0 V for crystal with RS = 40 K. 4. For rechargeable backup, VBAT(max) may be considered VCC.
Table 10.
Symbol fO RS CL
Crystal electrical characteristics
Parameter (1)(2) Resonant frequency Series resistance Load capacitance 12.5 Mi n Typ 32.768 60 Max Units kHz K pF
1. Externally supplied if using the SO8 package. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp for further information on this crystal type. 2. Load capacitors are integrated within the M41T00. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account.
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M41T00
Package mechanical data
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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Package mechanical data
M41T00
Figure 15. SO8 8-lead plastic small outline, 150 mils body width, package mechanical data
h x 45 A2 b e 0.25 mm GAUGE PLANE k
8
A ccc c
D
E1
1
E A1 L L1
SO-A
1. Drawing is not to scale.
Table 11.
SO8 8-lead plastic small outline, 150 mils body width, package mechanical data
millimeters inches Max 1.75 0.10 1.25 0.28 0.17 0.48 0.23 0.10 4.90 6.00 3.90 1.27 4.80 5.80 3.80 0.25 0 0.40 1.04 5.00 6.20 4.00 0.50 8 1.27 0.041 0.193 0.236 0.154 0.050 0.189 0.228 0.150 0.010 0 0.016 0.25 0.004 0.049 0.011 0.007 0.019 0.009 0.004 0.197 0.244 0.157 0.020 8 0.050 Typ Min Max 0.069 0.010
Symbol Typ A A1 A2 b c ccc D E E1 e h k L L1 Min
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M41T00
Part numbering
7
Part numbering
Table 12.
Example:
Ordering information scheme
M41T 00 M 6 E
Device type M41T
Supply voltage and WRITE protect voltage 00 = VCC = 2.0 to 5.5 V
Package M = SO8 (150 mils width)
Temperature range 6 = 40 to 85 C
Shipping method E = ECOPACK package, tubes F = ECOPACK package, tape & reel
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Revision history
M41T00
8
Revision history
Table 13.
Date Mar-1999 15-May-2000 25-Jul-2000 12-Dec-2000 24-Jan-2001 27-Feb-2001 17-Jul-2001 27-Nov-2001
Revision history
Revision 1.0 1.1 1.2 1.3 2.0 3.0 3.1 3.2 First Issue AC Characteristic conditions changed (Table 2) Crystal Electrical Characteristics: RS Max changed (Table 10) Edit VSO (Table 3) Reformatted Document Status changed Change to DC and AC Characteristics (Table 9, Table 2); added temp./voltage info. to tables Features, (page 1); DC Characteristics (Table 9); Crystal Electrical (Table 10); Power Down/Up Trip Points (Table 3) changes; add table footnote (Table 10) Fix table footnotes (Table 9, Table 10) Modify reflow time and temperature footnote (Table 6) Corrected operating voltage Modify "Clock Operation" text, Crystal Electrical Characteristics table footnote (Table 10) Correct figure name on page1 Reformatted; add Lead-free information; update characteristics (Figure 12; Table 6, Table 9) New features summary Updated Inside Cover to new template; AIN pin removed from Table 1: Pin description; small text change in Section 3: M41T00 clock operation; updated package mechanical data (Section 6: Package mechanical data). Corrected Table 11: SO8 8-lead plastic small outline, 150 mils body width, package mechanical data. Datasheet status updated to "not for new design" (updated cover page), updated Table 6. Changes
21-Jan-2002 13-May-2002 05-Jun-2002 03-Jul-2002 07-Nov-2002 15-Jun-04 28-Jun-2004 08-Dec-2006
3.3 3.4 3.5 3.6 3.7 5.0 6 7
22-Dec-2006 15-May-2008
8 9
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M41T00
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