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ST72141K - 8-BIT MCU FOR ELECTRIC-MOTOR CONTROL WITH ROM/OTP/EPROM, 256 BYTES RAM, ADC, 16-BIT TIMERS, SPI INTERFACE

Datasheet

Format: (1494 kb)

Last Updated: 01/09/2002

Pages: 132

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ST72141K
8-BIT MCU WITH ELECTRIC-MOTOR CONTROL, ADC, 16-BIT TIMERS, SPI INTERFACE
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M e m o ri e s 8K Program memory (ROM/OTP/EPROM) 256 Bytes RAM Clock, Reset and Supply Management Enhanced reset system Low voltage supply supervisor 3 Power saving modes 14 I/O Ports 14 multifunctional bidirectional I/O lines with: External interrupt capability (2 vectors), 13 alternate function lines, 3 high sink outputs Motor Control peripheral 6 PWM output channels Emergency pin to force outputs to HiZ state 3 analog inputs for rotor position detection with no need for additional sensors Comparator for current limitation 3 Timers Two 16-bit timers with: 2 input captures, 2 output compares, external clock input, PWM and Pulse generator modes Watchdog timer for system integrity Communications Interface SPI synchronous serial interface Analog Peripheral 8-bit ADC with 8 input pins

SDIP32

S O 34S

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s

Instruction Set 8-bit data manipulation 63 basic instructions 17 main addressing modes 8 x 8 unsigned multiply instruction True bit manipulation Development Tools Full hardware/software development package
ST72141K2

Device Summary
Features Program memory - bytes RAM (stack) - bytes Peripherals Operating Supply CPU Frequency Operating Temperature Packages 8K 256 (64) Motor control, Watchdog, Two 16-bit timers, SPI, ADC 4V to 5.5V 4 or 8 MHz (with 8 or 16 MHz oscillator) -40C to +85C / -40C to +125C SO34 / SDIP32

Rev. 1.8
October 2001 1/132

1

Table of Contents
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 EXTERNAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.5 EPROM PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 RESET MANAGER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 3.3 LOW CONSUMPTION OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4 MAIN CLOCK CONTROLLER (MCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3 W AIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 31 31 34

6.3.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.1 I/O PORT INTERRUPT SENSITIVITY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.3 CLOCK PRESCALER SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.4 MISCELLANEOUS REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.1 MOTOR CONTROLLER (MTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8. 1. 1 8. 1. 2 8. 1. 3 8. 1. 4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 . ... Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 40 40 44

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Table of Contents
8.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 W ATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 66 67 75 75 75 76 76 76 76 78 78 78 78 90 90 90 91 96

8.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.4.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.4.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.5 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9. 1. 1 I nheren t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9. 1. 3 D i r ec t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.7 Relative Mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 109 110 110 110 111 112 112 113 113 113 113 113 114 114 115

10 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 10.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 10.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

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Table of Contents
10.4 GEN ERAL TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.5 I/O PORT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 10.6 SUPPLY, RESET AND CLOCK CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 121 10.6.1 Supply Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6.2 RESET Sequence Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6.3 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7 MEMORY AND PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 121 121 122

11 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 11.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 11.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 12 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

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1

ST72141K

1 GENERAL DESCRIPTION
1.1 INTRODUCTION The ST72141K devices are members of the ST7 microcontroller family designed specifically for motor control applications and including A/D conversion and SPI interface capabilities. They include an on-chip Moter Controller peripheral for control of electric brushless moters with or without sensors. An example application, for 6-step control of a Permanent Magnet DC motor, is shown in Figure 1. The ST72141K devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. Under software control, they can be placed in WAIT, SLOW, or HALT mode, reducing power consumption when the application is in idle or standby state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. Figure 1. Example of a 6-step-controlled Motor
ST7
M O -0 C5
6

300V 0

2 B I1 I6

4

M IB C

MTC
M IA C M IC C
A

I4 I3 I5 3 5 I2 C 1

Net

1

2

3

4

Step
5

6

1

2

3

0 1 2 3 4 5 A B C
30 0 V 15 0 V 0 3 0 0V 1 5 0V 0 3 0 0V 1 5 0V 0

Figure 2. Device Block Diagram
Internal CLOCK OSC OSC2 VDD VSS RESET POWER SUPPLY LVD DIV 8-BIT ADC TIMER B TIMER A CONTROL
ADDRESS AND DATA BUS

OSC1

PORT A PA7:0 (8-BIT) OC1A MCO5:0 MCIA:C MOTOR CTRL MCES MCCFI PORT B SPI PB5:0 (6-BIT)

8-BIT CORE ALU

8K-EPROM

256b-RAM

WAT CHDOG

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4

ST72141K

1.2 PIN DESCRIPTION Figure 3. 34-Pin SO Package Pinout

MCO5 MCO4 MCO3 MCO2 MCO1 MCO0 MCES MISO/PB5 NC MOSI/PB4 SCK/PB3 SS/ (HS) PB2 EXTCLK_B/ (HS) PB1 EXTCLK_A/ (HS) PB0 OSC1 OSC2 RESET

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 EI0 EI1

34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18

MCIA MCIB MCIC MCCFI VD D V SS V PP OCMP1_A NC PA7/AIN7/OCMP2_A PA6/AIN6/ICAP1_A PA5/AIN5/ICAP2_A PA4/AIN4/OCMP1_B PA3/AIN3/OCMP2_B PA2/AIN2/ICAP1_B PA1/AIN1/ICAP2_B PA0/AIN0

Figure 4. 32-Pin SDIP Package Pinout

MCO5 MCO4 MCO3 MCO2 MCO1 MCO0 MCES MISO/PB5 MOSI/PB4 SCK/PB3 SS/ (HS) PB2 EXTCLK_B/ (HS) PB1 EXTCLK_A/ (HS) PB0 OSC1 OSC2 RESET

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 EI0

32 31 30 29 28 27 26 25 24 23 22 EI1 21 20 19 18 17

MCIA MCIB MCIC MCCFI VDD VSS VPP OCMP1_A PA7/AIN7/OCMP2_A PA6/AIN6/ICAP1_A PA5/AIN5/ICAP2_A PA4/AIN4/OCMP1_B PA3/AIN3/OCMP2_B PA2/AIN2/ICAP1_B PA1/AIN1/ICAP2_B PA0/AIN0

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ST72141K

PIN DESCRIPTION (Cont'd) Legend / Abbreviations: Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C = CMOS 0.3VDD/0.7VDD, CT= CMOS 0.3VDD/0.7VDD with input trigger Output level: HS = high sink (on N-buffer only), R = 70/100 ratio of logical levels. Analog level if used as PWM filtered with an external capacitor Port configuration capabilities: Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog Output: OD = open drain, T = true open drain, PP = push-pull Note: the Reset configuration of each pin is shown in bold. Table 1. Device Pin Description
Pin n Type SDIP32 SO34 Pin Name Level Output Input Port / Control Input float wpu ana int Output OD PP Main Function (after reset) Alternate Function

1 2 3 4 5 6 7 8

1 MCO5 2 MCO4 3 MCO3 4 MCO2 5 MCO1 6 MCO0 7 MCES 8 PB5/MISO 9 NC

O O O O O O I I/O CT

C C C C C C X X EI1 X

X X X X X X

Motor Control Output Channel 5 Motor Control Output Channel 4 Motor Control Output Channel 3 Motor Control Output Channel 2 Motor Control Output Channel 1 Motor Control Output Channel 0 Motor Control Emergency Stop Input

CT

X

Port B5

SPI Master In / Slave Out Data

Not Connected I/O I/O CT CT X X X X X EI1 EI1 EI1 EI1 EI1 X X T T T X X Port B4 Port B3 Port B2 Port B1 Port B0 SPI Master Out / Slave In Data SPI Serial Clock SPI Slave Select (active low) Timer B Input Clock Timer A Input Clock

9

10 PB4/MOSI

10 11 PB3/SCK 11 12 PB2/SS 12 13 PB1/EXTCLK_B 13 14 PB0/EXTCLK_A 14 15 OSC1 15 16 OSC2 16 17 RESET 17 18 PA0/AIN0 18 19 PA1/ICAP2_B/AIN1 19 20 PA2/ICAP1_B/AIN2

I/O CT HS I/O CT HS I/O CT HS

These pins connect a crystal or ceramic resonator, or an external RC, or an external source to the on-chip oscillator I/O I/O I/O I/O C CT CT CT X X X X EI0 EI0 EI0 X X X X X X X X X X Top priority non maskable interrupt (active low) Port A0 Port A1 Port A2 ADC Analog Input 0 Timer B Input Capture 2 or ADC Analog Input 1 Timer B Input Capture 1 or ADC Analog Input 2

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Pin n Type SDIP32 SO34 Pin Name

Level Output Input

Port / Control Input float wpu ana int Output OD PP Main Function (after reset) Alternate Function

20 21 PA3/OCMP2_B/AIN3 21 22 PA4/OCMP1_B/AIN4 22 23 PA5/ICAP2_A/AIN5 23 24 PA6/ICAP1_A/AIN6 24 25 PA7/OCMP2_A/AIN7 26 NC 25 27 OCMP1_A 26 28 VPP 27 29 VSS 28 30 VDD 29 31 MCCFI 30 32 MCIC 31 33 MCIB 32 34 MCIA

I/O I/O I/O I/O I/O

CT CT CT CT CT

X X X X X

EI0 EI0 EI0 EI0 EI0

X X X X X

X X X X X

X X X X X

Port A3 Port A4 Port A5 Port A6 Port A7

Timer B Output Compare 2 or ADC Analog Input 3 Timer B Output Compare 1 or ADC Analog Input 4 Timer A Input Capture 2 or ADC Analog Input 5 Timer A Input Capture 1 or ADC Analog Input 6 Timer A Output Compare 2 or ADC Analog Input 7

Not Connected O I S S I I I I A A A A R Timer A Output Compare 1 Must be tied low during normal operating mode,EPROM Programming voltage pin. Ground Main power supply Motor Control Current Feedback Input Motor Control Input C Motor Control Input B Motor Control Input A

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1.3 EXTERNAL CONNECTIONS The following figure shows the recommended external connections for the device. The VPP pin is only used for programming OTP and EPROM devices and must be tied to ground in user mode. The 10 nF and 0.1 F decoupling capacitors on the power supply lines are a suggested EMC performance/cost tradeoff. Figure 5. Recommended External Connections The external reset network is intended to protect the device against parasitic resets, especially in noisy environments. Unused I/Os should be tied high to avoid any unnecessary power consumption on floating lines. An alternative solution is to program the unused ports as inputs with pull-up.

VPP VDD
10F +

VDD
0.1F

VSS

Option al if Low Voltage Dete ctor (LVD) is used

V DD VDD
4.7K 0.1F

EXTERNAL RESET CIRCUIT 0.1F

RESET VSS
See Clocks Sect ion

OSC1 OSC2

Or configure unused I/O ports by software as input with pull-up

VDD

10K

Unused I/O

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1.4 REGISTER & MEMORY MAP As shown in Figure 6, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, 256 bytes of RAM and 8Kbytes of user program memory. The RAM Figure 6. Memory Map
0080h 0000h 007Fh 0080h

space includes up to 64 bytes for the stack from 0140h to 017Fh. The highest address bytes contain the user reset and interrupt vectors.

HW Registers (see Table 3)

Short Addressing RAM "Zero page" (128 Bytes)
00FFh 0100h

256 Bytes RAM
017Fh 0180h

Reserved
DFFFh E000h

16-bit Addressing RAM (64 Bytes)
013Fh 0140h

Program Memory (8K Bytes)
FFD Fh FFE0h FFFFh

Interrupt & Reset Vectors (see Table 2)

017Fh

Stack or 16-bit Addressing RAM (64 Bytes)

Table 2. Interrupt Vector Map
Vector Address FFE0-FFE1h FFE2-FFE3h FFE4-FFE5h FFE6-FFE7h FFE8-FFE9h FFEA-FFEBh FFEC-FFEDh FFEE-FFEFh FFF0-FFF1h FFF2-FFF3h FFF4-FFF5h FFF6-FFF7h FFF8-FFF9h FFFA-FFFBh FFFC-FFFDh FFFE-FFFFh Description Not used Not used Not used Not used Not used TIMER B interrupt vector TIMER A interrupt vector SPI interrupt vector Motor control interrupt vector (events: E, O) Motor control interrupt vector (events: C, D) Motor control interrupt vector (events: R, Z) External interrupt vector EI1: port B7..0 External interrupt vector EI0: port A7..0 Not used TRAP (software) interrupt vector RESET vector Remarks Internal Interrupt

External Interrupt External Interrupt CPU Interrupt

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Table 3. Hardware Register Map
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h to 001F 0020h 0021h 0022h 0023h 0024h 0025h 0026h to 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer SPI MISCR SPIDR SPICR SPISR WDGCR WDGSR Port B PBDR PBDDR PBOR Block Register Label PADR PADDR PAOR Register Name Port A Data Register Port A Data Direction Register Port A Option Register Reserved Area (1 Byte) Port B Data Register Port B Data Direction Register Port B Option Register Reserved Area (24 Byte) Miscellaneous Register SPI Data I/O Register SPI Control Register SPI Status Register Watchdog Control Register Watchdog Status Register Reserved Area (11 Bytes) A Control Register 2 A Control Register 1 A Status Register A Input Capture 1 High Register A Input Capture 1 Low Register A Output Compare 1 High Register A Output Compare 1 Low Register A Counter High Register A Counter Low Register A Alternate Counter High Register A Alternate Counter Low Register A Input Capture 2 High Register A Input Capture 2 Low Register A Output Compare 2 High Register A Output Compare 2 Low Register Reserved Area (1 Byte) 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W 00h xxh 0xh 00h 7Fh x0h R/W R/W R/W Read Only R/W Read Only 00h 00h 00h R/W R/W R/W. Reset Status 00h 00h 00h Remarks R/W R/W R/W

Port A

WATCHDOG

TIMER A

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Address 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h to 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh to 006Fh 0070h 0071h 0072h to 007Fh

Block

Register Label TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer

Register Name B Control Register 2 B Control Register 1 B Status Register B Input Capture 1 High Register B Input Capture 1 Low Register B Output Compare 1 High Register B Output Compare 1 Low Register B Counter High Register B Counter Low Register B Alternate Counter High Register B Alternate Counter Low Register B Input Capture 2 High Register B Input Capture 2 Low Register B Output Compare 2 High Register B Output Compare 2 Low Register Reserved Area (16 Bytes)

Reset Status 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h

Remarks R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W

TIMER B

MOTOR CONTROL

MTIM MZPRV MZREG MCOMP MDREG MWGHT MPRSR MIMR MISR MCRA MCRB MPHST MPAR MPOL

Timer Counter Register Zn-1 Capture Register Zn Capture Register Cn+1Compare Register D capture/Compare Register Weight Register Prescaler and Ratio Register Interrupt Mask Register Interrupt Status Register Control Register A Control Register B Phase State Register Output Parity Register Output Polarity Register Reserved Area (2 bytes)

00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

ADC

ADCDR ADCCSR

Data Register Control/Status Register Reserved Area (14 Bytes)

00h 00h

Read Only R/W

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1.5 EPROM PROGRAM MEMORY The program memory of the OTP and EPROM devices can be programmed with EPROM programming tools available from STMicroelectronics. EPROM Erasure EPROM devices are erased by exposure to high intensity UV light admitted through the transparent window. This exposure discharges the floating gate to its initial state through induced photo current. It is recommended that the EPROM devices be kept out of direct sunlight, since the UV content of sunlight can be sufficient to cause functional failure. Extended exposure to room level fluorescent lighting may also cause erasure. An opaque coating (paint, tape, label, etc...) should be placed over the package window if the product is to be operated under these lighting conditions. Covering the window also reduces IDD in power-saving modes due to photo-diode leakage currents.

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2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 2.2 MAIN FEATURES
s s s s s s s s

63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit index registers 16-bit stack pointer Low power modes Maskable hardware interrupts Non-maskable software interrupt

2.3 CPU REGISTERS The 6 CPU registers shown in Figure 7 are not present in the memory mapping and are accessed by specific instructions. Figure 7. CPU Registers
7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 0 0 0

Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate dat a. Index Registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 111HI 0 NZC CONDITION CODE REGISTER

RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value

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CPU REGISTERS (Cont'd) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx
7 1 1 1 H I N Z 0 C

because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions. Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions.

The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 3 = I Interrupt mask. This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptable

Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions.

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CEN TRAL PROCESSING UNIT (Cont'd) Stack Pointer (SP) Read/Write Reset Value: 01 7Fh
15 0 7 0 SP6 SP5 SP4 SP3 SP2 SP1 0 0 0 0 0 0 8 1 0 SP0

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 8). Since the stack is 128 bytes deep, the 9th most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP6 to SP0 bits are set) which is the stack higher address. Figure 8. Stack Manipulation Example
CALL Subroutine @ 0100h Interrupt Event PUSH Y

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 8. When an interrupt is received, the SP is decremented and the context is pushed on the stack. On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area.

POP Y

IRET

RET or RSP

SP SP CC A X PCH SP PCH @ 017Fh PCL PCL PCH PCL Y CC A X PCH PCL PCH PCL SP CC A X PCH PCL PCH PCL SP PCH PCL SP

Stack Higher Address = 017Fh Stack Lower Address = 0100h

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3 SUPPLY, RESET AND CLOCK MANAGEMENT
The ST72141K includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 9. Main Features s M ain supply low voltage detection (LVD) s RESET Manager s L ow co nsump tio n resonator oscillator s M ain clock controller (MCC)

Figure 9. Clock, RESET, Option and Supply Management Overview
fMOTOR_CONTROL fSPI M AIN C LO CK C ONTRO LLE R (MC C) f C PU

OS C2 OS CILLA TO R OS C1

fOSC

R ESET

RE S ET

F RO M WATCH DOG P ER IP HER AL

VDD VSS

LOW VOLTAGE D ETEC TO R (LV D)

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3.1 LOW VOLTAGE DETECTOR (LVD) To allow the integration of power management features in the application, the Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VLVDf reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The V LVDf reference value for a voltage drop is lower than the V LVDr reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD Reset circuitry generates a reset when VDD is below: VLVDr when VDD is rising VLVDf when VDD is falling The LVD function is illustrated in Figure 10. Figure 10. Low Voltage Detector vs Reset
VDD

Provided the minimum VDD value (guaranteed for the oscillator frequency) is below VLVDf, the MCU can only be in two modes: under full software control in static safe reset In these conditions, secure operation is always ensured for the application without the need for external reset hardware. During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Notes: The LVD allows the device to be used without any external RESET circuitry.

HYSTERISIS

VLVDhyst VLVDr VLVDf

R ESET

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3.2 RESET MANAGER The RESET block includes three RESET sources as shown in Figure 11: s External RESET source pulse s Internal LVD RESET (Low Voltage Detection) s Internal WATCHDOG RESET Th e RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. A 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The RESET vector fetch phase duration is 2 clock cycles.

Figure 11. Reset Block Diagram

V DD

f C PU C OUN TE R

INTER NAL R ES ET

RON

RESET

W A TC HDO G R ES ET LVD R ES ET

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RESET MANAGER (Cont'd) External RESET pin The RESET pin is both an input and an open-drain output with integrated R ON weak pull-up resistor (see Figure 11). This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. A RESET signal originating from an external source must have a duration of at least tPULSE in order to be recognized. Two RESET sequences can be associated with this RESET source as shown in Figure 12. When the RESET is generated by a internal source, during the two first phases of the RESET sequence, the device RESET pin acts as an output that is pulled low. Generic Power On RESET The function of the POR circuit consists of waking up the MCU by detecting (at around 2V) a dynamic (rising edge) variation of the VDD Supply. At the beginning of this sequence, the MCU is configured in the RESET state. When the power supply voltage rises to a sufficient level, the oscillator starts to operate, whereupon an internal 4096 CPU cycles delay is initiated, in order to allow the oscillator to fully stabilize before executing the first instruction. The initialization sequence is executed immediately following the internal delay. To ensure correct start-up, the user should take care that the VDD Supply is stabilized at a sufficient level for the chosen frequency (see Electrical Characteristics) before the reset signal is released. In addition, supply rising must start from 0V . As a consequence, the POR does not allow to supervise static, slowly rising, or falling, or noisy (oscillating) VDD supplies. An external RC network connected to the RESET pin, or the LVD reset can be used instead to get the best performance.

Figure 12. External RESET Sequences
VDD
VDD nominal VL VDf

RESET RUN
DELAY tPUL SE INTERNAL RESET 4096 CLOCK CYCLES FETCH VECTOR

RUN

EXTERNAL RESET SOURCE

RESET PIN

WATCHDOG RESET

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RESET MANAGER (Cont'd) Internal Low Voltage Detection RESET (option) Two different RESET sequences caused by the internal LVD circuitry can be distinguished: - LVD Power-On RESET - Voltage Drop RESET Figure 13. LVD RESET Sequences
VDDnominal VLVDr VDD

In the second sequence, a "delay" phase is used to keep the device in RESET state until VDD rises up to VLVDr (see Figure 13).

LVD POWER-ON RESET

POWEROFF

RESET
INTERNAL RESET FETCH 4096 CLOCK CYCLES VECTOR

RUN

EXTERNAL RESET SOURCE

RESET PIN

WATCHDOG RESET

VDD VDDnominal VLVDr VLVDf

RESET RUN
DELAY

VOLTAGE DROP RESET

INTERNAL RESET FETCH 4096 CLOCK CYCLES VECTOR

RUN

EXTERNAL RESET SOURCE

RESET PIN

WATCHDOG RESET

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RESET MANAGER (Cont'd) Internal Watchdog RESET The RESET sequence generated by a internal Watchdog counter overflow has the shortest reset phase (see Figure 14).

Figure 14. Watchdog RESET Sequence
VDD VDDnominal VLVDf

RESET RUN
INTERNAL RESET 4096 CLOCK CYCLES FETCH VECTOR

RUN

EXTERNAL RESET SOURCE

tWDGRST
RESET PIN

WATCHDOG RESET

WATCHDOG UNDERFLOW

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3.3 LOW CONSUMPTION OSCILLATOR The main clock of the ST7 can be generated by two different sources: s a n external source s a crystal or ceramic resonator oscillators External Clock Source In this mode, a square clock signal with ~50% duty cycle has to drive the OSC2 pin while the OSC1 pin is tied to V SS (see Figure 15). Crystal/Ceramic Oscillators This oscillator (based on constant current source) is optimized in terms of consumption and has the advantage of producing a very accurate rate on the main clock of the ST7. When using this oscillator, the resonator and the load capacitances have to be connected as shown in Figure 16 and have to be mounted as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. This oscillator is not stopped during the RESET phase to avoid losing time in the oscillator start-up phas e.

Figure 15. External Clock Figure 16. Crystal/Ceramic Resonator
ST7 OS C1 OS C2 OSC 1 ST7 OS C2

EXTER NAL SO URC E

CL0

L OA D CAP A CITAN CE S

CL1

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3.4 MAIN CLOCK CONTROLLER (MCC) The MCC block supplies the clock for the ST7 CPU and its internal peripherals. It allows the SLOW power saving mode and the Motor Contral and SPI peripheral clocks to be managed independently. The MCC functionality is controlled by two bits of the MISCR register: SMS and XT16. The XT16 bit acts on the clock of the motor control and SPI peripherals while the SMS bit acts on the CPU and the other peripherals.

Figure 17. Main Clock Controller (MCC) Block Diagram

OSC2 OSCILLATOR OSC1 MC C fOSC
DIV 2 DIV 16

fCPU

CPU CLOCK TO CPU AND PERIPHERALS

XT16

-

-

-

-

-

-

SMS

MISCR

DIV 2

4MHz MOTOR CONTROL PERIPHERAL

DIV 2

4MHz SPI PERIPHERAL

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4 INTERRUPTS
The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 18. The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). Note: After reset, all interrupts are disabled. When an interrupt has to be serviced: Normal processing is suspended at the end of the current instruction execution. The PC, X, A and CC registers are saved onto the stack. The I bit of the CC register is set to prevent additional interrupts. The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping Table for vector addresses). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume. Priority Management By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine. In the case when several interrupts are simultaneously pending, an hardware priority defines which one will be serviced first (see the Interrupt Mapping Table). Interrupts and Low Power Mode All interrupts allow the processor to leave the WAIT low power mode. Only external and specifically mentioned interrupts allow the processor to leave the HALT low power mode (refer to the "Exit from HALT" column in the Interrupt Mapping Table) . 4.1 NON MASKABLE SOFTWARE INTERRUPT This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. It will be serviced according to the flowchart on Figure 18. 4.2 EXTERNAL INTERRUPTS External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power m ode. The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins, connected to the same interrupt vector, are configured as interrupts, their signals are logically NANDed before entering the edge/level detection block. Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of a NANDed source (as described on the I/O ports section), a low level on an I/O pin configured as input with interrupt, masks the interrupt request even in case of risingedge sensitivity. 4.3 PERIPHERAL INTERRUPTS Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: The I bit of the CC register is cleared. The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by: Writing "0" to the corresponding bit in the status register or Access to the status register while the flag is set followed by a read or write of an associated register. Note: the clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being enabled) will therefore be lost if the clear sequence is ex ec ut ed.

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INTERRUPTS (Cont'd) Figure 18. Interrupt Processing Flowchart
FROM RESET I BIT SET? Y N

N

INTERRUPT PENDING? Y

FETCH NEXT INSTRUCTION

N

IRET ? Y

ST ACK PC, X, A, CC SET I BIT LOAD PC FROM INTERRUPT VECTOR

EXECUTE INSTRUCTION

RESTORE PC, X, A, CC FROM ST ACK THIS CLEARS I BIT BY DEFAULT

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INTERRUPTS (Cont'd) Table 4. Interrupt Mapping
N Source Block RESET TRAP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 SPI TIMER A TIMER B MTC EI0 EI1 Reset Software Interrupt Not used External Interrupt Port A7..0 (C5..0*) External Interrupt Port B7..0 (C5..0*) Motor Control Interrupt (events: R, Z) Motor Control Interrupt (events: C, D) Motor Control Interrupt (events: E, O) SPI Peripheral Interrupts TIMER A Peripheral Interrupts TIMER B Peripheral Interrupts Not used Not used Not used Not Used Not Used Lowest Priority SPISR TASR TBSR MISR N/A yes yes no no no no no no Description Register Label N/A Priority Order Highest Priority Exit from HALT yes no Address Vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFFAh-FFFBh FFF8h-FFF9h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h FFE2h-FFE3h FFE0h-FFE1h

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5 POWER SAVING MODES
5.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, three main power saving modes are implemented in the ST7 (see Figure 19). After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (f CPU). From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the the oscillator status. Figure 19. Power saving mode consumption / transitions

HALT Low POWER CONSUMPTION

SLOW WAIT

WAIT

SLOW

RUN High

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POWER SAVING MODES (Cont'd) 5.2 HALT Mode The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the ST7 HALT instruction (see Figure 21). The MCU can exit HALT mode on reception of either an external interrupt or a reset (see Table 2). When exiting HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 20). Figure 20. HALT Mode timing overview
RUN HALT 4096 CPU CYCLE DELAY RUN

When entering HALT mode, the I bit in the CC Register is forced to 0 to enable interrupts. In the HALT mode the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator).

HALT INSTRUCTION

RESET OR INTERRUPT

FETCH VECTOR

Figure 21. HALT modes flow-chart

N HALT OSCILLATOR PERIPHERALS CPU I BIT OFF OFF OFF 0

WAT CHDOG ENABLE

Y

HALT INSTRUCTION

N

RESET Y

4096 clock cycles delay

N

EXTERNAL* INTERRUPT OSCILLATOR PERIPHERALS CPU ON O FF O FF

OSCILLATOR PERIPHERALS CPU

ON ON ON

Y

FETCH RESET VECTOR OR SERVICE INTERRUPT**

Notes:

* External interrupt or internal interrupts with Exit from Halt Mode capability * * Before servicing an interrupt, the CC register is pushed on the stack.

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POWER SAVING MODES (Cont'd) 5.3 WAIT Mode WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the "WFI" ST7 software instruction. All peripherals remain active. During WAIT mode, the I bit of the CC register are forced to 0, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 22. Figure 22. WAIT mode flow-chart 5.4 SLOW Mode This mode has two targets: To reduce power consumption by decreasing the internal clock in the device, To adapt the internal clock frequency (fCPU) to the available supply voltage. SLOW mode is controlled by the SMS bit in the MISCR register. This bit enables or disables Slow mode selecting the internal slow frequency (fCPU). In this mode, the oscillator frequency can be divided by 32 instead of 2 in normal operating mode. The CPU and peripherals are clocked at this lower frequency except the Motor Control and the SPI peripherals which have their own clock selection bit (XT16) in the MISCR register.

WFI INSTRUCTION

OSCILLATOR PERIPHERALS CPU I BIT

ON ON O FF 0

N

RESET Y if exit caused by a RESET, a 4096 CPU clock cycle delay is inserted.

N INTERRUPT Y

OSCILLATOR PERIPHERALS C PU

ON OFF* OFF

OSCILLATOR PERIPHERALS CPU

ON ON ON

FETCH RESET VECTOR OR SERVICE INTERRUPT**

Note:

* The peripheral clock is stopped only when exit caused by RESET and not by an interrupt. ** Before servicing an interrupt, the CC register is pushed on the stack.

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6 I/O PORTS
6.1 INTRODUCTION The I/O ports offer different functional modes: transfer of data through digital inputs and outputs and for specific pins: external interrupt generation alternate signal input/output for the on-chip peripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 6.2 FUNCTIONAL DESCRIPTION Each port has 2 main registers: Data Register (DR) Data Direction Register (DDR) and one optional register: Option Register (OR) Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is shown in Figure 23 6.2.1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Notes: 1. Writing the DR register modifies the latch value but does not affect the pin status. 2. When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. External interrupt function When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the Miscellaneous register. Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt source, these are logically NANDed. For this reason if one of the interrupt pins is tied low, it masks the other ones. In case of a floating input with interrupt configuration, special care must be taken when changing the configuration (see Figure 24). The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the Miscellaneous register must be modified. 6.2.2 Output Modes The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Tw o different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status:
DR 0 1 Push-pull VSS V DD Open-drain Vss Floating

6.2.3 Alternate Functions When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register. Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.

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I/O PORTS (Cont'd) Figure 23. I/O Port General Block Diagram
REGISTER ACCESS ALTERNATE OUTPUT 1 VDD 0 ALTERNATE ENABLE DR

P-BUFFER (see table below) PULL-UP (see table below) VDD

DDR PULL-UP CONFIGURATION If implemented OR SEL N-BUFFER DDR SEL CMOS SCHMITT TRIGGER ANALOG INPUT DIODES (see table below) PAD

OR

EXTERNAL INTERRUPT SOURCE (eix)

Table 5. I/O Port Mode Options
Configuration Mode Input Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) True Open Drain Pull-Up Off On Off NI P-Buffer Off On Off NI On On Diodes to VDD to VSS

Output

Legend: N I - not implemented Off - implemented not activated On - implemented and activated

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DATA BUS

DR SEL

1 0

ALTERNATE INPUT FROM OTHER BITS

POLARITY SELECTION

NI (see note)

Note: The diode to V DD is not implemented in the true open drain pads. A local protection between the pad and VSS is implemented to protect the device against positive stress.

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I/O PORTS (Cont'd) Table 6. I/O Port Configurations
Hardware Configuration
NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS VDD RPU PAD PULL-UP CONF IGURATION DR REGISTER ACCESS

DR REGISTER

W DATA BUS R

INPUT 1)

ALT ERNATE INPUT FROM OTHER PINS INTERRUPT CONFIGURATION POLARITY SELECTION ANALOG INPUT NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS

EXTERNAL INTERRUPT SOURCE (eix)

OPEN-DRAIN OUTPUT 2)

VDD RPU

DR REGIST ER ACCESS

PAD

DR REGISTER

R/W

DATA BUS

ALTERNATE ENABLE

ALTERNATE OUTPUT

PUSH-PULL OUTPUT 2)

NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS

VDD RPU

DR REGIST ER ACCESS

PAD

DR REGISTER

R/W

DATA BUS

ALTERNATE ENABLE

ALTERNATE OUTPUT

Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.

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I/O PORTS (Cont'd) CAUTION: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) sw itches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin. WARNING: The analog input voltage level must be within the limits stated in the absolute maximum ratings. 6.3 I/O PORT IMPLEMENTATION The hardware implementation on each I/O port depends on the settings in the DDR and OR registers

and specific feature of the I/O port such as ADC Input or true open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 24 Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. Figure 24. Interrupt I/O Port State Transitions
01
INPUT floating/pull-up interrupt

00
INPUT floating (reset state)

10
OUTPUT open-drain

11
OUTPUT push-pull

XX

= DDR, OR

The I/O port register configurations are summarized as follows.

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I/O PORTS (Cont'd) Interrupt Ports PA7:0, PB5:3 (with pull-up)
MODE floating input pull-up interrupt input open drain output push-pull output DDR 0 0 1 1 OR 0 1 0 1

True Open Drain Interrupt Ports PB2:0 (without pull-up)
MODE floating input floating interrupt input true open drain (high sink ports) DDR 0 0 1 OR 0 1 X

Table 7. Port Configuration
Input Port Port A Port B Pin name OR = 0 PA7:0 PB5:3 PB2:0 floating floating floating OR = 1 pull-up interrupt pull-up interrupt floating interrupt OR = 0 OR = 1 open drain push-pull open drain push-pull true open drain Output

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I/O PORTS (Cont'd) 6.3.1 Register Description DATA REGISTER (DR) Port x Data Register PxDR with x = A or B. Read / Write Reset Value: 0000 0000 (00h)
7 D7 D6 D5 D4 D3 D2 D1 0 D0

OPTION REGISTER (OR) Port x Option Register PxOR with x = A or B. Read / Write Reset Value: 0000 0000 (00h)
7 O7 O6 O5 O4 O3 O2 O1 0 O0

Bit 7:0 = D[7:0] Data register 8 bits. The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken into account even if the pin is configured as an input; this allows to always have the expected level on the pin when toggling to output mode. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input). DATA DIRECTION REGISTER (DDR) Port x Data Direction Register PxDDR with x = A or B. Read / Write Reset Value: 0000 0000 (00h)
7 DD7 DD6 DD5 DD4 DD3 DD2 DD1 0 DD0

Bit 7:0 = O[7:0] Option register 8 bits. For specific I/O pins, this register is not implemented. In this case the DDR register is enough to select the I/O pin configuration. The OR register allows to distinguish: in input mode if the pull-up with interrupt capability or the basic pull-up configuration is selected, in output mode if the push-pull or open drain configuration is selected. Each bit is set and cleared by software. Input mode: 0: floating input 1: pull-up input with or without interrupt Output mode: 0: output open drain (with P-Buffer unactivated) 1: output push-pull (when available)

Bit 7:0 = DD[7:0] Data direction register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bits is set and cleared by software. 0: Input mode 1: Output mode

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I/O PORTS (Cont'd) Table 8. I/O Port Register Map and Reset Values
Address (Hex.) Register Label 7 6 5 4 3 2 1 0

Reset Value of all IO port registers 0000h 0001h 0002h 0004h 0005h 0006h PADR PADDR PAOR PBDR PBDDR PBOR

0

0

0

0

0

0

0

0

MSB

LSB

MSB

LSB

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7 MISCELLANEOUS REGISTER
The miscellaneous register allows control over several different features such as the external interrupts or the I/O alternate functions. 7.1 I/O Port Interrupt Sensitivity Description The external interrupt sensitivity is controlled by the ISxx bits of the Miscellaneous register. This control allows to have two fully independent external interrupt source sensitivities as shown in Figure 25. Each external interrupt source can be generated on four different events on the pin: s F alli ng edge s Ri sing edge s F alli ng and rising edge s F alli ng edge and low level To guaranty correct functionality, a modification of the sensitivity in the MISCR register must be done only when the I bit of the CC register is set to 1 (interrupt masked). See I/O port register and Miscellaneous register descriptions for more details on the programming. Figure 25. External Interrupt Sensitivity
MI SC R IS01 IS00 EI0 INTERRUPT SOURCE

7.2 I/O Port Alternate Functions The MISCR register manages the SPI SS pin alternate function configuration. This makes it possible to use the PB2 I/O port function while the SPI is active. These functions are described in detail in Section 7.4 Miscellaneous Register Description. 7.3 Clock Prescaler Selection The MISCR register is used to select the SLOW mode (see Section 5.4 SLOW Mode for more details) and the SPI and Motor Control peripheral clock prescaler.

PA7

SENSITIVITY CONTROL

PA0

MI SC R IS11 IS10 EI1 INTERRUPT SOURCE

PB7

SENSITIVITY CONTROL

PB0

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MISCELLAN EOUS REGISTER (Cont'd) 7.4 Miscellaneous Register Description MISCELLAN EOUS REGISTER (MISCR) Read / Write Reset Value: 0000 0000 (00h)
7 XT16 SSM SSI IS11 IS10 IS01 IS00 0 SMS 0 0 1 0 1 Falling edge & low level Rising edge only Falling edge only Rising and falling edge 0 1 1

Bits 4:3 = IS1[1:0] EI1 sensitivity The interrupt sensitivity defined using the IS1[1:0] bits combination is applied to the EI1 external interrupts. These two bits can be written only when the I bit of the CC register is set to 1 (interrupt masked). EI1: Port B
IS11 IS10 External Interrupt Sensitivity

Bit 7 = XT16 MTC and SPI clock selection This bit is set and cleared by software. The maximum allowed frequency is 4MHz. 0: MTC and SPI clock supplied with fOSC/2 1: MTC and SPI clock supplied with fOSC/4 Bit 6 = SSM SS mode selection This bit is set and cleared by software. 0: Normal mode - the level of the SPI SS signal is the external SS pin. 1: I/O mode, the level of the SPI SS signal is read from the SSI bit. Bit 5 = SSI SS internal mode This bit replaces the SS pin of the SPI when the SSM bit is set to 1. (see SPI description). It is set and cleared by software.

Bits 2:1 = IS0[1:0] EI0 sensitivity The interrupt sensitivity defined using the IS0[1:0] bits combination is applied to the EI1 external interrupts. These two bits can be written only when the I bit of the CC register is set to 1 (interrupt masked). EI0: Port A
IS01 IS00 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge

Bit 0 = SMS Slow mode select This bit is set and cleared by software. 0: Normal mode. fCPU = fOSC / 2 1: Slow mode. fCPU = fOSC / 32 See sections on low power consumption mode and MCC for more details.

Table 9. Miscellaneous Register Map and Reset Values
Address (Hex.) 0020h Register Label MISCR Reset Value 7 XT16 0 6 SSM 0 5 SSI 0 4 IS11 0 3 IS10 0 2 IS01 0 1 IS00 0 0 SMS 0

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8 ON-CHIP PERIPHERALS
8.1 MOTOR CONTROLLER (MTC) 8.1.1 Introduction The ST7 Motor Controller (MTC) can be seen as a Pulse Width Modulator multiplexed on six output channels, and a Back Electromotive Force (BEMF) zero-crossing detector for sensorless control of Permanent Magnet Direct Current (PMDC) brushless motors. The MTC is particularly suited to driving synchronous motors and supports operating modes like: Commutation step control with motor voltage regulation and current limitation Commutation step control with motor current regulation, i.e. direct torque control Sensor or sensorless motor phase commutation control BEMF zero-crossing detection with high sensitivity. The integrated phase voltage comparator is directly referred to the full BEMF voltage without any attenuation. A BEMF voltage down to 200 mV can be detected, providing high noise immunity and self-commutated operation in a large speed range. Realtime motor winding demagnetization detection for fine-tuning the phase voltage masking time to be applied before BEMF monitoring. Automatic and programmable delay between BEMF zero-crossing detection and motor phase commutation. 8.1.2 Main Features s T wo on-chip analog comparators, one for BEMF zero-crossing detection with 100 mV hysteresis, the other for current regulation or limitation s F our selectable reference voltages for the hysteresis comparator (0.2 V, 0.6 V, 1.2 V, 2.5 V) s 8 -b it timer (MTIM) with two compare registers and two capture features s M easurem ent window generator for BEMF zero-crossing detection s Auto-calib ra ted prescaler with 16 division steps s 8 x8 -b it multiplier s Phase input multiplexer s Soph isti ca ted output management: The six output channels can be split into two groups (odd & even). The PWM signal can be multiplexed on even, odd or both groups, alternatively or simultaneously. The output polarity is programmable channel by channel. An software enabled bit (active low) forces the outputs in HiZ. An "emergency stop" input pin (active low) asynchronously forces the outputs in HiZ. Table 10. MTC Registers
Register MTIM MZPRV MZREG MCOMP MDREG MWGHT MPRSR MIMR MISR MCRA MCRB MPHST MPAR MPOL Description Timer Counter Register Capture Zn-1 Register Capture Zn Register Compare Cn+1 Register Demagnetization Register An Weight Register Prescaler & Sampling Register Interrupt Mask Register Interrupt Status Register Control Register A Control Register B Phase State Register Parity Register Polarity Register Page 67 67 67 67 67 67 67 68 68 69 70 71 71 71

8.1.3 Application Example This example shows a six-step command sequence for a 3-phase permanent magnet DC brushless motor (PMDC motor). Figure 27 shows the phase steps and voltage, while Table 11 shows the relevant phase configurations. To run this kind of motor efficiently, an autoswitching mode has to be used, i.e. the position of the rotor must self-generate the powered winding commutation. The BEMF zero crossing (Z event) on the non-excited winding is used by the MTC as a rotor position sensor. The delay between this event and the commutation is computed by the MTC and the commutation event Cn is automatically generated after this delay. After the commutation occurs, the MTC waits until the winding is completely demagnetized by the free-wheeling diode: during this phase the winding is tied to 0V or to the HV high voltage rail and no BEMF can be read. At the end of this phase a new BEMF zero-crossing detection is enabled. The end of demagnetization event (D), is also detected by the MTC or simulated with a timer compare feature when no detection is possible.

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MOTOR CONTROLLER (Cont'd) The MTC manages these three events always in the same order: Z generates C after a delay computed in realtime, then waits for D in order to enable the peripheral to detect another Z event. The speed regulation is managed by the microcontroller, by means of an adjustable reference current level in case of current control, or by direct PW M duty-cycle adjustment in case of voltage control.

All detections of Zn events are done during a short measurement window while the high side switch is turned off. For this reason the PWM signal is applied on the high side switches. When the high side switch is off, the high side winding is tied to 0V by the free-wheeling diode, the low side winding voltage is also held at 0V by the low side ON switch and the complete BEMF voltage is present on the third winding: detection is then possible.

Figure 26. Chronogram of Events (in Autoswitched Mode)
C event Z event DH event DS event Cn processing Wait for Cn Wait for Dn Wait for Z T Zn Dn Cn Z > Zn min C > Cn min

t Voltage on phase A

Voltage on phase B

Voltage on phase C BEMF sampling P signal when sampled (Output of the V DD analog MUX) V RE F (Threshold value for VSS Input comparator)

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MOTOR CONTROLLER (Cont'd) Figure 27. Example of Command Sequence for 6-step Mode (typical 3-phase PMDC Motor Control)
Step Switch 0 1 I1 2 3 I3 4 5 Node A
HV HV/2 0

1

2

3

4

5

6

1

2

3

HV

T0

T2 B I6

T4

I4

A I5

I2

C

T3

T5

T1

B

HV HV/2 0 HV HV/2 0

C

Note: Control & sampling PWM influence is not represented on these simplified chronograms. 1 2 3 4 5
HV

6

C2 D2
HV/2

C4

Superimposed voltage (BEMF induced by rotor) - approx. HV/2 (PWM on) - approx. 0V (PWM off)

0V

Z2 Demagnetization Commutation delay

D 5 Z5 t PWM off pulses

Wait for BEMF = 0

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MOTOR CONTROLLER (Cont'd) Table 11. Step Configuration Summary
Configuration BEMF BEMF Phase state edge input register Current direction High side Low side OO[5:0] bits in MPHST register Measurement done on: IS[1:0] bits in MPHST register Back EMF shape CPB bit in MCRB register (ZVD bit = 0) Voltage on measured point at the start of demagnetization Step 1 A to B T0 T5 100001 MCIC 10 Falling 0 0V

2 A to C T0 T1
000011 MCIB 01 Rising 1 HV

3 B to C T2 T1
000110 MCIA 00 Falling 0 0V

4 B to A T2 T3
001100 MCIC 10 Rising 1 HV

5 C to A T4 T3
011000 MCIB 01 Falling 0 0V

6 C to B T4 T5
110000 MCIA 00 Rising 1 HV

Hardware-software

demagnetization

Hardware or

HDM-SDM bits in MCRB register

10

11

10

11

10

11

Demagnetization

PWM side selection to accelerate Odd Side Even Side Odd Side Even Side Odd Side Even Side demagnetization switch Driver selection to accelerate demagnetization

T5

T0

T1

T2

T3

T4

For a detailed description of the MTC registers, see Section 8.1.7.

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MOTOR CONTROLLER (Cont'd) 8.1.4 Functional Description The MTC can be split into four main parts as shown in the simplified block diagram in Figure 28. The BEMF ZERO-CROSSING DETECTOR with a comparator and an input multiplexer. The DELAY MANAGER with an 8-bit timer (MTIM) and an 8x8 bit multiplier. The PWM MANAGER, including a measurement window generator, a mode selector and a current comparator. Figure 28. Simplified MTC Block Diagram

The CHANNEL MANAGER with the PWM multiplexer, polarity programming capability and emergency HiZ configuration input. 8.1.4.1 Input Detection Block This block can operate in sensor mode or sensorless mode. The mode is selected via the SR bit in the MCRA register. The block diagram is shown in Figure 29.

DELAY MANAGER

DELAY WEIGHT

CAPTURE Zn

MTIM TIMER

BEMF ZERO-CROSSING DETECTOR BEMF=0 [Z]

MCIA MCIB MCIC

Internal VREF DELAY = WEIGHT x Zn =? COMMUTE [C] MCO5 PHASE MEASUREMENT WINDOW GENERATOR (I) CURRENT VOLTAGE (V) (I) (V) MODE NMCES PWM (1) (V) (I) VDD MCCFI OCP1A MCO4 MCO3 MCO2 MCO1 MCO0

PWM MANAGER
Note 1: The PWM signal is generated by the ST7 16-bit Timer [Z] : Back EMF Zero-crossing event Zn : Time elapsed between two consecutive Z events [C] : Commutation event Cn : Time delayed after Z event to generate C event (I): Current mode (V): Voltage mode

CHANNEL MANAGER

R1ext (V) R2ext

Cext (I)

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MOTOR CONTROLLER (Cont'd) Input Pins The MCIA, MCIB and MCIC input pins can be used as analog pins in Sensorless mode or as digital pins in Sensor mode. In sensorless mode, the analog inputs are used to measure the BEMF zero crossing and to detect the end of demagnetization if required. In Sensor mode, they are connected to sensor outputs. Due to the presence of diodes, these pins can permanently support an input current of 5 mA. In Sensorless mode, this feature enables the inputs to be Figure 29. Input Stage
External Input Block Input Comparator Block MPHST Register Inputn Sel Reg MCIA A MCIB B MCIC C 00 C P +
DQ

connected to each motor phase through a single resistor. Note: In high voltage applications, in Sensorless mode and for certain motors and power topologies (with parasitic capacitance or other), it may be required to add external pull-up Schottky 0.4 V (e.g. BAT48) diodes on the MCIA, MCIB and MCIC pins. A multiplexer, programmed by the IS[1:0] bits in MPH ST register selects the input pins and connects them to the rotor position control logic in either Sensorless or Sensor mode.

Event Detection

IS[1:0]

01

Sample
CP

10

VREF
2

DS,H C

1

MCRB Register VR[1:0]
Freq (T=1.25s) for demagnetization and sensors Sampling frequency 16-bit Timer PWM
Notes:
Reg Regn I V C Z DS,H E R O
1

I V

MCRA Register V0C1 bit
Updated/Shifted on R Updated with Regn+1 on C

* = Preload register, changes taken into account at next C event.

MPAR Register DS,H C Sample
2

MCRB Register MPAR Register CPBn bit* ZVD bit 20 s / D
or or or

Current Mode Voltage Mode ev en ts : Commutation BEFM Zero-crossing End Of Demagnetization Eme rgen cy Stop Ra tio Updated (+1 or -1) Mu lt ip lie r Overflow Branch taken after C event Branch taken after D event

REO bit

Z

20 s / C
1
or

MCRA Register SR bit DH

+/-

2

CPBn bit*

HDMn bit*

MCRB Register

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MOTOR CONTROLLER (Cont'd) Sensorless Mode This mode is used to detect BEMF zero crossing and end of demagnetization events. The analog phase multiplexer connects the nonexcited motor winding to an analog 100mV hysteresis comparator referred to a selectable reference voltage. The VR[1:0] bits in the MCRB register select the reference voltage from four internal values depending on the noise level and the application voltage supply. BEMF detections are performed during the measurement window, when the excited windings are free-wheeling through the low side switches and diodes. At this stage the common star connection voltage is near to ground voltage (instead of V DD/2 when the excited windings are powered) and the complete BEMF voltage is present on the non-excited winding terminal, referred to the ground terminal. The zero crossing sampling frequency is then defined, in current mode, by the measurement window generator frequency (SA[3:0] bits in the MPRSR register) or, in voltage mode, by the 16-bit Timer PWM frequency and duty cycle. Table 12. ZVD and CPB Edge Selection Bits
ZVD bit CPB bit 20-s filter 0 0 Event generation vs input data sampled 20-s filter

During a short period after a phase commutation (C event), the winding is no longer excited but needs a demagnetisation phase during which the BEMF cannot be read. A demagnetization current goes through the free-wheeling diodes and the winding voltage is stuck at the high voltage or to the ground terminal. For this reason an "end of demagnetization event" D must be detected on the winding before the detector can sense a BEMF zero crossing. For the end-of-demagnetization detection, no special PWM configuration is needed, the comparator sensing is done at a fixed 800kHz sampling frequency. So, the three events: C (commutation), D (demagnetization) and Z (BEMF zero crossing) must always occur in this order. The comparator output is processed by a detector that automatically recognizes the D or Z event, depending on the CPB or ZVD edge and level configuration bits as described in Table 12. A 20-s filter after a C event disables a D event if spurious spikes occur. Another 20-s filter after a D event disables a Z event if spurious spikes occur.

C
20-s filter 0 1

DH
20-s filter

Z

C
20-s filter 1 0

DH
20-s filter

Z

C
20-s filter 1 1

DH
20-s filter

Z

C

DH

Z

Note: The ZVD bit is located in the MPAR register, the CPB bit is in the MCRB register.

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MOTOR CONTROLLER (Cont'd) Demagnetization (D) Event At the end of the demagnetization phase, current no longer goes through the free-wheeling diodes. The voltage on the non-excited winding terminal goes from one of the power rail voltages to the common star connection voltage plus the BEMF voltage. In some cases (if the BEMF voltage is positive and the free-wheeling diodes are at ground for example) this end of demagnetization can be seen as a voltage edge on the selected MCIx input and it is called a hardware demagnetization event D H. See Table 12. If enabled by the HDM bit in the MCRB register, the current value of the MTIM timer is captured in register MDREG when this event occurs in order to be able to simulate the demagnetization phase for the next steps. When enabled by the SDM bit in the MCRB register, demagnetization can also be simulated by comparing the MTIM timer with the MDREG register. This kind of demagnetization is called software demagnetization D S. If the HDM and SDM bits are both set, the first event that occurs, triggers a demagnetization event. For this to work correctly, a D S event must Figure 30. D Event Generation Mechanism
DS,H C Sample
2 1
or

not precede a DH event because the latter could be detected as a Z event. Software demagnetization can also be always used if the HDM bit is reset and the SDM bit is set. This mode works as a programmable masking time between the C and Z events. To drive the motor securely, the masking time must be always greater than the real demagnetization time in order to avoid a spurious Z event. When an event occurs, (either DH or DS) the DI bit in the MISR register is set and an interrupt request is generated if the DIM bit of register MIMR is set. Warning 1: Due to the alternate automatic capture and compare of the MTIM timer with MDREG register by DH and DS events, the MDREG register should be manipulated with special care. Warning 2: To avoid a system stop, the value written to the MDREG register in Soft Demagnetization Mode (SDM = 1) should always be: Greater than the MCOMP value of the commutation before the related demagnetization Greater than the value in the MTIM counter at that moment (when writing to the MDREG register).

MTIM [8-bit Up Counter]§ 8 To Z event detection 20 s / C MCRA Register
SR bit

DH MDREG [Dn]§ Compare

DH
CPBn bit* HDM n bit*

MCRB Register SDM bit

20s / C

MCRB Register

DS DH HDM bit SDM bit

DS F(x) D = DH & HDM bit + DS & SDM bit D

updated on R event * = Preload register, changes taken into account at next C event

§ Register

To interrupt generator

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MOTOR CONTROLLER (Cont'd) Table 13. Demagnetisation (D) Event Generation (example for ZVD=0)
HDM bit Meaning CPB bit = 1 CPB bit = 0 (Even ) (Odd ) D = DS = Output Compare [MDREG, MTIM registers] Undershoot due to motor parasite or first sampling 2
HVV HV

Weak / null undershoot and BEMF positive 2
HVV

5 DS C

C Software Mode 0 (SDM bit =1 and HDM bit = 0)
HV/2

DS

( *)
HV/2

DS

C
HV/ 2

( *)

(*)

0V

0V

0V

Z D = D H + DS

Z

Z D = DH (Hardware detection only)

(Hardware detection or Output compare true) Undershoot due to Weak / null motor parasite or first undershoot and sampling BEMF positive 2 2
HV HV

5
HV

C 1 Hardware/Simulated Mode (SDM bit = 1 and HDM bit = 1)
HV/2

DS

C

( *)
HV/2

DS

C
HV/ 2

( *)

(*)

0V

0V

0V

DH

Z

Z

DH

Z

(*) Note: This is a zoom to the additional voltage induced by the rotor (Back EMF)

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MOTOR CONTROLLER (Cont'd) BEMF Zero Crossing (Z) Event When both C and D events have occurred, the PW M may be switched to another group of outputs (depending on the OS[2:0] bits in the MCRB register) and the real BEMF zero crossing sampling can start (see Figure 32). A BEMF voltage is present on the non-powered terminal but referred to common star connection of the motor whose voltage is equal to V DD/2. When a winding is free-wheeling (during PWM offtime) its terminal voltage changes to the other power rail voltage, that means if the PWM is applied on the high side driver, free-wheeling will be done through the high side diode and the terminal will be 0V. This is used to force the common star connection to 0V in order to read the BEMF referred to the ground terminal. Figure 31. Sampling and Zero Crossing Blocks Output of hysteresis comparator Freq. (T=1.25us) for Demagnetization and Sensor
1

Consequently, BEMF reading (i.e. comparison with a voltage close to 0V) can only be done when the PWM is applied on the high side drivers. For this reason the MTC outputs can be split in two groups called ODD and EVEN and the BEMF reading will be done only when PWM is applied on one of these two groups. The REO bit in the MPAR register is used to select the group to be used for BEMF sensing (high side group) Refer to Table 15 for an overview of when a BEMF can be read depending on REO bit, PWM mode and function mode of peripheral. Depending on the edge and level selection (ZVD and CPB) bits and when PWM is applied on the correct group, a BEMF zero crossing detection sets the ZI bit in the MISR register and generates an interrupt if the ZIM bit is set. The Z event also triggers some timer/multiplier operations, for more details see Section 8.1.4.2

Sample
DQ C P

Sampling frequency 16-bit Timer PWM
Notes:
Reg Regn I V C Z DS,H E R+/O
1

I V
MCRA Register

2

DS,H C

V0C1 bit
Updated/Shifted on R Updated with Regn+1 on C

MPAR Register DS,H C REO bit

MCRB Register MPAR Register CPBn bit* ZVD bit 20s / D
or or or

Current M de o Voltage M de o events: Commutation BEFM Zero-crossing End Of Demagnetization Em rgency Stop e Ratio Updated (+1 or -1) M ltiplier Overflow u Branch taken after C event Branch taken after D event

Sample

2 1

Z SR bit MCRA Register

To D detection

2

* = Preload register, changes taken into account at next C event.

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MOTOR CONTROLLER (Cont'd) Sensor Mode In sensor mode, the rotor position information is given to the peripheral by means of logical data on the three inputs MCIA, MCIB and MCIC. For each step one of these three inputs is selected (IS[1:0] bits in register MPHST) in order to detect the Z event. In this case Demagnetization has no meaning and the relevant features such as the special PWM configuration, D S or DH management, 20-s filter; are not available (see Table 14). For this configuration the rotor detection doesn't need a particular phase configuration to validate the measurement and a Z event can be read from any detection window. A fixed sampling frequency (800 kHz) is used, that means the Z event and position sensoring is more precise than it is in sensorless mode. Table 14. Sensor mode selection
SR bit 0 1 Mode Sensors not used Sensors used OS2 bit use Enabled Disabled Event detection sampling clock D: Clock 1.25s Z: SA&OT config. Z: Clock 1.25s Filtering 20s after C for D event 20s after D for Z event 20s after C for Z event Behaviour of the output PWM "Before D" behaviour & "after D" behaviour Only "after D" behaviour

The minimum off time for current control PWM is also reduced to 1.25s. Procedure for reading sensor inputs in Direct Access mode: In Direct Access mode, the peripheral clock is disabled as shown in Table 25. As the data present on the selected input is synchronized by a 800 kH z clock, the sensor can't be read directly (the value is latched). To read the sensor data the following steps have to be performed: 1. Select the appropriate MCIx input pin by means of the IS[1:0] bits in the MPHST register 2. Switch from direct access mode to indirect access mode in order to latch the sensor data (DAC bit in MCRA register). 3. Switch back to direct access mode. 4. Read the comparator output (HST bit in the MIMR register)

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MOTOR CONTROLLER (Cont'd) Figure 32. Functional Diagram of Z Detection after D Event
DS or DH

Begin

20s Filter turned on Switch Sampling Clock[D] -> Sampling Clock[Z]

Side change on Output PWM ? Yes

No

Change the side according to OS[2:0]

Wait for next sampling clock edge

Read enable by REO ? Yes

No

Filter off ? Yes Read enabled

No

End

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MOTOR CONTROLLER (Cont'd) Table 15. Modes permitting BEMF reading after Demagnetization (D event)
SR bit (Sensor/ Demagnetization Sensorless Mode) V0C1 bit (Voltage/ Current Mode) OS[2:0] bits (PWM Output Config.) x00 REO bit Significant (Read PWM BEMF on Group Even/Odd group) Even 0

BEMF reading permitted after D event when:

x01 1 x10

Odd

1

Even

0

x10

Odd

1

000 After D event

Even

0

0

001

Odd

1

100 0 101

Even

0

Odd

1

110

Even

0

110

Odd Even and Odd Odd or Even

1

x 1 Not Used x

x11 xxx

x x

Other cases

Sensorless mode, Current Mode, PWM output only on Even group and BEMF read on Even group Sensorless mode, Current Mode, PWM output only on Odd group and BEMF read on Odd group Sensorless mode, Current Mode, PWM output on alternate groups but BEMF read only on Even group Sensorless mode, Current Mode, PWM output on alternate groups but BEMF read only on Odd group Sensorless mode, Voltage Mode, PWM output only on Even group and BEMF read on Even group Sensorless mode, Voltage Mode, PWM output only on Odd group and BEMF read on Odd group Sensorless mode, Voltage Mode, PWM output only on Even group and BEMF Read on Even group Sensorless mode, Voltage Mode, PWM output only on Odd group and BEMF Read on Odd group Sensorless mode, Voltage Mode, PWM output on alternate groups but BEMF read only on Even group Sensorless mode, Voltage Mode, PWM output on alternate groups but BEMF read on Odd group Sensorless mode, Current or Voltage Mode, PWM output on both groups, BEMF read on either group Sensor Mode, in any PWM output configuration, BEMF read on either group BEMF reading forbidden

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MOTOR CONTROLLER (Cont'd) 8.1.4.2 Delay Manager Figure 33. Overview of MTIM Timer
Tratio ck 8-bit Up Counter MTIM§ 8 Z MZREG [Zn]§ Z MZPRV [Zn-1]§ DH MDREG [Dn]§
c lr
1 0

MCRA register SWA bit
Z C

Compare MCRB register SDM bit MCOMP [Cn+1]§

20s/C
DS

Compare C C DS,H
§

To interrupt generator To interrupt generator To interrupt generator

= Register updated on R event

Z

This part of the MTC contains all the time-related functions, its architecture is based on an 8-bit shift left/shift right timer shown in Figure 33. The MTIM timer includes: An auto-updated prescaler A capture/compare register for software demagnetization simulation (MDREG) Two cascaded capture register (MZREG and MZPRV) for storing the times between two consecutive BEMF zero crossings (Z events) An 8x8 bit multiplier for auto computing the next commutation time One compare register for phase commutation generation (MCOMP) The MTIM timer module can work in two main modes. In switched mode the user must process the step duration and commutation time by software, in autoswitched mode the commutation action is performed automatically depending on the rotor position information and register contents.

Table 16. Switched and Autoswitched Modes SWA bit
0 1

Commutation Type Switched mode Autoswitched mode

MCOMP User access Read/Write Read only

Switched Mode This feature allows the motor to be run step-bystep. This is useful when the rotor speed is still too low to generate a BEMF. It can also run other kinds of motor without BEMF generation such as induction motors or switch reluctance motors. This mode can also be used for autoswitching with all computation for the next commutation time done by software (hardware multiplier not used) and using the powerful interrupt set of the peripheral. In this mode, the step time is directly written by software in the commutation compare register MCOMP. When the MTIM timer reaches this value a commutation occurs (C event) and the MTIM timer is reset.

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MOTOR CONTROLLER (Cont'd) At this time all registers with a preload function are loaded (registers marked with (*) in Section 8.1.7). The CI bit of MISR is set and if the CIM bit in the MISR register is set an interrupt is generated. An overflow of the MTIM timer generates an RPI interrupt if the RIM bit is set. The MTIM timer prescaler (Step ratio bits ST[3:0] in the MPRSR register) is user programmable. Access to this register is not allowed while the MTIM timer is running (access is possible only before the starting the timer by means of the MOE bit) but the prescaler contents can be incremented/decremented at the next commutation event by setting the RMI (decrement) or RPI (increment) bits in the MISR register. When this method is used, at the next commutation event the prescaler value will be Table 17. Step Ratio Update
MOE bit SWA bit Clock State 0 1 1 x 0 1 Disabled Enabled Enabled Always possible Read

updated but also all the MTIM timer-related registers will be shifted in the appropriate direction to keep their value. After it has been taken into account, (at commutation) the RPI or RMI bit is reset. See Table 17. Only one update per step is allowed, so if both RPI and RMI are set together, RPI is taken into account at the next commutation and RMI is used one commutation latter. In switched mode, BEMF and demagnetization detection are already possible in order to pass in autoswitched mode as soon as possible but Z and D events do not affect the timer contents. Warning: In this mode, MCOMP must never be written to 0.

Ratio Increment Ratio Decrement (Slow Down) (Speed-Up) Write the ST[3:0] value directly in the MPRSR register Set RPI bit in the MISR register Set RMI bit in the MISR register till next commutation till next commutation Automatically updated according to MZREG value

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MOTOR CONTROLLER (Cont'd) Figure 34. Step Ratio Functional Diagram
4MHz R+ +1 MPRSR Register MTIM Timer = FFh? 4 1 / 2Ratio Zn < 55h? RTratio ck 2 MHz - 62.5 Hz MTIM Timer control over Tratio and register operation 1/2

ST[3:0] Bits

-1

MTIM Timer Overflow

Z Capture with MTIM Timer Underflow (Zn < 55h)

Begin

Begin

No Ratio < Fh? Ratio > 0?

No

Yes Ratio = Ratio + 1 Zn = Zn / 2 Zn+1 = Zn+1/2 Dn = Dn/2 Counter = Counter/2 Re-compute Cn

Yes Ratio = Ratio - 1 Zn = Zn x 2 Zn+1 = Zn+1 x 2 Dn = Dn x 2 Counter = Counter x 2 Compute Cn

End

End

Slow-down control

Speed-up control

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MOTOR CONTROLLER (Cont'd) Autoswitched Mode In this mode the MCOMP register content is automatically computed in real time as described below and in Figure 35. This register is READ ONLY. The C event has no effect on the contents of the MTIM timer. When a Z event occurs the MTIM timer value is captured in the MZREG register, the previous captured value is shifted into the MZPRV register and the MTIM timer is reset. See Figure 26. One of these two registers (depending on the DCB bit in the MCRA register) is multiplied with the contents of the MWGHT register and divided by 32. The result is loaded in the MCOMP compare register, which automatically triggers the next commutation (C event) Table 18. Multiplier Result
DCB bit 0 1 Commutation Delay MCOMP = MWGHT x MZPRV / 32 MCOMP = MWGHT x MZREG / 32

When an overflow occurs during the multiply operation, FFh is written in the MCOMP register and an interrupt (O event) is generated if enabled by the OIM bit in the MIMR register. Figure 35. Commutation Processor Block
MZREG [Zn]§ Z MZPRV [Zn-1]§ MCRA Register DCB bit MWGHT [an+1] 8 A x B / 32 MCRA Register SWA bit 8 MCOMP [Cn+1]§
§

n-1

n

8

O

To interrupt generator

3 set

When the timer reaches this value an RPI interrupt is generated (timer overflow). After each shift operation the multiply is recomputed for greater precision. Using either the MZREG or MZPRV register depends on the motor symmetry and type. The MWGHT register gives directly the phase shift between the motor driven voltage and the BEMF. This parameter generally depends on the motor and on the speed. Auto-updated Step Ratio Register: In switched mode, the MTIM timer is driven by software only and any prescaler change has to be done by software (see Section 8.1.4.2 for more details). In autoswitched mode an auto-updated prescaler always configures the MTIM timer for best accuracy. Figure 34 shows process of updating the Step Ratio bits: When the MTIM timer value reaches FFh, the prescaler is automatically incremented in order to slow down the MTIM timer and avoid an overflow. To keep consistent values, the MTIM register and all the relevant registers are shifted right (divided by two). The RPI bit in the MISR register is set and an interrupt is generated (if RIM is set). When a Z-event occurs, if the MTIM timer value is below 55h, the prescaler is automatically decremented in order to speed up the MTIM timer and keep precision better than 1.2%. The MTIM register and all the relevant registers are shifted left (multiplied by two). The RMI bit in the MISR register is set and an interrupt is generated if RIM is set. If the prescaler contents reach the value 0, it can no longer be automatically decremented, the MTC continues working with the same prescaler value, i.e. with a lower accuracy. No RMI interrrupt can be generated. If the prescaler contents reach the value 15, it can no longer be automatically incremented. When the timer reaches the value FFh, the prescaler and all the relevant registers remain unchanged and no interrupt is generated, the timer clock is disabled, and its contents stay at FFh The PWM is still generated and the D and Z detection circuitry still work, enabling the capture of the maximum timer value. The automatically updated registers are: MTIM, MZREG, MZPRV, MCOMP and MDREG. Access to these registers is summarised in Table 21.

= Register updated on R event

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MOTOR CONTROLLER (Cont'd) Table 19. MTIM Timer-related Registers
Name MTIM MZPRV MZREG MCOMP MDREG Reset Value 00h 00h 00h 00h 00h Contents Timer Value Capture Zn-1 Capture Zn Compare Cn+1 Demagnetization Dn

These configuration bits are: CPB, HDM, SDM and OS2 in the MCRB register and IS[1:0], OO[5:0] in the MPHST register. Note on initializing the MTC: As shown in Table 21 all the MTIM timer registers are in read-write mode until the MTC clock is enabled (with the MOE and DAC bits). This allows the timer, prescaler and compare registers to be properly initialized for start-up. In sensorless mode, the motor has to be started in switched mode until a BEMF voltage is present on the inputs. This means the prescaler ST[3:0] bits and MCOMP register have to be modified by software. When running the ST[3:0] bits can only be incremented/decremented, so the initial value is very important. When starting directly in autoswitched mode (in sensor mode for example), write an appropriate value in the MZREG and MZPRV register to perform a step calculation as soon as the clock is enabl ed.

Note on using the auto-updated MTIM timer: The auto-updated MTIM timer works accurately within its operating range but some care has to be taken when processing timer-dependent data such as the step duration for regulation or demagnetization. For example if an overflow occurs when calculating a software end of demagnetization (MCOMP+demagnetisation_time>FFh), the value that stored in MDREG will be: 7Fh+(MCOMP+demagnetization_time-FFh)/2. Note on commutation interrupts: It is good practice to modify the configuration for the next step as soon as possible, i.e within the commutation interrupt routine. All registers that need to be changed at each step have a preload register that enables the modifications for a complete new configuration to be performed at the same time (at C event in normal mode or when writing the MPHST register in direct access mode).

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MOTOR CONTROLLER (Cont'd) The Figure 36 gives the step ratio register value (left axis) and the number of BEMF sampling during one electrical step with the corresponding accuracy on the measure (right axis) as a function of the mechanical frequency. For a given prescaler value (step ratio register) the mechanical frequency can vary between two fixed values shown on the graph as the segment ends. In autoswitched mode, this register is automatically incremented/decremented when the step frequency goes out of this segment.

At fcpu=4MHz, the range covered by the Step Ratio mechanism goes from 2.39 to 235000 (pole pair x rpm) with a minimum accuracy of 1.2% on the step period. To read the number of samples for Zn within one step (right Y axis), select the mechanical frequency on the X axis and the sampling frequency curve used for BEMF detection (PWM frequency or measurment window frequency). For example, for N.Frpm = 15,000 and a sampling frequency of 20kHz, there are approximately 10 samples in one step and there is a 10% error rate on the measurem ent .

Figure 36. Step Ratio Bits decoding and accuracy results and BEMF Sampling Rate
avg Zn ~ 55h 1.2%

ST[3:0] Step Ratio (Decimal)

av g Zn ~ 7Fh 0.6% avg Zn ~ FFh 0.4%

BEMF samples

Zn/Zn

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
avg Zn ~ FFh 0.4% Fn F n+1 = 2.Fn

1 100%

avg Zn ~ 55h 1.2%

200 Hz 20 kHz
3.Fn+1 = 6.Fn

avg Zn ~ 7Fh 0.6% 3.Fn

2

50%

4

10

10% 0%

N.Frpm
76.6 115 153 230 306 460 614 920 1230 1840 2450 3680 4900 7350 9800 14700 19600 29400 39200 58800 78400 118000 1 157000 235000 2.39 4.79 7.18 9.57 14.4 19.1 28.7 38.3 57.4

Fstep = 6.N.Frpm = N.F / 10 N.F = 10.Fstep
Fstep: Electrical step frequency N: Pole pair number

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MOTOR CONTROLLER (Cont'd) Table 20. Step Frequency/Period Range
Step Ratio Bits ST[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Maximum Step Frequency 23.5 kHz 11.7 kHz 5.88 kHz 2.94 kHz 1.47 kHz 735 Hz 367 Hz 183 Hz 91.9 Hz 45.9 Hz 22.9 Hz 11.4 Hz 5.74 Hz 2.87 Hz 1.43 Hz 0.718 Hz Minimum Step Frequency 7.85 kHz 3.93 kHz 1.96 kHz 980 Hz 490 Hz 245 Hz 123 Hz 61.3 Hz 30.7 Hz 15.4 Hz 7.66 Hz 3.83 Hz 1.92 Hz 0.958 Hz 0.479 Hz 0.240 Hz Minimum Step Period 42.5 s 8 5 s 170 s 340 s 680 s 1.36 ms 2.72 ms 5.44 ms 10.9 ms 21.8 ms 43.6 ms 87 ms 174 ms 349 ms 697 ms 1.40 s Maximum Step Period 127.5 s 2 55 s 510 s 1.02 ms 2.04 ms 4.08 ms 8.16 ms 16.32 ms 32.6 ms 65.2 ms 130 ms 261 ms 522 ms 1.04 s 2.08 s 4.17 s

Table 21. Modes of Accessing MTIM Timer-Related Registers
RST bit 0 State of MCRA Register Bits SWA bit MOE bit Mode 0 0 Configuration Mode Access to MTIM Timer Related Registers Read Only Access Read / Write Access MTIM, MZPRV, MZREG, MCOMP, MDREG, ST[3:0] MCOMP, MDREG, MTIM, MZPRV, MZREG, ST[3:0] RMI bit of MISR: 0: No action 1: Decrement ST[3:0] RPI bit of MISR: 0: No action 1: Increment ST[3:0] MTIM, MZPRV, MZREG, MCOMP, MDREG, ST[3:0] MDREG,RMI, RPI bit of MISR: Set by hardware, (increment ST[3:0]) Cleared by software

0

0

1

Switched Mode

0 0

1 1

0 1

Emergency Stop Autoswitched Mode MTIM, MZPRV, MZREG, MCOMP, ST[3:0]

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MOTOR CONTROLLER (Cont'd) 8.1.4.3 PWM Manager The PWM manager controls the motor via the six output channels in voltage mode or current mode depending on the V0C1 bit in the MCRA register. A block diagram of this part is given in Figure 37. Voltage Mode In Voltage mode (V0C1 bit = "0"), the PWM is generated by the 16-bit A Timer. Its duty cycle is programmed by software (refer to the chapter on the 16-bit Timer) as required by the application (speed regulation for example). The current comparator is used for safety purposes as a current limitation. For this feature, the detected current must be present on the MCCFI pin and the current limitation must be present on pin OCP1A. This current limitation is fixed by a voltage reference depending on the maximum current acceptable for the motor. This current limitation is generated with the V DD voltage by means of an external divider but can also be adjusted with an external reference voltage ( 3.7 V). The external components are adjusted by the user depending on the application needs. In Voltage mode, it is mandatory to set a current limitation. In sensorless mode the BEMF zero crossing is done during the PWM off time. Figure 37. Current Feedback

The PWM signal is directed to the channel manager that connects it to the programmed outputs (See Figure 39). Current Mode In current mode, the PWM output signal is generated by a combination of the output of the measurement window generator (see Figure 38) and the output of the current comparator, and is directed to the output channel manager as well (Figure 39) . The current reference is provided to the comparator by the PWM output of the 16-bit Timer (0.25% accuracy), filtered through a RC filter (external capacitor on pin OCP1A and an internal voltage divider 30K and 70K). The detected current input must be present on the MCCFI pin. To avoid spurious commutations due to parasitic noise after switching on the PWM, a 2.5-s filter can be applied on the comparator output by setting the CFF bit in the MCRB register. The On state of the resulting PWM starts at the end of the measurement window (rising edge), and ends either at the beginning of the next measurement window (falling edge), or when the current level is reached.

16-bit Timer - PWM

MCRA Register V0C1 bit (V) VDD R1ext (I) MCCFI OCP1A (V) C EXT R2ext + VCREF (I) R1 R2

MCRA Register CFF bit

Sampling frequency

2.5-s Filter To Phase State Control

Common Mode = VDD - (1,4...1,0)V VCREF MAX = VDD - 1,3 V Power down mode

LEGEND: (I): Current mode (V): Voltage mode

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MOTOR CONTROLLER (Cont'd) The measurement window frequency can be programmed between 195Hz and 25KHz by the means of the SA[3:0] bits in the MPRSR register. In sensorless mode this measurement window can be used to detect either End of Demagnetization or BEMF zero crossing events. Its width can be defined between 5s and 30s in sensorless mode by the OT[1:0] bits in the MPOL register. In sensor mode (SR=1) this off time is fixed at 1.25s. Table 22. Off-Time Table
OT1 bit 0 0 1 1 OT0 bit 0 1 0 1 Off-Time Sensorless Mode (SR bit=0) 5 s 10 s 15 s 30 s Off-Time Sensor Mode (SR bit =1) 1.25 s

Table 23. Sampling Frequency Selection
SA3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SA2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SA1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SA0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Sampling Frequency 25.0 KHz 20.0 KHz 18.1 KHz 15.4 KHz 12.5 KHz 10.0 KHz 6.25 KHz 3.13 KHz 1.56 KHz 1.25 KHz 1.14 KHz 961 Hz 781 Hz 625 Hz 390 Hz 195 Hz

Figure 38. Sampling clock generation block
MPRSR Register SA[3:0] bits 4 4 MHz1 Frequency logic Off-Time logic 2 OT[1:0] bits MPOL Register (1) The MTC controller input frequency must always be 4 MHz, whatever the crystal frequency is. The appropriate internal frequency can be selected in the Miscellaneous register. R S Toff Q Tsampling

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MOTOR CONTROLLER (Cont'd) 8.1.4.4 Channel Manager The channel manager consists of: A Phase State register with preload and polarity function A multiplexer to direct the PWM to the odd and/ or even channel group A tristate buffer asynchronously driven by an emergency input. The block diagram is shown in Figure 39.

MPH ST Phase State Register A preload register enables software to asynchronously update (during the previous commutation interrupt routine for example) the channel configuration for the next step: the OO[5:0] bits in the MPH ST register are copied to the Phase register on a C event. Table 24. Output State
OP[5:0] bit 0 0 1 1 OO[5:0] bit 0 1 0 1 MCO[5:0] Pin 1 (OFF) 0-(PWM allowed) 0 (OFF) 1-(PWM allowed)

Figure 39. Channel Manager Block Diagram
MCRA Register V0C1 bit 16-bit Timer PWM 16-bit timer PWM V Sampling frequency Current comparator output MCRA Register CFF bit MCRA Register DAC bit C MPHST Register OO bits* MPAR Register OE[5:0] bits 6 6 Channel [5:0] Phasen Register* SQ I I V
Notes:
Reg Regn I V Updated/Shifted on R Updated with Regn+1 on C

Current M de o Voltage M de o

2.5-s Filter

R

events: C Commutation Z BEFM Zero-crossing DS H End Of Demagnetization , E Em rgency Stop e R+/- Ratio Updated (+1 or -1) O Multiplier Overflow
1

Branch taken after C event Branch taken after D event

2

MCRA Register SR bit

3

MCRB Register OS[2:0] bits*

MPOL Register OP[5:0] bits MRCA Register MOE bit

x6 6 x6 1

MCO4

NMCES

MCO1

MCO5

MCO3

* = Preload register, changes taken into account at next C event.

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MCO2

MCO0

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MOTOR CONTROLLER (Cont'd) Direct access to the phase register is also possible when the DAC bit in the MCRA register is set. Table 25. DAC and MOE Bit Meaning
MOE bit 0 1 1 DAC bit x 0 1 Effect on Effect on MTIM Output Timer High Z Clock disabled Standard runStandard running mode ning mode MPHST value same as MPOL Clock disabled value

The polarity register is used to match the polarity of the power drivers keeping the same control logic and software. If one of the OPx bits in the MPOL register is set, this means the switch x is ON when MCOx is VDD. Each output status depends also on the momentary state of the PWM, its group (odd or even), and the peripheral state. PW M Features The outputs can be split in two PWM groups in order to differentiate the high side and the low side sw itches. This output property can be programmed using the OE[5:0] bits in the MPAR register Table 26. Meaning of the OE[5:0] Bits
OE[5:0] 0 1 Channel group Even channel Odd channel

The OS[2:0] bits in the MCRB register allow the PWM configuration to be configured for each case as shown in Figure 41, Figure 42 and Figure 40. This configuration depends also on the current/ voltage mode (V0C1 bit in the MCRA register) because the OS[2:0] have not the same meaning in voltage mode and in current mode. During demagnetization, the OS2 bit is used to control PWM mode, and it is latched in a preload register so it can be modified when a commutation event occurs. The OS[1:0] bits are used to control the PWM between the D and C events. Warning: In Voltage Mode the OS[2:0] bits have a special configuration value: OS[2:0] = 010. In this mode, there is NO current limitation and NO PWM applied to active outputs. The active outputs are always at 100% whether in demagnetization, or normal mode. Note about demagnetization speed-up: during demagnetization the voltage on the winding has to be as high as possible in order to reduce the demagnetization time. Software can apply a different PWM configuration on the outputs between the C and D events, to force the free wheeling on the appropriate diodes to maximize the demagnetization voltage. Emergency Feature When the NMCES pin goes low The tristate output buffer is put in HiZ asynchronous l y The MOE bit in the MCRA register is reset An interrupt request is sent to the CPU if the EIM bit in the MIMR register is set This bit can be connected to an alarm signal from the drivers, thermal sensor or any other security c om ponent . This feature functions even if the MCU oscillator is off.

The multiplexer directs the PWM to the upper channel, the lower channel or both of them alternatively or simultaneously according to the peripheral state. This means that the PWM can affect any of the upper or lower channels allowing the selection of the most appropriate reference potential when freewheeling the motor in order to: Improve system efficiency Speed up the demagnetization phase Enable Back EMF zero crossing detection.

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MOTOR CONTROLLER (Cont'd) Figure 40. Step Behaviour of one Output Channel MCO[n] in Voltage Mode
(Voltage Mode without polarity effect) OS2 0 1
t] en Ev E[1:0 O 0] [2: O S :0 ] [5 OO de Mo

PWM behaviour before D Not Alternate Alternate

OS2 OS1 OS0

xxx

OS[1:0] 00 01 10 11

PWM behaviour after D On Even Channels On Odd Channels Alternate Odd/Even On all active Channels

Step C Demagnetization 1 0 D C

Off (0) Voltage (V0C1=0) On (1)

X

000 0 Even 1 Odd 001 0 Even 1 Odd 0 Even 010 1 Odd Even 011 0 1 Odd 100 0 1 101 0 1 Even Odd 110 0 1 111 0 1 Even Odd Even Odd Even Odd Even Odd

!

WARNING: OS[2:0] = 010 has NO current regulation!

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MOTOR CONTROLLER (Cont'd) Figure 41. Step Behaviour of one Output Channel MCO[n] in Current / Sensorless Mode
(Current Mode without polarity effect, sensorless mode: SR=0) OS2 0 1 PWM behaviour before D On Even Channels On Odd Channels OS[1:0] 00 01 10 11 Step C D Demagnetization x 1 0 1 0 1 0 1 0 1 0 OS1 xx 00 11 10 01 C OS0 65/132 C xx 00 11 10 01 1 0 1.25us 01 11 10 00 xx OS1 OS0 1.25us In sensor mode, there is no demagnetisation event and the PWM behaviour is the same for the complete step time. PWM behaviour after D On Even Channels On Odd Channels Alternate Odd/Even On all active Channels

Off (0) Current (V0C1=1)

X

On (1) Even (0)

Odd (1)

Figure 42. Step Behaviour of one Output Channel MCO[n] in Current / Sensor Mode
OS2 (Current Mode without polarity effect, sensor mode: SR=1) OS[1:0] Not used PWM behaviour after D 00 On Even Channels 01 On Odd Channels 10 Alternate Odd/Even 11 On all active Channels Step C

Off (0)

Current (V0C1=1)

Odd (1)

On (1) Even (0)

X

t en ] Ev [1:0 OE 0] [5: OO e d Mo

0 1

Toff

1 0 x

Toff

01 11 10 00 xx

OS2

t en 0] Ev [5: OE :0] [5 OO de Mo

ST72141K

MOTOR CONTROLLER (Cont'd) 8.1.5 Low Power Modes Before executing a HALT or WFI instruction, software must stop the motor, and may choose to put the outputs in high impedance. Mode WAIT Description No effect on MTC interface. MTC interrupts exit from Wait mode. MTC registers are frozen. In Halt mode, the MTC interface is inactive. The MTC interface becomes operational again when the MCU is w oken up by an interrupt with "exit from Halt mode" capability.

8.1.6 Interrupts
Interrupt Event Ratio increment Ratio decrement Multiplier overflow Emergency Stop BEMF Zero-Crossing End of Demagnetization Commutation Enable Exit Exit Event Control from from Flag Bit Wait Halt RPI Yes No RIM RMI Yes No OI OIM Yes No EI EIM Yes No ZI ZIM Yes No DI DIM Yes No CI CIM Yes No

HA LT

The MTC interrupt events are connected to the three interrupt vectors (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC register is reset (RIM instruction).

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MOTOR CONTROLLER (Cont'd) 8.1.7 Register Description TIMER COUNTER REGISTER (MTIM) Read/Write Reset Value: 0000 0000 (00h)
7 T7 T6 T5 T4 T3 T2 T1 0 T0

DEMAGNETIZATION REGISTER (MDREG) Read/Write Reset Value: 0000 0000 (00h)
7 DN7 DN6 DN5 DN4 DN3 DN2 DN1 0 DN0

Bits 7:0 = T[7:0]: MTIM Counter Value. These bits contain the current value of the 8-bit up counter. CAPTURE Z n-1 REGISTER (MZPRV) Read/Write Reset Value: 0000 0000 (00h)
7 Z P7 ZP 6 ZP 5 ZP 4 ZP 3 ZP 2 ZP 1 0 ZP 0

Bits 7:0 = DN[7:0]: D Value. These bits contain the compare value for software demagnetization (DN) and the captured value for hardware demagnetization (DH). AN WEIGHT REGISTER (MWGHT) Read/Write Reset Value: 0000 0000 (00h)
7 AN7 AN6 AN5 AN4 AN3 AN 2 AN 1 0 AN 0

Bits 7:0 = ZP[7:0]: Previous Z Value. These bits contain the previous captured BEMF value (ZN-1). CAPTURE Z n REGISTER (MZREG) Read/Write Reset Value: 0000 0000 (00h)
7 ZC7 Z C6 ZC 5 ZC 4 ZC 3 ZC 2 ZC 1 0 ZC0

Bits 7:0 = AN[7:0]: A Weight Value. These bits contain the AN weight value for the multiplier. In autoswitched mode the MCOMP register is automatically loaded with:
Zn x MWGHT 32(d) or ZN-1 x MWGHT 32(d) (*)

when a Z event occurs. (*) depending on the DCB bit in the MCRA regist er . PRESCA LER & SAMPLING REGISTER (MPRSR) Read/Write Reset Value: 0000 0000 (00h)
7 SA3 SA2 SA1 SA0 S T3 S T2 S T1 0 S T0

Bits 7:0 = ZC[7:0]: Current Z Value. These bits contain the current captured BEMF value (Z N). COMPARE Cn+1 REGISTER (MCOMP) Read/Write Reset Value: 0000 0000 (00h)
7 DC7 DC6 DC5 DC4 DC3 DC2 DC1 0 DC0

Bits 7:4 = SA[3:0]: Sampling Ratio. These bits contain the sampling ratio value for current mode. Refer to Table 23. Bits 3:0 = ST[3:0]: Step Ratio. These bits contain the step ratio value. It acts as a prescaler for the MTIM timer and is auto incremented/decremented with each R+ or R- event. Refer to Table 20.

Bits 7:0 = DC[7:0]: Next Compare Value. These bits contain the compare value for the next commutation (C N+1).

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MOTOR CONTROLLER (Cont'd) INTERRUPT MASK REGISTER (MIMR) Read/Write (except bits 7:6) Reset Value: 0000 0000 (00h)
7 HST CL RIM OIM EIM ZIM DIM 0 CIM

INTERRUPT STATUS REGISTER (MISR) Read/Write Reset Value: 0000 0000 (00h)
7 0 R PI RMI OI EI ZI DI 0 CI

Bit 7 = HST: Hysteresis Comparator Value. This read only bit contains the hysteresis comparator output. 0: Demagnetisation/BEMF comparator is under VREF 1: Demagnetisation/BEMF comparator is above VREF Bit 6 = CL: Current Loop Comparator Value. This read only bit contains the current loop comparator output value. 0: Current detect voltage is under VCREF 1: Current detect voltage is above VCREF Bit 5 = RIM: Ratio update Interrupt Mask bit. 0: Ratio update interrupts (R+ and R-) disabled 1: Ratio update interrupts (R+ and R-) enabled Bit 4 = OIM: Multiplier Overflow Interrupt Mask bit. 0: Multiplier Overflow interrupt disabled 1: Multiplier Overflow interrupt enabled Bit 3 = EIM: Emergency stop Interrupt Mask bit. 0: Emergency stop interrupt disabled 1: Emergency stop interrupt enabled Bit 2 = ZIM: Back EMF Zero-crossing Interrupt Mask bit. 0: BEMF Zero-crossing Interrupt disabled 1: BEMF Zero-crossing Interrupt enabled Bit 1 = DIM: End of Demagnetization Interrupt Mask bit. 0: End of Demagnetization interrupt disabled 1: End of Demagnetization interrupt enabled if the HDM or SDM bit in the MCRB register is set Bit 0 = CIM: Commutation Interrupt Mask bit 0: Commutation Interrupt disabled 1: Commutation Interrupt enabled

Bit 7 = Reserved. Forced by hardware to 0. Bit 6 = RPI: Ratio Increment interrupt flag. Autoswitched mode (SWA bit =0): 0: No R+ interrupt pending 1: R+ Interrupt pending Switched mode (SWA bit =1): 0: No R+ action 1: The hardware will increment the ST[3:0] bits when the next commutation occurs and shift all timer registers right. Bit 5 = RMI: Ratio Decrement interrupt flag. Autoswitched mode (SWA bit =0): 0: No R- interrupt pending 1: R- Interrupt pending Switched mode (SWA bit =1): 0: No R- action 1: T