Datasheets | Microcontrollers | 8-bit Microcontrollers | ST7 - 8-bit Microcontrollers

8-bit MCU with nested interrupts, EEPROM, ADC,16-bit timers, 8-bit PWM ART, SPI, SCI, CAN interfaces

Datasheet

Format: (3529 kb)

Last Updated: 12/05/2008

Pages: 151

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Related Application Notes

MCUS - 8/16/32-BIT MICROCONTROLLERS (MCUS) APPLICATION NOTES ABSTRACTS BY TOPICS

Related Programming Manuals

ST7 FAMILY PROGRAMMING MANUAL

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ST72311R, ST72511R
8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES

Memories 16K to 60K bytes Program memory (ROM,OTP and EPROM) with read-out protection 256 bytes E2PROM Data memory (only on ST72532R4) 1024 to 2048 bytes RAM Clock, Reset and Supply Management Enhanced reset system Low voltage supply supervisor Clock sources: crystal/ceramic resonator oscillator or external clock Beep and Clock-out capability 4 Power Saving Modes: Halt, Active-Halt, Wait and Slow Interrupt Management Nested interrupt controller 13 interrupt vectors plus TRAP and RESET 15 external interrupt lines (on 4 vectors) TLI dedicated top level interrupt pin 48 I/O Ports 48 multifunctional bidirectional I/O lines 32 alternate function lines 12 high sink outputs 5 Timers Configurable watchdog timer Real time clock timer One 8-bit auto-reload timer with 4 independent PWM output channels, 2 output compares and external clock with event detector (except on ST725x2R4)

TQFP64 14 x 14

Two 16-bit timers with: 2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes 3 Communications Interfaces SPI synchronous serial interface SCI asynchronous serial interface CAN interface (except on ST72311Rx) 1 Analog peripheral 8-bit ADC with 8 input channels Instruction Set 8-bit data manipulation 63 basic instructions 17 main addressing modes 8 x 8 unsigned multiply instruction True bit manipulation Development Tools Full hardware/software development package
ST72T311R9 60K 2048 (256) ST72T311R7 48K 1536 (256) ST72T311R6 32K 1024 (256) -

Device Summary
Features Program memory - bytes RAM (stack) - bytes EEPROM - bytes Peripherals Operating Supply CPU Frequency Operating Temperature Packages ST72T511R9 ST72T511R6 60K 32K 2048 (256) 1024 (256) Watchdog, two 16-bit timers, 8-bit PWM ART, SPI, SCI, CAN, ADC

Watchdog, two 16-bit timers, 8-bit PWM ART, SPI, SCI, ADC

3.0V to 5.5 V 2 to 8 MHz (with 4 to 16 MHz oscillator) -40C to +85C (-40C to +105/125C optional) TQFP64

Note 1. See Section 12.3.1 on page 119 for more information on VDD versus fOSC.

April 2008

Rev. 3

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Table of Contents
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 I NTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 1.3 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 EPROM PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 3.3 3.4 3.5 3.6 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 4.3 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 25 26 26 26 27 5.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3 Internal Low Voltage Detection RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.4 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 LOW CONSUMPTION OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 6.3 6.4 6.5 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.2 7.3 7.4 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 36 37 38 38

7.4.1 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 I NTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 . 38 ... 8.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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8.3 8.4 8.5 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.5.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.2 9.3 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.4 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC) . . . . . . . 10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 49 49 50 50 50 50 52 52 52 52 53 53 53 54 54 55 58 61 61 61 61 73 73 73 74 79 79 79 79 81 88 88 89 92

10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

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10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 10.6.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 10.6.4 LIN Protocol support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 10.6.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 10.6.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.6.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.6.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10.7 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 10.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 107 107 108 108 109 111 111 112 112 112 112 112 113 113 114

12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 117 117 117 117 118 118 118 118 119

12.3.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12.3.2 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . 120 12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 12.4.1 RUN and SLOW Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 12.4.2 WAIT and SLOW WAIT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 12.4.3 HALT and ACTIVE-HALT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 12.4.4 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 12.4.5 On-Chip Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 151 12.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 12.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

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12.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 12.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6.2 EEPROM Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6.3 EPROM Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7.1 Functional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7.2 Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7.3 ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 125 125 126 126 127 129 131

12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 12.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 12.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 12.9.2 VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 12.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 12.10.1Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.10.28-Bit PWM-ART Auto-Reload Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.10.316-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.11 COMMUNICATIONS INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . 12.11.1SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.11.2SCI - Serial Communications Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.11.3CAN - Controller Area Network Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.12 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 134 134 135 135 137 137 138

13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 13.3 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 14 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 143 14.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 144 14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 14.3.1 Package/socket Footprint Proposal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 15 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

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1 GENERAL DESCRIPTION
1.1 INTRODUCTION The ST72311R, ST72511R, and ST72532R devices are members of the ST7 microcontroller family. They can be grouped as follows: ST725xxR devices are designed for mid-range applications with a CAN bus interface (Controller Area Network). These devices are available in OTP and EPROM versions only. ST72311R devices target the same range of applications but without the CAN interface. These devices are available in ROM, OTP and EPROM versions. All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set. Figure 1. Device Block Diagram
8-BIT CORE ALU RESET VPP TLI VD D VSS OSC 1 OSC 2 CONTROL RAM (1024, 2048 Bytes) LVD OSC ADDRESS AND DATA BUS EEP ROM (256 Bytes)

Under software control, all devices can be placed in WAIT, SLOW, ACTIVE-HALT or HALT mode, reducing power consumption when the application is in idle or standby state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

PROGRAM MEMORY (16K - 60K Bytes)

MCC/RTC

WATCHDOG PO RT A PORT B PB7:0 (8-BIT) PWM ART PORT C TIM E R B SPI PC7:0 (8-BIT) PA7:0 (8-BIT)

PORT F PF7:0 (8-BIT) T IM E R A BEEP PORT E PE7:0 (8-BIT) CAN SCI PO RT D PD7:0 (8-BIT) 8-BIT ADC VDDA VSSA

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1.2 PIN DESCRIPTION Figure 2. 64-Pin TQFP Package Pinout

(HS) PE4 (HS) PE5 (HS) PE6 (HS) PE7 PWM3 / PB0 PWM2 / PB1 PWM1 / PB2 PWM0 / PB3 ARTCLK / PB4 PB5 PB6 PB7 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3

64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

PE3 / CANRX PE2 / CANTX PE1 / RDI PE0 / TDO VDD_2 OSC1 OSC2 VSS_2 TLI nc RESET VPP PA7 (HS) PA6 (HS) PA5 (HS) PA4 (HS) 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 ei0 44 43 ei2 42 41 40 39 ei3 38 37 36 35 ei1 34 33 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

VSS_1 VDD_1 PA3 PA2 PA1 PA0 PC7 / SS PC6 / SCK PC5 / MOSI PC4 / MISO PC3 (HS) / ICAP1_B PC2 (HS) / ICAP2_B PC1 / OCMP1_B PC0 / OCMP2_B VSS_0 VDD_0

AIN4 / PD4 AIN5 / PD5 AIN6 / PD6 AIN7 / PD7 VDDA VSSA VDD_3 VSS_3 MCO / PF0 BEEP / PF1 PF2 OCMP2_A / PF3 OCMP1_A / PF4 ICAP2_A / PF5 ICAP1_A / (HS) PF6 EXTCLK_A / (HS) PF7 (HS) 20mA high sink capability eix associated external interrupt vector

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PIN DESCRIPTION (Cont'd) For external pin connection guidelines, refer to Section 12 on page 117. Legend / Abbreviations for Table 1: Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C = CMOS 0.3VDD/0.7VDD, CT= CMOS 0.3VDD/0.7VDD with input trigger Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration: Input: float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog Output: OD = open drain 2), PP = push-pull Refer to Section 8 "I/O PORTS" on page 38 for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state. Table 1. Device Pin Description
Pin n TQFP64 Type Pin Name Level Output Input Port Input float wpu ana int O u tput OD PP Main function (after reset) Port E4 Port E5 Port E6 Port E7 Port B0 Port B1 Port B2 Port B3 Port B4 Port B5 Port B6 Port B7 Port D0 Port D1 Port D2 Port D3 Port D4 Port D5 Port D6 Port D7 ADC Analog Input 0 ADC Analog Input 1 ADC Analog Input 2 ADC Analog Input 3 ADC Analog Input 4 ADC Analog Input 5 ADC Analog Input 6 ADC Analog Input 7 PWM Output 3 PWM Output 2 PWM Output 1 PWM Output 0 PWM-ART External Clock

Alternate function

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

PE4 (HS) PE5 (HS) PE6 (HS) PE7 (HS) PB0/PWM 3 PB1/PWM 2 PB2/PWM 1 PB3/PWM 0 PB4/ARTCLK PB5 PB6 PB7 PD0/AIN 0 PD1/AIN 1 PD2/AIN 2 PD3/AIN 3 PD4/AIN 4 PD5/AIN 5 PD6/AIN 6 PD7/AIN 7 V DDA VSSA V DD_3 VSS_3

I/O CT HS I/O CT HS I/O CT HS I/O CT HS I/O CT I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O S S S S CT CT CT CT CT CT CT CT CT CT CT CT CT CT CT

X X X X X X X X X X X X X X X X X X X X

X X X X ei2 ei2 ei2 ei2 ei3 ei3 ei3 ei3 X X X X X X X X X X X X X X X X

X X X X X X X X X X X X X X X X X X X X

X X X X X X X X X X X X X X X X X X X X

Analog Power Supply Voltage Analog Ground Voltage Digital Main Supply Voltage Digital Ground Voltage

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Pin n TQFP64 Type Pin Name

Level Output Input

Port Input fl oat wpu ana int O u tput OD PP

Main function (after reset) Port F0 Port F1 Port F2 Port F3 Port F4 Port F5 Port F6 Port F7

Alternate function

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

PF0/MCO PF1/BEEP PF2 PF3/OCMP 2_A PF4/OCMP 1_A PF5/ICAP 2_A PF6 (HS)/ICAP1_A V DD_0 VSS_0 PC0/OCM P2_B PC1/OCM P1_B PC2 (HS)/ICAP2_B PC3 (HS)/ICAP1_B PC4/MISO PC5/MOS I PC6/SCK PC7/ SS PA0 PA1 PA2 PA3 V DD_1 VSS_1 PA4 (HS) PA5 (HS) PA6 (HS) PA7 (HS) V PP RES ET NC NM I VSS_3 OSC2 3) OSC1 3) V DD_3 PE0/TDO

I/O I/O I/O I/O I/O I/O

CT CT CT CT CT CT

X X X X X X X X

ei1 ei1 ei1 X X X X X

X X X X X X X X

X X X X X X X X

Main clock output (fOSC/2) Beep signal output Timer A Output Compare 2 Timer A Output Compare 1 Timer A Input Capture 2 Timer A Input Capture 1 Timer A External Clock Source

I/O CT HS PF7 (HS)/EXTCLK_A I/O CT HS S S I/O I/O CT CT

Digital Main Supply Voltage Digital Ground Voltage X X X X X X X X X X X X X X X X X X X X ei0 ei0 ei0 ei0 X X X X X X X X X X X X X X X X X X X X X X X X Port C0 Port C1 Port C2 Port C3 Port C4 Port C5 Port C6 Port C7 Port A0 Port A1 Port A2 Port A3 Digital Main Supply Voltage Digital Ground Voltage X X X X X X X X T T X X Port A4 Port A5 Port A6 Port A7 Must be tied low in user mode. In programming mode when available, this pin acts as the programming voltage input VPP . C CT X X X Top priority non maskable interrupt (active low) Non maskable interrupt input pin Digital Ground Voltage External clock mode input pull-up or crystal/ceramic resonator oscillator inverter output External clock input or crystal/ceramic resonator oscillator inverter input Digital Main Supply Voltage CT X X X X Port E0 SCI Transmit Data Out Timer B Output Compare 2 Timer B Output Compare 1 Timer B Input Capture 2 Timer B Input Capture 1 SPI Master In / Slave Out Data SPI Master Out / Slave In Data SPI Serial Clock SPI Slave Select (active low)

I/O CT HS I/O CT HS I/O CT I/O I/O I/O I/O I/O I/O I/O S S I/O CT HS I/O CT HS I/O CT HS I/O CT HS I I/O I S I/O I S I/O CT CT CT CT CT CT CT

Not Connected

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Pin n TQFP64 Type Pin Name

Level Output Input

Port Input fl oat wpu ana int O u tput OD PP

Main function (after reset) Port E1 Port E2 Port E3

Alternate function

62 63 64

PE1/RDI PE2/CANTX PE3/CANRX

I/O I/O I/O

CT CT CT

X X

X X X

X X

X X

SCI Receive Data In CAN Transmit Data Output CAN Receive Data Input

Notes: 1. In the interrupt input column, "eiX" defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input. 2. In the open drain output column, "T" defines a true open drain I/O (P-Buffer and protection diode to VDD are not implemented). See Section 8 "I/O PORTS" on page 38 and Section 12.8 "I/O PORT PIN CHARACTERISTICS" on page 131 for more details. 3. OSC1 and OSC2 pins connect a crystal/ceramic resonator or an external source to the on-chip oscillator see Section 1.2 "PIN DESCRIPTION" on page 7 and Section 12.5 "CLOCK AND TIMING CHARACTERISTICS" on page 124 for more details.

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1.3 REGISTER & MEMORY MAP As shown in the Figure 3, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register location, up to 2Kbytes of RAM, up to 256 bytes of data EEPROM and up to Figure 3. Memory Map
0000h 007Fh 0080h

60Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh. The highest address bytes contain the user reset and interrupt vectors.

HW Registers (see Table 2) 1024 Bytes RAM 1536 Bytes RAM

0080h

Short Addressing RAM (zero page)
00FFh 0100h 01FFh 0200h

087Fh 0880h 0BFFh 0C00h

2048 Bytes RAM Reserved Optional EEPROM (256 Bytes)

Stack (256 Bytes) 16-bit Addressing RAM

047Fh or 067Fh or 087Fh 1000h

0CFFh 0D00h

Reserved
0FFFh 1000h 4000h

60 KBytes 48 KBytes

Program Memory (60K, 48K, 32K, 16K Bytes)
FFDFh FFE0h FFFFh

8000h

32 KBytes
C000h

Interrupt & Reset Vectors (see Table 7 on page 32)

16 KBytes
FFFFh

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Table 2. Hardware Register Map
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h to 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h MC C MCCSR MIS CR1 SPID R SPICR SPISR ISPR 0 ISPR1 ISPR2 ISPR3 PFDR PFDDR PFOR PDDR PDDDR PDOR PEDR PEDDR PEOR PBDR PBDDR PBOR PCDR PCDDR PCOR Block Register Label PADR PADDR PAOR Register Name Port A Data Register Port A Data Direction Register Port A Option Register Reserved Area (1 Byte) Port C Data Register Port C Data Direction Register Port C Option Register Reserved Area (1 Byte) Port B Data Register Port B Data Direction Register Port B Option Register Reserved Area (1 Byte) Port E Data Register Port E Data Direction Register Port E Option Register Reserved Area (1 Byte) Port D Data Register Port D Data Direction Register Port D Option Register Reserved Area (1 Byte) Port F Data Register Port F Data Direction Register Port F Option Register 00h 1) 00h 00h R/W R/W R/W 00h 1) 00h 00h R/W R/W R/W 00h 1) 00h 00h R/W R/W 2) R/W 2) 00h 1) 00h 00h R/W R/W R/W 00h 1) 00h 00h R/W R/W R/W Reset Status 00h 1) 00h 00h Remarks R/W R/W R/W 2)

Port A

Port C

Port B

Port E

Port D

Port F

Reserved Area (9 Bytes)

Miscellaneous Register 1 SPI Data I/O Register SPI Control Register SPI Status Register Interrupt Software Priority Register 0 Interrupt Software Priority Register 1 Interrupt Software Priority Register 2 Interrupt Software Priority Register 3 Reserved Area (1 Byte) Main Clock Control / Status Register

00h xxh 0xh 00h FFh FFh FFh FFh

R/W R/W R/W Read Only R/W R/W R/W R/W

SPI

ITC

01h

R/W

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Address 002Ah 002Bh 002Ch 002Dh to 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h

Block

Register Label WDG C R WDGSR EECSR

Register Name Watchdog Control Register Watchdog Status Register Data EEPROM Control/Status Register

Reset Status 7Fh 000x 000x 00h

Remarks R/W R/W R/W

W ATCHDOG EE PROM

Reserved Area (4 Bytes)

TIMER A

TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR MIS CR2 TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR SCIETPR

Timer A Control Register 2 Timer A Control Register 1 Timer A Status Register Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low Register Timer A Input Capture 2 High Register Timer A Input Capture 2 Low Register Timer A Output Compare 2 High Register Timer A Output Compare 2 Low Register Miscellaneous Register 2 Timer B Control Register 2 Timer B Control Register 1 Timer B Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 SCI Extended Receive Prescaler Register Reserved area SCI Extended Transmit Prescaler Register

00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h 00h 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h C0h xxh 00xx xxxx xxh 00h 00h 00h

R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W R/W R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W Read Only R/W R/W R/W R/W R/W R/W

TIMER B

SCI

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Address 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h to 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah to 007Fh

Block

Register Label

Register Name

Reset Status

Remarks

Reserved Area (2 Bytes) CANISR CANICR CANCSR CANBRPR CANBTR CANPSR CAN Interrupt Status Register CAN Interrupt Control Register CAN Control / Status Register CAN Baud Rate Prescaler Register CAN Bit Timing Register CAN Page Selection Register First address to Last address of CAN page X Data Register Control/Status Register PWM AR Timer Duty Cycle Register 3 PWM AR Timer Duty Cycle Register 2 PWM AR Timer Duty Cycle Register 1 PWM AR Timer Duty Cycle Register 0 PWM AR Timer Control Register Auto-Reload Timer Control/Status Register Auto-Reload Timer Counter Access Register Auto-Reload Timer Auto-Reload Register 00h 00h 00h 00h 23h 00h R/W R/W R/W R/W R/W R/W See CAN Description

CAN

ADC

ADCDR ADCCSR PWMDCR3 PWMDCR2 PWMDCR1 PWMDCR0 PWMCR ARTCSR ARTCAR ARTARR

xxh 00h 00h 00h 00h 00h 00h 00h 00h 00h

Read Only R/W R/W R/W R/W R/W R/W R/W R/W R/W

PWM ART

Reserved Area (6 Bytes)

Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value.

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2 EPROM PROGRAM MEMORY
The program memory of the OTP and EPROM devices can be programmed with EPROM programming tools available from STMicroelectronics EPROM Erasure EPROM devices are erased by exposure to high intensity UV light admitted through the transparent window. This exposure discharges the floating gate to its initial state through induced photo current. It is recommended that the EPROM devices be kept out of direct sunlight, since the UV content of sunlight can be sufficient to cause functional failure. Extended exposure to room level fluorescent lighting may also cause erasure. An opaque coating (paint, tape, label, etc...) should be placed over the package window if the product is to be operated under these lighting conditions. Covering the window also reduces IDD in power-saving modes due to photo-diode leakage currents.

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3 DATA EEPROM
3.1 INTRODUCTION The Electrically Erasable Programmable Read Only Memory can be used as a non volatile backup for storing data. Using the EEPROM requires a basic access protocol described in this chapter. 3.2 MAIN FEATURES

Up to 16 Bytes programmed in the same cycle EEPROM mono-voltage (charge pump) Chained erase and programming cycles Internal control of the global programming cycle duration End of programming cycle interrupt flag WAIT mode management

Figure 4. EEPROM Block Diagram

EEPROM INTERRUPT

FALLING EDGE DETECTOR

HIGH VOLTAGE PUMP RESERVED EEPROM 0 IE LAT PGM

EECSR

0

0

0

0

ADDRESS DECODER

4

ROW DECODER

EEPROM MEMORY MATRIX (1 ROW = 16 x 8 BITS)

128 DATA MULTIPLEXE R 4

128 16 x 8 BITS DATA LATCHES

4

ADDRESS BUS

DATA BUS

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DATA EEPROM (Cont'd) 3.3 MEMORY ACCESS The Data EEPROM memory read/write access modes are controlled by the LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in Figure 5 describes these different memory access modes. Read Operation (LAT=0) The EEPROM can be read as a normal ROM location when the LAT bit of the EECSR register is cleared. In a read cycle, the byte to be accessed is put on the data bus in less than 1 CPU clock cycle. This means that reading data from EEPROM takes the same time as reading data from EPROM, but this memory cannot be used to execute machine code. Note: In order to ensure the correct read out of the EEPROM over the entire temperature range, the cell whose contents will be read, must be read twice in compliance with the following conditions: a first reading must be immediately followed by a second reading all interrupts must be disabled until the two readings are performed no other instructions are allowed between the two reading instructions the data of the first reading has to be discarded The described procedure corresponds to the following code sequence: sim ld A,eeprom_var ld A,eeprom_var Figure 5. Data EEPROM Programming Flowchart
READ MODE LAT=0 PGM=0 WRITE MODE LAT=1 PGM=0

rim where eeprom_var adresses the EERPOM cell to be read. Any of the ST7 addressing modes may be used. Write Operation (LAT=1) To access the write mode, the LAT bit has to be set by software (the PGM bit remains cleared). When a write access to the EEPROM area occurs, the value is latched inside the 16 data latches according to its address. When PGM bit is set by the software, all the previous bytes written in the data latches (up to 16) are programmed in the EEPROM cells. The effective high address (row) is determined by the last EEPROM write sequence. To avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same high address: only the four Least Significant Bits of the address can change. At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously, and an interrupt is generated if the IE bit is set. The Data EEPROM interrupt request is cleared by hardware when the Data EEPROM interrupt vector is fetched. Note: Care should be taken during the programming cycle. Writing to the same memory location will over-program the memory (logical AND between the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of LAT bit. It is not possible to read the latched data. This note is ilustrated by the Figure 6.

READ BYTES IN EEPROM AREA

WRITE UP TO 16 BYTES IN EEPROM AREA (with the same 12 MSB of the address) START PROGRAMMING CYCLE LAT=1 PGM=1 (set by software)

INTERRUPT GENERATION IF IE=1 CLEARED BY HARDWARE

0

LAT

1

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DATA EEPROM (Cont'd) 3.4 POWER SAVING MODES Wait mode The DATA EEPROM can enter WAIT mode on execution of the WFI instruction of the microcontroller. The DATA EEPROM will immediately enter this mode if there is no programming in progress, otherwise the DATA EEPROM will finish the cycle and then enter WAIT mode. Halt mode The DATA EEPROM immediatly enters HALT mode if the microcontroller executes the HALT instruction. Therefore the EEPROM will stop the function in progress, and data may be corrupted. Figure 6. Data EEPROM Programming Cycle
READ OPERATION NOT POSSIBLE INTERNAL PROGRAMMING VOLTAGE ERASE CYCLE WRITE OF DATA LATCHES WRITE CYCLE READ OPERATION POSSIBLE

3.5 ACCESS ERROR HANDLING If a read access occurs while LAT=1, then the data bus will not be driven. If a write access occurs while LAT=0, then the data on the bus will not be latched. If a programming cycle is interrupted (by software/ RESET action), the memory data will not be guaranteed.

tPROG

LAT

P GM

EEPROM INTERRUPT

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DATA EEPROM (Cont'd) 3.6 REGISTER DESCRIPTION CONTROL/STATUS REGISTER (CSR) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 0 IE LAT 0 PGM

Bit 1 = LAT Latch Access Transfer This bit is set by software. It is cleared by hardware at the end of the programming cycle. It can only be cleared by software if PGM bit is cleared. 0: Read mode 1: Write mode Bit 0 = PGM Programming control and status This bit is set by software to begin the programming cycle. At the end of the programming cycle, this bit is cleared by hardware and an interrupt is generated if the ITE bit is set. 0: Programming finished or not yet started 1: Programming cycle is in progress Note: if the PGM bit is cleared during the programming cycle, the memory data is not guaranteed

Bits 7:3 = Reserved, forced by hardware to 0. Bit 2 = IE Interrupt enable This bit is set and cleared by software. It enables the Data EEPROM interrupt capability when the PGM bit is cleared by hardware. The interrupt request is automatically cleared when the software enters the interrupt routine. 0: Interrupt disabled 1: Interrupt enabled

Table 3. DATA EEPROM Register Map and Reset Values
Address (Hex.) 002Ch Register Label E ECSR Reset Value 0 0 0 0 0 7 6 5 4 3 2 IE 0 1 RW M 0 0 PGM 0

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4 CENTRAL PROCESSING UNIT
4.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 4.2 MAIN FEATURES

4.3 CPU REGISTERS The six CPU registers shown in Figure 7 are not present in the memory mapping and are accessed by specific instructions. Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures. Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

Enable executing 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) Two 8-bit index registers 16-bit stack pointer Low power HALT and WAIT modes Priority maskable hardware interrupts Non-maskable software/hardware interrupts

Figure 7. CPU Registers
7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 0 CONDITION CODE REGISTER 1 1 I1 H I0 N Z C RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value 0 Y INDEX REGISTER 0 X INDEX REGISTER 0 ACCUMULATOR

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CENTRAL PROCESSING UNIT (Cont'd) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx
7
1 1 I1 H I0 N Z

Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions. Interrupt Management Bits Bit 5,3 = I1, I0 Interrupt The combination of the I1 and I0 bits gives the current interrupt software priority.
Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) I1 1 0 0 1 I0 0 1 0 1

0 C

The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Arithmetic Management Bits Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It's a copy of the result 7th bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions.

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See the interrupt management chapter for more details.

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CENTRAL PROCESSING UNIT (Cont'd) Stack Pointer (SP) Read/Write Reset Value: 01 FFh
15 0 7
SP7 SP6 SP5 SP4 SP3 SP2 SP1

8 0 0 0 0 0 0 1 0 SP0

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 8). Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address. Figure 8. Stack Manipulation Example
CALL Subroutine @ 0100h Interrupt Event P USH Y

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 8. When an interrupt is received, the SP is decremented and the context is pushed on the stack. On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area.

PO P Y

IRET

RET or RSP

SP SP CC A X PC H SP PCH @ 01FFh PCL P CL PCH PCL Y CC A X PCH PCL PCH PC L SP CC A X PCH PCL PCH PCL SP PCH PCL SP

Stack Higher Address = 01FFh Stack Lower Address = 0100h

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5 SUPPLY, RESET AND CLOCK MANAGEMENT
The ST72311R, ST72511R and ST72532R microcontrollers include a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 9. Main features Main supply low voltage detection (LVD) RESET Manager (RSM) Low consumption resonator oscillator

Figure 9. Clock, RESET, Option and Supply Management Overview

OSC2 OS CILLATOR OSC1

fOSC

TO MAIN CLOCK CONTROLLER

RESET

RESET

FROM WATCHDOG PERIPHERAL

VDD VSS

LOW VOLTAGE DETECTOR (LVD)

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5.1 LOW VOLTAGE DETECTOR (LVD) To allow the integration of power management features in the application, the Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT- reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD Reset circuitry generates a reset when VDD is below: VIT+ when VDD is rising VIT- when VDD is falling The LVD function is illustrated in Figure 10. Provided the minimum VDD value (guaranteed for the oscillator frequency) is below VIT-, the MCU can only be in two modes: Figure 10. Low Voltage Detector vs Reset
VDD

under full software control in static safe reset In these conditions, secure operation is always ensured for the application without the need for external reset hardware. During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Notes: The LVD allows the device to be used without any external RESET circuitry. The LVD is an optional function which can be selected when ordering the device (ordering information).

Vhys VIT+ VIT-

RESET

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5.2 RESET SEQUENCE MANAGER (RSM) 5.2.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 12: External RESET source pulse Internal LVD RESET (Low Voltage Detection) Internal WATCHDOG RESET These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases as shown in Figure 11: Delay depending on the RESET source 4096 CPU clock cycle delay RESET vector fetch Figure 12. Reset Block Diagram The 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The RESET vector fetch phase duration is 2 clock cycles. Figure 11. RESET Sequence Phases

RESET
DELAY INTERNAL RESET 4096 CLOCK CYCLES FETCH VECTOR

VDD

f CPU
COUNTER

INTERNAL RESET

RON
RESET

WATCHDOG RESET LVD RESET

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RESET SEQUENCE MANAGER (Cont'd) 5.2.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See electrical characteristics section for more details. A RESET signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized as shown in Figure 13. This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode. The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. 5.2.3 Internal Low Voltage Detection RESET Two different RESET sequences caused by the internal LVD circuitry can be distinguished: Power-On RESET Voltage Drop RESET The device RESET pin acts as an output that is pulled low when VDD
Figure 13. RESET Sequences VDD
V I T+ V I T-

WATCHDOG RESET LVD RESET SHORT EXT. RESET

RUN
DELAY

RUN
DELAY

RUN
DELAY

RUN

th(RSTL)in
EXTERNAL RESET SOURCE

tw(RSTL)out

RESET PIN

WATCHDOG RESET WATCHDOG UNDERFLOW INTERNAL RESET (4096 TCPU) FETCH VECTOR

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5.3 LOW CONSUMPTION OSCILLATOR The fOSC main clock of the ST7 can be generated by two different source types: an external source a crystal or ceramic resonator oscillators The associated hardware configuration are shown in Table 4. Refer to the electrical characteristics section for more details. External Clock Source In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground. Crystal/Ceramic Oscillator This oscillator (based on constant current source) is optimized in terms of consumption and has the advantage of producing a very accurate rate on the main clock of the ST7. When using this oscillator, the resonator and the load capacitances have to be connected as shown in Table 4 and have to be mounted as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. This oscillator is not stopped during the RESET phase to avoid losing time in the oscillator start-up phase. These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase. Table 4. ST7 Clock Sources
Hardware Configuration

External Clock

ST7 OS C1 OSC 2

V DD

EX TERNAL SO URCE

ROBP

Crystal/Ceramic Resonators

ST7 OSC 1 OSC2

CL1

LOA D CAPA CITO RS

CL 2

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6 INTERRUPTS
6.1 INTRODUCTION The CPU enhanced interrupt management provides the following features: Hardware interrupts Software interrupt (TRAP) Nested or concurrent interrupt management with flexible interrupt priority and level management: Up to 4 software programmable nesting levels Up to 16 interrupt vectors fixed by hardware 3 non maskable events: RESET, TRAP, TLI This interrupt management is based on: Bit 5 and bit 3 of the CPU CC register (I1:0), Interrupt software priority registers (ISPRx), Fixed interrupt vector addresses located at the high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order. This enhanced interrupt controller guarantees full upward compatibility with the standard (not nested) CPU interrupt controller. 6.2 MASKING AND PROCESSING FLOW The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector (see Table 1). The processing flow is shown in Figure 1. Figure 14. Interrupt Processing Flowchart
RESET PENDING INTERRUPT N Y TLI Interrupt has the same or a lower software priority than current one N I1:0 Interrupt has a higher software priority than current one Y

When an interrupt request has to be serviced: Normal processing is suspended at the end of the current instruction execution. The PC, X, A and CC registers are saved onto the stack. I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx registers of the serviced interrupt vector. The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to "Interrupt Mapping" table for vector addresses). The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume. Table 5. Interrupt Software Priority Levels
Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) Level Low I1 1 0 0 1 I0 0 1 0 1

High

FETCH NEXT INSTRUCTION

THE INTERRUPT STAYS PENDING

Y

"IRET" N

RESTORE PC, X, A, CC FROM STACK

EXECUTE INSTRUCTION

STACK PC, X, A, CC LOAD I1:0 FROM INTERRUPT SW REG. LOAD PC FROM INTERRUPT VECTOR

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INTERRUPTS (Cont'd) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: the highest software priority interrupt is serviced, if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first. Figure 2 describes this decision process. Figure 15. Priority Decision Process
PENDING INTERRUPTS

TLI (Top Level Hardware Interrupt) This hardware interrupt occurs when a specific edge is detected on the dedicated TLI pin. Caution: A TRAP instruction must not be used in a TLI service routine.

Same

SOFTWARE PRIORITY

Different

TRAP (Non Maskable Software Interrupt) This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the flowchart in Figure 1 as a TLI. Caution: TRAP can be interrupted by a TLI. RESET The RESET source has the highest priority in the CPU. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See the RESET chapter for more details.

HIGHEST SOFTWARE PRIORITY SERVICED HIGHEST HARDWARE PRIORITY SERVICED

When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. Note 1: The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt. Note 2: RESET, TRAP and TLI can be considered as having the highest software priority in the decision process. Different Interrupt Vector Sources Two interrupt source types are managed by the CPU interrupt controller: the non-maskable type (RESET, TLI, TRAP) and the maskable type (external or from internal peripherals). Non-Maskable Sources These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see Figure 1). After stacking the PC, X, A and CC registers (except for RESET), the corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level 3). These sources allow the processor to exit HALT mode.

Maskable Sources Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending. External Interrupts External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitivity is software selectable through the ITRFRE2 MISCR3 register. External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically NANDed. Peripheral Interrupts Usually the peripheral interrupts cause the Device to exit from HALT mode except those mentioned in the "Interrupt Mapping" table. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear sequence is executed.

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INTERRUPTS (Cont'd) 6.3 INTERRUPTS AND LOW POWER MODES All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT modes (see column "Exit from HALT" in "Interrupt Mapping" table). When several pending interrupts are present while exiting HALT mode, the first one serviced can only be an interrupt with exit from HALT mode capability and it is selected through the same decision process shown in Figure 2. Note: If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced. Figure 16. Concurrent Interrupt Management
SOFTW ARE PRIORITY LEVEL IT2 IT1 IT4 IT3 TLI IT0 I1 I0

6.4 CONCURRENT & NESTED MANAGEMENT The following Figure 3 and Figure 4 show two different interrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in Figure 4. The interrupt hardware priority is given in this order from the lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0, TLI. The software priority is given for each interrupt. Warning: A stack overflow may occur without notifying the software of the failure.

HARDWARE PRIORITY

TLI IT0 IT1 IT2 IT3 RIM IT4 MAIN MAIN IT1

3 3 3 3 3 3 3/0 10

11 11 11 11 11 11

11 / 10 Figure 17. Nested Interrupt Management

SOFTW ARE PRIORITY LEVEL

TLI

IT0

IT2

IT1

IT4

IT3

I1

I0

HARDWARE PRIORITY

TLI IT0 IT1 IT2 IT3 RIM IT4 MAIN IT4 MAIN IT1 IT2

3 3 2 1 3 3 3/0 10

11 11 00 01 11 11

11 / 10

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INTERRUPTS (Cont'd) 6.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read / Write Reset Value: 111x 1010 (xAh)
7 1 1 I1 H I0 N Z 0 C ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I0_9 I1_4 I1_8 I0_4 I0_8

INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX) Read/Write (bit 7:4 of ISPR3 are read only) Reset Value: 1111 1111 (FFh)
7 ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 0 I0_0

Bit 5, 3 = I1, I0 Software Interrupt Priority These two bits indicate the current interrupt software priority.
Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable*) Level Low I1 1 0 0 1 I0 0 1 0 1

ISPR2 ISPR3

I1_11 I0_11 I1_10 I0_10 I1_9 1 1 1 1

I1_13 I0_13 I1_12 I0_12

High

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see "Interrupt Dedicated Instruction Set" table). *Note: TLI, TRAP and RESET events can interrupt a level 3 program.

These four registers contain the interrupt software priority of each interrupt vector. Each interrupt vector (except RESET and TRAP) has corresponding bits in these registers where its own software priority is stored. This correspondance is shown in the following table.
Vector address FFFBh-FFFAh FFF9h-FFF8h ... FFE1h-FFE0h ISPRx bits I1_0 and I0_0 bits* I1_1 and I0_1 bits ... I1_13 and I0_13 bits

Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits in the CC register. Level 0 can not be written (I1_x=1, I0_x=0). In this case, the previously stored value is kept. (example: previous=CFh, write=64h, result=44h) The RESET, TRAP and TLI vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set. *Note: Bits in the ISPRx registers which correspond to the TLI can be read and written but they are not significant in the interrupt process management. Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behaviour has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x).

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INTERRUPTS (Cont'd) Table 6. Dedicated Interrupt Instruction Set
Instruction H ALT IRET JRM JRNM POP CC RIM SIM TR AP WFI New Description Entering Halt mode Interrupt routine return Jump if I1:0=11 Jump if I1:0<>11 Pop CC from the Stack Enable interrupt (level 0 set) Disable interrupt (level 3 set) Software trap Wait for interrupt Pop CC, A, X, PC I1:0=11 ? I1:0<>11 ? Mem => CC Load 10 in I1:0 of CC Load 11 in I1:0 of CC Software NMI I1 1 1 1 1 H I0 0 1 1 0 N Z C Function/Example I1 1 I1 H H I0 0 I0 N Z C N Z C

Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions. In order not to lose the current software priority level, the RIM, SIM, HALT, WFI and POP CC instructions should never be used in an interrupt routine.

Table 7. Interrupt Mapping
N Source Block RES ET TRAP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 PWM ART TLI MC C/RTC ei0 ei1 ei2 ei3 CAN S PI TIMER A TIMER B S CI EE PROM Reset Software Interrupt External Top Level Interrupt Main Clock Controller Time Base Interrupt External Interrupt Port A3..0 External Interrupt Port F2..0 External Interrupt Port B3..0 External Interrupt Port B7..4 CAN Peripheral Interrupts SPI Peripheral Interrupts TIMER A Peripheral Interrupts TIMER B Peripheral Interrupts SCI Peripheral Interrupts EEPROM Interrupt Not Used PWM ART Overflow Interrupt AR TCSR CANIS R SPISR TA SR TB SR SCISR EECSR Lowest Priority Yes no N/A Description Register Label N/A MISC R2 MCCSR Priority Order Highest Priority Exit from HALT 1) yes no yes Address Vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h FFE2h-FFE3h FFE0h-FFE1h

Note 1: Valid for HALT and ACTIVE-HALT modes except for the MCC/RTC interrupt source which exits from ACTIVE-HALT mode only.

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INTERRUPTS (Cont'd) Table 8. Nested Interrupts Register Map and Reset Values
Address (Hex.) Register Label 7 ei1 0024h ISPR0 Reset Value I1_3 1 SP I 0025h ISPR1 Reset Value I1_7 1 I0_7 1 I1_6 1 SCI I1_10 1 I0_10 1 I0_3 1 I1_2 1 CAN I0_6 1 I1_5 1 6 5 ei0 I0_2 1 4 3 2 1 TLI 1 ei2 I0_5 1 I1_4 1 I0_4 1 1 0

MCC/RTC I1_1 1 ei3 I0_1 1

EEP ROM 0026h ISPR2 Reset Value I1_11 1 I0_11 1

TIM E R B I1_9 1 I0_9 1

TIME R A I1_8 1 I0_8 1

PWM ART 0027h ISPR3 Reset Value 1 1 1 1 I1_13 1 I0_13 1

Not Used I1_12 1 I0_12 1

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7 POWER SAVING MODES
7.1 INTRODUCTION To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 18): SLOW, WAIT (SLOW WAIT), ACTIVE HALT and HALT. After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (fCPU). From RUN mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. Figure 18. Power Saving Mode Transitions
High RUN
fCPU

7.2 SLOW MODE This mode has two targets: To reduce power consumption by decreasing the internal clock in the device, To adapt the internal clock frequency (fCPU) to the available supply voltage. SLOW mode is controlled by three bits in the MISCR1 register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (fCPU). In this mode, the oscillator frequency can be divided by 4, 8, 16 or 32 instead of 2 in normal operating mode. The CPU and peripherals are clocked at this lower frequency. Note: SLOW-WAIT mode is activated when entering the WAIT mode while the device is already in SLOW mode. Figure 19. SLOW Mode Clock Transitions
fOSC/4 fOSC/8 fOSC/2

SLOW
fOSC/2

WAIT SLOW WAIT ACTIVE HALT HALT Low PO WER CONS UMPTION

MISCR1

CP1:0 SMS

00

01

NEW SLOW FREQUENCY REQUEST

NORMAL RUN MODE REQUEST

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POWER SAVING MODES (Cont'd) 7.3 WAIT MODE WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the `WFI' instruction. All peripherals remain active. During WAIT mode, the I[1:0] bits of the CC register are forced to `10', to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or RESET occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 20. Figure 20. WAIT Mode Flow-chart
OSCILLATOR PERIPHERALS CP U I[1:0] BITS ON ON OFF 10

WFI I N S T R U C T I O N

N RE SET N INTERRUP T Y OSCILLATOR PERIPHERALS CP U I[1:0] BITS ON OFF ON 10 Y

4096 CPU CLOCK CYCLE DELAY

OSCILLATOR ON PERIPHERALS ON CP U ON I[1:0] BITS XX 1)

FETC H RES ET VEC TOR O R SE RVICE I NTERRUPT

Note: 1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.

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POWER SAVING MODES (Cont'd) 7.4 ACTIVE-HALT AND HALT MODES ACTIVE-HALT and HALT modes are the two lowest power consumption modes of the MCU. They are both entered by executing the `HALT' instruction. The decision to enter either in ACTIVE-HALT or HALT mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR register).
MCCSR OIE bit 0 1 Power Saving Mode entered when HALT instruction is executed HALT mode ACTIVE-HALT mode H A L T INSTR UCTIO N (MC C SR. O IE=1)

Figure 21. ACTIVE-HALT Timing Overview
RUN ACTIVE HA LT 4096 CPU CYCLE D ELAY RESET OR INTER RUPT RUN

HA LT IN STRUCTION [MCCS R.OIE=1]

FE TCH VECTOR

Figure 22. ACTIVE-HALT Mode Flow-chart
OSCILLATOR ON PERIPHERALS 1) OFF CP U OFF I[1:0] BITS 10

7.4.1 ACTIVE-HALT MODE ACTIVE-HALT mode is the lowest power consumption mode of the MCU with a real time clock available. It is entered by executing the `HALT' instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is set (see Section 10.2 on page 52 for more details on the MCCSR register). The MCU can exit ACTIVE-HALT mode on reception of either an MCC/RTC interrupt, a specific interrupt (see Table 7, "Interrupt Mapping," on page 32) or a RESET. When exiting ACTIVEHALT mode by means of a RESET or an interrupt, a 4096 CPU cycle delay occurs. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 22). When entering ACTIVE-HALT mode, the I[1:0] bits in the CC register are forced to `10' to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In ACTIVE-HALT mode, only the main oscillator and its associated counter (MCC/RTC) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). The safeguard against staying locked in ACTIVEHALT mode is provided by the oscillator interrupt. Note: As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set), entering ACTIVE-HALT mode while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode.

N RE SET N Y INTERRUPT 2) Y OSCILLATOR ON PERIPHERALS OFF CP U ON I[1:0] BITS XX 3) 4096 CPU CLOCK CYCLE DELAY OSCILLATOR ON PERIPHERALS ON CP U ON I[1:0] BITS XX 3) FETC H RES ET VEC TOR O R SE RVICE I NTERRUPT

Notes: 1. Peripheral clocked with an external clock source can still be active. 2. Only the MCC/RTC interrupt and some specific interrupts can exit the MCU from ACTIVE-HALT mode (such as external interrupt). Refer to Table 7, "Interrupt Mapping," on page 32 for more details. 3. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and restored when the CC register is popped.

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POWER SAVING MODES (Cont'd) 7.4.2 HALT MODE The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the `HALT' instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is cleared (see Section 10.2 on page 52 for more details on the MCCSR register). The MCU can exit HALT mode on reception of either a specific interrupt (see Table 7, "Interrupt Mapping," on page 32) or a RESET. When exiting HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 24). When entering HALT mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes immediately. In HALT mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of Watchdog operation with HALT mode is configured by the "WDGHALT" option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see Section 14.1 on page 143 for more details). Figure 23. HALT Timing Overview
RUN HA LT 4096 CPU CYCLE D ELAY RESET OR INTER RUPT FE TCH VECTOR RUN

Figure 24. HALT Mode Flow-chart
H AL T INSTRUCTION (MCCSR.OIE=0) ENABLE W D GH A L T 1 ) 1 W ATCHDO G RE SET OSCILLATOR OFF PERIPHERALS 2) OFF CP U OFF I[1:0] BITS 10 0 W ATCHDOG DISABLE

N RE SET N Y INTERRUPT 3) Y OSCILLATOR ON PERIPHERALS OFF CP U ON I[1:0] BITS XX 4) 4096 CPU CLOCK CYCLE DELAY OSCILLATOR ON PERIPHERALS ON CP U ON I[1:0] BITS XX 4) FETC H RES ET VEC TOR O R SE RVICE I NTERRUPT

HA LT IN STRUCTION [MCCS R.OIE=0]

Notes: 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 7, "Interrupt Mapping," on page 32 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.

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8 I/O PORTS
8.1 INTRODUCTION The I/O ports offer different functional modes: transfer of data through digital inputs and outputs and for specific pins: external interrupt generation alternate signal input/output for the on-chip peripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 8.2 FUNCTIONAL DESCRIPTION Each port has 2 main registers: Data Register (DR) Data Direction Register (DDR) and one optional register: Option Register (OR) Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is shown in Figure 1. 8.2.1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Notes: 1. Writing the DR register modifies the latch value but does not affect the pin status. 2. When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. 3. Do not use read/modify/write instructions (BSET or BRES) to modify the DR register External interrupt function When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the Miscellaneous register. Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt source, these are logically NANDed. For this reason if one of the interrupt pins is tied low, it masks the other ones. In case of a floating input with interrupt configuration, special care must be taken when changing the configuration (see Figure 2). The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the Miscellaneous register must be modified. 8.2.2 Output Modes The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status:
DR 0 1 Push-pull VS S VDD Open-drain Vss Floating

8.2.3 Alternate Functions When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register. Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.

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I/O PORTS (Cont'd) Figure 25. I/O Port General Block Diagram
REGISTER ACCESS ALTERNATE O UT PUT 1 0 ALTERNATE EN ABLE DR

VDD

P-BUFFER (see table below) PULL-UP (see table below) VDD

DDR PULL-UP CONFIGURATION If implemented OR SEL N-BUFFER DDR SEL CMOS SCHMITT TRIG GER ANALO G INPUT DIOD ES (see table below) PAD

OR

EXTER NAL INTERR UPT SOURCE (eix)

Table 9. I/O Port Mode Options
Configuration Mode Input Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) True Open Drain Pull-Up Off On Off NI P-Buffer Off On Off NI On On Diodes to VDD to VSS

O u tput

Legend: NI - not implemented Off - implemented not activated On - implemented and activated

DATA BUS

DR SEL

1 0

ALTERNATE INPUT FROM OTHER BITS

POLARITY SELECTION

NI (see note)

Note: The diode to VDD is not implemented in the true open drain pads. A local protection between the pad and VSS is implemented to protect the device against positive stress.

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I/O PORTS (Cont'd) Table 10. I/O Port Configurations
Hardware Configuration
NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS VDD RPU PAD PULL-UP CONFIGURATION DR REGISTER ACCESS

DR REGISTER

W DATA BUS R

INPUT 1)

ALTERNATE INPUT FROM OTHER PINS INTERRUPT CONFIGURATION POLARITY SELECTION ANALOG INPUT NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS EXTERNAL INTERRUPT SOURCE (eix)

OPEN-DRAIN OUTPUT 2)

VDD RPU

DR REGISTER ACCESS

PAD

DR REGISTER

R/W

DATA BUS

ALTERNATE ENABLE

ALTERNATE OUTPUT

PUSH-PULL OUTPUT 2)

NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS

VDD RPU

DR REGISTER ACCESS

PAD

DR REGISTER

R/W

DATA BUS

ALTERNATE ENABLE

ALTERNATE OUTPUT

Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.

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I/O PORTS (Cont'd) CAUTION: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin. WARNING: The analog input voltage level must be within the limits stated in the absolute maximum ratings. 8.3 I/O PORT IMPLEMENTATION The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 2. Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. Figure 26. Interrupt I/O Port State Transitions
01 00 10 OUTPUT open-drain 11 O UT PUT push-pull

Standard Ports PA5:4, PC7:0, PD7:0, PE7:3, PE1:0, PF7:3
MODE floating input pull-up input open drain output push-pull output D DR 0 0 1 1 OR 0 1 0 1

Interrupt Ports PA2:0, PB7:5, PB2:0, PF1:0 (with pull-up)
MODE floating input pull-up interrupt input open drain output push-pull output D DR 0 0 1 1 OR 0 1 0 1

PA3, PB4, PB3, PF2 (without pull-up)
MODE floating input floating interrupt input open drain output push-pull output D DR 0 0 1 1 OR 0 1 0 1

True Open Drain Ports PA7:6
MODE floating input open drain (high sink ports) DDR 0 1

INPUT INPUT f l o a t i n g / p u l l - u p floating interrupt (reset state)

Pull-up Input Port (CANTX requirement) P E2
MO DE

XX = DDR, OR

pull-up input

The I/O port register configurations are summarized as follows.

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I/O PORTS (Cont'd) 8.4 LOW POWER MODES
Mode WAIT H ALT Description No effect on I/O ports. External interrupts cause the device to exit from WAIT mode. No effect on I/O ports. External interrupts cause the device to exit from HALT mode.

8.5 INTERRUPTS The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the interrupt mask in the CC register is not active (RIM instruction).
Interrupt Event External interrupt on selected external event Enable Event Control Flag Bit DDRx OR x Exit from Wait Yes Exit from Halt Yes

Table 11. Port Configuration
Input Port Pin name OR = 0 PA7:6 PA5:4 PA3 PA2:0 PB4, PB3 PB7:5, PB2:0 PC7:0 PD7:0 PE7:3, PE1:0 PE2 PF7:3 PF2 PF1:0 floating floating floating floating floating floating floating floating floating floating floating floating OR = 1 OR = 0 OR = 1 High-Sink Yes true open-drain pull-up open drain push-pull floating interrupt open drain push-pull pull-up interrupt open drain push-pull floating interrupt open drain push-pull pull-up interrupt open drain push-pull pull-up open drain push-pull pull-up open drain push-pull pull-up open drain push-pull pull-up input only * pull-up open drain push-pull floating interrupt open drain push-pull pull-up interrupt open drain push-pull Output

Port A

No

Port B Port C Port D Port E

PC3:2 only No PE7:4 only No PF7:6 only No

Port F

* Note: when the CANTX alternate function is selected the IO port operates in output push-pull mode.

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I/O PORTS (Cont'd) 8.5.1 Register Description DATA REGISTER (DR) Port x Data Register PxDR with x = A, B, C, D, E or F. Read / Write Reset Value: 0000 0000 (00h)
7 D7 D6 D5 D4 D3 D2 D1 0 D0

OPTION REGISTER (OR) Port x Option Register PxOR with x = A, B, C, D, E or F. Read / Write Reset Value: 0000 0000 (00h)
7 O7 O6 O5 O4 O3 O2 O1 0 O0

Bit 7:0 = D[7:0] Data register 8 bits. The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken into account even if the pin is configured as an input; this allows to always have the expected level on the pin when toggling to output mode. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input). DATA DIRECTION REGISTER (DDR) Port x Data Direction Register PxDDR with x = A, B, C, D, E or F. Read / Write Reset Value: 0000 0000 (00h)
7 DD7 DD6 DD5 DD4 DD3 DD2 DD1 0 DD0

Bit 7:0 = O[7:0] Option register 8 bits. For specific I/O pins, this register is not implemented. In this case the DDR register is enough to select the I/O pin configuration. The OR register allows to distinguish: in input mode if the pull-up with interrupt capability or the basic pull-up configuration is selected, in output mode if the push-pull or open drain configuration is selected. Each bit is set and cleared by software. Input mode: 0: floating input 1: pull-up input with or without interrupt Output mode: 0: output open drain (with P-Buffer unactivated) 1: output push-pull

Bit 7:0 = DD[7:0] Data direction register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bits is set and cleared by software. 0: Input mode 1: Output mode

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I/O PORTS (Cont'd) Table 12. I/O Port Register Map and Reset Values
Address (Hex.) Register Label 7 6 5 4 3 2 1 0

Reset Value of all IO port registers 0000h 0001h 0002h 0004h 0005h 0006h 0008h 0009h 000Ah 000Ch 000Dh 000Eh 0010h 0011h 0012h 0014h 0015h 0016h P ADR P ADDR P A OR P CDR P CDDR P C OR P BDR P BDDR P B OR P EDR P EDDR P E OR P DDR P DDDR P D OR P F DR P F DDR P F OR

0

0

0

0

0

0

0

0

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

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9 MISCELLANEOUS REGISTERS
The miscellaneous registers allow control over several features such as the external interrupts or the I/Oalternate functions. 9.1 I/O PORT INTERRUPT SENSITIVITY The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the Miscellaneous registers (Figure 27). This control allows to have up to 4 fully independent external interrupt source sensitivities. Each external interrupt source can be generated on four (or five) different events on the pin: Falling edge Rising edge Falling and rising edge Falling edge and low level Rising edge and high level (only for ei0 and ei2) To guarantee correct functionality, the sensitivity bits in the MISCR registers must be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3). See I/O port register and Miscellaneous register descriptions for more details on the programming. 9.2 I/O PORT ALTERNATE FUNCTIONS The MISCR registers allow to manage four I/O port miscellaneous alternate functions: Main clock signal (fOSC/2) output on PF0 A Beep signal output on PF1 (with three selectable audio frequencies) A TLI management on a dedicated pin A SPI SS pin internal control to use the PC7 I/O port function while the SPI is active. These functions are described in details in the Section 9.3 "MISCELLANEOUS REGISTERS" on page 46.

Figure 27. External Interrupt Sources vs MISCR
PA3 SOURCES PA2 PA1 PA0 SENSITIVITY MISCR2.IPA PF2 SOURCES PF1 PF0 ei1 INTERRUPT SOURCE CONTROL ei0 INTERRUPT SOURCE

MISCR1 IS20 IS21

PB3 SOURCES PB2 PB1 PB0 MISCR2.IPB PB7 SOURCES PB6 PB5 PB4

ei2 INTERRUPT SOURCE

MISCR1 IS10 IS11

SENSITIVITY ei3 INTERRUPT SOURCE CONTROL

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MISCELLANEOUS REGISTERS (Cont'd) 9.3 MISCELLANEOUS REGISTERS MISCELLANEOUS REGISTER 1 (MISCR1) Read / Write Reset Value: 0000 0000 (00h)
7 IS11 I S 1 0 MC O I S 2 1 IS20 CP1 CP0 0 SMS

Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following external interrupts: - ei0 (port A3..0)
External Interrupt Sensitivity I S 2 1 IS20 MISCR2.IPA=0 0 0 1 0 1 0 1 Falling edge & low level Rising edge only Falling edge only MIS CR2.IPA=1 Rising edge & high level Falling edge only Rising edge only

Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external interrupts: - ei2 (port B3..0)
External Interrupt Sensitivity I S 1 1 IS10 MISCR2.IPB=0 0 0 1 1 0 1 0 1 Falling edge & low level Rising edge only Falling edge only MISC R2.IPB=1 Rising edge & high level Falling edge only Rising edge only

1

Rising and falling edge

- ei1 (port F2..0)
I S 2 1 IS20 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge

Rising and falling edge

These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bit 2:1 = CP[1:0] CPU clock prescaler These bits select the CPU clock prescaler which is applied in the different slow modes. Their action is conditioned by the setting of the SMS bit. These two bits are set and cleared by software
fCPU in SLOW mode fOSC / 4 fOSC / 8 fOSC / 16 fOSC / 32 CP1 0 1 0 1 CP0 0 0 1 1

- ei3 (port B7..4)
I S 1 1 IS10 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge

These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bit 5 = MCO Main clock out selection This bit enables the MCO alternate function on the PF0 I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for general-purpose I/O) 1: MCO alternate function enabled (fOSC/2on I/O port) Note: To reduce power consumption, the MCO function is not active in ACTIVE-HALT mode.

Bit 0 = SMS Slow mode select This bit is set and cleared by software. 0: Normal mode. fCPU = fOSC / 2 1: Slow mode. fCPU is given by CP1, CP0 See Section 7.2 "SLOW MODE" on page 34 and Section 10.2 "MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC)" on page 52 for more details.

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MISCELLANEOUS REGISTERS (Cont'd) MISCELLANEOUS REGISTER 2 (MISCR2) Read / Write Reset Value: 0000 0000 (00h)
7 IPA IPB B C1 BC0 TLIS TLIE SS M 0 SSI

Bit 3 = TLIS TLI sensitivity This bit allows to toggle the TLI edge sensitivity. It can be set and cleared by software only when TLIE bit is cleared. 0: Falling edge 1: Rising edge Bit 2 = TLIE TLI enable This bit allows to enable or disable the TLI capability on the dedicated pin. It is set and cleared by software. 0: TLI disabled 1: TLI enabled Note: a parasitic interrupt can be generated when clearing the TLIE bit. Bit 1 = SSM SS mode selection This bit is set and cleared by software. 0: Normal mode - the level of the SPI SS signal is input from the external SS pin. 1: I/O mode (PC7), the level of the SPI SS signal is read from the SSI bit. Bit 0 = SSI SS internal mode This bit replaces pin SS of the SPI when bit SSM is set to 1. (see SPI description). It is set and cleared by software.

Bit 7 = IPA Interrupt polarity for port A This bit is used to invert the sensitivity of the port A [3:0] external interrupts. It is set and cleared by software. 0: No sensitivity inversion 1: Sensitivity inversion See Section 9.1 "I/O PORT INTERRUPT SENSITIVITY" on page 45 and the description of the IS2x bits of the MISCR1 register for more details. Bit 6 = IPB Interrupt polarity for port B This bit is used to invert the sensitivity of the port B [3:0] external interrupts. It is set and cleared by software. 0: No sensitivity inversion 1: Sensitivity inversion See Section 9.1 "I/O PORT INTERRUPT SENSITIVITY" on page 45 and the description of the IS1x bits of the MISCR1 register for more details. Bit 5:4 = BC[1:0] Beep control These 2 bits select the PF1 pin beep capability.
BC1 0 0 1 1 BC 0 0 1 0 1 ~2-KHz ~1-K Hz ~500-Hz Beep mode with fOSC=16MHz Off Output Beep signal ~50% duty cycle

The beep output signal is available in ACTIVEHALT mode but has to be disabled to reduce the consumption.

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MISCELLANEOUS REGISTERS (Cont'd) Table 13. Miscellaneous Register Map and Reset Values
Address (Hex.) 0020h 0040h Register Label MISCR1 Reset Value MISCR2 Reset Value 7 IS11 0 IPA 0 6 IS10 0 IPB 0 5 MCO 0 BC1 0 4 IS21 0 BC0 0 3 IS20 0 TLIS 0 2 CP 1 0 TLIE 0 1 CP0 0 S SM 0 0 SMS 0 SS I 0

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10 ON-CHIP PERIPHERALS
10.1 WATCHDOG TIMER (WDG) 10.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter's contents before the T6 bit becomes cleared. 10.1.2 Main Features Programmable timer (64 increments of 12288 CPU cycles) Programmable reset Reset (if watchdog activated) after a HALT instruction or when the T6 bit reaches zero Figure 28. Watchdog Block Diagram

Hardware Watchdog selectable by option byte Watchdog Reset indicated by status flag (in versions with Safe Reset option only)

10.1.3 Functional Description The counter value stored in the CR register (bits T[6:0]), is decremented every 12,288 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns.

RESET

WATCHDOG CONTROL REGISTER (CR) WDG A T6 T5 T4 T3 T2 T1 T0

7-BIT DOWNCOUNTER

fCPU

CLOCK DIVIDER ÷12288

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WATCHDOG TIMER (Cont'd) The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. The value to be stored in the CR register must be between FFh and C0h (see Table 14 .Watchdog Timing (fCPU = 8 MHz)): The WDGA bit is set (watchdog enabled) The T6 bit is set to prevent generating an immediate reset The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. Table 14.Watchdog Timing (fCPU = 8 MHz)
CR Register initial value Max Min FFh C0h WDG timeout period (ms) 98.304 1.536

10.1.7 Register Description CONTROL REGISTER (CR) Read / Write Reset Value: 0111 1111 (7F h)
7 WDG A T6 T5 T4 T3 T2 T1 0 T0

Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watchdog option is enabled by option byte. Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared). STATUS REGISTER (SR) Read / Write Reset Value*: 0000 0000 (00 h)
7 0 WDO GF

Notes: Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). If the watchdog is activated, the HALT instruction will generate a Reset. 10.1.4 Hardware Watchdog Option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used. Refer to the device-specific Option Byte description. 10.1.5 Low Power Modes
M ode WAIT HALT Description No effect on Watchdog.

Bit 0 = WDOGF Watchdog flag. This bit is set by a watchdog reset and cleared by software or a power on/off reset. This bit is useful for distinguishing power/on off or external reset and watchdog reset. 0: No Watchdog reset occurred 1: Watchdog reset occurred * Only by software and power on/off reset Note: This register is not used in versions without LVD Reset.

Immediate reset generation as soon as the HALT instruction is executed if the Watchdog is activated (WDGA bit is set).

10.1.6 Interrupts None.

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WATCHDOG TIMER (Cond't) Table 15. Watchdog Timer Register Map and Reset Values
Address (Hex.) 002Ah 002Bh Register Label W D GC R Reset Value W D GS R Reset Value 7 WD GA 0 0 6 T6 1 0 5 T5 1 0 4 T4 1 0 3 T3 1 0 2 T2 1 0 1 T1 1 0 0 T0 1 WDOG F 0

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10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC) The Main Clock Controller consists of three different functions: a programmable CPU clock prescaler a clock-out signal to supply external devices a real time clock timer with interrupt capability Each function can be used independently and simultaneously. 10.2.1 Programmable CPU Clock Prescaler The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal peripherals. It manages SLOW power saving mode (See Section 7.2 "SLOW MODE" on page 34 for more details). The prescaler selects the fCPU main clock frequency and is controlled by three bits in the MISCR1 register: CP[1:0] and SMS. CAUTION: The prescaler does not act on the CAN peripheral clock source. This peripheral is always supplied by the fOSC/2 clock source. 10.2.2 Clock-out Capability The clock-out capability is an alternate function of an I/O port pin that outputs a fOSC/2 clock to drive external devices. It is controlled by the MCO bit in the MISCR1 register. CAUTION: When selected, the clock out pin suspends the clock during ACTIVE-HALT mode. 10.2.3 Real Time Clock Timer (RTC) The counter of the real time clock timer allows an interrupt to be generated based on an accurate real time clock. Four different time bases depending directly on fOSC are available. The whole functionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and OIF. When the RTC interrupt is enabled (OIE bit set), the ST7 enters ACTIVE-HALT mode when the HALT instruction is executed. See Section 7.4 "ACTIVE-HALT AND HALT MODES" on page 36 for more details.

Figure 29. Main Clock Controller (MCC/RTC) Block Diagram
CLOCK TO CAN PERIPHERAL PORT ALTERNATE FUNCTION fOSC/2 MISCR1 MCO CP1 CP0 SMS

MCO

fOSC

DIV 2 RTC COUNTER

DIV 2, 4, 8, 16 fCPU

CPU CLOCK TO CPU AND PERIPHERALS

MCCSR 0 0 0 0 TB1 TB0 OIE OIF

MCC/RTC INTERRUPT

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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (Cont'd) 10.2.4 Register Description MISCELLANEOUS REGISTER 1 (MISCR1) See "MISCELLANEOUS REGISTERS" Section. MAIN CLOCK CONTROL/STATUS REGISTER (MCCSR) Read / Write Reset Value: 0000 0001 (01h)
7
0 0 0 0 TB1 TB0 OIE

Bit 0 = OIF Oscillator interrupt flag This bit is set by hardware and cleared by software reading the CSR register. It indicates when set that the main oscillator has reached the selected elapsed time (TB1:0). 0: Timeout not reached 1: Timeout reached CAUTION: The BRES and BSET instructions must not be used on the MCCSR register to avoid unintentionally clearing the OIF bit. 10.2.5 Low Power Modes

0
OIF

Mode

Description No effect on MCC/RTC peripheral. MCC/RTC interrupt cause the device to exit from WAIT mode. No effect on MCC/RTC counter (OIE bit is set), the registers are frozen. MCC/RTC interrupt cause the device to exit from ACTIVE-HALT mode. MCC/RTC counter and registers are frozen. MCC/RTC operation resumes when the MCU is woken up by an interrupt with "exit from HALT" capability.

Bit 7:4 = Reserved, always read as 0. Bit 3:2 = TB[1:0] Time base control These bits select the programmable divider time base. They are set and cleared by software.
Counter Prescaler 32000 64000 160000 40 0 0 Time Base TB1 fOSC =8MHz 4ms 8ms 20ms 50ms fOSC=16MHz 2ms 4ms 10m s 25m s 0 0 1 1 0 1 0 1 TB0

WAIT

A C TIVEH AL T

H AL T

10.2.6 Interrupts The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is set and the interrupt mask in the CC register is not active (RIM instruction).
Interrupt Event Time base overflow event Enable Event Control Flag Bit OIF OIE Exit from Wait Yes Exit from Halt No 1)

A modification of the time base is taken into account at the end of the current period (previously set) to avoid an unwanted time shift. This allows to use this time base as a real time clock. Bit 1 = OIE Oscillator interrupt enable This bit set and cleared by software. 0: Oscillator interrupt disabled 1: Oscillator interrupt enabled This interrupt can be used to exit from ACTIVEHALT mode. When this bit is set, calling the ST7 software HALT instruction enters the ACTIVE-HALT power saving mode.

Note: 1. The MCC/RTC interrupt allows to exit from ACTIVE-HALT mode, not from HALT mode.

Table 16. MCC/RTC Register Map and Reset Values
Address (Hex.) 0029h Register Label M CCSR Reset Value 7 6 5 4 3 TB1 0 2 TB0 0 1 OIE 0 0 OIF 1

0

0

0

0

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10.3 PWM AUTO-RELOAD TIMER (ART) 10.3.1 Introduction The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit auto reload counter with compare capabilities and of a 7-bit prescaler clock source. These resources allow three possible operating modes: Generation of up to 4 independent PWM signals Output compare and Time base interrupt External event detector Figure 30. PWM Auto-Reload Timer Block Diagram

The two first modes can be used together with a single counter frequency. The timer can be used to wake up the MCU from WAIT and HALT modes.

PWMCR

OEx

OPx

OCRx REGISTER LOAD

DCRx REGISTER

PWMx

PORT ALTERNATE FUNCTION

POLARITY CONTROL

COMPARE

ARR REGISTER

8-BIT COUNTER (CAR REGISTER)

LOAD

ARTCLK

fEXT f CPU

f COUNTER MUX fINPUT

PROGRAMMABLE PRESCALER

EXCL

CC2

CC1

CC0

TCE

FCRL

OIE

OVF

ARTCSR

OVF INTERRUPT

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ON-CHIP PERIPHERALS (Cont'd) 10.3.2 Functional Description Counter The free running 8-bit counter is fed by the output of the prescaler, and is incremented on every rising edge of the clock signal. It is possible to read or write the contents of the counter on the fly by reading or writing the Counter Access register (ARTCAR). When a counter overflow occurs, the counter is automatically reloaded with the contents of the ARTARR register (the prescaler is not affected). Counter clock and prescaler The counter clock frequency is given by: fCOUNTER = fINPUT / 2CC[2:0] The timer counter's input clock (fINPUT) feeds the 7-bit programmable prescaler, which selects one of the 8 available taps of the prescaler, as defined by CC[2:0] bits in the Control/Status Register (ARTCSR). Thus the division factor of the prescaler can be set to 2n (where n = 0, 1,..7). This fINPUT frequency source is selected through the EXCL bit of the ARTCSR register and can be either the fCPU or an external input frequency fEXT. The clock input to the counter is enabled by the TCE (Timer Counter Enable) bit in the ARTCSR register. When TCE is reset, the counter is stopped and the prescaler and counter contents are frozen. When TCE is set, the counter runs at the rate of the selected clock source. Figure 31. Output compare control
fCOUNTER AR TAR R =FD h COUNTER FDh FEh FFh FDh F Eh FFh FDh FEh FFh

Counter and Prescaler Initialization After RESET, the counter and the prescaler are cleared and fINPUT = fCPU. The counter can be initialized by: Writing to the ARTARR register and then setting the FCRL (Force Counter Re-Load) and the TCE (Timer Counter Enable) bits in the ARTCSR register. Writing to the ARTCAR counter access register, In both cases the 7-bit prescaler is also cleared, whereupon counting will start from a known value. Direct access to the prescaler is not possible. Output compare control The timer compare function is based on four different comparisons with the counter (one for each PWMx output). Each comparison is made between the counter value and an output compare register (OCRx) value. This OCRx register can not be accessed directly, it is loaded from the duty cycle register (PWMDCRx) at each overflow of the counter. This double buffering method avoids glitch generation when changing the duty cycle on the fly.

OCRx

FDh

F Eh

PWMDCRx

FDh

FEh

PWMx

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ON-CHIP PERIPHERALS (Cont'd) Independent PWM signal generation This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx output pins with minimum core processing overhead. This function is stopped during HALT mode. Each PWMx output signal can be selected independently using the corresponding OEx bit in the PWM Control register (PWMCR). When this bit is set, the corresponding I/O pin is configured as output push-pull alternate function. The PWM signals all have the same frequency which is controlled by the counter period and the ARTARR register value. fPWM = fCOUNTER / (256 - ARTARR) When a counter overflow occurs, the PWMx pin level is changed depending on the corresponding OPx (output polarity) bit in the PWMCR register. Figure 32. PWM Auto-reload Timer Function
255 DUTY CYCLE R EGIST ER (PWMDCRx)

When the counter reaches the value contained in one of the output compare register (OCRx) the corresponding PWMx pin level is restored. It should be noted that the reload values will also affect the value and the resolution of the duty cycle of the PWM output signal. To obtain a signal on a PWMx pin, the contents of the OCRx register must be greater than the contents of the ARTARR regis ter. The maximum available resolution for the PWMx duty cycle is: Resolution = 1 / (256 - ARTARR) Note: To get the maximum resolution (1/256), the ARTARR register must be 0. With this maximum resolution, 0% and 100% can be obtained by changing the polarity.

COUNTER

AUTO-RELOAD R EGIST ER (ARTARR) 000

t

PWMx OUTPUT

WITH OEx=1 AND OPx=0 WITH OEx=1 AND OPx=1

Figure 33. PWM Signal from 0% to 100% Duty Cycle
fCOUNTER AR TAR R =FD h COUNTER FDh FEh FFh FDh F Eh FFh FDh FEh

OCRx=FCh PWMx OUTPUT WITH OEx=1 AND OPx=0 OCRx=FDh OCRx=FEh OCRx=FFh

t

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ON-CHIP PERIPHERALS (Cont'd) Output compare and Time base interrupt On overflow, the OVF flag of the ARTCSR register is set and an overflow interrupt request is generated if the overflow interrupt enable bit, OIE, in the ARTCSR register, is set. The OVF flag must be reset by the user software. This interrupt can be used as a time base in the application. External clock and event detector mode Using the fEXT external prescaler input clock, the auto-reload timer can be used as an external clock event detector. In this mode, the ARTARR register is used to select the nEVENT number of events to be counted before setting the OVF flag. nEVENT = 256 - ARTARR Caution: The external clock function is not available in HALT mode. If HALT mode is used in the application, prior to executing the HALT instruction, the counter must be disabled by clearing the TCE bit in the ARTCSR register to avoid spurious counter increments.

Figure 34. External Event Detector Example (3 counts)

fEXT=fCOUNTER AR TAR R =FD h

COUNTER

FDh

FEh

FFh

FDh

F Eh

FFh

FDh

OVF

ARTCSR READ INTERRUPT IF OIE=1 INTERRUPT IF OIE=1

ARTCSR READ

t

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ON-CHIP PERIPHERALS (Cont'd) 10.3.3 Register Description CONTROL / STATUS REGISTER (ARTCSR) Read / Write Reset Value: 0000 0000 (00h)
7 EXCL CC2 CC1 CC0 TCE FCRL OIE 0 OVF 7 0 CA6 CA5 CA4 CA3 CA2 CA1 CA0

0: New transition not yet reached 1: Transition reached COUNTER ACCESS REGISTER (ARTCAR) Read / Write Reset Value: 0000 0000 (00h)

Bit 7 = EXCL External Clock This bit is set and cleared by software. It selects the input clock for the 7-bit prescaler. 0: CPU clock. 1: External clock. Bit 6:4 = CC[2:0] Counter Clock Control These bits are set and cleared by software. They determine the prescaler division ratio from fINPUT.
f COUNTER fINPUT fINPUT / 2 fINPUT / 4 fINPUT / 8 fINPUT / 16 fINPUT / 32 fINPUT / 64 fINPUT / 128 With fINPUT=8 MHz CC2 CC1 CC0 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

CA7

Bit 7:0 = CA[7:0] Counter Access Data These bits can be set and cleared either by hardware or by software. The ARTCAR register is used to read or write the auto-reload counter "on the fly" (while it is counting).

AUTO-RELOAD REGISTER (ARTARR) Read / Write Reset Value: 0000 0000 (00h)
7 AR7 AR6 AR5 AR4 AR3 AR2 AR1 0 AR0

Bit 3 = TCE Timer Counter Enable This bit is set and cleared by software. It puts the timer in the lowest power consumption mode. 0: Counter stopped (prescaler and counter frozen). 1: Counter running. Bit 2 = FCRL Force Counter Re-Load This bit is write-only and any attempt to read it will yield a logical zero. When set, it causes the contents of ARTARR register to be loaded into the counter, and the content of the prescaler register to be cleared in order to initialize the timer before starting to count. Bit 1 = OIE Overflow Interrupt Enable This bit is set and cleared by software. It allows to enable/disable the interrupt which is generated when the OVF bit is set. 0: Overflow Interrupt disable. 1: Overflow Interrupt enable. Bit 0 = OVF Overflow Flag This bit is set by hardware and cleared by software reading the ARTCSR register. It indicates the transition of the counter from FFh to the ARTARR value.

Bit 7:0 = AR[7:0] Counter Auto-Reload Data These bits are set and cleared by software. They are used to hold the auto-reload value which is automatically loaded in the counter when an overflow occurs. At the same time, the PWM output levels are changed according to the corresponding OPx bit in the PWMCR register. This register has two PWM management functions: Adjusting the PWM frequency Setting the PWM duty cycle resolution PWM Frequency vs Resolution:
ARTA RR value 0 [ 0..127 ] [ 128..191 ] [ 192..223 ] [ 224..239 ] Resolution Min 8-bit > 7-bit > 6-bit > 5-bit > 4-bit ~0.244 kHz ~0.244 kHz ~0.488 kHz ~0.977 kHz ~1.953 kHz fPWM Max 31.25 kHz 62.5 kHz 125 kHz 250 kHz 500 kHz

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ON-CHIP PERIPHERALS (Cont'd) PWM CONTROL REGISTER (PWMCR) Read / Write Reset Value: 0000 0000 (00h)
7 OE3 OE2 OE1 OE0 OP3 OP2 OP1 0 OP0

DUTY CYCLE REGISTERS (PWMDCRx) Read / Write Reset Value: 0000 0000 (00h)
7 DC7 DC6 DC5 DC4 DC3 DC2 DC1 0 DC0

Bit 7:4 = OE[3:0] PWM Output Enable These bits are set and cleared by software. They enable or disable the PWM output channels independently acting on the corresponding I/O pin. 0: PWM output disabled. 1: PWM output enabled. Bit 3:0 = OP[3:0] PWM Output Polarity These bits are set and cleared by software. They independently select the polarity of the four PWM output signals.
PWMx output level OPx Counter <= OCRx 1 0 Counter > OCRx 0 1 0 1

Bit 7:0 = DC[7:0] Duty Cycle Data These bits are set and cleared by software. A PWMDCRx register is associated with