Datasheets | Microcontrollers | 8-bit Microcontrollers | ST7 - 8-bit Microcontrollers

8-bit MCU with single voltage Flash memory, ADC, 16-bit timers, SPI, I2C interfaces

Datasheet

Format: (3232 kb)

Last Updated: 02/04/2008

Pages: 141

Untitled Document

Generic Part Number

Orderable Part Number

Status

ST72104G1	ST72C104G1M6	Active
	ST72C104G1B6	Active
ST72104G2	ST72C104G2M6	Active
	ST72C104G2B6	Active
ST72215G2	ST72C215G2M6	Active
	ST72C215G2B6	Active
	ST72C215G2M3	Active
ST72216G1	ST72C216G1M6	Active
	ST72C216G1B6	Active
ST72254G1	ST72C254G1B6	Active
	ST72C254G1M6	Active
ST72254G2	ST72C254G2M3	Active
	ST72C254G2M6	Active
	ST72C254G2B6	Active

Related Application Notes

MCUS - 8/16/32-BIT MICROCONTROLLERS (MCUS) APPLICATION NOTES ABSTRACTS BY TOPICS

Performance comparison between ST72254 and PIC16F876

Related Programming Manuals

ST7 FAMILY FLASH PROGRAMMING REFERENCE MANUAL

ST7 FAMILY PROGRAMMING MANUAL

ST7 Flash programming quick reference guide

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(Unformatted textual content of the document used by search engines)

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, I2C INTERFACES

Memories 4K or 8K bytes Program memory (ROM and single voltage FLASH) with read-out protection and in-situ programming (remote ISP) 256 bytes RAM Clock, Reset and Supply Management Enhanced reset system Enhanced low voltage supply supervisor with 3 programmable levels Clock sources: crystal/ceramic resonator oscillators or RC oscillators, external clock, backup Clock Security System Clock-out capability 3 Power Saving Modes: Halt, Wait and Slow Interrupt Management 7 interrupt vectors plus TRAP and RESET 22 external interrupt lines (on 2 vectors) 22 I/O Ports 22 multifunctional bidirectional I/O lines 14 alternate function lines 8 high sink outputs 3 Timers Configurable watchdog timer Two 16-bit timers with: 2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes (one only on ST72104Gx and ST72216G1) 2 Communications Interfaces SPI synchronous serial interface I2C multimaster interface (only on ST72254Gx) 1 Analog peripheral 8-bit ADC with 6 input channels (except on ST72104Gx)

SDIP32

SO28

Instruction Set 8-bit data manipulation 63 basic instructions 17 main addressing modes 8 x 8 unsigned multiply instruction True bit manipulation Development Tools Full hardware/software development package

Device Summary
Features Program memory - bytes RAM (stack) - bytes Peripherals Operating Supply CPU Frequency Operating Temperature Packages ST72104G1 4K ST72104G2 8K ST72216G1 4K ST72215G2 8K ST72254G1 4K ST72254G2 8K 256 (128) Watchdog timer, Watchdog timer, Watchdog timer, Watchdog timer, One 16-bit timer, One 16-bit timer, Two 16-bit timers, Two 16-bit timers, SPI SPI, ADC SPI, ADC SPI, I²C, ADC 3.2V to 5.5 V Up to 8 MHz (with oscillator up to 16 MHz) 0C to 70C / -10C to +85C (-40C to +85C / -40C to105C / -40C to 125C optional) SO28 / SDIP32

March 2008

Rev. 3

1/141

1

Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 4.3 4.4 4.5 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 STRUCTURAL ORGANISATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 IN-SITU PROGRAMMING (ISP) MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 MEMORY READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 5.3 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 20 20 20 21 22 22 22 22 23 6.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3 Internal Low Voltage Detection RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.4 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 6.4.1 Clock Filter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.2 Safe Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.3 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 CLOCK RESET AND SUPPLY REGISTER DESCRIPTION (CRSR) . . . . . . . . . . . . . . . 6.6

CLOCK SECURITY SYSTEM (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

MAIN CLOCK CONTROLLER (MCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1 NON-MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2 7.3 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.2 8.3 8.4 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 30 30 30 33 9.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141. ... 9.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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9.4 9.5 9.6 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.3 MISCELLANEOUS REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.4 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 39 39 40 40 40 40 42 42 42 42 54 54 54 55 60 60 60 60 62 69 69 70 73 73 73 73 75 79 79 80 86 86 86 86 87 87 88

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12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.7 Relative Mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 91 91 91 91 92 92 93

13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 13.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 96 96 96 96 97 97 97 97 98

13.3.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 13.3.2 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . 100 13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 13.4.1 RUN and SLOW Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2 WAIT and SLOW WAIT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.3 HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.4 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.5 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.4 RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.5 Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 103 104 104 104 105 105 105 106 110 111 112

13.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 13.6.2 FLASH Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 13.7.1 Functional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7.2 Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7.3 ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 114 116 118

13.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 118 ... 13.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

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Table of Contents
13.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 13.9.2 ISPSEL Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 13.10.1 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 13.10.2 16-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 13.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 125 13.11.1 SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 13.11.2 I2C - Inter IC Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 13.12 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 14.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 14.3 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 133 15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 134 15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 15.3.1 PACKAGE/SOCKET FOOTPRINT PROPOSAL . . . . . . . . . . . . . . . . . . . . . . . . 137 15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 16 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

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1 INTRODUCTION
The ST72104G, ST72215G, ST72216G and ST72254G devices are members of the ST7 microcontroller family. They can be grouped as follows : ST72254G devices are designed for mid-range applications with ADC and I²C interface capabilities. ST72215/6G devices target the same range of applications but without I²C interface. ST72104G devices are for applications that do not need ADC and I²C peripherals. All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set. The ST72C104G, ST72C215G, ST72C216G and ST72C254G versions feature single-voltage FLASH memory with byte-by-byte In-Situ Programming (ISP) capability. Figure 1. General Block Diagram Under software control, all devices can be placed in WAIT, SLOW, or HALT mode, reducing power consumption when the application is in idle or stand-by state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. For easy reference, all parametric data are located in Section 13 on page 96.

OSC1 OSC2

MULTI OSC + CLOCK FILTER
LVD

Internal CLOCK I2C PORT A PA7:0 (8 bits)

VDD VSS RESET

POWER SUPPLY
ADDRESS AND DATA BUS

SPI PORT B 16-BIT TIMER A PORT C 8-BIT ADC 16-BIT TIMER B PB7:0 (8 bits)

CONTROL 8-BIT CORE ALU PROGRAM MEMORY (4 or 8K Bytes)

PC5:0 (6 bits)

RAM (256 Bytes)

WATCHDOG

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2 PIN DESCRIPTION
Figure 2. 28-Pin SO Package Pinout
RE SET O SC1 O SC2 SS/ P B 7 ISPCLK/SCK/PB6 ISPDATA/MISO/PB5 MO SI/PB4 OC MP2_A/PB3 ICAP2_A/PB2 OC MP1_A/PB1 ICAP1_A/PB0 AIN5/EXTCLK_A/PC5 A I N 4 / O C MP 2 _ B / P C 4 AIN3/ICAP2_B/PC3 VDD VS S ISPSEL PA0 (HS) PA1 (HS) PA2 (HS) PA3 (HS) PA4 (HS)/SCLI PA5 (HS) PA6 (HS)/SDAI PA7 (HS) PC 0/IC AP1_B/A IN0 PC 1/OCM P 1_B/A IN1 PC2/MCO/AIN2
(HS) 20mA high sink capability eiX associated external interrupt vector

1 2 3 4 5 6 7 8 9 10 11 12 13 14 ei0 or ei1 ei1 ei0

28 27 26 25 24 23 22 21 20 19 18 17 16 15

Figure 3. 32-Pin SDIP Package Pinout
R ESET O SC1 O SC2 SS/ P B 7 ISPCLK/SCK/PB6 ISPDATA/MISO/PB5 MO SI/PB4 NC NC O CMP2_A/PB3 ICAP2_A/PB2 O CMP1_A/PB1 ICAP1_A/PB0 AIN5/EXTCLK_A/PC5 AIN4/O CMP2_B/PC4 AIN3/ICAP2_B/PC3 VDD VS S ISPSEL PA0 (HS) PA1 (HS) PA2 (HS) PA3 (HS) NC NC PA4 (HS)/SCLI PA5 (HS) PA6 (HS)/SDAI PA7 (HS) PC 0/ICAP1_B/AIN0 PC 1/OC MP1_B/AIN1 PC 2/MC O/AIN2
(HS) 20mA high sink capability eiX associated external interrupt vector

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ei0 or ei1 ei1 ei0 ei1 ei0

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

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PIN DESCRIPTION (Cont'd) For external pin connection guidelines, refer to Section 13 "ELECTRICAL CHARACTERISTICS" on page 96. Legend / Abbreviations for Table 1: Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C = CMOS 0.3VDD/0.7VDD, CT= CMOS 0.3VDD/0.7VDD with input trigger Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration: Input: float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog Output: OD = open drain 2), PP = push-pull Refer to Section 9 "I/O PORTS" on page 30 for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state. Table 1. Device Pin Description
Pin n Type SDIP32 SO 28 Pin Name Level Output Input Port / Control Input fl oat wpu ana int O u tput OD PP Main Function (after reset) Alternate Function

1 2 3 4 5 6 7 8 9 10 11

1 RESET 2 OSC1 3) 3 OSC2 3) 4 PB7/SS 5 PB6/SCK/ISPCLK 6 PB5/MISO/ISPDATA 7 PB4/MOSI NC

I/O CT I O I/O I/O I/O I/O CT CT CT CT X X X X

X

X

Top priority non maskable interrupt (active low) External clock input or Resonator oscillator inverter input or resistor input for RC oscillator Resonator oscillator inverter output or capacitor input for RC oscillator

ei1 ei1 ei1 ei1

X X X X

X X X X

Port B7 Port B6 Port B5 Port B4

SPI Slave Select (active low) SPI Serial Clock or ISP Clock SPI Master In/ Slave Out Data or ISP Data SPI Master Out / Slave In Data

Not Connected NC 8 PB3/OCMP2_A 9 PB2/ICAP2_A I/O I/O I/O I/O CT CT CT CT CT CT CT CT X X X X ei1 ei1 ei1 ei1 X X X X X X X X X X X X X X X X Port B3 Port B2 Port B1 Port B0 Port C5 Port C4 Port C3 Port C2 Timer A Output Compare 2 Timer A Input Capture 2 Timer A Output Compare 1 Timer A Input Capture 1 Timer A Input Clock or ADC Analog Input 5 Timer B Output Compare 2 or ADC Analog Input 4 Timer B Input Capture 2 or ADC Analog Input 3 Main clock output (fCPU) or ADC Analog Input 2

12 10 PB1 /OCMP1_A 13 11 PB0 /ICAP1_A

14 12 PC5/EXTCLK_A/AIN5 I/O 15 13 PC4/OCMP2_B/AIN4 16 14 PC3/ ICAP2_B/AIN3 17 15 PC2/MCO/AIN2 I/O I/O I/O

X ei0/ei1 X ei0/ei1 X ei0/ei1 X X ei0/ei1 X

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Pin n Type SDIP32 SO28 Pin Name

Level O u tput Input

Port / Control Input float wpu ana int O u tput OD PP Main Function (after reset) Port C1 Port C0 Port A7 Port A6 X Port A5 Port A4 Not Connected I2C Clock I2C Data Alternate Function

18 16 PC1/OCMP1_B/AIN1 19 17 PC0/ICAP1_B/AIN0 20 18 PA7 21 19 PA6 /SDAI 22 20 PA5 23 21 PA4 /SCLI 24 25 NC NC

I/O I/O

CT CT

X ei0/ei1 X X ei0/ei1 X X X X X ei0 ei0 ei0 ei0

X X X T X T

X X X

Timer B Output Compare 1 or ADC Analog Input 1 Timer B Input Capture 1 or ADC Analog Input 0

I/O CT HS I/O CT HS I/O CT HS I/O CT HS

26 22 PA3 27 23 PA2 28 24 PA1 29 25 PA0 30 26 ISPSEL 3 1 2 7 VS S 3 2 2 8 VDD

I/O CT HS I/O CT HS I/O CT HS I/O CT HS I S S C

X X X X X

ei0 ei0 ei0 ei0

X X X X

X X X X

Port A3 Port A2 Port A1 Port A0 In situ programming selection (Should be tied low in standard user mode). Ground Main power supply

Notes: 1. In the interrupt input column, "eiX" defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input. 2. In the open drain output column, "T" defines a true open drain I/O (P-Buffer and protection diode to VDD are not implemented). See Section 9 "I/O PORTS" on page 30 and Section 13.8 "I/O PORT PIN CHARACTERISTICS" on page 118 for more details. 3. OSC1 and OSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to the on-chip oscillator see Section 2 "PIN DESCRIPTION" on page 7 and Section 13.5 "CLOCK AND TIMING CHARACTERISTICS" on page 105 for more details.

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3 REGISTER & MEMORY MAP
As shown in the Figure 4, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register location, 256 bytes of RAM and up to 8Kbytes of user program memory. The RAM space includes up to 128 bytes for the stack from 0100h to 017Fh. The highest address bytes contain the user reset and interrupt vectors. Figure 4. Memory Map IMPORTANT: Memory locations marked as "Reserved" must never be accessed. Accessing a reserved area can have unpredictable effects on the device.

0000h 007Fh 0080h

HW Registers (see Table 2)

0080h

256 Bytes RAM
017Fh 0180h

00FFh 0100h

Short Addressing RAM Zero page (128 Bytes) Stack or 16-bit Addressing RAM (128 Bytes)

Reserved
DFFFh E000h

017Fh

Program Memory (4K, 8 KBytes)
FFDFh FFE0h FFFFh

E000h

8 KBytes
F000h

Interrupt & Reset Vectors (see Table 5 on page 26)

4 KBytes
FFFFh

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Table 2. Hardware Register Map
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh to 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh to 0030h I2CCR I2CSR1 I2CSR2 I2CCCR I2COAR1 I2COAR2 I2CDR SPI W ATCHDOG MIS CR1 SPID R SPICR SPISR WDG C R CRSR PADR PADDR PAOR Port B PBDR PBDDR PBOR Block Register Label PCDR PCDDR PCOR Register Name Port C Data Register Port C Data Direction Register Port C Option Register Reserved (1 Byte) Port B Data Register Port B Data Direction Register Port B Option Register Reserved (1 Byte) Port A Data Register Port A Data Direction Register Port A Option Register 00h 1) 00h 00h R/W R/W R/W 00h 1) 00h 00h R/W R/W R/W. Reset Status 00h 1) 00h 00h R e ma r k s R/W 2) R/W 2) R/W 2)

Port C

Port A

Reserved (21 Bytes) Miscellaneous Register 1 SPI Data I/O Register SPI Control Register SPI Status Register Watchdog Control Register 00h xxh 0xh 00h 7Fh R/W R/W R/W Read Only R/W

Clock, Reset, Supply Control / Status Register 000x 000x R/W Reserved (2 bytes) Control Register Status Register 1 Status Register 2 Clock Control Register Own Address Register 1 Own Address Register 2 Data Register Reserved (2 Bytes) 00h 00h 00h 00h 00h 00h 00h R/W Read Only Read Only R/W R/W R/W R/W

I 2C

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Address 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h to 006Fh 0070h 0071h 0072h to 007Fh

Block

Register Label TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR MIS CR2 TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR

Register Name Timer A Control Register 2 Timer A Control Register 1 Timer A Status Register Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low Register Timer A Input Capture 2 High Register Timer A Input Capture 2 Low Register Timer A Output Compare 2 High Register Timer A Output Compare 2 Low Register Miscellaneous Register 2 Timer B Control Register 2 Timer B Control Register 1 Timer B Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register Reserved (32 Bytes)

Reset Status 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h 00h 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h

R e ma r k s R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W R/W R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W

TIMER A

TIMER B

ADC

ADCDR ADCCSR

Data Register Control/Status Register Reserved (14 Bytes)

00h 00h

Read Only R/W

Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value.

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4 FLASH PROGRAM MEMORY
4.1 INTRODUCTION FLASH devices have a single voltage non-volatile FLASH memory that may be programmed in-situ (or plugged in a programming tool) on a byte-bybyte basis. 4.2 MAIN FEATURES

Remote In-Situ Programming (ISP) mode Up to 16 bytes programmed in the same cycle MTP memory (Multiple Time Programmable) Read-out memory protection against piracy

4.3 STRUCTURAL ORGANISATION The FLASH program memory is organised in a single 8-bit wide memory block which can be used for storing both code and data constants. The FLASH program memory is mapped in the upper part of the ST7 addressing space and includes the reset and interrupt user vector area . 4.4 IN-SITU PROGRAMMING (ISP) MODE The FLASH program memory can be programmed using Remote ISP mode. This ISP mode allows the contents of the ST7 program memory to be updated using a standard ST7 programming tools after the device is mounted on the application board. This feature can be implemented with a minimum number of added components and board area impact. An example Remote ISP hardware interface to the standard ST7 programming tool is described below. For more details on ISP programming, refer to the ST7 Programming Specification. Remote ISP Overview The Remote ISP mode is initiated by a specific sequence on the dedicated ISPSEL pin. The Remote ISP is performed in three steps: Selection of the RAM execution mode Download of Remote ISP code in RAM Execution of Remote ISP code in RAM to program the user program into the FLASH Remote ISP hardware configuration In Remote ISP mode, the ST7 has to be supplied with power (VDD and VSS) and a clock signal (oscillator and application crystal circuit for example).

This mode needs five signals (plus the VDD signal if necessary) to be connected to the programming tool. This signals are: RESET: device reset VSS: device ground power supply ISPCLK: ISP output serial clock pin ISPDATA: ISP input serial data pin ISPSEL: Remote ISP mode selection. This pin must be connected to VSS on the application board through a pull-down resistor. If any of these pins are used for other purposes on the application, a serial resistor has to be implemented to avoid a conflict if the other device forces the signal level. Figure 5 shows a typical hardware interface to a standard ST7 programming tool. For more details on the pin locations, refer to the device pinout description. Figure 5. Typical Remote ISP Interface XTAL
HE10 CONNECTOR TYPE TO PROGRAMMING TOOL

1 CL0 CL1

OSC2

OSC1

VDD

ISPSEL 10K VSS RESET

ST7

ISPCLK ISPDATA 47K

APPLICATION

4.5 MEMORY READ-OUT PROTECTION The read-out protection is enabled through an option bit. For FLASH devices, when this option is selected, the program and data stored in the FLASH memory are protected against read-out piracy (including a re-write protection). When this protection option is removed the entire FLASH program memory is first automatically erased. However, the E2PROM data memory (when available) can be protected only with ROM devices.

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5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES

63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit index registers 16-bit stack pointer Low power modes Maskable hardware interrupts Non-maskable software interrupt

5.3 CPU REGISTERS The six CPU registers shown in Figure 1 are not present in the memory mapping and are accessed by specific instructions. Figure 6. CPU Registers
7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 0 0 0

Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 111HI 0 NZC CONDITION CODE REGISTER

RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value

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CPU REGISTERS (cont'd) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx
7 1 1 1 H I N Z 0 C

because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. Bit 2 = N Negative This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions. Bit 1 = Z Zero This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions.

The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Bit 4 = H Half carry This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 3 = I Interrupt mask This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible

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CENTRAL PROCESSING UNIT (Cont'd) Stack Pointer (SP) Read/Write Reset Value: 01 7Fh
15 0 7 0 SP6 SP5 SP4 SP3 SP2 SP1 0 0 0 0 0 0 8 1 0 SP0

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 7). Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP6 to SP0 bits are set) which is the stack higher address. Figure 7. Stack Manipulation Example
CALL Subroutine @ 0100h Interrupt Event P USH Y

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 7. When an interrupt is received, the SP is decremented and the context is pushed on the stack. On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area.

PO P Y

IRET

RET or RSP

SP SP CC A X PC H SP PCH @ 017Fh PCL P CL PCH PCL Y CC A X PCH PCL PCH PC L SP CC A X PCH PCL PCH PCL SP PCH PCL SP

Stack Higher Address = 017Fh Stack Lower Address = 0100h

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6 SUPPLY, RESET AND CLOCK MANAGEMENT
The ST72104G, ST72215G, ST72216G and ST72254G microcontrollers include a range of utility features for securing the application in critical situations (for example in case of a power brownout), and reducing the number of external components. An overview is shown in Figure 8. See Section 13 "ELECTRICAL CHARACTERISTICS" on page 96 for more details. Main Features Supply Manager with main supply low voltage detection (LVD) Reset Sequence Manager (RSM) Multi-Oscillator (MO) 4 Crystal/Ceramic resonator oscillators 1 External RC oscillator 1 Internal RC oscillator Clock Security System (CSS) Clock Filter Backup Safe Oscillator Figure 8. Clock, Reset and Supply Block Diagram

MCO CLOCK SECURITY SYSTEM (CSS) OSC2 OSC1 MULTIOSCILLATOR (MO) FILTER OSC CLOCK SAFE fOSC MAIN CLOCK CONTROLLER (MCC) f CPU

RESET SEQUENCE RESET MANAGER (RSM) FROM WATCHDOG PERIPHERAL

VDD VSS

LOW VOLTAGE DETECTOR (LVD) CRSR 0 0 0 LVD RF 0 IE CSS D WDG RF

CSS INTERRUPT

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6.1 LOW VOLTAGE DETECTOR (LVD) To allow the integration of power management features in the application, the Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT- reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD Reset circuitry generates a reset when VDD is below: VIT+ when VDD is rising VIT- when VDD is falling The LVD function is illustrated in the Figure 9. Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-, the MCU can only be in two modes: under full software control in static safe reset Figure 9. Low Voltage Detector vs Reset VDD In these conditions, secure operation is always ensured for the application without the need for external reset hardware. During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Notes: 1. The LVD allows the device to be used without any external RESET circuitry. 2. Three different reference levels are selectable through the option byte according to the application requirement. LVD application note Application software can detect a reset caused by the LVD by reading the LVDRF bit in the CRSR register. This bit is set by hardware when a LVD reset is generated and cleared by software (writing zero).

V hyst VIT+ VIT-

RESET

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6.2 RESET SEQUENCE MANAGER (RSM) 6.2.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 11: External RESET source pulse Internal LVD RESET (Low Voltage Detection) Internal WATCHDOG RESET These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases as shown in Figure 10: Delay depending on the RESET source 4096 CPU clock cycle delay RESET vector fetch Figure 11. Reset Block Diagram The 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The RESET vector fetch phase duration is 2 clock cycles. Figure 10. RESET Sequence Phases

RESET
DELAY INTERNAL RESET 4096 CLOCK CYCLES FETCH VECTOR

VDD

f CPU
COUNTER

INTERNAL RESET

RON
RESET

WATCHDOG RESET LVD RESET

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RESET SEQUENCE MANAGER (Cont'd) 6.2.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See electrical characteristics section for more details. A RESET signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized. This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode. The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. Two RESET sequences can be associated with this RESET source: short or long external reset pulse (see Figure 12). Starting from the external RESET pulse recognition, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out. Figure 12. RESET Sequences VDD
V I T+ V I T-

6.2.3 Internal Low Voltage Detection RESET Two different RESET sequences caused by the internal LVD circuitry can be distinguished: Power-On RESET Voltage Drop RESET The device RESET pin acts as an output that is pulled low when VDD
LVD RESET

SHORT EXT. RESET

LONG EXT. RESET

WATCHDOG RESET

RUN
DELAY

RUN
DELAY

RUN
DELAY

RUN
DELAY

RUN

tw(RSTL)out th(RSTL)in
EXTERNAL RESET SOURCE

th(RSTL)in

tw(RSTL)out

RESET PIN

WATCHDOG RESET WATCHDOG UNDERFLOW INTERNAL RESET (4096 TCPU) FETCH VECTOR

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6.3 MULTI-OSCILLATOR (MO) The main clock of the ST7 can be generated by four different source types coming from the multioscillator block: an external source 4 crystal or ceramic resonator oscillators an external RC oscillator an internal high frequency RC oscillator Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configuration are shown in Table 3. Refer to the electrical characteristics section for more details. External Clock Source In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground. Crystal/Ceramic Oscillators This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption. In this mode of the multi-oscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator. These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase. External RC Oscillator This oscillator allows a low cost solution for the main clock of the ST7 using only an external resistor and an external capacitor. The frequency of the external RC oscillator (in the range of some MHz.) is fixed by the resistor and the capacitor values. Consequently in this MO mode, the accuracy of the clock is dependent on VDD, TA, process variations and the accuracy of the discrete components used. This option should not be used in applications that require accurate timing. Internal RC Oscillator The internal RC oscillator mode is based on the same principle as the external RC oscillator including the resistance and the capacitance of the device. This mode is the most cost effective one with the drawback of a lower frequency accuracy. Its frequency is in the range of several MHz. This option should not be used in applications that require accurate timing. In this mode, the two oscillator pins have to be tied to ground. Table 3. ST7 Clock Sources
Hardware Configuration

External Clock

ST7 OS C1 OSC 2

EX TERNAL SO URCE

Crystal/Ceramic Resonators

ST7 OSC 1 OSC2

CL 1

LOA D CAPA CITO RS
ST7 OSC1 OSC2

CL 2

External RC Oscillator

RE X

CE X

Internal RC Oscillator

ST7 OSC1 OSC2

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6.4 CLOCK SECURITY SYSTEM (CSS) The Clock Security System (CSS) protects the ST7 against main clock problems. To allow the integration of the security features in the applications, it is based on a clock filter control and an Internal safe oscillator. The CSS can be enabled or disabled by option byte. 6.4.1 Clock Filter Control The clock filter is based on a clock frequency limitation function. This filter function is able to detect and filter high frequency spikes on the ST7 main clock. If the oscillator is not working properly (e.g. working at a harmonic frequency of the resonator), the current active oscillator clock can be totally filtered, and then no clock signal is available for the ST7 from this oscillator anymore. If the original clock source recovers, the filtering is stopped automatically and the oscillator supplies the ST7 clock. 6.4.2 Safe Oscillator Control The safe oscillator of the CSS block is a low frequency back-up clock source (see Figure 13). If the clock signal disappears (due to a broken or disconnected resonator...) during a safe oscillator period, the safe oscillator delivers a low frequency clock signal which allows the ST7 to perform some rescue operations. Automatically, the ST7 clock source switches back from the safe oscillator if the original clock source recovers. Limitation detection The automatic safe oscillator selection is notified by hardware setting the CSSD bit of the CRSR register. An interrupt can be generated if the CSSIE bit has been previously set. These two bits are described in the CRSR register description. 6.4.3 Low Power Modes
Mode WAIT Description No effect on CSS. CSS interrupt cause the device to exit from Wait mode. The CRSR register is frozen. The CSS (including the safe oscillator) is disabled until HALT mode is exited. The previous CSS configuration resumes when the MCU is woken up by an interrupt with "exit from HALT mode" capability or from the counter reset value when the MCU is woken up by a RESET.

H AL T

6.4.4 Interrupts The CSS interrupt event generates an interrupt if the corresponding Enable Control Bit (CSSIE) is set and the interrupt mask in the CC register is reset (RIM instruction).
Interrupt Event Enable Event Control Flag Bit C SSIE Exit from Wait Yes Exit from Halt1) No

CSS event detection (safe oscillator acti- CSSD vated as main clock)

Note 1: This interrupt allows to exit from active-halt mode if this mode is available in the MCU. Figure 13. Clock Filter Function and Safe Oscillator Function
CLOCK FILTER FUNCTION

fOSC/2 f CPU

SAFE OSCILLATOR FUNCTION

fOSC/2 fSFOSC f CPU

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6.5 CLOCK RESET AND SUPPLY REGISTER DESCRIPTION (CRSR) Read / Write Reset Value: 000x 000x (XXh)
7 0 0 0 LVD RF 0 CSS IE 0 C S S WDG D RF

Bit 7:5 = Reserved, always read as 0. Bit 4 = LVDRF LVD reset flag This bit indicates that the last RESET was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag description for more details. When the LVD is disabled by option byte, the LVDRF bit value is undefined. Bit 3 = Reserved, always read as 0. Bit 2 = CSSIE Clock security syst. interrupt enable This bit enables the interrupt when a disturbance is detected by the clock security system (CSSD bit set). It is set and cleared by software. 0: Clock security system interrupt disabled 1: Clock security system interrupt enabled Refer to Table 5, "Interrupt Mapping," on page 26 for more details on the CSS interrupt vector. When the CSS is disabled by option byte, the CSSIE bit has no effect.

Bit 1 = CSSD Clock security system detection This bit indicates that the safe oscillator of the clock security system block has been selected by hardware due to a disturbance on the main clock signal (fOSC). It is set by hardware and cleared by reading the CRSR register when the original oscillator recovers. 0: Safe oscillator is not active 1: Safe oscillator has been activated When the CSS is disabled by option byte, the CSSD bit value is forced to 0. Bit 0 = WDGRF Watchdog reset flag This bit indicates that the last RESET was generated by the watchdog peripheral. It is set by hardware (Watchdog RESET) and cleared by software (writing zero) or an LVD RESET (to ensure a stable cleared state of the WDGRF flag when the CPU starts). Combined with the LVDRF flag information, the flag description is given by the following table.
RESET Sources External RESET pin Watchdog LVD LV DRF 0 0 1 WDG R F 0 1 X

Application notes The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can be detected by software while an external reset can not.

Table 4. Clock, Reset and Supply Register Map and Reset Values
Address (Hex.) 0025h Register Label C RSR Reset Value 7 6 5 4 LV DRF x 3 2 C SSIE 0 1 CSSD 0 0 WDG R F x

0

0

0

0

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6.6 MAIN CLOCK CONTROLLER (MCC) The Main Clock Controller (MCC) supplies the clock for the ST7 CPU and its internal peripherals. It allows SLOW power saving mode to be managed by the application. All functions are managed by the Miscellaneous register 1 (MISCR1). The MCC block consists of: A programmable CPU clock prescaler A clock-out signal to supply external devices The prescaler allows the selection of the main clock frequency and is controlled by three bits of the MISCR1: CP1, CP0 and SMS. The clock-out capability consists of a dedicated I/O port pin configurable as an fCPU clock output to drive external devices. It is controlled by the MCO bit in the MISCR1 register. See Section 10 "MISCELLANEOUS REGISTERS" on page 36 for more details.

Figure 14. Main Clock Controller (MCC) Block Diagram
CLOCK TO CAN PERIPHERAL PORT ALTERNATE FUNCTION fOSC/2 MISCR1 MCO CP1 CP0 SMS

MCO

fOSC

DIV 2

DIV 2, 4, 8, 16 fCPU

CPU CLOCK TO CPU AND PERIPHERALS

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7 INTERRUPTS
The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 1. The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). Note: After reset, all interrupts are disabled. When an interrupt has to be serviced: Normal processing is suspended at the end of the current instruction execution. The PC, X, A and CC registers are saved onto the stack. The I bit of the CC register is set to prevent additional interrupts. The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping Table for vector addresses). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume. Priority Management By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine. In the case when several interrupts are simultaneously pending, an hardware priority defines which one will be serviced first (see the Interrupt Mapping Table). Interrupts and Low Power Mode All interrupts allow the processor to leave the WAIT low power mode. Only external and specifically mentioned interrupts allow the processor to leave the HALT low power mode (refer to the "Exit from HALT" column in the Interrupt Mapping Table). 7.1 NON-MASKABLE SOFTWARE INTERRUPT This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. It will be serviced according to the flowchart on Figure 1. 7.2 EXTERNAL INTERRUPTS External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power mode. The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins, connected to the same interrupt vector, are configured as interrupts, their signals are logically NANDed before entering the edge/level detection block. Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of a NANDed source (as described on the I/O ports section), a low level on an I/O pin configured as input with interrupt, masks the interrupt request even in case of risingedge sensitivity. 7.3 PERIPHERAL INTERRUPTS Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: The I bit of the CC register is cleared. The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by: Writing "0" to the corresponding bit in the status register or Access to the status register while the flag is set followed by a read or write of an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (that is, waiting to be enabled) will therefore be lost if the clear sequence is executed.

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INTERRUPTS (Cont'd) Figure 15. Interrupt Processing Flowchart

FROM RESET I BIT SET? Y N

N

INTERRUPT PENDING? Y

FETCH NEXT INSTRUCTION

N

IRET? Y

STACK PC, X, A, CC SET I BIT LOAD PC FROM INTERRUPT VECTOR

EXECUTE INSTRUCTION

RESTORE PC, X, A, CC FROM STACK THIS CLEARS I BIT BY DEFAULT

Table 5. Interrupt Mapping
N Source Block RES ET TRAP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 I²C TIMER B ei0 ei1 CSS S PI TIMER A Reset Software Interrupt External Interrupt Port A7..0 (C5..01) External Interrupt Port B7..0 (C5..01) Clock Security System Interrupt SPI Peripheral Interrupts TIMER A Peripheral Interrupts Not used TIMER B Peripheral Interrupts Not used Not used Not used Not used I²C Peripheral Interrupt Not Used Not Used I2CSR x Lowest Priority no TB SR no CR SR SPISR TA SR no N/A Description Register Label Priority Order Highest Priority Exit from HALT yes no yes Address Vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h FFE2h-FFE3h FFE0h-FFE1h

Note 1. Configurable by option byte.

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8 POWER SAVING MODES
8.1 INTRODUCTION To give a large measure of flexibility to the application in terms of power consumption, three main power saving modes are implemented in the ST7 (see Figure 16). After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (fCPU). From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. Figure 16. Power Saving Mode Transitions
High RUN
fCPU

8.2 SLOW MODE This mode has two targets: To reduce power consumption by decreasing the internal clock in the device, To adapt the internal clock frequency (fCPU) to the available supply voltage. SLOW mode is controlled by three bits in the MISCR1 register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (fCPU). In this mode, the oscillator frequency can be divided by 4, 8, 16 or 32 instead of 2 in normal operating mode. The CPU and peripherals are clocked at this lower frequency. Note: SLOW-WAIT mode is activated when entering WAIT mode while the device is already in SLOW mode. Figure 17. SLOW Mode Clock Transitions
fOSC/4 fOSC/8 fOSC/2

SLOW
fOSC/2 MISCR1

WAIT SLOW WAIT HALT Low PO WER CONS UMPTION

CP1:0 SMS

00

01

NEW SLOW FREQUENCY REQUEST

NORMAL RUN MODE REQUEST

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POWER SAVING MODES (Cont'd) 8.3 WAIT MODE WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the "WFI" ST7 software instruction. All peripherals remain active. During WAIT mode, the I bit of the CC register is forced to 0, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 18. Figure 18. WAIT Mode Flow-chart
OSCILLATOR PERIPHERALS CP U I BIT ON ON OFF 0

WFI I N S T R U C T I O N

N RE SET N INTERRUP T Y OSCILLATOR PERIPHERALS CP U I BIT ON OFF ON 1 Y

4096 CPU CLOCK CYCLE DELAY

OSCILLATOR PERIPHERALS CP U I BI T

ON ON ON X 1)

FETC H RES ET VEC TOR OR SERVICE INTERRUPT

Note: 1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.

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POWER SAVING MODES (Cont'd) 8.4 HALT MODE The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the ST7 HALT instruction (see Figure 20). The MCU can exit HALT mode on reception of either a specific interrupt (see Table 5, "Interrupt Mapping," on page 26) or a RESET. When exiting HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 19). When entering HALT mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes immediately. In the HALT mode the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of Watchdog operation with HALT mode is configured by the "WDGHALT" option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see Section 15.1 "OPTION BYTES" on page 133 for more details). Figure 19. HALT Mode Timing Overview
RUN HALT 4096 CPU CYCLE D ELAY RUN FETC H RES ET VEC TOR OR SERVICE INTERRUPT

Figure 20. HALT Mode Flow-chart
H AL T INSTRUCTION ENABLE W D GH A L T 1 ) 1 W ATCHDO G RE SET OSCILLATOR OFF PERIPHERALS 2) OFF CP U OFF I BIT 0 0 W ATCHDOG DISABLE

N RE SET N Y INTERRUPT 3) Y OSCILLATOR PERIPHERALS CP U I BIT ON OFF ON 1

4096 CPU CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS CP U I BIT ON ON ON X 4)

HA LT IN STRUCTION

RESET OR INTER RUPT

FE TCH VECTOR

Notes: 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 5, "Interrupt Mapping," on page 26 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.

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9 I/O PORTS
9.1 INTRODUCTION The I/O ports offer different functional modes: transfer of data through digital inputs and outputs and for specific pins: external interrupt generation alternate signal input/output for the on-chip peripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 9.2 FUNCTIONAL DESCRIPTION Each port has 2 main registers: Data Register (DR) Data Direction Register (DDR) and one optional register: Option Register (OR) Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is shown in Figure 1. 9.2.1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Notes: 1. Writing the DR register modifies the latch value but does not affect the pin status. 2. When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. 3. Do not use read/modify/write instructions (BSET or BRES) to modify the DR register External interrupt function When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the Miscellaneous register. Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt source, these are logically NANDed. For this reason if one of the interrupt pins is tied low, it masks the other ones. In case of a floating input with interrupt configuration, special care must be taken when changing the configuration (see Figure 2). The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the Miscellaneous register must be modified. 9.2.2 Output Modes The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status:
DR 0 1 Push-pull VS S VDD Open-drain Vss Floating

9.2.3 Alternate Functions When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register. Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.

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I/O PORTS (Cont'd) Figure 21. I/O Port General Block Diagram
REGISTER ACCESS ALTERNATE O UT PUT 1 0 ALTERNATE EN ABLE DR

VDD

P-BUFFER (see table below) PULL-UP (see table below) VDD

DDR PULL-UP CONFIGURATION If implemented OR SEL N-BUFFER DDR SEL CMOS SCHMITT TRIG GER ANALO G INPUT DIOD ES (see table below) PAD

OR

EXTER NAL INTERR UPT SOURCE (eix)

Table 6. I/O Port Mode Options
Configuration Mode Input Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) True Open Drain Pull-Up Off On Off NI P-Buffer Off On Off NI On On Diodes to VDD to VSS

O u tput

Legend: NI - not implemented Off - implemented not activated On - implemented and activated

DATA BUS

DR SEL

1 0

ALTERNATE INPUT FROM OTHER BITS

POLARITY SELECTION

NI (see note)

Note: The diode to VDD is not implemented in the true open drain pads. A local protection between the pad and VSS is implemented to protect the device against positive stress.

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I/O PORTS (Cont'd) Table 7. I/O Port Configurations
Hardware Configuration
NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS VDD RPU PAD PULL-UP CONFIGURATION DR REGISTER ACCESS

DR REGISTER

W DATA BUS R

INPUT 1)

ALTERNATE INPUT FROM OTHER PINS INTERRUPT CONFIGURATION POLARITY SELECTION ANALOG INPUT NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS EXTERNAL INTERRUPT SOURCE (eix)

OPEN-DRAIN OUTPUT 2)

VDD RPU

DR REGISTER ACCESS

PAD

DR REGISTER

R/W

DATA BUS

ALTERNATE ENABLE

ALTERNATE OUTPUT

PUSH-PULL OUTPUT 2)

NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS

VDD RPU

DR REGISTER ACCESS

PAD

DR REGISTER

R/W

DATA BUS

ALTERNATE ENABLE

ALTERNATE OUTPUT

Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.

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I/O PORTS (Cont'd) CAUTION: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin. WARNING: The analog input voltage level must be within the limits stated in the absolute maximum ratings. 9.3 I/O PORT IMPLEMENTATION The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 2. Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. Table 8. Port Configuration
Input (DDR = 0) Port Pin name OR = 0 PA7 PA6 PA5 PA4 PA3:0 PB7:0 PC7:0 floating floating floating floating floating floating floating OR = 1

Figure 22. Interrupt I/O Port State Transitions
01 00 10 OUTPUT open-drain 11 O UT PUT push-pull

INPUT INPUT f l o a t i n g / p u l l - u p floating interrupt (reset state)

XX = DDR, OR

The I/O port register configurations are summarized as follows. Interrupt Ports PA7, PA5, PA3:0, PB7:0, PC5:0 (with pull-up)
MODE floating input pull-up interrupt input open drain output push-pull output D DR 0 0 1 1 OR 0 1 0 1

True Open Drain Interrupt Ports PA6, PA4 (without pull-up)
MODE floating input floating interrupt input open drain (high sink ports) D DR 0 0 1 OR 0 1 X

Output (DDR = 1) OR = 0 OR = 1 High-Sink

Port A

Port B Port C

pull-up interrupt floating interrupt pull-up interrupt floating interrupt pull-up interrupt pull-up interrupt pull-up interrupt

open drain push-pull true open-drain open drain push-pull true open-drain open drain push-pull open drain push-pull open drain push-pull

Y es

No

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I/O PORTS (Cont'd) 9.4 LOW POWER MODES
Mode WAIT H ALT Description No effect on I/O ports. External interrupts cause the device to exit from WAIT mode. No effect on I/O ports. External interrupts cause the device to exit from HALT mode.

DATA DIRECTION REGISTER (DDR) Port x Data Direction Register PxDDR with x = A, B or C. Read / Write Reset Value: 0000 0000 (00h)
7 DD7 DD6 DD5 DD4 DD3 DD2 DD1 0 DD0

9.5 INTERRUPTS The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the I-bit in the CC register is reset (RIM instruction).
Interrupt Event External interrupt on selected external event Enable Event Control Flag Bit DDRx ORx Exit from Wait Yes Exit from Halt Yes

Bit 7:0 = DD[7:0] Data direction register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bit is set and cleared by software. 0: Input mode 1: Output mode OPTION REGISTER (OR) Port x Option Register PxOR with x = A, B or C. Read / Write Reset Value: 0000 0000 (00h)
7 O7 O6 O5 O4 O3 O2 O1 0 O0

9.6 REGISTER DESCRIPTION DATA REGISTER (DR) Port x Data Register PxDR with x = A, B or C. Read / Write Reset Value: 0000 0000 (00h)
7 D7 D6 D5 D4 D3 D2 D1 0 D0

Bit 7:0 = D[7:0] Data register 8 bits. The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken into account even if the pin is configured as an input; this allows always having the expected level on the pin when toggling to output mode. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input).

Bit 7:0 = O[7:0] Option register 8 bits. For specific I/O pins, this register is not implemented. In this case the DDR register is enough to select the I/O pin configuration. The OR register allows to distinguish: in input mode if the pull-up with interrupt capability or the basic pull-up configuration is selected, in output mode if the push-pull or open drain configuration is selected. Each bit is set and cleared by software. Input mode: 0: Floating input 1: Pull-up input with or without interrupt Output mode: 0: Output open drain (with P-Buffer deactivated) 1: Output push-pull (when available)

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I/O PORTS (Cont'd) Table 9. I/O Port Register Map and Reset Values
Address (Hex.) Register Label 7 6 5 4 3 2 1 0

Reset Value of all I/O port registers 0000h 0001h 0002h 0004h 0005h 0006h 0008h 0009h 000Ah P CDR P CDDR P C OR P BDR P BDDR P B OR P ADR P ADDR P A OR

0

0

0

0

0

0

0

0

MSB

LSB

MSB

LSB

MSB

LSB

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10 MISCELLANEOUS REGISTERS
The miscellaneous registers allow control over several different features such as the external interrupts or the I/O alternate functions. 10.1 I/O PORT INTERRUPT SENSITIVITY The external interrupt sensitivity is controlled by the ISxx bits of the Miscellaneous register and the OPTION BYTE. This control allows having two fully independent external interrupt source sensitivities with configurable sources (using EXTIT option bit) as shown in Figure 23 and Figure 24. Each external interrupt source can be generated on four different events on the pin: Falling edge Rising edge Falling and rising edge Falling edge and low level To guarantee correct functionality, the sensitivity bits in the MISCR1 register must be modified only when the I bit of the CC register is set to 1 (interrupt masked). See I/O port register and Miscellaneous register descriptions for more details on the programming.
PA0 PC5

Figure 23. Ext. Interrupt Sensitivity (EXTIT=0)
MISCR1 ei0 INTERRUPT SOURCE IS00 IS01

PA7

SENSITIVITY CONTROL

PC0 MISCR1 ei1 INTERRUPT SOURCE IS10 IS11

PB7

SENSITIVITY CONTROL

PB0

Figure 24. Ext. Interrupt Sensitivity (EXTIT=1)
MISCR1 ei0 INTERRUPT SOURCE IS00 IS01

PA7

SENSITIVITY CONTROL

10.2 I/O PORT ALTERNATE FUNCTIONS The MISCR registers manage four I/O port miscellaneous alternate functions: Main clock signal (fCPU) output on PC2 SPI pin configuration: SS pin internal control to use the PB7 I/O port function while the SPI is active. Master output capability on MOSI pin (PB4) deactivated while the SPI is active. Slave output capability on MISO pin (PB5) deactivated while the SPI is active. These functions are described in detail in the Section 10.3 "MISCELLANEOUS REGISTER DESCRIPTION" on page 37.
PA0

PB7 ei1 INTERRUPT SOURCE

MISCR1 IS10 IS11

PB0 PC5

SENSITIVITY CONTROL

PC0

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MISCELLANEOUS REGISTERS (Cont'd) 10.3 MISCELLANEOUS REGISTER DESCRIPTION MISCELLANEOUS REGISTER 1 (MISCR1) Read / Write Reset Value: 0000 0000 (00h)
7 IS11 I S 1 0 MC O I S 0 1 IS00 CP1 CP0 0 fCPU in SLOW mode SMS fOSC / 4 fOSC / 8 fOSC / 16 CP1 0 1 0 1 CP0 0 0 1 1

Bit 2:1 = CP[1:0] CPU clock prescaler These bits select the CPU clock prescaler which is applied in the different slow modes. Their action is conditioned by the setting of the SMS bit. These two bits are set and cleared by software

Bit 7:6 = IS1[1:0] ei1 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the ei1 external interrupts. These two bits can be written only when the I bit of the CC register is set to 1 (interrupt masked). ei1: Port B (C optional)
External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge IS11 IS10 0 0 1 1 0 1 0 1

fOSC / 32

Bit 0 = SMS Slow mode select This bit is set and cleared by software. 0: Normal mode. fCPU = fOSC / 2 1: Slow mode. fCPU is given by CP1, CP0 See low power consumption mode and MCC chapters for more details.

Bit 5 = MCO Main clock out selection This bit enables the MCO alternate function on the PC2 I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for general-purpose I/O) 1: MCO alternate function enabled (fCPU on I/O port) Bit 4:3 = IS0[1:0] ei0 sensitivity The interrupt sensitivity, defined using the IS0[1:0] bits, is applied to the ei0 external interrupts. These two bits can be written only when the I bit of the CC register is set to 1 (interrupt masked). ei0: Port A (C optional)
External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge IS01 IS00 0 0 1 1 0 1 0 1

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MISCELLANEOUS REGISTERS (Cont'd) MISCELLANEOUS REGISTER 2 (MISCR2) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 M OD S O D S S M 0 SSI

Bit 7:4 = Reserved always read as 0 Bit 3 = MOD SPI Master Output Disable This bit is set and cleared by software. When set, it disables the SPI Master (MOSI) output signal. 0: SPI Master Output enabled. 1: SPI Master Output disabled. Bit 2 = SOD SPI Slave Output Disable This bit is set and cleared by software. When set it disable the SPI Slave (MISO) output signal. 0: SPI Slave Output enabled. 1: SPI Slave Output disabled. Bit 1 = SSM SS mode selection This bit is set and cleared by software. 0: Normal mode - the level of the SPI SS signal is input from the external SS pin. 1: I/O mode, the level of the SPI SS signal is read from the SSI bit. Bit 0 = SSI SS internal mode This bit replaces the SS pin of the SPI when the SSM bit is set to 1. (see SPI description). It is set and cleared by software.

Table 10. Miscellaneous Register Map and Reset Values
Address (Hex.) 0020h 0040h Register Label MISCR1 Reset Value MISCR2 Reset Value 7 IS11 0 0 6 IS10 0 0 5 MCO 0 0 4 IS01 0 0 3 IS00 0 MOD 0 2 CP 1 0 SO D 0 1 CP0 0 S SM 0 0 SMS 0 SS I 0

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11 ON-CHIP PERIPHERALS
11.1 WATCHDOG TIMER (WDG) 11.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter's contents before the T6 bit becomes cleared. 11.1.2 Main Features Programmable timer (64 increments of 12288 CPU cycles) Programmable reset Reset (if watchdog activated) when the T6 bit reaches zero Optional reset on HALT instruction (configurable by option byte) Hardware Watchdog selectable by option byte. 11.1.3 Functional Description The counter value stored in the CR register (bits T6:T0), is decremented every 12,288 machine cyFigure 25. Watchdog Block Diagram cles, and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T6:T0) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. The value to be stored in the CR register must be between FFh and C0h (see Table 11 . Watchdog Timing (fCPU = 8 MHz)): The WDGA bit is set (watchdog enabled) The T6 bit is set to prevent generating an immediate reset The T5:T0 bits contain the number of increments which represents the time delay before the watchdog produces a reset.

RESET

WATCHDOG CONTROL REGISTER (CR) WDG A T6 T5 T4 T3 T2 T1 T0

7-BIT DOWNCOUNTER

fCPU

CLOCK DIVIDER ÷12288

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WATCHDOG TIMER (Cont'd) Table 11. Watchdog Timing (fCPU = 8 MHz)
CR Register initial value Max Min FFh C0h WDG timeout period (ms) 98.304 1.536

Notes: Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). 11.1.4 Hardware Watchdog Option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used. Refer to the device-specific Option Byte description. 11.1.5 Low Power Modes WAIT Instruction No effect on Watchdog. HALT Instruction If the Watchdog reset on HALT option is selected by option byte, a HALT instruction causes an immediate reset generation if the Watchdog is activated (WDGA bit is set). 11.1.5.1 Using Halt Mode with the WDG (option) If the Watchdog reset on HALT option is not selected by option byte, the Halt mode can be used when the watchdog is enabled. In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the WDG stops counting and is no longer able to generate a reset until the microcontroller receives an external interrupt or a reset. If an external interrupt is received, the WDG restarts counting after 4096 CPU clocks. If a reset is generated, the WDG is disabled (reset state). Recommendations Make sure that an external event is available to wake up the microcontroller from Halt mode. Before executing the HALT instruction, refresh the WDG counter, to avoid an unexpected WDG

reset immediately after waking up the microcontroller. When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as "Input Pull-up with Interrupt" before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure. The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E. As the HALT instruction clears the I bit in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). 11.1.6 Interrupts None. 11.1.7 Register Description CONTROL REGISTER (CR) Read / Write Reset Value: 0111 1111 (7F h)
7 WDG A T6 T5 T4 T3 T2 T1 0 T0

Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).

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WATCHDOG TIMER (Cont'd) Table 12. Watchdog Timer Register Map and Reset Values
Address (Hex.) 0024h Register Label W D GC R Reset Value 7 W D GA 0 6 T6 1 5 T5 1 4 T4 1 3 T3 1 2 T2 1 1 T1 1 0 T0 1

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11.2 16-BIT TIMER 11.2.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of up to two input signals (input capture) or generating up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler. Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequencies are not modified. This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B). 11.2.2 Main Features Programmable prescaler: fCPU divided by 2, 4 or 8. Overflow status flag and maskable interrupt External clock input (must be at least 4 times slower than the CPU clock speed) with the choice of active edge Output compare functions with: 2 dedicated 16-bit registers 2 dedicated programmable signals 2 dedicated status flags 1 dedicated maskable interrupt Input capture functions with: 2 dedicated 16-bit registers 2 dedicated active edge selection signals 2 dedicated status flags 1 dedicated maskable interrupt Pulse Width Modulation mode (PWM) One Pulse mode 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)* The Block Diagram is shown in Figure 1. *Note: Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pin out description. When reading an input signal on a non-bonded pin, the value will always be `1'. 11.2.3 Functional Description 11.2.3.1 Counter The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high and low. Counter Register (CR) Counter High Register (CHR) is the most significant byte (MS Byte). Counter Low Register (CLR) is the least significant byte (LS Byte). Alternate Counter Register (ACR) Alternate Counter High Register (ACHR) is the most significant byte (MS Byte). Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte). These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register (SR). (See note at the end of paragraph titled 16-bit read sequence). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode. The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 1. The value in the counter register repeats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be fCPU/2, fCPU/4, fCPU/8 or an external frequency.

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16-BIT TIMER (Cont'd) Figure 26. Timer Block Diagram
ST7 INTERNAL BUS fCPU MCU-PERIPHERAL INTERFACE 8 low 8-bit buffer EXEDG 16 1/2 1/4 1/8 EXTCLK pin COUNTER REGISTER ALTERNA TE COUN TER REGISTER 16 CC[1:0] TIMER INTERNAL BUS 16 16 OVERFLOW DETECT CIRCU IT O UT PUT COMP ARE RE GISTE R 1 OUTPUT CO MPARE REGISTER 2 INPUT CAPTURE REGISTER 1 16 INPUT CAPTUR E REGISTER 2 16 8 high low 8 high 8 low 8 high 8 low 8 high 8 low 8

8 high

OUTPUT COMPARE CIRCUIT 6

EDGE DETECT CIR CUIT1

ICAP1 pin

EDGE DETECT CIRC UIT2

ICAP2 pin

LATCH1
ICF1 OCF1 TOF ICF2 OCF2 0

OCMP 1 pin OCMP2 pin

0

0 LATCH2

(Status Register) SR

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

OC1E OC2E OPM PWM

CC1

CC0 IEDG2 EXEDG

(Control Register 1) CR1

(Control Register 2) CR2

(See note) TIMER INTERRUPT
Note: If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See device Interrupt Vector Table)

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16-BIT TIMER (Cont'd) 16-bit Read Sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence At t0 Read MS Byte Other inst ructions Read At t0 +t LS Byte Sequence completed The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read. Whatever the timer mode used (input capture, output compare, One Pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: The TOF bit of the SR register is set. A timer interrupt is generated if: TOIE bit of the CR1 register is set and I bit of the CC register is cleared. If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true.
Returns the buffered

LS Byte is buffered

LS Byte value at t0

Clearing the overflow interrupt request is done in two steps: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. Note: The TOF bit is not cleared by accessing the ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously. The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset). 11.2.3.2 External Clock The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter. The counter is synchronized with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency.

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16-BIT TIMER (Cont'd) Figure 27. Counter Timing Diagram, internal clock divided by 2

CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFD FFFE FFFF 0000 0001 0002 0003

Figure 28. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000 0001

Figure 29. Counter Timing Diagram, internal clock divided by 8

CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000

Note: The MCU is in reset state when the internal reset signal is high. When it is low, the MCU is running.

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16-BIT TIMER (Cont'd) 11.2.3.3 Input Capture In this section, the index, i, may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are used to latch the value of the free running counter after a transition is detected by the ICAPi pin (see Figure 5).
ICiR MS Byte ICiHR LS Byte ICiLR

The ICiR register is a read-only register. The active transition is software programmable through the IEDGi bit of Control Registers (CRi). Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the input capture function, select the following in the CR2 register: Select the timer clock (CC[1:0]) (see Table 1). Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as a floating input or input with pull-up without interrupt if this configuration is available). And select the following in the CR1 register: Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as a floating input or input with pull-up without interrupt if this configuration is available).

When an input capture occurs: The ICFi bit is set. The ICiR register contains the value of the free running counter on the active transition on the ICAPi pin (see Figure 6). A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true. Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. Notes: 1. After reading the ICiHR register, the transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2. The ICiR register contains the free running counter value which corresponds to the most recent input capture. 3. The two input capture functions can be used together even if the timer also uses the two output compare functions. 4. In One Pulse mode and PWM mode only the input capture 2 function can be used. 5. The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any transitions on these pins activate the input capture function. Moreover if one of the ICAPi pin is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the ICiHR (see note 1). 6. The TOF bit can be used with an interrupt in order to measure events that exceed the timer range (FFFFh).

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16-BIT TIMER (Cont'd) Figure 30. Input Capture Block Diagram

ICAP1 pin ICAP2 pin EDGE DETECT CIRC UIT2 EDGE DETECT CIRC UIT1
ICIE

(Control Register 1) CR1
IEDG1

(Status Register) SR IC2R Register IC1R Register
ICF1 ICF2 0 0 0

16-BIT

(Control Register 2) CR2
CC1 CC0 IEDG2

16-BIT FREE RUNNING
CO UNTER

Figure 31. Input Capture Timing Diagram

TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER Note: Active edge is rising edge. FF03 FF01 FF02 FF03

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16-BIT TIMER (Cont'd) 11.2.3.4 Output Compare In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Compare register and the free running counter, the output compare function: Assigns pins with a programmable value if the OCiE bit is set Sets a flag in the status register Generates an interrupt if enabled Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle.
OCiR MS Byte OC i H R LS Byte OCiLR

The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset). A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is cleared in the CC register (CC). The OCiR register value required for a specific timing application can be calculated using the following formula:

OCiR =

t * fCPU
PRESC

Where: t = Output compare period (in seconds) fCPU = CPU clock frequency (in hertz) = Timer prescaler factor (2, 4 or 8 dePRESC pending on CC[1:0] bits, see Table 1) If the timer clock is an external clock, the formula is:

These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OCiR value to 8000h. Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the output compare function, select the following in the CR2 register: Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output compare i signal. Select the timer clock (CC[1:0]) (see Table 1). And select the following in the CR1 register: Select the OLVLi bit to applied to the OCMPi pins after the match occurs. Set the OCIE bit to generate an interrupt if it is needed. When a match is found between OCRi register and CR register: OCFi bit is set.

OCiR = t * fEXT
Where: t = Output compare period (in seconds) fEXT = External timer clock frequency (in hertz) Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by: 1. Reading the SR register while the OCFi bit is set. 2. An access (read or write) to the OCiLR register. The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OCiR register: Write to the OCiHR register (further compares are inhibited). Read the SR register (first step of the clearance of the OCFi bit, which may be already set). Write to the OCiLR register (enables the output compare function and clears the OCFi bit).

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16-BIT TIMER (Cont'd) Notes: 1. After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set. 3. When the timer clock is fCPU/2, OCFi and OCMPi are set while the counter value equals the OCiR register value (see Figure 8). This behavior is the same in OPM or PWM mode. When the timer clock is fCPU/4, fCPU/8 or in external clock mode, OCFi and OCMPi are set while the counter value equals the OCiR register value plus 1 (see Figure 9). 4. The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used. 5. The value in the 16-bit OCiR register and the OLVi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. Figure 32. Output Compare Block Diagram

Forced Compare Output capability When the FOLVi bit is set by so