ST72334J/N, ST72314J/N, ST72124J
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
s
s
s
s
s
s
M e m o ri e s 8K or 16K Program memory (ROM or single voltage FLASH) with read-out protection and in-situ programming (remote ISP) 256 bytes EEPROM Data memory (with readout protection option in ROM devices) 384 or 512 bytes RAM Clock, Reset and Supply Management Enhanced reset system Enhanced low voltage supply supervisor with 3 programmable levels Clock sources: crystal/ceramic resonator oscillators or RC oscillators, external clock, backup Clock Security System 4 Power Saving Modes: Halt, Active-Halt, Wait and Slow Beep and clock-out capabilities Interrupt Management 10 interrupt vectors plus TRAP and RESET 15 external interrupt lines (4 vectors) 44 or 32 I/O Ports 44 or 32 multifunctional bidirectional I/O lines: 21 or 19 alternate function lines 12 or 8 high sink outputs 4 Timers Configurable watchdog timer Realtime base Two 16-bit timers with: 2 input captures (only one on timer A), 2 output compares (only one on timer A), External clock input on timer A, PWM and Pulse generator modes 2 Communications Interfaces SPI synchronous serial interface SCI asynchronous serial interface (LIN compatible)
Features
PSDIP56
PSDIP42
TQFP64 14 x 14
TQFP44 10 x 10
s
1 Analog Peripheral 8-bit ADC with 8 input channels (6 only on ST72334Jx, not available on ST72124J2) Instruction Set 8-bit data manipulation 63 basic instructions 17 main addressing modes 8 x 8 unsigned multiply instruction True bit manipulation Development Tools Full hardware/software development package
s
s
Device Summary
ST72124J2 ST72314J2 ST72314J4 ST72314N2 ST72314N 4 ST72334J2 ST72334J4 ST72334N2 ST72334N 4 8K 384 (256) 8K 384 (256) 16K 512 (256) 8K 16K 384 (256) 512 (256) 256 256 W atchdog, Two 16-bit Timers, SPI, SCI AD C 3. 2V to 5.5V U p to 8 MHz (with up to 16 MHz oscillator) -40C to +85C (-40C to +105/125C optional) TQFP64 / SDIP56 T QFP44 / SDIP42
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Program memory - bytes R AM (stack) - bytes EEPR OM - bytes Peripherals Operating Supply C PU Frequency Operating Temperature Packages
8K 384 (256)
16K 512 (256)
8K 384 (256) 256
16K 512 (256) 256
TQFP44 / SDIP42
T QFP64 / SDIP56
Rev. 2.5
April 2003 1/153
1
Table of Contents
1 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 5 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 INTRODU CTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 5.3 5.4 5.5 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 STRUCTURAL ORGANISATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 IN-SITU PROGRAMMING (ISP) MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 MEMORY READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 INTRODU CTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2 6.3 6.4 6.5 6.6 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7 DATA EEPROM Register Map and Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1 READ -OUT PROTECTION OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.1 INTRODU CTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.2 8.3 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.1 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.2 9.3 9.4 9.5 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 CLOC K SECURITY SYSTEM (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 32
10 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11.1 INTRODU CTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 12 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.1 INTRODU CTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 153 12.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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12.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 12.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 13.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 13.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 13.3 REGISTERS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 14 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 14.1 WATCHD OG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 14.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC) . . . . . . . 52 14.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 14.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 14.6 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 15 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 15.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 15.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 16 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 16.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 16.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 16.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 16.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 16.5 CLOC K AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 16.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 16.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 16.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 16.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 16.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 16.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 135 16.12 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 17 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 17.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 17.2 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 18 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 144 18.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 18.2 TRANSFER OF CUSTOMER CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 18.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 18.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 19 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 19.1 SCI BAUD RATE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 20 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
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ST72334J/N, ST72314J/N, ST72124J
To obtain the most recent version of this datasheet, please check at www.st.com>products>technical literature>datasheet. Please also pay special attention to the Section "IMPORTANT NOTES" on page 151
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1 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION
New Features available on the ST72C334 s8 or 16K FLASH/ROM with In-Situ Programming and Read-out protection s Ne w ADC with a better accuracy and conversion time s Ne w configurable Clock, Reset and Supply system s Ne w power saving mode with real time base: Active Halt s Beep capability on PF1 s Ne w interrupt source: Clock security system (CSS) or Main clock controller (MCC) ST72C334 I/O Configuration and Pinout s Sam e pinout as ST72E331 s PA6 and PA7 are true open drain I/O ports without pull-up (same as ST72E331) s PA3, PB3, PB4 and PF2 have no pull-up configuration (all I/Os present on TQFP44) s PA5:4, PC3:2, PE7:4 and PF7:6 have high sink capabilities (20mA on N-buffer, 2mA on P-buffer and pull-up). On the ST72E331, all these pads (except PA5:4) were 2mA push-pull pads without high sink capabilities. PA4 and PA5 were 20mA true open drains. New Memory Locations in ST72C334 s 20h: MISCR register becomes MISCR1 register (naming change) s 29h: new control/status register for the MCC module s 2Bh: new control/status register for the Clock, Reset and Supply control. This register replaces the WDGSR register keeping the WDOGF flag compatibility. s 40h: new MISCR2 register
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2 INTRODUCTION
The ST72334J/N, ST72314J/N and ST72124J devices are members of the ST7 microcontroller family. They can be grouped as follows: ST72334J/N devices are designed for mid-range applications with Data EEPROM, ADC, SPI and SCI interface capabilities. ST72314J/N devices target the same range of applications but without Data EEPROM. ST72124J devices are for applications that do not need Data EEPROM and the ADC peripheral. All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set. The ST72C334J/N, ST72C314J/N and ST72C124J versions feature single-voltage
FLASH memory with byte-by-byte In-Situ Programming (ISP) capability. Under software control, all devices can be placed in WAIT, SLOW, ACTIVE-HALT or HALT mode, reducing power consumption when the application is in idle or standby state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing m odes . For easy reference, all parametric data are located in Section 16 on page 107.
Figure 1. General Block Diagram
8-BIT CORE AL U RESET ISPSEL VDD VSS OSC1 OSC2 CONTROL
PROGRAM MEMORY (8K or 16K Bytes) RAM (384 or 512 Bytes)
LVD MULTI OSC + CLOCK FILTER ADDRESS AND DATA BUS MCC/RTC
EEPROM (256 Bytes)
PORT A PORT B PORT C TIMER B SPI PORT D 8-BIT ADC
PORT F PF7,6,4,2:0 (6-BIT) TI ME R A BEEP PORT E PE7:0 (6-BIT for N versions) (2-BIT for J versions) SC I
PA7:0 (8-BIT for N versions) (5-BIT for J versions) PB7:0 (8-BIT for N versions) (5-BIT for J versions)
PC7:0 (8-BIT )
WATCHDOG
PD7:0 (8-BIT for N versions) (6-BIT for J versions) VDDA VSSA
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3 PIN DESCRIPTION
Figure 2. 64-Pin TQFP Package Pinout (N versions)
(HS) PE4 (HS) PE5 (HS) PE6 (HS) PE7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3
64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
NC NC PE1 / RDI PE0 / TDO VDD_2 OSC1 OSC2 VSS_2 NC NC RESET ISPSEL PA7 (HS) PA6 (HS) PA5 (HS) PA4 (HS) 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 ei0 44 43 e i2 42 41 40 39 e i3 38 37 36 35 e i1 34 33 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VSS_1 VDD_1 PA3 PA2 PA1 PA0 PC7 / SS PC6 / SCK / ISPCLK PC5 / MOSI PC4 / MISO / ISPDATA PC3 (HS) / ICAP1_B PC2 (HS) / ICAP2_B PC1 / OCMP1_B PC0 / OCMP2_B VSS_0 VDD_0
AIN4 / PD4 AIN5 / PD5 AIN6 / PD6 AIN7 / PD7 VDDA VSSA VDD_3 VSS_3 MCO / PF0 BEEP / PF1 PF 2 NC OCMP1_A / PF4 NC ICAP1_A / (HS) PF6 EXTCLK_A / (HS) PF7 (HS) 20mA high sink capability eix associated external interrupt vector
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PIN DESCRIPTION (Cont'd) Figure 3. 56-Pin SDIP Package Pinout (N versions)
PB4 PB5 PB6 PB7 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4 AIN5 / PD5 AIN6 / PD6 AIN7 / PD7 VDDA VSSA MCO / PF0 BEEP / PF1 P F2 OCMP1_A / PF4 ICAP1_A / (HS) PF6 EXTCLK_A / (HS) PF7 VDD_0 VSS_0 OCMP2_B / PC0 OCMP1_B / PC1 ICAP2_B / (HS) PC2 ICAP1_B / (HS) PC3 ISPDATA/ MISO / PC4 MOSI / PC5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
ei3
e i2
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
PB3 PB2 PB1 PB0 PE7 (HS) PE6 (HS) PE5 (HS) PE4 (HS) PE1 / RDI PE0 / TDO VDD_2 OSC1 OSC2 VSS_2 RESET ISPSEL PA7 (HS) PA6 (HS)I PA5 (HS) PA4 (HS) VSS_1 VDD_1 PA3 PA2 PA1 PA0 PC7 / SS PC6 / SCK / ISPCLK (HS) 20mA high sink capability eix associated external interrupt vector
ei1
e i0
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PIN DESCRIPTION (Cont'd) Figure 4. 44-Pin TQFP and 42-Pin SDIP Package Pinouts (J versions)
PE1 / RDI PB0 PB1 PB2 PB3 PB4 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4
44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 3 31 e i0 ei2 4 30 5 29 ei3 6 28 7 27 8 26 9 25 ei1 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 AIN5 / PD5 VDDA VSSA MCO / PF0 BEEP / PF1 P F2 OCMP1_A / PF4 ICAP1_A / (HS) PF6 EXTCLK_A / (HS) PF7 VDD_0 VSS_0
PE0 / TDO VDD_2 OSC1 OSC2 VSS_2 RESET ISPSEL PA7 (HS) PA6 (HS) PA5 (HS) PA4 (HS)
VSS_1 VDD_1 PA3 PC7 / SS PC6 / SCK / ISPCLK PC5 / MOSI PC4 / MISO / ISPDATA PC3 (HS) / ICAP1_B PC2 (HS) / ICAP2_B PC1 / OCMP1_B PC0 / OCMP2_B
PB4 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4 AIN5 / PD5 VDDA VSSA MCO / PF0 BEEP / PF1 P F2 OCMP1_A / PF4 ICAP1_A / (HS) PF6 EXTCLK_A / (HS) PF7 OCMP2_B / PC0 OCMP1_B / PC1 ICAP2_B/ (HS) PC2 ICAP1_B / (HS) PC3 ISPDATA / MISO / PC4 MOSI / PC5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
EI3 ei2
42 41 40 39 38 37 36 35 34 33
PB3 PB2 PB1 PB0 PE1 / RDI PE0 / TDO VDD_2 OSC1 OSC2 VSS_2 RESET ISPSEL PA7 (HS) PA6 (HS) PA5 (HS) PA4 (HS) VSS_1 VDD_1 PA3 PC7 / SS PC6 / SCK / ISPCLK (HS) 20mA high sink capability eix associated external interrupt vector
ei1
32 31 30 29 28 27 26 ei0 25 24 23 22
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ST72334J/N, ST72314J/N, ST72124J
PIN DESCRIPTION (Cont'd) For external pin connection guidelines, refer to Section 16 "ELECTRICAL CHARACTERISTICS" on page 107. Legend / Abbreviations for Table 1: Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C = CMOS 0.3VDD/0.7VDD, CT= CMOS 0.3VDD/0.7VDD with input trigger Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration: Input: float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog Output: OD = open drain 2), PP = push-pull Refer to Section 12 "I/O PORTS" on page 39 for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state. Table 1. Device Pin Description
Pin n TQFP64 Type SDIP56 QFP44 SDIP42 Pin Name Level Output Input float wpu Port Input ana int Main Output function (after reset) OD X X X X X X X X X X X X X X X X X X X X X X X X X X X X PP X X X X X X X X X X X X X X X X X X X X Port E4 Port E5 Port E6 Port E7 Port B0 Port B1 Port B2 Port B3 Port B4 Port B5 Port B6 Port B7 Port D0 ADC Analog Input 0 Port D1 ADC Analog Input 1 Port D2 ADC Analog Input 2 Port D3 ADC Analog Input 3 Port D4 ADC Analog Input 4 Port D5 ADC Analog Input 5 Port D6 ADC Analog Input 6 Port D7 ADC Analog Input 7 Analog Power Supply Voltage Analog Ground Voltage Digital Main Supply Voltage
Alternate function
1 49 2 50 3 51 4 52
PE4 (HS) PE5 (HS) PE6 (HS) PE7 (HS)
I/O CT HS I/O CT HS I/O CT HS I/O CT HS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O S S S CT CT CT CT CT CT CT CT CT CT CT CT CT CT CT CT
X X X X X X X X X X X X X X X X X X X X
X X X X ei2 ei2 ei2 ei2 ei3 ei3 ei3 ei3 X X X X X X X X
5 53 2 39 PB0 6 54 3 40 PB1 7 55 4 41 PB2 8 56 5 42 PB3 9 1 6 1 PB4 10 2 11 3 12 4 PB5 PB6 PB7
13 5 7 2 PD0/AIN0 14 6 8 3 PD1/AIN1 15 7 9 4 PD2/AIN2 16 8 10 5 PD3/AIN3 17 9 11 6 PD4/AIN4 18 10 12 7 PD5/AIN5 19 11 20 12 PD6/AIN6 PD7/AIN7
21 13 13 8 VDDA 22 14 14 9 VSSA 23 VDD_3
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Pin n TQFP64 Type SDIP56 QFP44 SDIP42 Pin Name
Level Output Input float wpu
Port Input an a in t
OD
Main Output function (after reset) PP
Alternate function
24
VSS_3
S I/O I/O I/O I/O CT CT CT CT X X X X X X X X X ei1 ei1 ei1 X X X X X X X X X X X X
Digital Ground Voltage Port F0 Port F1 Port F2 Port F4 Port F6 Port F7 Timer A Output Compare 1 Timer A Input Capture 1 Timer A External Clock Source Main clock output (fOSC/2) Beep signal output
25 15 15 10 PF0/MCO 26 16 16 11 PF1/BEEP 27 17 17 12 PF2 28 30 NC NC 29 18 18 13 PF4/OCMP1_A 31 19 19 14 PF6 (HS)/ICAP1_A 33 21 21 34 22 22 VDD_0 VSS_0
Not Connected Not Connected I/O CT HS S S I/O I/O CT CT X X X X X X X X X X X X X X X X X X X X ei0 ei0 ei0 ei0 X X X X X X X X X X X X X X X X X X X X X X X X
32 20 20 15 PF7 (HS)/EXTCLK_A I/O CT HS
Digital Main Supply Voltage Digital Ground Voltage Port C0 Timer B Output Compare 2 Port C1 Timer B Output Compare 1 Port C2 Timer B Input Capture 2 Port C3 Timer B Input Capture 1 Port C4 SPI Master In / Slave Out Data Port C5 SPI Master Out / Slave In Data Port C6 SPI Serial Clock Port C7 SPI Slave Select (active low) Port A0 Port A1 Port A2 Port A3 Digital Main Supply Voltage Digital Ground Voltage X X X X X X X X T T X X Port A4 Port A5 Port A6 Port A7 Must be tied low in user mode. In programming mode when available, this pin acts as In-Situ Programming mode selection. C X X Top priority non maskable interrupt (active low)
35 23 23 16 PC0/OCMP2_B 36 24 24 17 PC1/OCMP1_B 37 25 25 18 PC2 (HS)/ICAP2_B 38 26 26 19 PC3 (HS)/ICAP1_B 39 27 27 20 PC4/MISO 40 28 28 21 PC5/MOSI 41 29 29 22 PC6/SCK 42 30 30 23 PC7/SS 43 31 44 32 45 33 PA0 PA1 PA2
I/O CT HS I/O CT HS I/O I/O I/O I/O I/O I/O I/O I/O S S I/O CT HS I/O CT HS I/O CT HS I/O CT HS I CT CT CT CT CT CT CT CT
46 34 31 24 PA3 47 35 32 25 VDD_1 48 36 33 26 VSS_1 49 37 34 27 PA4 (HS) 50 38 35 28 PA5 (HS) 51 39 36 29 PA6 (HS) 52 40 37 30 PA7 (HS) 53 41 38 31 ISPSEL
54 42 39 32 RESET 55 56 NC NC
I/O
Not Connected S O Digital Ground Voltage Resonator oscillator inverter output or capacitor input for RC oscillator
57 43 40 33 VSS_3 58 44 41 34 OSC2 3)
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Pin n TQFP64 Type SDIP56 QFP44 SDIP42 Pin Name
Level Output Input float wpu
Port Input an a in t
OD
Main Output function (after reset) PP
Alternate function
59 45 42 35 OSC1 3) 60 46 43 36 VDD_3 61 47 44 37 PE0/TDO 62 48 1 38 PE1/RDI 63 64 NC NC
I S I/O I/O CT CT X X X X X X X X
External clock input or Resonator oscillator inverter input or resistor input for RC oscillator Digital Main Supply Voltage Port E0 Port E1 SCI Transmit Data Out SCI Receive Data In
Not Connected
Notes: 1. In the interrupt input column, "eix" defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input. 2. In the open drain output column, "T" defines a true open drain I/O (P-Buffer and protection diode to VDD are not implemented). See Section 12 "I/O PORTS" on page 39 and Section 16.8 "I/O PORT PIN CHARACTERISTICS" on page 128 for more details. 3. OSC1 and OSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to the on-chip oscillator see Section 3 "PIN DESCRIPTION" on page 7 and Section 16.5 "CLOCK AND TIMING CHARACTERISTICS" on page 116 for more details.
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4 REGISTER & MEMORY MAP
As shown in the Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, 384 or 512 bytes of RAM, up to 256 bytes of data EEPROM and 4 or 8 Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh. The highest address bytes contain the user reset and interrupt vectors. IMPOR TANT: Memory locations marked as "Reserved" must never be accessed. Accessing a reserved area can have unpredictable effects on the device.
Figure 5. Memory Map
0000h 0080h
HW Registers (see Table 2)
007Fh 0080h
00FFh 0100h
Short Addressing RAM Zero page (128 Bytes) Stack or 16-bit Addressing RAM (256 Bytes)
384 Bytes RAM
01FFh 027F h 0200h / 0280h
01FFh
512 Bytes RAM
0080h
Reserved
0BFFh 0C00h 0CFFh 0D00h B FFFh C000h E000h FF DFh FFE 0 h FFFFh
00FFh 0100h
Short Addressing RAM Zero page (128 Bytes)
256 Bytes Data EEPROM Reserved 16K Bytes Program Memory
Stack or 16-bit Addressing RAM (256 Bytes) 01FFh
0200h 027Fh
16-bit Addressing RAM
8K Bytes Program Memory
C000h
16 KBytes
E000h FFFFh
Interrupt & Reset Vectors (see Table 5 on page 34)
8 KBytes
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REGISTER & MEMORY MAP (Cont'd) Table 2. Hardware Register Map
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h to 001Fh 0020h 0021h 0022h 0023h 0024h to 0028h 0029h MCC MCCSR MISCR1 SPIDR SPICR SPISR PFDR PFDDR PFOR PDDR PDDDR PDOR PEDR PEDDR PEOR PBDR PBDDR PBOR PCDR PCDDR PCOR Block Register Label PADR PADDR PAOR Register Name Port A Data Register Port A Data Direction Register Port A Option Register Reserved Area (1 Byte) Port C Data Register Port C Data Direction Register Port C Option Register Reserved Area (1 Byte) Port B Data Register Port B Data Direction Register Port B Option Register Reserved Area (1 Byte) Port E Data Register Port E Data Direction Register Port E Option Register Reserved Area (1 Byte) Port D Data Register Port D Data Direction Register Port D Option Register Reserved Area (1 Byte) Port F Data Register Port F Data Direction Register Port F Option Register 00h1) 00h 00h R/W R/W R/W 00h1) 00h 00h R/W R/W R/W 2) 00h1) 00h 00h R/W R/W R/W 2) 00h1) 00h 00h R/W R/W R/W 2) 00h1) 00h 00h R/W R/W R/W Reset Status 00h1) 00h 00h Remarks R/W R/W R/W 2)
Port A
Port C
Port B
Port E
Port D
Port F
Reserved Area (9 Bytes)
Miscellaneous Register 1 SPI Data I/O Register SPI Control Register SPI Status Register
00h xxh 0xh 00h
R/W R/W R/W Read Only
SPI
Reserved Area (5 Bytes)
Main Clock Control / Status Register
01h
R/W
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Address 002Ah 002Bh 002Ch 002Dh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h
Block WATCHDOG
Register Label WDGCR CRSR
Register Name Watchdog Control Register
Reset Status 7Fh
Remarks R/W R/W R/W
Clock, Reset, Supply Control / Status Register 000x 000x Data-EEPROM Control/Status Register Reserved Area (4 Bytes) 00h
Data-EEPROM
EECSR
TIMER A
TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR MISCR2 TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR SCIETPR
Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer
A Control Register 2 A Control Register 1 A Status Register A Input Capture 1 High Register A Input Capture 1 Low Register A Output Compare 1 High Register A Output Compare 1 Low Register A Counter High Register A Counter Low Register A Alternate Counter High Register A Alternate Counter Low Register A Input Capture 2 High Register A Input Capture 2 Low Register A Output Compare 2 High Register A Output Compare 2 Low Register
00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h 00h 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h C0h xxh 00xx xxxx xxh 00h 00h --00h
R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only 3) Read Only 3) R/W 3) R/W 3) R/W R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W Read Only R/W R/W R/W R/W R/W R/W
Miscellaneous Register 2 Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer B Control Register 2 B Control Register 1 B Status Register B Input Capture 1 High Register B Input Capture 1 Low Register B Output Compare 1 High Register B Output Compare 1 Low Register B Counter High Register B Counter Low Register B Alternate Counter High Register B Alternate Counter Low Register B Input Capture 2 High Register B Input Capture 2 Low Register B Output Compare 2 High Register B Output Compare 2 Low Register
TIMER B
SCI
SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 SCI Extended Receive Prescaler Register Reserved area SCI Extended Transmit Prescaler Register
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Address 0058h 006Fh 0070h 0071h 0072h to 007Fh
Block
Register Label
Register Name
Reset Status
Remarks
Reserved Area (24 Bytes) ADCDR ADCCSR Data Register Control/Status Register xxh 00h Read Only R/W
ADC
Reserved Area (14 Bytes)
Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits corresponding to unavailable pins are forced to 1 by hardware, affecting accordingly the reset status value. These bits must always keep their reset value. 3. External pin not available.
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5 FLASH PROGRAM MEMORY
5.1 INTRODUCTION FLASH devices have a single voltage non-volatile FLASH memory that may be programmed in-situ (or plugged in a programming tool) on a byte-bybyte basis. 5.2 MAIN FEATURES
s s s s
Remote In-Situ Programming (ISP) mode Up to 16 bytes programmed in the same cycle MTP memory (Multiple Time Programmable) Read-out memory protection against piracy
5.3 STRUCTURAL ORGANISATION The FLASH program memory is organised in a single 8-bit wide memory block which can be used for storing both code and data constants. The FLASH program memory is mapped in the upper part of the ST7 addressing space and includes the reset and interrupt user vector area . 5.4 IN-SITU PROGRAMMING (ISP) MODE The FLASH program memory can be programmed using Remote ISP mode. This ISP mode allows the contents of the ST7 program memory to be updated using a standard ST7 programming tools after the device is mounted on the application board. This feature can be implemented with a minimum number of added components and board area impact. An example Remote ISP hardware interface to the standard ST7 programming tool is described below. For more details on ISP programming, refer to the ST7 Programming Specification. Remote ISP Overview The Remote ISP mode is initiated by a specific sequence on the dedicated ISPSEL pin. The Remote ISP is performed in three steps: Selection of the RAM execution mode Download of Remote ISP code in RAM Execution of Remote ISP code in RAM to program the user program into the FLASH Remote ISP hardware configuration In Remote ISP mode, the ST7 has to be supplied with power (VDD and VSS) and a clock signal (oscillator and application crystal circuit for example).
This mode needs five signals (plus the VDD signal if necessary) to be connected to the programming tool. This signals are: RESET: device reset VSS: device ground power supply ISPCLK: ISP output serial clock pin ISPDATA: ISP input serial data pin ISPSEL: Remote ISP mode selection. This pin must be connected to VSS on the application board through a pull-down resistor. If any of these pins are used for other purposes on the application, a serial resistor has to be implemented to avoid a conflict if the other device forces the signal level. Figure 6 shows a typical hardware interface to a standard ST7 programming tool. For more details on the pin locations, refer to the device pinout description. Figure 6. Typical Remote ISP Interface XTAL
HE10 CONNECTOR TYPE TO PROGRAMMING TOOL
1 C L0 C L1
OSC2
OSC1
VDD
ISPSEL 10K VSS RESET
ST7
ISPCLK ISPDATA 47K
APPLICATION
5.5 MEMORY READ-OUT PROTECTION The read-out protection is enabled through an option bit. For FLASH devices, when this option is selected, the program and data stored in the FLASH memory are protected against read-out piracy (including a re-write protection). When this protection option is removed the entire FLASH program memory is first automatically erased. However, the E2PROM data memory (when available) can be protected only with ROM devices.
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6 DATA EEPROM
6.1 INTRODUCTION The Electrically Erasable Programmable Read Only Memory can be used as a non volatile backup for storing data. Using the EEPROM requires a basic access protocol described in this chapter. 6.2 MAIN FEATURES
s s s s
s s
Up to 16 Bytes programmed in the same cycle EEPROM mono-voltage (charge pump) Chained erase and programming cycles Internal control of the global programming cycle duration End of programming cycle interrupt flag WAIT mode management
Figure 7. EEPROM Block Diagram
EE PR OM INTER RU PT
FALLING E DG E DETEC TOR
H IGH VOLTAGE P UM P R ES ER VE D EEPROM 0 IE LAT PGM
E E CS R
0
0
0
0
ADD RESS D EC ODER
4
R OW DE CO DE R
EEPR OM M EMO RY MATR IX (1 R OW = 16 x 8 BITS)
128 DAT A MU LTIPLEXER 4
128 16 x 8 BITS DATA LATC HES
4
AD DRE SS B U S
DATA BUS
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DATA EEPROM (Cont'd) 6.3 MEMORY ACCESS The Data EEPROM memory read/write access modes are controlled by the LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in Figure 8 describes these different memory access modes. Read Operation (LAT=0) The EEPROM can be read as a normal ROM location when the LAT bit of the EECSR register is cleared. In a read cycle, the byte to be accessed is put on the data bus in less than 1 CPU clock cycle. This means that reading data from EEPROM takes the same time as reading data from EPROM, but this memory cannot be used to execute machine code. Write Operation (LAT=1) To access the write mode, the LAT bit has to be set by software (the PGM bit remains cleared). When a write access to the EEPROM area occurs, the value is latched inside the 16 data latches according to its address. Figure 8. Data EEPROM Programming Flowchart When PGM bit is set by the software, all the previous bytes written in the data latches (up to 16) are programmed in the EEPROM cells. The effective high address (row) is determined by the last EEPROM write sequence. To avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same high address: only the four Least Significant Bits of the address can change. At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously, and an interrupt is generated if the IE bit is set. The Data EEPROM interrupt request is cleared by hardware when the Data EEPROM interrupt vector is fetched. Note: Care should be taken during the programming cycle. Writing to the same memory location will over-program the memory (logical AND between the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of LAT bit. It is not possible to read the latched data. This note is ilustrated by the Figure 9.
R EA D MO DE LAT=0 PG M=0
W RI T E M O DE LAT=1 P GM = 0
R EAD BY TE S IN EEPROM AR EA
WR ITE UP TO 16 BYTES IN EEPRO M AREA (with the same 11 MSB of the addr ess)
STAR T PR OGR AMMING CYCLE LAT=1 PG M=1 (set by software)
IN TERR UPT GEN ER ATIO N IF IE=1 CLEA RE D BY HARD WARE
0
LAT
1
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DATA EEPROM (Cont'd) 6.4 POWER SAVING MODES Wait mode The DATA EEPROM can enter WAIT mode on execution of the WFI instruction of the microcontroller. The DATA EEPROM will immediately enter this mode if there is no programming in progress, otherwise the DATA EEPROM will finish the cycle and then enter WAIT mode. Halt mode The DATA EEPROM immediatly enters HALT mode if the microcontroller executes the HALT instruction. Therefore the EEPROM will stop the function in progress, and data may be corrupted. Figure 9. Data EEPROM Programming Cycle
READ OPERATION NOT POSSIBLE INTERNAL PROGRAMMING VOLTAG E ERASE CYCLE WRITE OF DATA LATCHES WRITE CYCLE READ O PERATIO N POSSIBLE
6.5 ACCESS ERROR HANDLING If a read access occurs while LAT=1, then the data bus will not be driven. If a write access occurs while LAT=0, then the data on the bus will not be latched. If a programming cycle is interrupted (by software/ RESET action), the memory data will not be guarant eed.
tPROG
LAT
PGM
EEPROM I NTERRUPT
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DATA EEPROM (Cont'd) 6.6 REGISTER DESCRIPTION CONTROL/STATUS REGISTER (CSR) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 0 IE LAT 0 PGM
Bit 1 = LAT Latch Access Transfer This bit is set by software. It is cleared by hardware at the end of the programming cycle. It can only be cleared by software if PGM bit is cleared. 0: Read mode 1: Write mode Bit 0 = PGM Programming control and status This bit is set by software to begin the programming cycle. At the end of the programming cycle, this bit is cleared by hardware and an interrupt is generated if the ITE bit is set. 0: Programming finished or not yet started 1: Programming cycle is in progress Note: if the PGM bit is cleared during the programming cycle, the memory data is not guaranteed
Bit 7:3 = Reserved, forced by hardware to 0. Bit 2 = IE Interrupt enable This bit is set and cleared by software. It enables the Data EEPROM interrupt capability when the PGM bit is cleared by hardware. The interrupt request is automatically cleared when the software enters the interrupt routine. 0: Interrupt disabled 1: Interrupt enabled
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7 DATA EEPROM Register Map and Reset Values
Address (Hex.) 002Ch Register Label EECSR Reset Value 0 0 0 0 0 7 6 5 4 3 2 IE 0 1 RWM 0 0 PGM 0
7.1 READ-OUT PROTECTION OPTION The Data EEPROM can be optionally read-out protected in ST72334 ROM devices (see option list on page 146). ST72C334 Flash devices do not have this protection option.
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8 CENTRAL PROCESSING UNIT
8.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 8.2 MAIN FEATURES
s s s s s s s s
63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit index registers 16-bit stack pointer Low power modes Maskable hardware interrupts Non-maskable software interrupt
8.3 CPU REGISTERS The 6 CPU registers shown in Figure 10 are not present in the memory mapping and are accessed by specific instructions. Figure 10. CPU Registers
7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 0 0 0
Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate dat a. Index Registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 111HI 0 NZC CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value
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CPU REGISTERS (Cont'd) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx
7 1 1 1 H I N Z 0 C
The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 3 = I Interrupt mask. This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptable because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine.
Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions. Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions.
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CEN TRAL PROCESSING UNIT (Cont'd) Stack Pointer (SP) Read/Write Reset Value: 01 FFh
15 0 7 SP7 SP6 SP5 SP4 SP3 SP2 SP1 0 0 0 0 0 0 8 1 0 SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 11). Since the stack is 256 bytes deep, the 8th most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address. Figure 11. Stack Manipulation Example
CALL Subroutine @ 0100h Interrupt Event PUSH Y
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 11. When an interrupt is received, the SP is decremented and the context is pushed on the stack. On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area.
POP Y
IRET
RET or RSP
SP SP CC A X PCH SP PCH @ 01FFh PCL PCL PCH PCL Y CC A X PCH PCL PCH PCL SP CC A X PCH PCL PCH PCL SP PCH PCL SP
Stack Higher Address = 01FFh Stack Lower Address = 0100h
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9 SUPPLY, RESET AND CLOCK MANAGEMENT
The ST72334J/N, ST72314J/N and ST72124J microcontrollers include a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 12. See Section 16 "ELECTRICAL CHARACTERISTICS" on page 107 for more details. Main Features s Supp ly Manager with main supply low voltage detection (LVD) s Re se t Sequence Manager (RSM) Figure 12. Clock, Reset and Supply Block Diagram
s
s
Multi-Oscillator (MO) 4 Crystal/Ceramic resonator oscillators 1 External RC oscillator 1 Internal RC oscillator Clock Security System (CSS) Clock Filter Backup Safe Oscillator
CLOCK SECURITY SYSTEM (CSS) OSC2 OSC1 MULTIOSCILLATOR (MO) FILTER OSC CLOCK S A FE fOSC
TO MAIN CLOC K CON TR OLLER
RESET SEQUENCE RESET MANAGER (RSM) FROM WATCHDOG PERIPHERAL
VDD VSS
LOW VOLTAGE DETECTOR (LVD) CRSR 0 0 0 LVD RF 0 IE C SS D WDG RF
CSS INTERRUPT
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9.1 LOW VOLTAGE DETECTOR (LVD) To allow the integration of power management features in the application, the Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT- reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD Reset circuitry generates a reset when VDD is below: VIT+ when VDD is rising VIT- when VDD is falling The LVD function is illustrated in the Figure 13. Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-, the MCU can only be in two modes: under full software control in static safe reset Figure 13. Low Voltage Detector vs Reset V DD In these conditions, secure operation is always ensured for the application without the need for external reset hardware. During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Notes: 1. The LVD allows the device to be used without any external RESET circuitry. 2. Three different reference levels are selectable through the option byte according to the application requirement. LVD application note Application software can detect a reset caused by the LVD by reading the LVDRF bit in the CRSR register. This bit is set by hardware when a LVD reset is generated and cleared by software (writing zero).
Vhyst VIT+ VIT-
R ESET
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9.2 RESET SEQUENCE MANAGER (RSM) 9.2.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 15: s External RESET source pulse s Internal LVD RESET (Low Voltage Detection) s Internal WATCHDOG RESET These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases as shown in Figure 14: s De lay depending on the RESET source s 4 096 CPU clock cycle delay s RESET vector fetch Figure 15. Reset Block Diagram The 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The RESET vector fetch phase duration is 2 clock cycles. Figure 14. RESET Sequence Phases
RESET
DELAY INTERNAL RESET 4096 CLOCK CYCLES FETCH VECTO R
VDD
fCPU
COU NTER
INTER NAL R ESET
RON
RESET
W A TC HDO G R ES ET LVD R ESET
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RESET SEQUENCE MANAGER (Cont'd) 9.2.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See electrical characteristics section for more details. A RESET signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized. This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode. The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. Two RESET sequences can be associated with this RESET source: short or long external reset pulse (see Figure 16). Starting from the external RESET pulse recognition, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out. Figure 16. RESET Sequences VDD
VIT+ VIT-
9.2.3 Internal Low Voltage Detection RESET Tw o different RESET sequences caused by the internal LVD circuitry can be distinguished: s Power-On RESET s Voltage Drop RESET The device RESET pin acts as an output that is pulled low when VDD
RUN
DELAY
RUN
RUN
DELAY
RUN
DELAY
DELAY
tw(RSTL)out th(RSTL)in
EXTERNAL RESET SOURCE
th(RSTL)in
tw(RSTL)out
RESET PIN
WATCHDOG RESET WATCHDO G UNDERFLOW
INTERNAL RESET (4096 TCPU) FETCH VECTOR
0 0 00 0 00 0 00 0 00 0 0000
0 0 00 0 0000 0 0 00 0 00 0 00 0 00 0 00
0 0 00 0 00 0 00 0 00 0 0000
0 0 00 0 00 0 00 0 00 0 0000
0 0 00 0 00 0 00 0 00 0 00
LVD RESET
SHORT EXT. RESET
LONG EXT. RESET
WATCHDOG RESET
RUN
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9.3 MULTI-OSCILLATOR (MO) The main clock of the ST7 can be generated by four different source types coming from the multioscillator block: s a n external source s 4 crystal or ceramic resonator oscillators s a n external RC oscillator s a n internal high frequency RC oscillator Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configuration are shown in Table 3. Refer to the electrical characteristics section for more details. External Clock Source In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground. Crystal/Ceramic Oscillators This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption. In this mode of the multi-oscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator. These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase. External RC Oscillator This oscillator allows a low cost solution for the main clock of the ST7 using only an external resistor and an external capacitor. The frequency of the external RC oscillator (in the range of some MHz.) is fixed by the resistor and the capacitor values. Consequently in this MO mode, the accuracy of the clock is directly linked to the accuracy of the discrete components. The corresponding formula is fOSC=4/(REXCEX) Internal RC Oscillator The internal RC oscillator mode is based on the same principle as the external RC oscillator including the resistance and the capacitance of the device. This mode is the most cost effective one with the drawback of a lower frequency accuracy. Its frequency is in the range of several MHz. In this mode, the two oscillator pins have to be tied to ground. Table 3. ST7 Clock Sources
Hardware Configuration
External Clock
ST7 OSC1 OSC2
EXTERNAL SOURCE
Crystal/Ceramic Resonators
ST7 OSC1 OSC2
CL 1
LOAD CAPACITORS
ST7 OS C1 OS C2
CL2
External RC Oscillator
REX
CEX
Internal RC Oscillator
ST7 O SC 1 O S C2
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9.4 CLOCK SECURITY SYSTEM (CSS) The Clock Security System (CSS) protects the ST7 against main clock problems. To allow the integration of the security features in the applications, it is based on a clock filter control and an Internal safe oscillator. The CSS can be enabled or disabled by option byte. 9.4.1 Clock Filter Control The clock filter is based on a clock frequency limitation function. This filter function is able to detect and filter high frequency spikes on the ST7 main clock. If the oscillator is not working properly (e.g. working at a harmonic frequency of the resonator), the current active oscillator clock can be totally filtered, and then no clock signal is available for the ST7 from this oscillator anymore. If the original clock source recovers, the filtering is stopped automatically and the oscillator supplies the ST7 clock. 9.4.2 Safe Oscillator Control The safe oscillator of the CSS block is a low frequency back-up clock source (see Figure 17). If the clock signal disappears (due to a broken or disconnected resonator...) during a safe oscillator period, the safe oscillator delivers a low frequency clock signal which allows the ST7 to perform some rescue operations. Automatically, the ST7 clock source switches back from the safe oscillator if the original clock source recovers. Limitation detection The automatic safe oscillator selection is notified by hardware setting the CSSD bit of the CRSR register. An interrupt can be generated if the CSSIE bit has been previously set. These two bits are described in the CRSR register description. 9.4.3 Low Power Modes
Mode WAIT Description No effect on CSS. CSS interrupt cause the device to exit from Wait mode. The CRSR register is frozen. The CSS (including the safe oscillator) is disabled until HALT mode is exited. The previous CSS configuration resumes when the MCU is woken up by an interrupt with "exit from HALT mode" capability or from the counter reset value when the MCU is woken up by a RESET.
HALT
9.4.4 Interrupts The CSS interrupt event generates an interrupt if the corresponding Enable Control Bit (CSSIE) is set and the interrupt mask in the CC register is reset (RIM instruction).
Interrupt Event Enable Event Control Flag Bit CSSIE Exit from Wait Yes Exit from Halt1) No
CSS event detection (safe oscillator acti- CSSD vated as main clock)
Note 1: This interrupt allows to exit from active-halt mode if this mode is available in the MCU. Figure 17. Clock Filter Function and Safe Oscillator Function
CLOCK FILTER FUNCTION
fOSC/2 fCPU
SAFE OSCILLATOR FUNCTION
fOSC/2 fSFOSC fCPU
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9.5 SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION Read / Write Reset Value: 000x 000x (xxh)
7 0 0 0 LVD RF 0 CSS IE 0 CSS WDG D RF
Bit 7:5 = Reserved, always read as 0. Bit 4 = LVDRF LVD reset flag This bit indicates that the last RESET was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag description for more details. When the LVD is disabled by option byte, the LVDRF bit value is undefined. Bit 3 = Reserved, always read as 0. Bit 2 = CSSIE Clock security syst. interrupt enable This bit enables the interrupt when a disturbance is detected by the clock security system (CSSD bit set). It is set and cleared by software. 0: Clock security system interrupt disabled 1: Clock security system interrupt enabled Refer to Table 5, "Interrupt mapping," on page 34 for more details on the CSS interrupt vector. When the CSS is disabled by option byte, the CSSIE bit has no effect.
Bit 1 = CSSD Clock security system detection This bit indicates that the safe oscillator of the clock security system block has been selected by hardware due to a disturbance on the main clock signal (fOSC). It is set by hardware and cleared by reading the CRSR register when the original oscillator recovers. 0: Safe oscillator is not active 1: Safe oscillator has been activated When the CSS is disabled by option byte, the CSSD bit value is forced to 0. Bit 0 = WDGRF Watchdog reset flag This bit indicates that the last RESET was generated by the watchdog peripheral. It is set by hardware (Watchdog RESET) and cleared by software (writing zero) or an LVD RESET (to ensure a stable cleared state of the WDGRF flag when the CPU starts). Combined with the LVDRF flag information, the flag description is given by the following table.
RESET Sources External RESET pin Watchdog LVD LVDRF 0 0 1 WDGRF 0 1 X
Application notes The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can be detected by software while an external reset can not.
Table 4. Clock, Reset and Supply Register Map and Reset Values
Address (Hex.) 002Bh Register Label CRSR Reset Value 7 6 5 4 LVDRF x 3 2 CFIE 0 1 CSSD 0 0 WDGRF x
0
0
0
0
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10 INTERRUPTS
The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 18. The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). Note: After reset, all interrupts are disabled. When an interrupt has to be serviced: Normal processing is suspended at the end of the current instruction execution. The PC, X, A and CC registers are saved onto the stack. The I bit of the CC register is set to prevent additional interrupts. The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping Table for vector addresses). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume. Priority Management By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine. In the case when several interrupts are simultaneously pending, an hardware priority defines which one will be serviced first (see the Interrupt Mapping Table). Interrupts and Low Power Mode All interrupts allow the processor to leave the WAIT low power mode. Only external and specifically mentioned interrupts allow the processor to leave the HALT low power mode (refer to the "Exit from HALT" column in the Interrupt Mapping Table). 10.1 NON INTERRUPT MASKABLE SOFTWARE It will be serviced according to the flowchart on Figure 18. 10.2 EXTERNAL INTERRUPTS External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power m ode. The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins, connected to the same interrupt vector, are configured as interrupts, their signals are logically NANDed before entering the edge/level detection block. Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of a NANDed source (as described on the I/O ports section), a low level on an I/O pin configured as input with interrupt, masks the interrupt request even in case of risingedge sensitivity. 10.3 PERIPHERAL INTERRUPTS Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: The I bit of the CC register is cleared. The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by: Writing "0" to the corresponding bit in the status register or Access to the status register while the flag is set followed by a read or write of an associated register. Note: the clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being enabled) will therefore be lost if the clear sequence is ex ec ut ed.
This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit.
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INTERRUPTS (Cont'd) Figure 18. Interrupt Processing Flowchart
FROM RESET I BIT SET? Y N
N
INTERRUPT PENDING? Y
FETCH NEXT INSTRUCTION
N
IRET? Y
ST ACK PC, X, A, CC SET I B IT LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM ST ACK THIS CLEARS I BIT BY DEFAULT
Table 5. Interrupt mapping
N Source Block RESET TRAP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 SPI TIMER A TIMER B SCI MCC/RTC CSS ei0 ei1 ei2 ei3 Reset Software Interrupt Not used Main Clock Controller Time Base Interrupt or Clock Security System Interrupt External Interrupt Port A3..0 External Interrupt Port F2..0 External Interrupt Port B3..0 External Interrupt Port B7..4 Not used SPI Peripheral Interrupts TIMER A Peripheral Interrupts TIMER B Peripheral Interrupts SCI Peripheral Interrupts SPISR TASR TBSR SCISR EECSR Lowest Priority no N/A MCCSR CRSR yes Description Register Label N/A Priority Order Highest Priority Exit from HALT1) yes no Address Vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h FFE2h-FFE3h FFE0h-FFE1h
Data-EEPROM Data EEPROM Interrupt Not used
Note 1. Valid for HALT and ACTIVE-HALT modes except for the MCC/RTC or CSS interrupt source which exits from ACTIVE-HALT mode only.
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11 POWER SAVING MODES
11.1 INTRODUCTION To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 19): SLOW, WAIT (SLOW WAIT), ACTIVE HALT and HALT. After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (fCPU). From RUN mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. Figure 19. Power Saving Mode Transitions
High RUN
fCPU
11.2 SLOW MODE This mode has two targets: To reduce power consumption by decreasing the internal clock in the device, To adapt the internal clock frequency (fCPU) to the available supply voltage. SLOW mode is controlled by three bits in the MISCR1 register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (fCPU). In this mode, the oscillator frequency can be divided by 4, 8, 16 or 32 instead of 2 in normal operating mode. The CPU and peripherals are clocked at this lower frequency. Note: SLOW-WAIT mode is activated when entering the WAIT mode while the device is already in SLOW mode. Figure 20. SLOW Mode Clock Transitions
fOSC/4 fOSC/8 fOSC/2
SLOW
fOSC /2 MISCR1
WAIT SLOW WAIT ACTIVE HALT HALT Low POWER CONSUMPTION
CP1:0 SMS
00
01
NEW SLOW FREQUENCY REQUEST
NORMAL RUN MODE REQUEST
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POWER SAVING MODES (Cont'd) 11.3 WAIT MODE WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the `WFI' instruction. All peripherals remain active. During WAIT mode, the I bit of the CC register is cleared, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or RESET occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 21. Figure 21. WAIT Mode Flow-chart
OSCILLATOR PERIPHERALS CPU I BIT ON ON OFF 0
WFI INSTRUCTION
N RESET N INTERRUPT Y OSCILLATOR PERIPHERALS CPU I BIT ON OFF ON 0 Y
4096 CPU CLOCK CYCLE DELAY
OSCILLATOR PERIPHERALS CPU I BIT
ON ON ON X 1)
FETCH RESET VECTOR OR SERVICE INTERRUPT
Note: 1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
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POWER SAVING MODES (Cont'd) 11.4 ACTIVE-HALT AND HALT MODES ACTIVE-HALT and HALT modes are the two lowest power consumption modes of the MCU. They are both entered by executing the `HALT' instruction. The decision to enter either in ACTIVE-HALT or HALT mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR register).
MCCSR OIE bit 0 1 Power Saving Mode entered when HALT instruction is executed HALT mode ACTIVE-HALT mode HALT INSTRUCTION (MCCSR.OIE=1)
Figure 22. ACTIVE-HALT Timing Overview
RUN ACTIVE HALT 4096 CPU CYCLE DELAY RESET OR INTERRUPT RUN
HALT INSTRUCTION [MCCSR.OIE=1]
FETCH VECTOR
Figure 23. ACTIVE-HALT Mode Flow-chart
OSCILLATOR ON PERIPHERALS 1) OFF CPU OFF I BIT 0
11.4.1 ACTIVE-HALT MODE ACTIVE-HALT mode is the lowest power consumption mode of the MCU with a real time clock available. It is entered by executing the `HALT' instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is set (see Section 14.2 "MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC)" on page 52 for more details on the MCCSR register). The MCU can exit ACTIVE-HALT mode on reception of either an MCC/RTC interrupt, a specific interrupt (see Table 5, "Interrupt mapping," on page 34) or a RESET. When exiting ACTIVEHALT mode by means of a RESET or an interrupt, a 4096 CPU cycle delay occurs. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 23). When entering ACTIVE-HALT mode, the I bit in the CC register is cleared to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In ACTIVE-HALT mode, only the main oscillator and its associated counter (MCC/RTC) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). The safeguard against staying locked in ACTIVEHALT mode is provided by the oscillator interrupt. Note: As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set), entering ACTIVE-HALT mode while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode.
N RESET N Y INTERRUPT 2) Y OSCILLATOR ON PERIPHERALS 1) OFF CPU ON I BIT X 3) 4096 CPU CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS CPU I BITS ON ON ON X 3)
FETCH RESET VECTOR OR SERVICE INTERRUPT
Notes: 1. Peripheral clocked with an external clock source can still be active. 2. Only the MCC/RTC interrupt and some specific interrupts can exit the MCU from ACTIVE-HALT mode (such as external interrupt). Refer to Table 5, "Interrupt mapping," on page 34 for more details. 3. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
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POWER SAVING MODES (Cont'd) 11.4.2 HALT MODE The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the `HALT' instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is cleared (see Section 14.2 "MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC) " on page 52 for more details on the MCCSR register). The MCU can exit HALT mode on reception of either a specific interrupt (see Table 5, "Interrupt mapping," on page 34) or a RESET. When exiting HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 25). When entering HALT mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes immediately. In HALT mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of Watchdog operation with HALT mode is configured by the "WDGHALT" option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see Section 18.1 on page 144 for more details). Figure 24. HALT Timing Overview
RUN HALT 4096 CPU CYCLE DELAY RESET OR INTERRUPT FETCH VECTOR RUN
Figure 25. HALT Mode Flow-chart
HALT INSTRUCTION (MCCSR.OIE=0) ENABLE WDGHALT 1) 1 WATCHDOG RESET OSCILLATOR OFF PERIPHERALS 2) OFF CPU OFF I BIT 0 0 WATCHDOG DISABLE
N RESET N Y INTERRUPT 3) Y OSCILLATOR PERIPHERALS CPU I BIT ON OFF ON X 4)
4096 CPU CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS CPU I BITS ON ON ON X 4)
FETCH RESET VECTOR OR SERVICE INTERRUPT
HALT INSTRUCTION [MCCSR.OIE=0]
Notes: 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 5, "Interrupt mapping," on page 34 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
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12 I/O PORTS
12.1 INTRODUCTION The I/O ports offer different functional modes: transfer of data through digital inputs and outputs and for specific pins: external interrupt generation alternate signal input/output for the on-chip peripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 12.2 FUNCTIONAL DESCRIPTION Each port has 2 main registers: Data Register (DR) Data Direction Register (DDR) and one optional register: Option Register (OR) Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is shown in Figure 26 12.2.1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Notes: 1. Writing the DR register modifies the latch value but does not affect the pin status. 2. When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. 3. Do not use read/modify/write instructions (BSET or BRES) to modify the DR register External interrupt function When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the Miscellaneous register. Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt source, these are logically NANDed. For this reason if one of the interrupt pins is tied low, it masks the other ones. In case of a floating input with interrupt configuration, special care must be taken when changing the configuration (see Figure 27). The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the Miscellaneous register must be modified. 12.2.2 Output Modes The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Tw o different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status:
DR 0 1 Push-pull VSS VDD Open-drain Vss Floating
12.2.3 Alternate Functions When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register. Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.
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I/O PORTS (Cont'd) Figure 26. I/O Port General Block Diagram
REGISTER ACCESS ALTERNATE OUTPUT 1 0 ALTERNATE ENABLE DR
V DD
P-BUFFER (see table below) PULL-UP (see table below) V DD
DDR PULL-UP CONFIGURATION If implemented OR SEL N-BUFFER DDR SEL CMOS SCHMITT TRIGGER ANALOG INPUT DIODES (see table below) PAD
OR
EXTERNAL INTERRUPT SOURCE (eix)
Table 6. I/O Port Mode Options
Configuration Mode Input Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) True Open Drain Pull-Up Off On Off NI P-Buffer Off On Off NI On On Diodes to VDD to VSS
Output
Legend: N I - not implemented Off - implemented not activated On - implemented and activated
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DATA BUS
DR SEL
1 0
ALTERNATE INPUT FROM OTHER BITS
POLARITY SELECTION
NI (see note)
Note: The diode to VDD is not implemented in the true open drain pads. A local protection between the pad and VSS is implemented to protect the device against positive stress.
ST72334J/N, ST72314J/N, ST72124J
I/O PORTS (Cont'd) Table 7. I/O Port Configurations
Hardware Configuration
NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS VDD RPU PAD PULL-UP CONF IGURATION DR REGISTER ACCESS
DR REGISTER
W DATA BUS R
INPUT 1)
ALT ERNATE INPUT FROM OTHER PINS INTERRUPT CONFIGURATION POLARITY SELECTION ANALOG INPUT NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS EXTERNAL INTERRUPT SOURCE (eix)
OPEN-DRAIN OUTPUT 2)
VDD RPU
DR REGIST ER ACCESS
PAD
DR REGISTER
R/W
DATA BUS
ALTERNATE ENABLE
ALTERNATE OUTPUT
PUSH-PULL OUTPUT 2)
NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS
VDD RPU
DR REGIST ER ACCESS
PAD
DR REGISTER
R/W
DATA BUS
ALTERNATE ENABLE
ALTERNATE OUTPUT
Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.
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I/O PORTS (Cont'd) CAUTION: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) sw itches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin. WARNING: The analog input voltage level must be within the limits stated in the absolute maximum ratings. 12.3 I/O PORT IMPLEMENTATION The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 27 Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. Figure 27. Interrupt I/O Port State Transitions
01
INPUT floating/pull-up interrupt
Standard Ports PA5:4, PC7:0, PD7:0, PE7:4, PE1:0, PF7:6, PF4
MODE floating input pull-up input open drain output push-pull output DDR 0 0 1 1 OR 0 1 0 1
Interrupt Ports PA2:0, PB7:5, PB2:0, PF1:0 (with pull-up)
MODE floating input pull-up interrupt input open drain output push-pull output DDR 0 0 1 1 OR 0 1 0 1
PA3, PB4, PB3, PF2 (without pull-up)
MODE floating input floating interrupt input open drain output push-pull output DDR 0 0 1 1 OR 0 1 0 1
True Open Drain Ports P A 7: 6
MODE floating input open drain (high sink ports) DDR 0 1
00
INPUT floating (reset state)
10
OUTPUT open-drain
11
OUTPUT push-pull
XX
= DDR, OR
The I/O port register configurations are summarized as follows.
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I/O PORTS (Cont'd) 12.4 LOW POWER MODES
Mode WAIT HALT Description No effect on I/O ports. External interrupts cause the device to exit from WAIT mode. No effect on I/O ports. External interrupts cause the device to exit from HALT mode.
12.5 INTERRUPTS The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the I-bit in the CC register is reset (RIM instruction).
Interrupt Event External interrupt on selected external event Enable Event Control Flag Bit DDRx ORx Exit from Wait Y es Exit from Halt Yes
Table 8. Port Configuration
Input Port Pin name OR = 0 PA7:6 PA5:4 PA3 PA2:0 PB4:3 PB7:5, PB2:0 PC7:4, PC1:0 PC3:2 PD7:0 PE7:4 PE1:0 PF7:6 PF4 PF2 PF1:0 floating floating floating floating floating floating floating floating floating floating floating floating floating floating floating pull-up floating interrupt pull-up interrupt floating interrupt pull-up interrupt pull-up pull-up pull-up pull-up pull-up pull-up pull-up floating interrupt pull-up interrupt OR = 1 OR = 0 OR = 1 High-Sink Yes true open-drain open drain push-pull open drain push-pull open drain push-pull open drain push-pull open drain push-pull open drain push-pull open drain push-pull open drain push-pull open drain push-pull open drain push-pull open drain push-pull open drain push-pull open drain push-pull open drain push-pull Output
Port A
Port B Port C Port D Port E
No
Yes No Yes No Yes No
Port F
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I/O PORTS (Cont'd) 12.5.1 Register Description DATA REGISTER (DR) Port x Data Register PxDR with x = A, B, C, D, E or F. Read / Write Reset Value: 0000 0000 (00h)
7 D7 D6 D5 D4 D3 D2 D1 0 D0
OPTION REGISTER (OR) Port x Option Register PxOR with x = A, B, C, D, E or F. Read / Write Reset Value: 0000 0000 (00h)
7 O7 O6 O5 O4 O3 O2 O1 0 O0
Bit 7:0 = D[7:0] Data register 8 bits. The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken into account even if the pin is configured as an input; this allows to always have the expected level on the pin when toggling to output mode. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input). DATA DIRECTION REGISTER (DDR) Port x Data Direction Register PxDDR with x = A, B, C, D, E or F. Read / Write Reset Value: 0000 0000 (00h)
7 DD7 DD6 DD5 DD4 DD3 DD2 DD1 0 DD0
Bit 7:0 = O[7:0] Option register 8 bits. For specific I/O pins, this register is not implemented. In this case the DDR register is enough to select the I/O pin configuration. The OR register allows to distinguish: in input mode if the pull-up with interrupt capability or the basic pull-up configuration is selected, in output mode if the push-pull or open drain configuration is selected. Each bit is set and cleared by software. Input mode: 0: floating input 1: pull-up input with or without interrupt Output mode: 0: output open drain (with P-Buffer deactivated) 1: output push-pull
Bit 7:0 = DD[7:0] Data direction register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bits is set and cleared by software. 0: Input mode 1: Output mode
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I/O PORTS (Cont'd) Table 9. I/O Port Register Map and Reset Values
Address (Hex.) Register Label 7 6 5 4 3 2 1 0
Reset Value of all IO port registers 0000h 0001h 0002h 0004h 0005h 0006h 0008h 0009h 000Ah 000Ch 000Dh 000Eh 0010h 0011h 0012h 0014h 0015h 0016h PADR PADDR PAOR 1) PCDR PCDDR PCOR PBDR PBDDR PBOR PEDR PEDDR PEOR 1) PDDR PDDDR PDOR PFDR PFDDR PFOR
1) 1)
0
0
0
0
0
0
0
0
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
Notes: 1) The bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value.
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13 MISCELLANEOUS REGISTERS
The miscellaneous registers allow control over several different features such as the external interrupts or the I/O alternate functions. 13.1 I/O PORT INTERRUPT SENSITIVITY
PB0
Figure 28. Ext. Interrupt Sensitivity
MISCR1 IS10 PB1 PB2 PB3 PB4 PB5 PB6 PB7 MISCR1 IS20 PA0 PA1 PA2 PA3 P F0 P F1 P F2 INT ERRUPT SOURCE ei0 ei1 IS21 INTERRUPT SOURCE ei2 e i3 IS11
The external interrupt sensitivity is controlled by the ISxx bits of the MISCR1 miscellaneous register. This control allows to have two fully independent external interrupt source sensitivities. Each external interrupt source can be generated on four different events on the pin: s F alli ng edge s Ri sing edge s F alli ng and rising edge s F alli ng edge and low level To guarantee correct functionality, the sensitivity bits in the MISCR1 register must be modified only when the I bit of the CC register is set to 1 (interrupt masked). See I/O port register and Miscellaneous register descriptions for more details on the programming. 13.2 I/O PORT ALTERNATE FUNCTIONS The MISCR registers manage four I/O port miscellaneous alternate functions: s M ain clock signal (fC PU) output on PF0 s A beep signal output on PF1 (with 3 selectable audio frequencies) s SPI pin configuration: SS pin internal control to use the PC7 I/O port function while the SPI is active. These functions are described in detail in the Section 13 "MISCELLANEOUS REGISTERS" on page 46.
SENSITIVITY CONT ROL
SENSITIVIT Y CONTROL
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MISCELLAN EOUS REGISTERS (Cont'd) 13.3 REGISTERS DESCRIPTION MISCELLAN EOUS REGISTER 1 (MISCR1) Read / Write Reset Value: 0000 0000 (00h)
7 IS11 IS10 MCO IS21 IS20 CP1 CP0 0 SMS
Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following external interrupts:ei0 (port A3..0) and ei1 (port F2..0). These 2 bits can be written only when the I bit of the CC register is set to 1 (interrupt disabled). Bit 2:1 = CP[1:0] CPU clock prescaler These bits select the CPU clock prescaler which is applied in the different slow modes. Their action is conditioned by the setting of the SMS bit. These two bits are set and cleared by software
fCPU in SLOW mode fOSC / 4 fOSC / 8 fOSC / 16 fOSC / 32 CP1 CP0 0 1 0 1 0 0 1 1
Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external interrupts: ei2 (port B3..0) and ei3 (port B7..4). These 2 bits can be written only when the I bit of the CC register is set to 1 (interrupt disabled).
External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge IS11 IS10 0 0 1 1 0 1 0 1
Bit 5 = MCO Main clock out selection This bit enables the MCO alternate function on the I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for general-purpose I/O) 1: MCO alternate function enabled (fOSC/2 on I/O port) Note: To reduce power consumption, the MCO function is not active in ACTIVE-HALT mode.
Bit 0 = SMS Slow mode select This bit is set and cleared by software. 0: Normal mode. fCPU = fOSC / 2 1: Slow mode. fCPU is given by CP1, CP0 See low power consumption mode and MCC chapters for more details.
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MISCELLAN EOUS REGISTERS (Cont'd) MISCELLAN EOUS REGISTER 2 (MISCR2) Read / Write Reset Value: 0000 0000 (00h)
7 BC1 BC0 SSM 0 SSI
Bit 7:6 = Reserved Must always be cleared Bit 5:4 = BC[1:0] Beep control These 2 bits select the PF1 pin beep capability.
Beep mode with fOSC=16MHz Off ~2-KHz ~1-KHz ~500-Hz Output Beep signal ~50% duty cycle BC1 BC0 0 0 1 1 0 1 0 1
The beep output signal is available in ACTIVEHALT mode but has to be disabled to reduce the consumption. Bit 3:2 = Reserved Must always be cleared Bit 1 = SSM SS mode selection It is set and cleared by software. 0: Normal mode - SS uses information coming from the SS pin of the SPI. 1: I/O mode, the SPI uses the information stored into bit SSI. Bit 0 = SSI SS internal mode This bit replaces pin SS of the SPI when bit SSM is set to 1. (see SPI description). It is set and cleared by software.
Table 10. Miscellaneous Register Map and Reset Values
Address (Hex.) 0020h 0040h Register Label MISCR1 Reset Value MISCR2 Reset Value 7 IS11 0 0 6 IS10 0 0 5 MCO 0 BC1 0 4 IS21 0 BC0 0 3 IS20 0 0 2 CP1 0 0 1 CP0 0 SSM 0 0 SMS 0 SSI 0
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14 ON-CHIP PERIPHERALS
14.1 WATCHDOG TIMER (WDG) 14.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter's contents before the T6 bit becomes cleared. 14.1.2 Main Features s Program m able timer (64 increments of 12288 CPU cycles) s Program m able reset s Re se t (if watchdog activated) after a HALT instruction or when the T6 bit reaches zero Figure 29. Watchdog Block Diagram
s s
Hardware Watchdog selectable by option byte Watchdog Reset indicated by status flag (in versions with Safe Reset option only)
14.1.3 Functional Description The counter value stored in the CR register (bits T[6:0]), is decremented every 12,288 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns.
RESET
WATCHDOG CONTROL REGISTER (CR) WDGA T6 T5 T4 T3 T2 T1 T0
7-BIT DOWNCOUNTER
fCPU
CLOCK DIVIDER ÷12288
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WATC HDOG TIMER (Cont'd) The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. The value to be stored in the CR register must be between FFh and C0h (see Table 11 .Watchdog Timing (fCPU = 8 MHz)): The WDGA bit is set (watchdog enabled) The T6 bit is set to prevent generating an immediate reset The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. Table 11.Watchdog Timing (fCPU = 8 MHz)
CR Register initial value Max Min FFh C0h WDG timeout period (ms) 98.304 1.536
14.1.7 Register Description CON TROL REGISTER (CR) Read / Write Reset Value: 0111 1111 (7Fh)
7 WDGA T6 T5 T4 T3 T2 T1 0 T0
Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watchdog option is enabled by option byte. Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared). STATUS REGISTER (SR) Read / Write Reset Value*: 0000 0000 (00h)
7 0 WDOGF
Notes: Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). If the watchdog is activated, the HALT instruction will generate a Reset. 14.1.4 Hardware Watchdog Option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used. Refer to the device-specific Option Byte description. 14.1.5 Low Power Modes
Mode WAIT HALT Description No effect on Watchdog.
Bit 0 = WDOGF Watchdog flag. This bit is set by a watchdog reset and cleared by software or a power on/off reset. This bit is useful for distinguishing power/on off or external reset and watchdog reset. 0: No Watchdog reset occurred 1: Watchdog reset occurred * Only by software and power on/off reset Note: This register is not used in versions without LVD Reset.
Immediate reset generation as soon as the HALT instruction is executed if the Watchdog is activated (WDGA bit is set).
14.1.6 Interrupts None.
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WATC HDOG TIMER (Cont'd) Table 12. Watchdog Timer Register Map and Reset Values
Address (Hex.) 002Ah Register Label WDGCR Reset Value 7 WDGA 0 6 T6 1 5 T5 1 4 T4 1 3 T3 1 2 T2 1 1 T1 1 0 T0 1
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14.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC) The Main Clock Controller consists of three different functions: s a programmable CPU clock prescaler s a clock-out signal to supply external devices s a real time clock timer with interrupt capability Each function can be used independently and simultaneously. 14.2.1 Programmable CPU clock prescaler The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal peripherals. It manages SLOW power saving mode (See Section 11.2 "SLOW MODE" on page 35 for more details). The prescaler selects the fCPU main clock frequency and is controlled by three bits in the MISCR1 register: CP[1:0] and SMS. CAUTION: The prescaler does not act on the CAN peripheral clock source. This peripheral is always supplied by the fOSC/2 clock source. 14.2.2 Clock-out capability The clock-out capability is an alternate function of an I/O port pin that outputs a fOSC/2 clock to drive external devices. It is controlled by the MCO bit in the MISCR1 register. CAUTION: When selected, the clock out pin suspends the clock during ACTIVE-HALT mode. 14.2.3 Real time clock timer (RTC) The counter of the real time clock timer allows an interrupt to be generated based on an accurate real time clock. Four different time bases depending directly on fOSC are available. The whole functionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and OIF. When the RTC interrupt is enabled (OIE bit set), the ST7 enters ACTIVE-HALT mode when the HALT instruction is executed. See Section 11.4 "ACTIVE-HALT AND HALT MODES" on page 37 for more details.
Figure 30. Main Clock Controller (MCC/RTC) Block Diagram
P O RT ALTERN ATE FU NCTIO N
fOSC/2
M CO
M I SC R 1 M CO CP1 C P0 SMS
fOSC
DIV 2 RTC COUNTER
DIV 2, 4, 8, 16 fCPU
C PU CLOCK TO CPU AND PERIPHERALS
MCC SR 0 0 0 0 TB1 TB0 OIE OIF
M CC/RTC INTERRU PT
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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (Cont'd) MISCELLAN EOUS REGISTER 1 (MISCR1) See Section 13 on page 46. MAIN CLOCK CONTROL/STATUS REGISTER (MCCSR) Read / Write Reset Value: 0000 0001 (01h)
7
0 0 0 0 TB 1 TB 0 OIE
0
OIF
Bit 0 = OIF Oscillator interrupt flag This bit is set by hardware and cleared by software reading the CSR register. It indicates when set that the main oscillator has measured the selected elapsed time (TB1:0). 0: Timeout not reached 1: Timeout reached CAUTION: The BRES and BSET instructions must not be used on the MCCSR register to avoid unintentionally clearing the OIF bit. 14.2.4 Low Power Modes
Bit 7:4 = Reserved, always read as 0. Bit 3:2 = TB[1:0] Time base control These bits select the programmable divider time base. They are set and cleared by software.
Counter Prescaler 32000 64000 160000 40 0 0 Time Base TB1 fOSC =8MHz 4ms 8ms 20ms 50ms fOSC=16MHz 2ms 4ms 10ms 25ms 0 0 1 1 0 1 0 1 TB0
Mode WAIT
Description No effect on MCC/RTC peripheral. MCC/RTC interrupt cause the device to exit from WAIT mode. No effect on MCC/RTC counter (OIE bit is set), the registers are frozen. MCC/RTC interrupt cause the device to exit from ACTIVE-HALT mode. MCC/RTC counter and registers are frozen. MCC/RTC operation resumes when the MCU is woken up by an interrupt with "exit from HALT" capability.
ACTIVEHALT
HALT
A modification of the time base is taken into account at the end of the current period (previously set) to avoid unwanted time shift. This allows to use this time base as a real time clock. Bit 1 = OIE Oscillator interrupt enable This bit set and cleared by software. 0: Oscillator interrupt disabled 1: Oscillator interrupt enabled This interrupt allows to exit from ACTIVE-HALT mode. When this bit is set, calling the ST7 software HALT instruction enters the ACTIVE-HALT power saving mode.
14.2.5 Interrupts The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is set and the interrupt mask in the CC register is not active (RIM instruction).
Interrupt Event Time base overflow event Enable Event Control Flag Bit OIF OIE Exit from Wait Yes Exit from Halt No 1)
Note: 1. The MCC/RTC interrupt allows to exit from ACTIVE-H ALT mode, not from HALT mode.
Table 13. MCC Register Map and Reset Values
Address (Hex.) 0029h Register Label MCCSR Reset Value 7 6 5 4 3 TB1 0 2 TB0 0 1 OIE 0 0 OIF 1
0
0
0
0
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14.3 16-BIT TIMER 14.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of up to two input signals (input capture) or generating up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler. Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequencies are not modified. This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B). 14.3.2 Main Features s Program m able prescaler: fCPU divided by 2, 4 or 8. s O verflo w status flag and maskable interrupt s External clock input (must be at least 4 times slower than the CPU clock speed) with the choice of active edge s O utput compare functions with: 2 dedicated 16-bit registers 2 dedicated programmable signals 2 dedicated status flags 1 dedicated maskable interrupt s Input capture functions with: 2 dedicated 16-bit registers 2 dedicated active edge selection signals 2 dedicated status flags 1 dedicated maskable interrupt s Pul se Width Modulation mode (PWM) s O ne Pulse mode s 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)* The Block Diagram is shown in Figure 31. *Note: Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pin out description. When reading an input signal on a non-bonded pin, the value will always be `1'. 14.3.3 Functional Description 14.3.3.1 Counter The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low. Counter Register (CR): Counter High Register (CHR) is the most significant byte (MS Byte). Counter Low Register (CLR) is the least significant byte (LS Byte). Alternate Counter Register (ACR) Alternate Counter High Register (ACHR) is the most significant byte (MS Byte). Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte). These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register (SR). (See note at the end of paragraph titled 16-bit read sequence). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode. The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 14 Clock Control Bits. The value in the counter register repeats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be fCPU/2, fCPU/4, fCPU/8 or an external frequency.
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16-BIT TIMER (Cont'd) Figure 31. Timer Block Diagram
ST7 INTERNAL BUS fCPU MCU-PERIPHERAL INTERFACE
8 high
8 low
8-bit buffer
8 high low
8 high
8 low
8 high
8 low
8 high
8 low
8
EXEDG
16
1/2 1/4 1/8 EXTCLK pin COUNTER REGISTER ALTERNATE COUNTER REGISTER OUTPUT COMPARE REGISTER 1 OUTPUT COMPARE REGISTER 2 INPUT CAPTURE REGISTER 1 INPUT CAPTURE REGISTER 2
16
16
16
CC[1:0] TIMER INTERNAL BUS 16 16 OVERFLOW DETECT CIRCUIT
OUTPUT COMPARE CIRCUIT
EDGE DETECT CIRCUIT1
ICAP1 pin
6
EDGE DETECT CIRCUIT2
ICAP2 pin
LATCH1
ICF1 OCF1 TOF ICF2 OCF2 0
OCMP1 pin OCMP2 pin
0
0 LATCH2
(Status Register) SR
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
OC1E OC2E OPM PWM
CC1
CC0 IEDG2 EXEDG
(Control Register 1) CR1
(Control Register 2) CR2
(See note) TIMER INTERRUPT
Note: If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See device Interrupt Vector Table)
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16-BIT TIMER (Cont'd) 16-bit Read Sequence: (from either the Counter Register or the Alternate Counter Register).
Beginning of the sequence
At t0 Re ad MS Byte Ot her instructions Rea d At t0 +t LS Byte
Returns the buffered
LS Byte is buffered
LS Byte value at t0
Sequence completed
The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read. Whatever the timer mode used (input capture, output compare, One Pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: The TOF bit of the SR register is set. A timer interrupt is generated if: TOIE bit of the CR1 register is set and I bit of the CC register is cleared. If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true.
Clearing the overflow interrupt request is done in two steps: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. Note: The TOF bit is not cleared by accessing the ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously. The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset). 14.3.3.2 External Clock The external clock (where available) is selected if CC0=1 and CC1=1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter. The counter is synchronised with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency.
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