M48T35AV
3.3V, 256Kbit (32Kbit x 8) TIMEKEEPER SRAM
Features
Integrated, ultra low power SRAM, real-time clock, power-fail control circuit and battery BYTEWIDETM RAM-like clock access BCD coded year, month, day, date, hours, minutes, and seconds Battery low flag (BOK) Frequency test output for real-time clock Automatic power-fail chip deselect and write protection Write protect voltages (VPFD = Power-fail deselect voltage): M48T35AY: VCC = 4.5 to 5.5V 4.2V VPFD 4.5V M48T35AV: VCC = 3.0 to 3.6V 2.7V VPFD 3.0V Self-contained battery and crystal in the CAPHATTM DIP package SOIC package provides direct connection for a SNAPHAT housing containing the battery and crystal SNAPHAT housing (battery and crystal) is replaceable Pin and function compatible with JEDEC standard 32Kbit x 8 SRAMs RoHS compliant Lead-free second level interconnect
PCDIP28 (PC) battery/crystal CAPHAT
28 1
SNAPHAT (SH) battery/crystal
28 1
SOH28 (MH)
November 2007
Rev 6
1/28
www.st.com 1
Contents
M48T35AV
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 3.2 3.3 3.4 3.5 3.6 Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 5 6 7 8
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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M48T35AV
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PCDIP28 28-pin plastic DIP, battery CAPHATTM, pack. mech. data . . . . . . . . . . . . . . . . 22 SOH28 28-lead plastic small outline, 4-socket battery SNAPHAT, pack. mech. data . . . 23 SH 4-pin SNAPHAT housing for 48mAh battery & crystal, pack. mech. data . . . . . . . . . 24 SH 4-pin SNAPHAT housing for 120mAh battery & crystal, pack. mech. data . . . . . . . . 25 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SNAPHAT battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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List of figures
M48T35AV
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Read mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write enable controlled, write mode AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip enable controlled, write mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Checking the BOK flag status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PCDIP28 28-pin plastic DIP, battery CAPHATTM, package outline . . . . . . . . . . . . . . . . . 22 SOH28 28-lead plastic small outline, 4-socket battery SNAPHAT, package outline . . . . 23 SH 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline . . . . . . . . . . 24 SH 4-pin SNAPHAT housing for 120mAh battery & crystal, pack. outline. . . . . . . . . . . . 25
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M48T35AV
Description
1
Description
The M48T35AV TIMEKEEPER RAM is a 32Kbit x 8 non-volatile static RAM and real-time clock. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory and real-time clock solution. The M48T35AV is a non-volatile pin and function equivalent to any JEDEC standard 32Kb x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. The 28-pin, 600mil DIP CAPHATTM houses the M48T35AV silicon with a quartz crystal and a long-life lithium button cell in a single package. The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in tape & reel form. For the 28-lead SOIC, the battery/crystal package (e.g. SNAPHAT) part numbers are listed in Table 17 on page 26. Figure 1. Logic diagram
VCC
15 A0-A14
8 DQ0-DQ7
W M48T35AV E G
VSS
AI02797B
5/28
Description Table 1.
A0-A14 DQ0-DQ7 E G W VCC VSS
M48T35AV Signal names
Address inputs Data inputs / outputs Chip enable Output enable WRITE enable Supply voltage Ground
Figure 2.
DIP connections
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 M48T35AV 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
AI02798B
Figure 3.
SOIC connections
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 M48T35AV 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
AI02799
6/28
M48T35AV Figure 4. Block diagram
Description
OSCILLATOR AND CLOCK CHAIN 32,768 Hz CRYSTAL POWER
8 x 8 BiPORT SRAM ARRAY
A0-A14
32,760 x 8 SRAM ARRAY LITHIUM CELL VOLTAGE SENSE AND SWITCHING CIRCUITRY VPFD
DQ0-DQ7
E W G
VCC
VSS
AI01623
7/28
Operation modes
M48T35AV
2
Operation modes
As Figure 4 on page 7 shows, the static memory array and the quartz controlled clock oscillator of the M48T35AV are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDETM clock information in the bytes with addresses 7FF8h-7FFFh. The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. Byte 7FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORTTM READ/WRITE memory cells. The M48T35AV includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T35AV also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 3V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below the Battery Back-up Switchover Voltage (VSO), the control circuitry connects the battery which maintains data and clock operation until valid power returns. Table 2.
Mode Deselect WRITE READ READ Deselect Deselect VSO to VPFD (min)(1) VSO(1) 3.0 to 3.6V
Operating modes
VCC E VIH VIL VIL VIL X X X X VIL VIH X X G X VIL VIH VIH X X W DQ0-DQ7 High Z DIN DOUT High Z High Z High Z Power Standby Active Active Active CMOS standby Battery back-up mode
1. See Table 11 on page 21 for details.
Note:
X = VIH or VIL; VSO = Battery back-up switchover voltage.
2.1
Read mode
The M48T35AV is in the READ Mode whenever W (WRITE Enable) is high and E (Chip Enable) is low. The unique address specified by the 15 address inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the Chip Enable Access time (tELQV) or Output Enable Access time (tGLQV).
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M48T35AV
Operation modes The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access. Figure 5. Read mode AC waveforms
tAVAV A0-A14 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 VALID
AI00925
VALID tAXQX tEHQZ
tGHQZ
Note:
WRITE Enable (W) = High. Table 3. Read mode AC characteristics
M48T35AV Symbol Parameter(1) Min tAVAV tAVQV tELQV tGLQV tELQX(2) tGLQX(2) tEHQZ(2) tGHQZ(2) tAXQX
2. CL = 5pF.
100 Max
Unit
READ cycle time Address valid to output valid Chip enable low to output valid Output enable low to output valid Chip enable low to output transition Output enable low to output transition Chip enable high to output Hi-Z Output enable high to output Hi-Z Address transition to output transition
100 100 100 50 10 5 50 40 10
ns ns ns ns ns ns ns ns ns
1. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 3.0 to 3.6V (except where noted).
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Operation modes
M48T35AV
2.2
Write mode
The M48T35AV is in the WRITE Mode whenever W and E are low. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; however, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls.
Figure 6.
Write enable controlled, write mode AC waveform
tAVAV A0-A14 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI00926
tWHAX
tWHQX
Figure 7.
Chip enable controlled, write mode AC waveforms
tAVAV A0-A14 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI00927
tELEH
tEHAX
10/28
M48T35AV Table 4.
Symbol tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ(2)(3) tAVWH tAVEH tWHQX(2)(3)
2. CL = 5pF.
Operation modes Write mode AC characteristics
Parameter(1) WRITE cycle time Address valid to WRITE enable low Address valid to chip enable low WRITE enable pulse width Chip enable low to chip enable high WRITE enable high to address transition Chip enable high to address transition Input valid to WRITE enable high Input valid to chip enable high WRITE enable high to input transition Chip enable high to input transition WRITE enable low to output Hi-Z Address valid to WRITE enable high Address valid to chip enable high WRITE enable high to output transition 80 80 10 M48T35AV Unit Min 100 0 0 80 80 10 10 50 50 5 5 50 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 3.0 to 3.6V (except where noted). 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Data retention mode
With valid VCC applied, the M48T35AV operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD (min) window (see Figure 13, Table 10, and Table 11 on page 21). All outputs become high impedance, and all inputs are treated as "don't care."
Note:
A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48T35AV may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery which preserves data and powers the clock. The internal button cell will maintain data in the M48T35AV for an accumulated period of at least 7 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min) plus trec (min). E should be kept high as VCC rises past VPFD (min) to prevent inadvertent WRITE cycles prior to processor stabilization. Normal RAM operation can resume trec after VCC exceeds VPFD (max).
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Operation modes
M48T35AV
Also, as VCC rises, the battery voltage is checked. If the voltage is less than approximately 2.5V, an internal Battery Not OK (BOK) flag will be set. The BOK flag can be checked after power up. If the BOK flag is set, the first WRITE attempted will be blocked. The flag is automatically cleared after the first WRITE, and normal RAM operation resumes. Figure 8 illustrates how a BOK check routine could be structured. For more information on Battery Storage Life refer to the Application Note AN1012. Figure 8. Checking the BOK flag status
POWER-UP
READ DATA AT ANY ADDRESS
WRITE DATA COMPLEMENT BACK TO SAME ADDRESS
READ DATA AT SAME ADDRESS AGAIN
IS DATA COMPLEMENT OF FIRST READ? (BATTERY OK) YES
NO (BATTERY LOW)
NOTIFY SYSTEM OF LOW BATTERY (DATA MAY BE CORRUPTED)
WRITE ORIGINAL DATA BACK TO SAME ADDRESS
CONTINUE
AI00607
12/28
M48T35AV
Clock operations
3
3.1
Clock operations
Reading the clock
Updates to the TIMEKEEPER registers (see Table 5) should be halted before clock data is read to prevent reading data in transition. The BiPORTTM TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ Bit, D6 in the Control Register 7FF8h. As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a '0.'
3.2
Setting the clock
Bit D7 of the Control Register 7FF8h is the WRITE Bit. Setting the WRITE Bit to a '1,' like the READ Bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24 hour BCD format (seeTable 5). Resetting the WRITE Bit to a '0' then transfers the values of all time registers 7FF9h-7FFFh to the actual TIMEKEEPER counters and allows normal operation to resume. The FT Bit and the bits marked as '0' in Table 5 must be written to '0' to allow for normal TIMEKEEPER and RAM operation. After the WRITE Bit is reset, the next clock update will occur within one second. See the Application Note AN923, "TIMEKEEPER Rolling Into the 21st Century" for information on Century Rollover.
3.3
Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP Bit is the MSB of the seconds register. Setting it to a '1' stops the oscillator. The M48T35AV is shipped from STMicroelectronics with the STOP Bit set to a '1.' When reset to a '0,' the M48T35AV oscillator starts within 1 second.
13/28
Clock operations Table 5.
Address D7
7FFFh 7FFEh 7FFDh 7FFCh 7FFBh 7FFAh 7FF9h 7FF8h 0 0 0 0 0 ST W R 0 0 FT 0
M48T35AV
Register map
Data D6 D5 D4 D3 D2
Year 0 10 M. 10 Date CEB CB 0 Hours Minutes Seconds Calibration Month Date Day
D1
D0
Function/range BCD format
Year Month Date Centur y/day Hours Minutes Seconds Control 00-99 01-12 01-31 00-01/01-07 00-23 00-59 00-59
10 Years
10 Hours 10 minutes 10 seconds S
Keys: S = Sign bit FT = Frequency test bit (must be set to '0' upon power for normal operation) R = Read bit W = Write bit ST = Stop bit 0 = Must be set to '0' CEB = Century enable bit CB = Century bit Note: When CEB is set to '1,' CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century (dependent upon the initial value set). When CEB is set to '0,' CB will not toggle. The WRITE Bit does not need to be set to write to CEB.
3.4
Calibrating the clock
The M48T35AV is driven by a quartz-controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25C, which equates to about 1.53 minutes per month. With the calibration bits properly set, the accuracy of each M48T35AV improves to better than +1/2 ppm at 25C. The oscillation rate of any crystal changes with temperature (see Figure 9 on page 16). Most clock chips compensate for crystal frequency and temperature shift error with cumbersome "trim" capacitors. The M48T35AV design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 10 on page 16. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration Byte occupies the five lower order bits (D4-D0) in the Control Register 7FF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is the Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a
14/28
M48T35AV
Clock operations binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or 2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz, each of the 31 increments in the Calibration Byte would represent +10.7 or 5.35 seconds per month which corresponds to a total range of +5.5 or 2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M48T35AV may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. The second approach is better suited to a manufacturing environment, and involves the use of some test equipment. When the Frequency Test (FT) Bit, the seventh-most significant bit in the Day Register is set to a '1,' and D7 of the Seconds Register is a '0' (Oscillator Running), DQ0 will toggle at 512 Hz during a READ of the Seconds Register. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a 10 (WR001010) to be loaded into the Calibration Byte for correction.
Note:
Setting or changing the Calibration Byte does not affect the Frequency Test output frequency. The FT Bit MUST be reset to '0' for normal clock operations to resume. The FT Bit is automatically Reset on power-down. For more information on calibration, see Application Note AN934, "TIMEKEEPER Calibration."
3.5
Century bit
Bit D5 and D4 of Clock Register 7FFCh contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle.
Note:
The WRITE Bit must be set in order to write to the CENTURY Bit.
15/28
Clock operations Figure 9. Crystal accuracy across temperature
ppm 20
M48T35AV
0
-20
-40 F = -0.038 ppm (T - T )2 10% 0 F C2 T0 = 25 C -80
-60
-100 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 C
AI02124
Figure 10. Clock calibration
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
16/28
M48T35AV
Clock operations
3.6
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A bypass capacitor value of 0.1F (as shown in Figure 11) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 11. Supply voltage protection
VCC VCC
0.1F
DEVICE
VSS
AI02169
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Maximum rating
M48T35AV
4
Maximum rating
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 6.
Symbol TA TSTG TSLD(1)(2) VIO VCC IO PD
Absolute maximum ratings
Parameter Ambient operating temperature Storage temperature (VCC off, oscillator off) Lead solder temperature for 10 seconds Input or output voltages Supply voltage Output current Power dissipation Value 0 to 70 40 to 85 260 0.3 to 4.6 0.3 to 4.6 20 1 Unit C C C V V mA W
1. For DIP package: Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds). 2. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds).
Caution: Caution:
Negative undershoots below 0.3V are not allowed on any pin while in the Battery Back-up mode. Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
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M48T35AV
DC and AC parameters
5
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 7. Operating and AC measurement conditions
Parameter Supply voltage (VCC) Ambient operating temperature (TA) Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages M48T35AV 3.0 to 3.6 0 to 70 50 5 0 to 3 1.5 Unit V C pF ns V V
Note:
Output Hi-Z is defined as the point where data is no longer driven. Figure 12. AC measurement load circuit
DEVICE UNDER TEST
CL = 50pF (or 5pF)
1.75V
CL includes JIG capacitance
AI02586
Table 8.
Symbol CIN COUT(3)
Capacitance
Parameter(1)(2) Input capacitance Output capacitance Min Max 10 10 Unit pF pF
1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs deselected.
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DC and AC parameters Table 9.
Symbol ILI ILO(2) ICC ICC1 ICC2 VIL
(3)
M48T35AV
DC characteristics
Parameter Input leakage current Output leakage current Supply current Supply current (standby) TTL Supply current (standby) CMOS Input low voltage Input high voltage Output low voltage Output high voltage IOL = 2.1mA IOH = 1mA 2.4 Test condition(1) 0V VIN VCC 0V VOUT VCC Outputs open E = VIH E = VCC 0.2V 0.3 2.2 M48T35AV Unit Min Max 1 1 30 2 2 0.8 VCC + 0.3 0.4 A A mA mA mA V V V V
VIH VOL VOH
1. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 3.0 to 3.6V (except where noted). 2. Outputs deselected. 3. Negative spikes of 1V allowed for up to 10ns once per cycle.
Figure 13. Power down/up mode AC waveforms
VCC VPFD (max) VPFD (min) VSO tF tFB tPD INPUTS
RECOGNIZED
tR tRB tDR DON'T CARE trec
RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI01168C
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M48T35AV Table 10.
Symbol tPD tF(2) tFB(3) tR tRB t rec
DC and AC parameters Power down/up AC characteristics
Parameter(1) E or W at VIH before power down VPFD (max) to VPFD (min) VCC fall time VPFD (min) to VSS VCC fall time VPFD (min) to VPFD (max) VCC rise time VSS to VPFD (min) VCC Rise Time VPFD (max) to inputs recognized Min 0 300 150 10 1 40 200 Max Unit s s s s s ms
1. Valid for ambient operating temperature: TA = 0 to 70C or 40 to 85C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 11.
Symbol VPFD VSO tDR(3)
Power down/up trip points DC characteristics
Parameter(1)(2) Power-fail deselect voltage Battery back-up switchover voltage Expected data retention time 10(4) Min 2.7 Typ 2.9 VPFD 100mV Max 3.0 Unit V V YEARS
1. Valid for ambient operating temperature: TA = 0 to 70C or 40 to 85C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. All voltages referenced to VSS. 3. At 25C, VCC = 0V. 4. CAPHAT and M4T32-BR12SH1 SNAPHAT only, M4T28-BR12SH1 SNAPHAT top tDR = 7 years (typ).
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Package mechanical data
M48T35AV
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 14. PCDIP28 28-pin plastic DIP, battery CAPHATTM, package outline
A2
A
A1 B1 B e3 D
N
L eA
C
e1
E
1 PCDIP
Note:
Drawing is not to scale. Table 12.
Symb Typ A A1 A2 B B1 C D E e1 e3 eA L N Min 8.89 0.38 8.38 0.38 1.14 0.20 39.37 17.83 2.29 29.72 15.24 3.05 28 Max 9.65 0.76 8.89 0.53 1.78 0.31 39.88 18.34 2.79 36.32 16.00 3.81 Typ Min 0.350 0.015 0.330 0.015 0.045 0.008 1.550 0.702 0.090 1.170 0.600 0.120 28 Max 0.380 0.030 0.350 0.021 0.070 0.012 1.570 0.722 0.110 1.430 0.630 0.150
PCDIP28 28-pin plastic DIP, battery CAPHATTM, pack. mech. data
mm inches
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M48T35AV
Package mechanical data
Figure 15. SOH28 28-lead plastic small outline, 4-socket battery SNAPHAT, package outline
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH-A
Note: Table 13.
Symb
Drawing is not to scale. SOH28 28-lead plastic small outline, 4-socket battery SNAPHAT, pack. mech. data
mm Typ A A1 A2 B C D E e eB H L a N CP 1.27 0.05 2.34 0.36 0.15 17.71 8.23 3.20 11.51 0.41 0 28 0.10 Mi n Max 3.05 0.36 2.69 0.51 0.32 18.49 8.89 3.61 12.70 1.27 8 0.050 0.002 0.092 0.014 0.006 0.697 0.324 0.126 0.453 0.016 0 28 0.004 Typ inches Mi n Max 0.120 0.014 0.106 0.020 0.012 0.728 0.350 0.142 0.500 0.050 8
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Package mechanical data
M48T35AV
Figure 16. SH 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Note:
Drawing is not to scale. Table 14.
Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 14.22 15.55 3.20 2.03 6.73 6.48 Mi n Max 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 0.018 0.835 0.560 0.612 0.126 0.080 0.265 0.255 Typ Min Max 0.385 0.285 0.275 0.015 0.022 0.860 0.590 0.628 0.142 0.090
SH 4-pin SNAPHAT housing for 48mAh battery & crystal, pack. mech. data
mm inches
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M48T35AV
Package mechanical data
Figure 17. SH 4-pin SNAPHAT housing for 120mAh battery & crystal, pack. outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Note: Table 15.
Symb
Drawing is not to scale. SH 4-pin SNAPHAT housing for 120mAh battery & crystal, pack. mech. data
mm Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 17.27 15.55 3.20 2.03 8.00 7.24 Min Max 10.54 8.51 8.00 0.38 0.56 21.84 18.03 15.95 3.61 2.29 0.018 0.835 0.680 0.612 0.126 0.080 0.315 0.285 Typ inches Min Max 0.415 0.335 0.315 0.015 0.022 0.860 0.710 0.628 0.142 0.090
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Part numbering
M48T35AV
7
Part numbering
Table 16.
Example:
Ordering information scheme
M48T 35AV 10 MH 1 E
Device type M48T Supply voltage and write protect voltage 35AV = VCC = 3.0 to 3.6V; VPFD = 2.7 to 3.0V Speed 10 = 100ns (35AV) Package PC = PCDIP28 MH(1) = SOH28 Temperature range 1 = 0 to 70C Shipping method For SOH28: E = Lead-free package (ECOPACK), tubes F = Lead-free package (ECOPACK), tape & reel For PCDIP28: blank = tubes
1. The SOIC package (SOH28) requires the SNAPHAT battery package which is ordered separately under the part number "M4TXX-BR12SHx" in plastic tubes (see Table 17).
Caution:
Do not place the SNAPHAT battery package "M4TXX-BR12SH" in conductive foam as it will drain the lithium button-cell battery. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. Table 17. SNAPHAT battery table
Description Lithium battery (48mAh) SNAPHAT Lithium battery (120mAh) SNAPHAT Lithium battery (120mAh) SNAPHAT, -40 to +85C crystal Package SH SH SH
Part number M4T28-BR12SH1 M4T32-BR12SH1 M4T32-BR12SH6
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M48T35AV
Revision history
8
Revision history
Table 18.
Date Nov-1999 21-Apr-2000 29-May-2000 20-Jul-2001 20-May-2002 31-Mar-2003 01-Apr-2004 21-Nov-2007
Document revision history
Revision 1.0 2.0 2.1 3.0 3.1 4.0 5.0 6 First Issue From Preliminary Data to Data Sheet tFB change (Table 10) Reformatted; temp./voltage info. added to tables (Table 8, 9, 3, 4, 10, 11); add Century Bit text Modify reflow time and temperature footnotes (Table 6) v2.2 template applied; data retention condition updated (Table 11) Reformatted; updated with lead-free package information (Table 6, 16) Reformatted document; added lead-free second level interconnect information to cover page and Section 6: Package mechanical data, updated Table 16, 17; removed M48T35AY and all references. Changes
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M48T35AV
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