ST7262
LOW SPEED USB 8-BIT MCU WITH 3 ENDPOINTS, FLASH OR ROM MEMORY, LVD, WDG, 10-BIT ADC, 2 TIMERS, SCI, SPI
Memories 8K or 16K Program memory (ROM or Dual voltage FLASH) with read-write protection In-Application and In-Circuit Programming for FLASH versions 384 to 768 bytes RAM (128-byte stack) Clock, Reset and Supply Management Enhanced Reset System (Power On Reset) Low Voltage Detector (LVD) Clock-out capability 6 or 12 MHz Oscillator (8, 4, 2, 1 MHz internal frequencies) 3 Power saving modes USB (Universal Serial Bus) Interface DMA for low speed applications compliant with USB specification (version 2.0): Integrated 3.3V voltage regulator and transceivers Suspend and Resume operations 3 Endpoints Up to 31 I/O Ports Up to 31 multifunctional bidirectional I/O lines Up to 12 External interrupts (3 vectors) 13 alternate function lines 8 high sink outputs (8 mA@0.4 V/20 mA@1.3 V) 2 true open drain pins (N buffer 8 mA@0.4 V) 3 Timers Configurable watchdog timer (8 to 500 ms timeout) 8-bit Auto Reload Timer (ART) with 2 Input Captures, 2 PWM outputs and External Clock 8-bit Time Base Unit (TBU) for generating periodic interrupts cascadable with ART
SO20
PDIP20
SO34 shrink
PDIP32 shrink
LQFP44
PDIP42 shrink
Analog Peripheral 10-bit A/D Converter with up to 8 input pins. 2 Communications Interfaces Asynchronous Serial Communication interface Synchronous Serial Peripheral Interface Instruction Set 8-bit data manipulation 63 basic instructions 17 main addressing modes 8 x 8 unsigned multiply instruction True bit manipulation Nested interrupts Development Tools Full hardware/software development package
ST72622L2 ST72621L4 ST72621J4
Device Summary
Features Program memory - bytes RAM (stack) - bytes Peripherals Serial I/O I/Os Operating Supply Operating Temperature Packages ST72623F2 ST72621K4 8K 16K 8K 16K 16K 384 (128) 768 (128) 384 (128) 768 (128) 768 (128) USB, Watchdog, Low Voltage Detector, 8-bit Auto-Reload timer, Timebase unit, A/D Converter SPI + SCI SPI SPI + SCI 11 21 23 31 4.0V to 5.5V (Low voltage 3.0V to 5.5V ROM versions available) 0C to +70C PDIP20/SO20 PDIP32 SO34 PDIP42/LQFP44
Rev. 4.0
March 2006 1/139
1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 PCB LAYOUT RECOMMENDATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.8 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 CLOCKS AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.2 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.3 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.3 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.2 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.3 TIMEBASE UNIT (TBU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 139 10.6 USB INTERFACE (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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10.7 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.10TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 12.11COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 117 12.1210-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 14 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 128 14.1 OPTION BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . 128 14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 15 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 15.1 A/ D CONVERTER ACCURACY FOR FIRST CONVERSION . . . . . . . . . . . . . . . . . . . . 135 15.2 A/D CONVERTER CONVERSION SPEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 15.3 SCI WRONG BREAK DURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 15.4 UNEXPECTED RESET FETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 15.5 HALT MODE POWER CONSUMPTION WITH ADC ON . . . . . . . . . . . . . . . . . . . . . . . . . 136 16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
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ST7262
1 INTRODUCTION
The ST7262 and ST72F62 devices are members of the ST7 microcontroller family designed for USB applic ations. All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set. The ST7262 devices are ROM versions. The ST72F62 versions feature dual-voltage FLASH memory with FLASH Programming capability . Under software control, all devices can be placed in WAIT, SLOW, or HALT mode, reducing power Figure 1. General Block Diagram consumption when the application is in idle or standby state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.
OSCIN OSCOUT
Internal CLOCK
OSCILLATOR
LVD
10-BIT ADC PORT A SCI PORT B
ADDRESS AND DATA BUS
PA7:0 (8 bits)
VDD VSS RESET
POWER SUPPLY CONTROL 8-BIT CORE ALU USB DMA PROGRAM MEMORY (8 or 16K Bytes) RAM (384, or 768 Bytes)
PB7:0 (8 bits)
PWM ART TIME BASE UNIT USBDP USBDM USBVCC PORT C SPI PORT D WATCHDOG PD6:0 (7 bits) PC7:0 (8 bits)
VDDA VSSA
USB SIE
VPP
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ST7262
2 PIN DESCRIPTION
Figure 2. 44-pin LQFP and 42-Pin SDIP Package Pinouts
Reserved* VDDA USBVCC USBDP USBDM VSSA RESET PA0 / AIN0 / IT1 / USBOE PA1 / AIN1 / IT2 PA2 / AIN2 / IT3 PA3 / AIN3 / IT4 PA4 / AIN4 PA5 / AIN5 PA6 / AIN6 PA7 / AIN7 PB0 (HS) / MCO PB1 (HS) / RDI
PD2 PD3 PD4 VPP PD1 PD0 PC7 MOSI / PC6 IT12 / MISO / PC5 IT11 / SS / PC4 IT10 / SCK / PC3 IT9 / PC2 OSCIN OSCOUT
44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 3 31 4 30 5 29 6 28 7 27 8 26 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 N.C. ICCDATA /IT7 / PWM0 / PB6 (HS) ICCCLK / IT6 / ARTIC2 / PB5 (HS) IT5 / ARTIC1 / PB4 (HS) ARTCLK / PB3 (HS) TDO / PB2 (HS) VSS VDD PC1 PC0 IT8 / PWM1 / PB7
PD5 PD6
* Pin 39 of the LQFP44 package must be left unconnected.
PD6 PD5 PD4 PD3 PD2 V PP PD1 PD0 PC7 MOSI / PC6 IT12 / MISO / PC5 IT11 / SS / PC4 IT10 / SCK / PC3 IT9 / PC2 OSCIN OSCOUT VSS VDD PC1 PC0 IT8 / PWM1 / PB7 (HS)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
VDDA USBVCC USBDP USBDM VSSA RESET PA0 / AIN0 / IT1 / USBOE PA1 / AIN1 / IT2 PA2 / AIN2 / IT3 PA3 / AIN3 / IT4 PA4 / AIN4 PA5 / AIN5 PA6 / AIN6 PA7 / AIN7 PB0 (HS) / MCO PB1 (HS) / RDI PB2 (HS) / TDO PB3 (HS) / ARTCLK PB4 (HS) / ARTIC1 / IT5 PB5 (HS) / ARTIC2 / IT6 / ICCCLK PB6 (HS) / PWM0 / IT7 / ICCDATA
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PIN DESCRIPTION (Cont'd) Figure 3. 34-Pin SO and 32-Pin SDIP Package Pinouts
IT10 / SCK / PC3 IT9 / PC2 OSCIN OS COUT VSS VDD P C1 IT8 / PWM1 / PB7 (HS) ICCDATA / IT7 / PWM0 / PB6 (HS) ICCCLK / IT6 /ARTIC2 / PB5 (HS) IT5 / ARTIC1 / PB4 (HS) ARTCLK / PB3 (HS) TDO / PB2 (HS) RDI / PB1 (HS) MCO / PB0 (HS) AIN7 / PA7 AIN6 / PA6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18
PC4 / SS / INT11 PC5 / MISO / IT12 PC6 / MOSI PC7 RES ET VP P VDDA USB VCC USB DP USB DM VSSA PA0 / AIN0 / IT1 / USBOE PA1 / AIN1 / IT2 PA2 / AIN2 / IT3 PA3 / AIN3 / IT4 PA4 / AIN4 PA5 / AIN5
IT10 / SCK / PC3 IT9 / PC2 OSCIN OSCO UT VSS VDD IT8 / PWM1 / PB7 (HS) ICCDATA / IT7 / PWM0 / PB6 (HS) ICCCLK / IT6 / ARTIC2 / PB5 (HS) IT5 / ARTIC1 / PB4 (HS) ARTCLK / PB3 (HS) TDO / PB2 (HS) RDI / PB1 (HS) MCO / PB0 (HS) AIN7 / PA7 AIN6 / PA6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
PC4 / SS / INT11 PC5 / MISO / IT12 PC6 / MOSI RESET VP P VDD A US BVCC US BDP US BDM VS S A PA0 / AIN0 / IT1 / USBOE PA1 / AIN1 / IT2 PA2 / AIN2 / IT3 PA3 / AIN3 / IT4 PA4 / AIN4 PA5 / AIN5
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Figure 4. 20-pin SO20 Package Pinout
IT3 / AIN2 / PA2 IT2 / AIN1 / PA1 USBOE/ IT1 / AIN0/ PA0 VSS USBDM USB DP USBV CC VDD VPP RESET
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
PB0 (HS) / MCO PB1 (HS) PB2 (HS) PB3 (HS) / ARTCLK PB4 (HS) / ARTIC1 / IT5 PB5 (HS) / ARTIC2 / IT6 / ICCCLK PB6 (HS) / PWM0 / IT7/ ICCDATA PB7 (HS) / PWM1 / IT8 OSCO UT OSCIN
Figure 5. 20-pin DIP20 Package Pinout
IT5 / ARTIC1 / PB4 (HS) ARTCLK / PB3 (HS) PB2 (HS) PB1 (HS) MCO / PB0 (HS) IT3 / AIN2 / PA2 IT2 / AIN1/ PA1 USBOE / IT1 / AIN0 / PA0 VSS US BDM
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
PB5 (HS) / ARTIC2 / IT6 / ICCCLK PB6 (HS) / PWM0 / IT7/ICCDATA PB7 (HS) / PWM1 / IT8 OSCO UT OSCIN RESET VP P VDD USBVCC USBDP
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PIN DESCRIPTION (Cont'd) Legend / Abbreviations: Type: I = Input, O = Output, S = Supply Input level: A = Dedicated analog input Input level: C = CMOS 0.3VDD/0.7VDD, CT= CMOS 0.3VDD/0.7VDD with input trigger Output level: HS = High Sink (on N-buffer only) Port configuration capabilities: Input:float = floating, wpu = weak pull-up, int = interrupt (\ =falling edge, / =rising edge), ana = analog Output: OD = open drain, T = true open drain (N buffer 8mA@0.4 V), PP = push-pull Table 1. Device Pin Description
Pin n LQFP44 Type DIP42 DIP32 DIP20 SO34 SO20 Pin Name Level O u tput Input Port / Control Input float w pu ana int Main Output Function Alternate Function (after reset) OD PP x x x x x x FLASH programming voltage (12V), must be tied low in user mode. Port D1 Port D0 Port C7 Port C6 Port C5 SPI Master Out / Slave In 1) SPI Master In / Slave Out 1) / Interrupt 12 input SPI Slave Select (active low) 1)/ Interrupt 11 input SPI Serial Clock 1)/ Interrupt 10 input Interrupt 9 input
1 2 3 4
6 29 28 9 14 VP P 7 8 PD1 PD0 PC7 PC 6 / M O S I PC5/MISO/IT12
S I/O CT I/O CT I/O CT I/O CT I/O CT
x x x x x x
9 31
5 10 32 30 6 11 33 31
7 12 34 32 8 13 1 1 2 -
-
-
P C 4 / S S /I T11 PC3/SCK/IT10
I/O CT I/O CT I/O CT
x x x
x x x
x x x
Port C4 Port C3 Port C2
9 14 2 10 15 3 11 16 4 12 17 5 13 18 6 14 19 7 15 20 -
-
PC2/IT9
3 11 16 OSCIN 4 1 2 1 7 O S C OU T 5 6 4 9 VS S S S I/O CT I/O CT I/O CT HS x x x \ T T x
These pins are used connect an external clock source to the onchip main oscillator. Digital Ground Voltage Digital Main Power Supply Voltage Port C1 Port C0 Port B7 ART PWM output 1/ Interrupt 8 input
8 1 3 VDD PC1 PC0
16 21 8 17 -
PB7/PWM1/IT8/ 7 1 3 1 8 RX_SE Z /DATAOU T/DA9 N.C.
Not Connected
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Pin n LQFP44 Type DIP42 DIP32 DIP20 SO34 SO20 Pin Name
Level O u tput Input
Port / Control Input float wpu ana int
OD
PP
Main Output Function Alternate Function (after reset) ART PWM output 0/ Interrupt 7 input/InCircuit Communication Data ART Input Capture 2/ Interrupt 6 input/ In-Circuit Communication Clock ART Input Capture 1/Interrupt 5 input ART Clock input SCI Transmit Data Output 1) SCI Receive Data Input 1) CPU clock output ADC Analog Input 7 ADC Analog Input 6 ADC Analog Input 5 ADC Analog Input 4
18 22 9
PB6/PWM0/IT7/ 8 14 19 ICCDATA
I/O CT HS
x
\
x
Port B6
19 23 10 9 15 20
PB5/ARTIC2/IT6/ ICCCLK
I/O CT HS
x
/
x
Port B5
20 24 11 10 16 1 PB4/ARTIC 1/IT5 21 25 12 11 17 2 PB3/ARTCLK 22 26 13 12 18 3 PB2/TDO 23 27 14 13 19 4 PB1/RDI 24 28 15 14 20 5 PB0/MCO 25 29 16 15 26 30 17 16 27 31 18 17 28 32 19 18 29 33 20 19 PA7/AIN7 PA6/AIN6 PA5/AIN5 PA4/AIN4 PA3/AIN3/IT4
I/O CT HS I/O CT HS I/O C T HS I/O C T HS I/O C T HS I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT I/O S I/O I/O S S C
x x x x x x x x x x x x x
/
x x x x x x x x x x x x x x x x x
Port B4 Port B3 Port B2 Port B1 Port B0 Port A7 Port A6 Port A5 Port A4 Port A3
\ \ \ \
x x x x
30 34 21 20 1 31 35 22 21 2 32 36 23 22 3
6 PA2/AIN2/IT3 7 PA1/AIN1/IT2 8 PA0/ AIN0/ IT1/ USBO E
33 37 30 29 10 15 RESE T 34 38 24 23 VSSA
ADC Analog Input 3/ Interrupt 4 input ADC Analog Input 2/ Port A2 Interrupt 3 input ADC Analog Input 1/ Port A1 Interrupt 2 input ADC Analog Input 0/ Port A0 Interrupt 1 input/ USB Output Enable Top priority non maskable interrupt (active low) Analog Ground Voltage, must be connected externally to VSS. USB bidirectional data (data -) USB bidirectional data (data +) USB power supply 3.3V output Analog Power Supply Voltage, must be connected externally to VDD. Must be left unconnected.
35 39 25 24 5 10 USBD M 36 40 26 25 6 11 USBD P 37 41 27 26 7 12 USBV CC 38 42 28 27 39 VDDA Reserved PD6 PD5 PD4
40 1 41 2 42 3
I/O C T I/O C T I/O C T
x x x
x x x
Port D6 Port D5 Port D4
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Pin n LQFP44 Type DIP42 DIP32 DIP20 SO34 SO20 Pin Name
Level O u tput Input
Port / Control Input float wpu ana int
OD
43 4 44 5
-
-
-
-
PD3 PD2
I/O C T I/O C T
x x
PP x x
Main Output Function Alternate Function (after reset) Port D3 Port D2
Note 1: Peripheral not present on all devices. Refer to "Device Summary" on page 1. 2.1 PCB LAYOUT RECOMMENDATION In the case of DIP20 devices the user should layout the PCB so that the DIP20 ST7262 device and the USB connector are centered on the same axis ensuring that the D- and D+ lines are of equal length. Refer to Figure 6 Figure 6. Recommended PCB Layout for USB Interface with DIP20 package
1 2 3 4 20 19 18 17
6 7 8 9
ST7262
5
16 15 14 13 12 11
U SBVCC U SBDP
USB DM
10
1.5KOhm pull-up resistor Ground USB Connector Ground
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3 REGISTER & MEMORY MAP
As shown in the Figure 7, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 64 bytes of register locations, 768 bytes of RAM and up to 16 Kbytes of user program memory. The RAM space includes up to 128 bytes for the stack from 0100h to 017Fh. The highest address bytes contain the user reset and interrupt vectors. Figure 7. Memory Map
0040h 0000h 003Fh 0040h
IMPORTANT: Memory locations marked as "Reserved" must never be accessed. Accessing a reseved area can have unpredictable effects on the device.
HW Registers (see Table 2) 384 Bytes RAM
00FFh
Short Addressing RAM (zero page) 192 Bytes 16-bit Addressing RAM or Stack (128 Bytes) 16-bit Addressing RAM 64 Bytes
017Fh
768 Bytes RAM
033Fh 0340h
01BFh
Reserved
BFFFh C000h
0040h
Program Memory 16 KBytes
E000h
00FFh
Short Addressing RAM (zero page) 192 Bytes 16-bit Addressing RAM or Stack (128 Bytes) 16-bit Addressing RAM 448 Bytes
017Fh
8 KBytes
FFDFh FFE0h 033Fh
Interrupt & Reset Vectors (see Table 6)
FFFFh
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Table 2. Hardware Register Map
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000A h 000B h 000C h 000D h 000E h 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001A h 001B h 001C h 001Dh 001E h 001Fh 0020h 0021h 0022h 0023h 0024h SPI SPIDR SPICR SPICSR PW MDCR1 PW MDCR0 PW MCR ARTCS R ARTCA R ARTAR R ARTICCSR ARTICR1 ARTICR2 SCIERPR SCIETPR SCI SCISR SCIDR SCIBRR SCICR1 SCICR2 AD C W DG Block Register Label PADR PADD R PBDR PBDD R PCDR PCDD R PDDR PDDD R ITRFRE1 MISC Register Name Port A Data Register Port A Data Direction Register Port B Data Register Port B Data Direction Register Port C Data Register Port C Data Direction Register Port D Data Register Port D Data Direction Register Interrupt Register 1 Miscellaneous Register R eset Status 00h1 ) 00h 00h1 ) 00h 00h1 ) 00h 00h1 ) 00h 00h 00h 00h 00h 00h 7Fh R e ma r k s R/W2) R/W2) R/W2) R/W2) R/W2) R/W2) R/W2) R/W2) R/W R/W Read Only Read Only R/W R/W
Port A Port B Port C Port D
ADCDRMSB ADC Data Register (bit 9:2) ADCDRLSB ADC Data Register (bit 1:0) ADCC SR ADC Control Status Register W DGCR Watchdog Control Register Reserved Area (3 Bytes) SPI Data I/O Register SPI Control Register SPI Control Status Register PWM AR Timer Duty Cycle Register 1 PWM AR Timer Duty Cycle Register 0 PWM AR Timer Control Register Auto-Reload Timer Control/Status Register Auto-Reload Timer Counter Access Register Auto-Reload Timer Auto-Reload Register ART Input Capture Control/Status Register ART Input Capture Register 1 ART Input Capture Register 2 SCI Extended Receive Prescaler register SCI Extended Transmit Prescaler Register Reserved Area SCI Status register SCI Data register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2
xxh 0xh 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h -C0h xxh 00h x000 0000b 00h
R/W R/W Read Only R/W R/W R/W R/W R/W R/W R/W Read Only Read Only R/W R/W Read Only R/W R/W R/W R/W
PWM ART
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Address 0025h 0026h 0027h 0028h 0029h 002A h 002B h 002C h 002D h 002E h 002Fh 0030h 0031h 0032h to 0035h 0036h 0037h 0038h 0039h 003A h to 003Fh
Block
Register Label USBP IDR USBD MAR USBIDR USBISTR USBIMR USBC TLR USBD ADDR USBE P0RA USBE P0RB USBE P1RA USBE P1RB USBE P2RA USBE P2RB
Register Name USB PID Register USB DMA Address register USB Interrupt/DMA Register USB Interrupt Status Register USB Interrupt Mask Register USB Control Register USB Device Address Register USB Endpoint 0 Register A USB Endpoint 0 Register B USB Endpoint 1 Register A USB Endpoint 1 Register B USB Endpoint 2 Register A USB Endpoint 2 Register B Reserved Area (4 Bytes)
R eset Status x0h xxh x0h 00h 00h 06h 00h 0000 xxxxb 80h 0000 xxxxb 0000 xxxxb 0000 xxxxb 0000 xxxxb
R e ma r k s Read Only R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
US B
TBU FLAS H
TBUCV TBUCS R FCSR ITRFRE2
TBU Counter Value Register TBU Control/Status Register Flash Control/Status Register Interrupt Register 2 Reserved Area (6 Bytes)
00h 00h 00h 00h
R/W R/W R/W R/W
Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always be kept at their reset value.
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4 FLASH PROGRAM MEMORY
4.1 Introduction The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external VPP supply. The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming). The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 Main Features
Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (see Table 3). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required. The first two sectors have a fixed size of 4 Kbytes (see Figure 8). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000hFFFFh). Table 3. Sectors available in Flash devices
Flash Size (bytes) 4K 8K > 8K Available Sectors Sector 0 Sectors 0,1 Sectors 0,1, 2
Three Flash programming modes: Insertion in a programming tool. In this mode, all sectors including option bytes can be programmed or erased. ICP (In-Circuit Programming). In this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board. IAP (In-Application Programming) In this mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board and while the application is running. ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM Read-out protection Register Access Security System (RASS) to prevent accidental programming or erasing
4.3 Structure The Flash memory is organised in sectors and can be used for both code and data storage. Figure 8. Memory Map and Sector Address
4K
1000h 3FFFh 7FFFh 9FFFh BFFFh D7FFh DFFFh EFFFh FFFFh
4.3.1 Read-out Protection Read-out protection, when selected, provides a protection against Program Memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. In Flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased and the device can be reprogrammed. Read-out protection selection depends on the device type: In Flash devices it is enabled and removed through the FMP_R bit in the option byte. In ROM devices it is enabled by mask option specified in the Option List.
8K
10K
16K
24K
32K
48K
60K
FLASH MEMORY SIZE
SECTOR 2 2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes 52 Kbytes 4 Kbytes 4 Kbytes SECTOR 1 SECTOR 0
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FLASH PROGRAM MEMORY (Cont'd) 4.4 ICC Interface ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see Figure 9). These pins are: RESET: device reset VSS: device power supply ground Figure 9. Typical ICC Interface
PROGRAMMING TOOL ICC CONNECTOR ICC Cable APPLICATION BOARD (See Note 3) OPTIONAL (See Note 4) ICC CONNECTOR HE10 CONNECTOR TYPE 9 10 7 8 5 6 3 4 1 2 APPLICATION RESET SOURCE See Note 2 10k APPLICATION POWER SUPPLY CL2 CL1 See Note 1 APPLICATION I/O
ICCCLK: ICC output serial clock pin ICCDATA: ICC input/output serial data pin ICCSEL/VPP: programming voltage OSC1(or OSCIN): main clock input for external source (optional) VDD: application board power supply (see Figure 9, Note 3)
ST7
Notes: 1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values. 2. During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset man-
agement IC with open drain output and pull-up resistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session. 3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual. 4. Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case.
ICCSEL/VPP
ICCDATA
RESET
ICCCLK
OSC2
OSC1
VDD
VSS
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FLASH PROGRAM MEMORY (Cont'd) 4.5 ICP (In-Circuit Programming) To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool. Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 9). For more details on the pin locations, refer to the device pinout description. 4.6 IAP (In-Application Programming) This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool). This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). For example, it is possible to download code from the SPI, SCI or other type of serial interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/ erase protected to allow recovery in case errors occur during the programming operation. 4.7 Related Documentation For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual. 4.8 Register Description FLASH CONTROL/STATUS REGISTER (FCSR) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 0 0 0 0 0
This register is reserved for use by Programming Tool software. It controls the Flash programming and erasing operations.
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5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES
5.3 CPU REGISTERS The 6 CPU registers shown in Figure 10 are not present in the memory mapping and are accessed by specific instructions. Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures. Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
Enable executing 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) Two 8-bit index registers 16-bit stack pointer Low power HALT and WAIT modes Priority maskable hardware interrupts Non-maskable software/hardware interrupts
Figure 10. CPU Registers
7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 0 CONDITION CODE REGISTER 1 1 I1 H I0 N Z C RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value 0 Y INDEX REGISTER 0 X INDEX REGISTER 0 ACCUMULATOR
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CENTRAL PROCESSING UNIT (Cont'd) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx
7
1 1 I1 H I0 N Z
0 C
This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test inst ructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions. Interrupt Management Bits Bit 5,3 = I1, I0 Interrupt The combination of the I1 and I0 bits gives the current interrupt software priority.
Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) I1 1 0 0 1 I0 0 1 0 1
The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Arithmetic Management Bits Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It's a copy of the result 7th bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions. Bit 1 = Z Zero.
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See the interrupt management chapter for more details.
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CPU REGISTERS (Cont'd) STACK POINTER (SP) Read/Write Reset Value: 017Fh
15 0 7 1 SP6 SP5 S P4 SP3 SP2 SP 1 0 0 0 0 0 0 8 1 0 SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 11). Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP6 to SP0 bits are set) which is the stack higher address. The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Figure 11. Stack Manipulation Example
CALL Subroutine @ 0100h Interrupt Event P USH Y
Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 11. When an interrupt is received, the SP is decremented and the context is pushed on the stack. On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area.
PO P Y
IRET
RET or RSP
SP SP CC A X PC H SP PCH @ 017Fh PCL P CL PCH PCL Y CC A X PCH PCL PCH PC L SP CC A X PCH PCL PCH PCL SP PCH PCL SP
Stack Higher Address = 017Fh Stack Lower Address = 0100h
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6 CLOCKS AND RESET
6.1 CLOCK SYSTEM 6.1.1 General Description The MCU accepts either a Crystal or Ceramic resonator, or an external clock signal to drive the internal oscillator. The internal clock (fCPU) is derived from the external oscillator frequency (fOSC), by dividing by 3 and multiplying by 2. By setting the OSC12/6 bit in the option byte, a 12 MHz external clock can be used giving an internal frequency of 8 MHz while maintaining a 6 MHz clock for USB (refer to Figure 14). The internal clock signal (fCPU) consists of a square wave with a duty cycle of 50%. It is further divided by 1, 2, 4 or 8 depending on the Slow Mode Selection bits in the Miscellaneous register (SMS[1:0]) The internal oscillator is designed to operate with an AT-cut parallel resonant quartz or ceramic resonator in the frequency range specified for fosc. The circuit shown in Figure 13 is recommended when using a crystal, and Table 4 lists the recommended capacitors. The crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilization time. Table 4. Recommended Values for 12 MHz Crystal Resonator
RSMAX COSCIN C OSCOUT 20 56pF 56pF 1-10 M 25 47pF 47pF 1-10 M 70 22pF 22pF 1-10 M
OSCIN OSCOUT
6.1.2 External Clock input An external clock may be applied to the OSCIN input with the OSCOUT pin not connected, as shown on Figure 12. The tOXOV specifications does not apply when using an external clock input. The equivalent specification of the external clock source should be used instead of tOXOV (see Electrical Characteristics). 6.1.3 Clock Output Pin (MCO) The internal clock (fCPU) can be output on Port B0 by setting the MCO bit in the Miscellaneous register.
Figure 12. External Clock Source Connections
OSCIN
OSCOUT NC
EXTERNAL CLOCK
Figure 13. Crystal/Ceramic Resonator
RP
Note: RSMAX is the equivalent serial resistor of the crystal (see crystal specification). Note: When a crystal is used, and to not overstress the crystal, ST recommends to add a serial resistor on the OSCOUT pin to limit the drive level in accordance with the crystal manufacturer's specification. Please also refer to Section 12.5.4.
COSCIN
COSCOUT
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Figure 14. Clock block diagram
Slow M ode % 1/2/4/8 x2 SMS[1:0] fCPU 8/4/2/1 MHz (or 4/2/1/0.5 MHz) to CPU and peripherals
%3 OS C12/6 0 12 or 6 MHz Crystal 6 MHz (USB) %2 1 MCO pin
6.2 RESET The Reset procedure is used to provide an orderly software start-up or to exit low power modes. Three reset modes are provided: a low voltage reset, a watchdog reset and an external reset at the RESET pin. A reset causes the reset vector to be fetched from addresses FFFEh and FFFFh in order to be loaded into the PC and with program execution starting from this point. An internal circuitry provides a 514 CPU clock cycle delay from the time that the oscillator becomes a c t iv e . 6.2.1 Low Voltage Reset Low voltage reset circuitry generates a reset when VDD is: below VIT+ when VDD is rising, below VIT- when VDD is falling. During low voltage reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Notes: The Low Voltage Detector can be disabled by setting the LVD bit of the Option byte. It is recommended to make sure that the VDD supply voltage rises monotonously when the device is exiting from Reset, to ensure the application functions properly. 6.2.2 Watchdog Reset When a watchdog reset occurs, the RESET pin is pulled low permitting the MCU to reset other devices as when low voltage reset (Figure 15). 6.2.3 External Reset The external reset is an active low input signal applied to the RESET pin of the MCU. As shown in Figure 18, the RESET signal must stay low for a minimum of one and a half CPU clock cycles. An internal Schmitt trigger at the RESET pin is provided to improve noise immunity.
Figure 15. Low Voltage Reset functional Diagram
RESET
VDD
LOW VOLTAGE RESET
INTERNAL RESET
FROM WATCHDOG RESET
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Figure 16. Low Voltage Reset Signal Output
VIT+ VITVDD
RESET
Note: Typical hysteresis (VIT+-VIT-) of 250 mV is expected. Figure 17. Temporization Timing Diagram after an internal Reset VIT+
VDD
Temporization (514 CPU clock cycles) Addresses $FFFE
Figure 18. Reset Timing Diagram
t DDR VDD
OSCIN tOXOV f CPU
PC RE SET
FFFE
FFFF
514 CPU CLOCK CYCLES D EL AY
Note: Refer to Electrical Characteristics for values of tDDR, tOXOV, VIT+ and VIT-.
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Figure 19. Reset Block Diagram
VDD
RON
RESET
200ns Filter INTERNAL RESET
tw(RSTL)out + 128 fOSC delay
PULSE GE NERATOR
WATCHDOG RESET LVD RESET
Note: The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
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7 INTERRUPTS
7.1 INTRODUCTION The CPU enhanced interrupt management provides the following features: Hardware interrupts Software interrupt (TRAP) Nested or concurrent interrupt management with flexible interrupt priority and level management: Up to 4 software programmable nesting levels Up to 16 interrupt vectors fixed by hardware 3 non maskable events: RESET, TRAP, TLI This interrupt management is based on: Bit 5 and bit 3 of the CPU CC register (I1:0), Interrupt software priority registers (ISPRx), Fixed interrupt vector addresses located at the high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order. This enhanced interrupt controller guarantees full upward compatibility with the standard (not nested) CPU interrupt controller. 7.2 MASKING AND PROCESSING FLOW The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector (see Table 5). The processing flow is shown in Figure 20. Figure 20. Interrupt Processing Flowchart
RESET PENDING INTERRUPT N Y TLI Interrupt has the same or a lower software priority than current one N I1:0 Interrupt has a higher software priority than current one Y
When an interrupt request has to be serviced: Normal processing is suspended at the end of the current instruction execution. The PC, X, A and CC registers are saved onto the stack. I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx registers of the serviced interrupt vector. The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to "Interrupt Mapping" table for vector addresses). The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume. Table 5. Interrupt Software Priority Levels
Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) Level Low I1 1 0 0 1 I0 0 1 0 1
High
FETCH NEXT INSTRUCTION
THE INTERRUPT STAYS PENDING
Y
"IRET" N
RESTORE PC, X, A, CC FROM STACK
EXECUTE INSTRUCTION
STACK PC, X, A, CC LOAD I1:0 FROM INTERRUPT SW REG. LOAD PC FROM INTERRUPT VECTOR
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INTERRUPTS (Cont'd) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: the highest software priority interrupt is serviced, if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first. Figure 21 describes this decision process. Figure 21. Priority Decision Process
PENDING INTERRUPTS
TLI (Top Level Hardware Interrupt) This hardware interrupt occurs when a specific edge is detected on the dedicated TLI pin. Caution: A TRAP instruction must not be used in a TLI service routine.
Same
SOFTWARE PRIORITY
Different
TRAP (Non Maskable Software Interrupt) This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the flowchart in Figure 20 as a TLI. Caution: TRAP can be interrupted by a TLI. RESET The RESET source has the highest priority in the CPU. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See the RESET chapter for more details.
HIGHEST SOFTWARE PRIORITY SERVICED HIGHEST HARDWARE PRIORITY SERVICED
When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. Note 1: The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt. Note 2: RESET, TRAP and TLI can be considered as having the highest software priority in the decision process. Different Interrupt Vector Sources Two interrupt source types are managed by the CPU interrupt controller: the non-maskable type (RESET, TLI, TRAP) and the maskable type (external or from internal peripherals). Non-Maskable Sources These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see Figure 20). After stacking the PC, X, A and CC registers (except for RESET), the corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level 3). These sources allow the processor to exit HALT mode.
Maskable Sources Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending. External Interrupts External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitivity is software selectable through the ITRFRE2 register. External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically NANDed. Peripheral Interrupts Usually the peripheral interrupts cause the Device to exit from HALT mode except those mentioned in the "Interrupt Mapping" table. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear sequence is executed.
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INTERRUPTS (Cont'd) 7.3 INTERRUPTS AND LOW POWER MODES All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT modes (see column "Exit from HALT" in "Interrupt Mapping" table). When several pending interrupts are present while exiting HALT mode, the first one serviced can only be an interrupt with exit from HALT mode capability and it is selected through the same decision process shown in Figure 21. Note: If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced. Figure 22. Concurrent Interrupt Management
SOFTW ARE PRIORITY LEVEL IT2 IT1 IT4 IT3 TLI IT0 I1 I0
7.4 CONCURRENT & NESTED MANAGEMENT The following Figure 22 and Figure 23 show two different interrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in Figure 23. The interrupt hardware priority is given in this order from the lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0, TLI. The software priority is given for each interrupt. Warning: A stack overflow may occur without notifying the software of the failure.
HARDWARE PRIORITY
TLI IT0 IT1 IT2 IT3 RIM IT4 MAIN MAIN IT1
3 3 3 3 3 3 3/0 10
11 11 11 11 11 11
11 / 10 Figure 23. Nested Interrupt Management
SOFTW ARE PRIORITY LEVEL
TLI
IT0
IT2
IT1
IT4
IT3
I1
I0
HARDWARE PRIORITY
TLI IT0 IT1 IT2 IT3 RIM IT4 MAIN IT4 MAIN IT1 IT2
3 3 2 1 3 3 3/0 10
11 11 00 01 11 11
11 / 10
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USED STACK = 20 BY TES
USED STACK = 10 BYTES
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INTERRUPTS (Cont'd) 7.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read / Write Reset Value: 111x 1010 (xAh)
7 1 1 I1 H I0 N Z 0 C ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I0_9 I1_4 I1_8 I0_4 I0_8
INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX) Read/Write (bit 7:4 of ISPR3 are read only) Reset Value: 1111 1111 (FFh)
7 ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 0 I0_0
Bit 5, 3 = I1, I0 Software Interrupt Priority These two bits indicate the current interrupt software priority.
Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable*) Level Low I1 1 0 0 1 I0 0 1 0 1
ISPR2 ISPR3
I1_11 I0_11 I1_10 I0_10 I1_9 1 1 1 1
I1_13 I0_13 I1_12 I0_12
High
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see "Interrupt Dedicated Instruction Set" table). *Note: TLI, TRAP and RESET events can interrupt a level 3 program.
These four registers contain the interrupt software priority of each interrupt vector. Each interrupt vector (except RESET and TRAP) has corresponding bits in these registers where its own software priority is stored. This correspondance is shown in the following table.
Vector address FFFBh-FFFAh FFF9h-FFF8h ... FFE1h-FFE0h ISPRx bits I1_0 and I0_0 bits* I1_1 and I0_1 bits ... I1_13 and I0_13 bits
Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits in the CC register. Level 0 can not be written (I1_x=1, I0_x=0). In this case, the previously stored value is kept. (example: previous=CFh, write=64h, result=44h) The RESET, TRAP and TLI vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set. *Note: Bits in the ISPRx registers which correspond to the TLI can be read and written but they are not significant in the interrupt process management. Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behaviour has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x).
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INTERRUPTS (Cont'd) INTERRUPT REGISTER 1 (ITRFRE1) Address: 0008h - Read/Write Reset Value: 0000 0000 (00h)
7 0
Bit 5:4 = CTL[1:0] IT[10:9]1nterrupt Sensitivity These bits are set and cleared by software. They are used to configure the edge and level sensitivity of the IT10 and IT9 external interrupt pins (this means that both must have the same sensitivity).
C TL1 0 0 1 1 CTL0 0 1 0 1 IT[10:9] Sensitivity Falling edge and low level Rising edge only Falling edge only Rising and falling edge
IT8E
IT7E
IT6E
IT5E
IT4E
IT3E
IT2E
IT1E
Bit 7:0 = ITiE Interrupt Enable 0: I/O pin free for general purpose I/O 1: ITi external interrupt enabled. Note: The corresponding interrupt is generated when: a rising edge occurs on the IT5/IT6 pins a falling edge occurs on the IT1, 2, 3, 4, 7 and 8 pins INTERRUPT REGISTER 2 (ITRFRE2) Address: 0039h - Read/Write Reset Value: 0000 0000 (00h)
7 0
Bit 3:0 = ITiE Interrupt Enable 0: I/O pin free for general purpose I/O 1: ITi external interrupt enabled.
CTL3 CTL2 CTL1 CTL0 IT12E IT11E IT10E IT9E
Bit 7:6 = CTL[3:2] IT[12:11] Interrupt Sensitivity These bits are set and cleared by software. They are used to configure the edge and level sensitivity of the IT12 and IT11 external interrupt pins (this means that both must have the same sensitivity).
CTL3 0 0 1 1 C TL2 0 1 0 1 IT[12:11] Sensitivity Falling edge and low level Rising edge only Falling edge only Rising and falling edge
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INTERRUPTS (Cont'd) Table 6. Interrupt Mapping
N Source Block Reset TRAP software interrupt 0 1 2 3 4 5 6 7 8 9 10 TBU AR T S PI S CI USB ADC I/O Ports I CP USB FLASH Start programming NMI interrupt USB End Suspend interrupt Port A external interrupts IT[4:1] Port B external interrupts IT[8:5] Port C external interrupts IT[12:9] Timebase Unit interrupt ART/PWM Timer interrupt SPI interrupt vector SCI interrupt vector USB interrupt vector A/D End of conversion interrupt Reserved area USBISTR I TRFRE1 I TRFRE1 ITRFRE2 TBU CSR ICCSR SPISR SCISR USBISTR ADC CSR Lowest Priority Description Register Label Priority Order Highest Priority Exit from HALT Yes No Yes Yes Yes Yes Yes No Yes Yes No No No Address Vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE0h-FFE5h
Table 7. Nested Interrupts Register Map and Reset Values
Address (Hex.) Register Label 7 6 5 4 3 2 1 Not Used 1 1 0
Ext. Interrupt Port B 0032h ISPR0 Reset Value I1_3 1 SPI 0033h ISPR1 Reset Value I1_7 1 I0_7 1 I0_3 1
Ext. Interrupt Port A I1_2 1 ART I1_6 1 ADC I1_10 1 I0_10 1 I0_6 1 I0_2 1
USB END SUSP I1_1 1 TBU I1_5 1 U SB I1_9 1 I0_9 1 I0_5 1 I0_1 1
Ext. Interrupt Port C I1_4 1 SCI I1_8 1 I0_8 1 I0_4 1
Not Used 0034h ISPR2 Reset Value I1_11 1 I0_11 1
Not Used 0035h ISPR3 Reset Value 1 1 1 1 I1_13 1 I0_13 1
Not Used I1_12 1 I0_12 1
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8 POWER SAVING MODES
8.1 INTRODUCTION There are three Power Saving modes. Slow Mode is selected by setting the SMS bits in the Miscellaneous register. Wait and Halt modes may be entered using the WFI and HALT instructions. After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 3 and multiplied by 2 (fCPU). From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. 8.1.1 Slow Mode In Slow mode, the oscillator frequency can be divided by a value defined in the Miscellaneous Register. The CPU and peripherals are clocked at this lower frequency. Slow mode is used to reduce power consumption, and enables the user to adapt clock frequency to available supply voltage. Figure 24. WAIT Mode Flow Chart
WFI INSTRUCTION
OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT
ON ON OFF CLEAR ED
N RESET N INTERRUP T
Y
Y 8.2 WAIT MODE WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the "WFI" ST7 software instruction. All peripherals remain active. During WAIT mode, the I bit of the CC register is forced to 0, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 24.
OSCILLATOR PERIPH. CLOCK CPU CLOCK I- BIT
ON ON ON SET
IF RESET 514 CPU CLOCK CYCLES DELAY
FETCH RESET VECTOR OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped.
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POWER SAVING MODES (Cont'd) 8.3 HALT MODE The HALT mode is the MCU lowest power consumption mode. The HALT mode is entered by executing the HALT instruction. The internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals. When entering HALT mode, the I bit in the Condition Code Register is cleared. Thus, any of the external interrupts (ITi or USB end suspend mode), are allowed and if an interrupt occurs, the CPU clock becomes active. The MCU can exit HALT mode on reception of either an external interrupt on ITi, an end suspend mode interrupt coming from USB peripheral, or a reset. The oscillator is then turned on and a stabilization time is provided before releasing CPU operation. The stabilization time is 514 CPU clock cycles. After the start up delay, the CPU continues operation by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up.
Figure 25. HALT Mode Flow Chart
HALT INSTRUCTION
OSCILLATOR PERIPH. CLOCK CPU CLOCK I- BIT
OFF OFF OFF CLEARED
N RE SET N
EXTERNAL INTERRUPT*
Y
Y OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT ON ON ON SET
514 CPU CLOCK CYCLES DELAY
FETCH RESET VECTOR OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped.
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9 I/O PORTS
9.1 INTRODUCTION The I/O ports offer different functional modes: transfer of data through digital inputs and outputs and for specific pins: Analog signal input (ADC) Alternate signal input/output for the on-chip peripherals. External interrupt generation An I/O port is composed of up to 8 pins. Each pin can be programmed independently as digital input or digital output. 9.2 FUNCTIONAL DESCRIPTION Each port is associated with 2 main registers: Data Register (DR) Data Direction Register (DDR) Each I/O pin may be programmed using the corresponding register bits in DDR register: bit x corresponding to pin x of the port. The same correspondence is used for the DR register. Table 8. I/O Pin Functions
D DR 0 1 M OD E Input Ou t p u t
9.2.1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Notes: 1. All the inputs are triggered by a Schmitt trigger. 2. When switching from input mode to output mode, the DR register should be written first to output the correct value as soon as the port is configured as an output. Interrupt function When an external interrupt function of an I/O pin, is enabled using the ITFRE registers, an event on this I/O can generate an external Interrupt request to the CPU. The interrupt sensitivity is programma-
ble, the options are given in the description of the ITRFRE interrupt registers. Each pin can independently generate an Interrupt request. Each external interrupt vector is linked to a dedicated group of I/O port pins (see Interrupts section). If more than one input pin is selected simultaneously as interrupt source, this is logically ANDed and inverted. For this reason, if an event occurs on one of the interrupt pins, it masks the other ones. 9.2.2 Output Mode The pin is configured in output mode by setting the corresponding DDR register bit (see Table 7). In this mode, writing "0" or "1" to the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Note: In this mode, the interrupt function is disabled. 9.2.3 Alternate Functions Digital Alternate Functions When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin has to be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register. Notes: 1. Input pull-up configuration can cause an unexpected value at the alternate peripheral input. 2. When the on-chip peripheral uses a pin as input and output, this pin must be configured as an input (DDR = 0). Warning: Alternate functions of peripherals must must not be activated when the external interrupts are enabled on the same pin, in order to avoid generating spurious interrupts.
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I/O PORTS (Cont'd) Analog Alternate Functions When the pin is used as an ADC input, the I/O must be configured as input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to
have clocking pins located close to a selected analog pin. Warning: The analog input voltage level must be within the limits stated in the Absolute Maximum Ratings. 9.2.4 I/O Port Implementation The hardware implementation on each I/O port depends on the settings in the DDR register and specific features of the I/O port such as ADC Input or true open drain.
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I/O PORTS (Cont'd) 9.2.5 Port A Table 9. Port A Description
PO RT A I/O Input* Output USBO E PA 0 floating push-pull IT1 Schmitt triggered input AIN0 (ADC) PA 1 floating push-pull IT2 Schmitt triggered input AIN1 (ADC) IT3 Schmitt triggered input AIN2 (ADC) IT4 Schmitt triggered input AIN3 (ADC) AIN4 (ADC) AIN5 (ADC) AIN6 (ADC) AIN7 (ADC) Signal Alternate Function Condition USBOE = 1 (MISC) IT1E = 1 (ITRFRE1) CS[2:0] = 000 (ADCCSR) IT2E = 1 (ITRFRE1) CS[2:0] = 001 (ADCCSR) IT3E = 1 (ITRFRE1) CS[2:0] = 010 (ADCCSR) IT4E = 1 (ITRFRE1) CS[2:0] = 011 (ADCCSR) CS[2:0] = 100 (ADCCSR) CS[2:0] = 101 (ADCCSR) CS[2:0] = 110 (ADCCSR) CS[2:0] = 111 (ADCCSR)
PA 2
floating
push-pull
PA 3 PA 4 PA 5 PA 6 PA 7 *Reset State
floating floating floating floating floating
push-pull push-pull push-pull push-pull push-pull
Figure 26. PA[7:0] Configuration
ALTERNATE ENABLE ALTERNATE OUTPUT DR LATCH ALTERNATE ENABLE DDR LATCH PAD ANALOG ENABLE (ADC) DDR SEL 1 0 P-BUFFER VDD
V DD
ALTERNATE INPUT
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COMMON ANALOG RAIL
DATA BUS
ANALOG SWITCH N-BUFFER 1 ALTERNATE ENABLE 0 DIGITAL ENABLE VSS
DIODES
DR SEL
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I/O PORTS (Cont'd) 9.2.6 Port B Table 10. Port B Description
I/O POR T B Input* PB0 PB1 PB2 PB3 PB4 floating floating floating floating floating Output push-pull (high sink) push-pull (high sink) push-pull (high sink) push-pull (high sink) push-pull (high sink) IT5 Schmitt triggered input ARTIC2 PB5 floating push-pull (high sink) IT6 Schmitt triggered input PW M1 PB6 floating push-pull (high sink) IT7 Schmitt triggered input PW M2 PB7 *Reset State floating push-pull (high sink) IT8 Schmitt triggered input IT8E = 1 (ITRFRE1) IT7E = 1 (ITRFRE1) OE1 = 1 (PWMCR) IT6E = 1 (ITRFRE1) OE0 = 1 (PWMCR) IT5E = 1 (ITRFRE1) ART Timer enabled Signal MCO (Main Clock Output) RDI TDO ARTCLK ARTIC1 Co n d i t i o n MCO = 1 (MISCR) SCI enabled TE = 1 (SCICR2) EXCL = 1 (ARTCSR) ART Timer enabled Alternate Function
Figure 27. Port B and Port C [7:2] Configuration
ALTERNATE ENABLE ALTERNATE 1 OUTPUT 0 VDD
P-BUFFER
DR LATCH ALTERNATE ENABLE DDR LATCH DDR SEL
DATA BUS
VDD
PULL-UP*
PAD
N-BUFFER DR SEL 1 DIODES ALTERNATE ENABLE VSS
ALTERNATE INPUT
0
CMOS SCHMITT TRIGGER
* PULL-UP ON PORT C [7:2] ONLY
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I/O PORTS (Cont'd) 9.2.7 Port C Table 11. Port C Description
I/O PO RT C Input* PC0 PC1 PC2 PC3 f loating f loating with pull-up with pull-up Output true open drain true open drain push-pull push-pull IT10 Schmitt triggered input SS PC4 with pull-up push-pull IT11 Schmitt triggered input MISO PC5 PC6 PC7 *Reset State with pull-up with pull-up with pull-up push-pull IT12 Schmitt triggered input push-pull push-pull MOSI IT12E = 1 (ITRFRE2) SPI enabled IT11E = 1 (ITRFRE2) SPI enabled IT10E = 1 (ITRFRE2) SPI enabled IT9 Schmitt triggered input SCK IT9E = 1 (ITRFRE2) SPI enabled Signal Condition Alternate Function
Figure 28. Port C[1:0] Configuration
ALTERNATE ENABLE ALTERNATE 1 OUTPUT 0 DR LATCH
DDR LATCH
DATA BUS
PAD
DDR SEL
N-BUFFER
DIODES
DR SEL
1 0
ALTERNATE ENABLE VSS CMOS SCHMITT TRIGGER
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I/O PORTS (Cont'd) 9.2.8 Port D Table 12. Port D Description
I/O PO RT D Input* PD0 PD1 PD2 PD3 PD4 PD5 PD6 *Reset State with pull-up with pull-up with pull-up with pull-up with pull-up w ith pull-up with pull-up Output push-pull push-pull push-pull push-pull push-pull push-pull push-pull Signal Condition Alternate Function
Figure 29. Port D Configuration
ALTERNATE ENABLE ALTERNATE 1 OUTPUT 0 VDD
P-BUFFER
DR LATCH ALTERNATE ENABLE
DATA BUS
PULL-UP
VDD
DDR LATCH DDR SEL PAD
N-BUFFER 1
DR SEL
DIOD ES
ALTERNATE ENABLE
0 ALTERNATE INPUT
VSS
CMOS SCHMITT TRIGGER
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I/O PORTS (Cont'd) 9.2.9 Register Description DATA REGISTER (DR) Port x Data Register PxDR with x = A, B, C or D. Read / Write Reset Value: 0000 0000 (00h)
7 D7 D6 D5 D4 D3 D2 D1 0 D0
DATA DIRECTION REGISTER (DDR) Port x Data Direction Register PxDDR with x = A, B, C or D. Read / Write Reset Value: 0000 0000 (00h)
7 DD7 DD6 DD5 DD4 DD3 DD2 DD1 0 DD0
Bits 7:0 = D[7:0] Data register 8 bits. The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken into account even if the pin is configured as an input; this allows to always have the expected level on the pin when toggling to output mode. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input).
Bits 7:0 = DD[7:0] Data direction register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bit is set and cleared by software. 0: Input mode 1: Output mode
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I/O PORTS (Cont'd) Table 13. I/O Port Register Map and Reset Values
Address (Hex.) Register Label 7 6 5 4 3 2 1 0
Reset Value of all I/O port registers 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h P ADR
0
0
0
0
0
0
0
0
MSB P ADDR P BDR MSB P BDDR P CDR MSB P CDDR P DDR MSB P DDDR
LSB
LSB
LSB
LSB
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9.3 MISCELLANEOUS REGISTER MISCELLANEOUS REGISTER Read Write Reset Value - 0000 0000 (00h)
7 S M S 1 S MS 0 USBO E 0 MCO
Bit 1 = USBOE USB Output Enable 0: PA0 port free for general purpose I/O 1: USBOE alternate function enabled. The USB output enable signal is output on the PA0 port (at "1" when the ST7 USB is transmitting data). Bit 0 = MCO Main Clock Out 0: PB0 port free for general purpose I/O 1: MCO alternate function enabled (fCPU output on PB0 I/O port)
Bits 7:4 = Reserved Bits 3:2 = SMS[1:0] Slow Mode Selection These bits select the Slow Mode frequency (depending on the oscillator frequency configured by option byte).
O S C12/6 S MS1 S MS0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Slow Mode Frequency (MHz.) 4 2 1 0. 5 8 4 2 1
fOSC= 6 MHz.
fOSC= 12 MHz.
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10 ON-CHIP PERIPHERALS
10.1 WATCHDOG TIMER (WDG) 10.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter's contents before the T6 bit becomes cleared. 10.1.2 Main Features Programmable free-running downcounter (64 increments of 65536 CPU cycles) Programmable reset Reset (if watchdog activated) when the T6 bit reaches zero Hardware Watchdog selectable by option byte 10.1.3 Functional Description The counter value stored in the CR register (bits T[6:0]), is decremented every 65,536 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments. Figure 30. Watchdog Block Diagram
RESET
If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 30s. The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. This downcounter is freerunning: it counts down even if the watchdog is diabled The value to be stored in the CR register must be between FFh and C0h (see Table 14): The WDGA bit is set (watchdog enabled) The T6 bit is set to prevent generating an immediate reset The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. Table 14.Watchdog Timing (fCPU = 8 MHz)
CR Register initial value Max Min FFh C0 h WDG timeout period (ms) 524.288 8.192
WATCHDOG CONTROL REGISTER (CR) WDG A T6 T5 T4 T3 T2 T1 T0
7-BIT DOWNCOUNTER
fCPU
CLOCK DIVIDER ÷65536
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WATCHDOG TIMER (Cont'd) 10.1.4 Software Watchdog Option If Software Watchdog is selected by option byte, the watchdog is disabled following a reset. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). 10.1.5 Hardware Watchdog Option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used. 10.1.6 Low Power Modes WAIT Instruction No effect on Watchdog. HALT Instruction Halt mode can be used when the watchdog is enabled. When the oscillator is stopped, the WDG stops counting and is no longer able to generate a reset until the microcontroller receives an external interrupt or a reset. If an external interrupt is received, the WDG restarts counting after 514 CPU clocks. In the case of the Software Watchdog option, if a reset is generated, the WDG is disabled (reset state). Recommendations Make sure that an external event is available to wake up the microcontroller from Halt mode. Before executing the HALT instruction, refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller. When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as Input before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition.
The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E. As the HALT instruction clears the I bit in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). 10.1.7 Interrupts None. 10.1.8 Register Desc4ription CONTROL REGISTER (CR) Read / Write Reset Value: 0111 1111 (7Fh)
7 WDG A T6 T5 T4 T3 T2 T1 0 T0
Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watchdog option is enabled by option byte. Bits 6:0 = T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).
Table 15. Watchdog Timer Register Map and Reset Values
Address (Hex.) 0Dh Register Label W D GC R Reset Value 7 WD GA 0 6 T6 1 5 T5 1 4 T4 1 3 T3 1 2 T2 1 1 T1 1 0 T0 1
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10.2 PWM AUTO-RELOAD TIMER (ART) 10.2.1 Introduction The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit auto reload counter with compare/capture capabilities and of a 7-bit prescaler clock source. These resources allow five possible operating modes: Generation of up to 2 independent PWM signals Output compare and Time base interrupt Figure 31. PWM Auto-Reload Timer Block Diagram
PWMCR OEx OPx OCRx REGISTER LOAD PWMx PORT ALTERNATE FUNCTION POLARITY CONTROL COMPARE PWMDCRx REGISTER
Up to two input capture functions External event detector Up to two external interrupt sources The three first modes can be used together with a single counter frequency. The timer can be used to wake up the MCU from WAIT and HALT modes.
ARTARR REGISTER
8-BIT COUNTER (ARTCAR REGISTER)
LOAD
ARTICx
INPUT CAPTURE CONTROL
LOAD
ARTICRx REGISTER
ICSx
ICIEx
ICFx
ARTICCSR
ARTCLK
fEXT f CPU f COUNTER
ICx INTERRUPT
MUX fINPUT
PROGRAMMABLE PRESCALER
EXCL
CC2
CC1
CC0
TCE
FCRL
OIE
OVF
ARTCSR
OVF INTERRUPT
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PWM AUTO-RELOAD TIMER (Cont'd) 10.2.2 Functional Description Counter The free running 8-bit counter is fed by the output of the prescaler, and is incremented on every rising edge of the clock signal. It is possible to read or write the contents of the counter on the fly by reading or writing the Counter Access register (ARTCAR). When a counter overflow occurs, the counter is automatically reloaded with the contents of the ARTARR register (the prescaler is not affected). Counter clock and prescaler The counter clock frequency is given by: fCOUNTER = fINPUT / 2CC[2:0] The timer counter's input clock (fINPUT) feeds the 7-bit programmable prescaler, which selects one of the 8 available taps of the prescaler, as defined by CC[2:0] bits in the Control/Status Register (ARTCSR). Thus the division factor of the prescaler can be set to 2n (where n = 0, 1,..7). This fINPUT frequency source is selected through the EXCL bit of the ARTCSR register and can be either the fCPU or an external input frequency fEXT. The clock input to the counter is enabled by the TCE (Timer Counter Enable) bit in the ARTCSR register. When TCE is reset, the counter is stopped and the prescaler and counter contents are frozen. When TCE is set, the counter runs at the rate of the selected clock source. Figure 32. Output compare control
fCOUNTER AR TAR R =FD h COUNTER FDh FEh FFh FDh F Eh FFh FDh FEh FFh
Counter and Prescaler Initialization After RESET, the counter and the prescaler are cleared and fINPUT = fCPU. The counter can be initialized by: Writing to the ARTARR register and then setting the FCRL (Force Counter Re-Load) and the TCE (Timer Counter Enable) bits in the ARTCSR register. Writing to the ARTCAR counter access register, In both cases the 7-bit prescaler is also cleared, whereupon counting will start from a known value. Direct access to the prescaler is not possible. Output compare control The timer compare function is based on four different comparisons with the counter (one for each PWMx output). Each comparison is made between the counter value and an output compare register (OCRx) value. This OCRx register can not be accessed directly, it is loaded from the duty cycle register (PWMDCRx) at each overflow of the counter. This double buffering method avoids glitch generation when changing the duty cycle on the fly.
OCRx
FDh
F Eh
PWMDCRx
FDh
FEh
PWMx
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PWM AUTO-RELOAD TIMER (Cont'd) Independent PWM signal generation This mode allows up to two Pulse Width Modulated signals to be generated on the PWMx output pins with minimum core processing overhead. This function is stopped during HALT mode. Each PWMx output signal can be selected independently using the corresponding OEx bit in the PWM Control register (PWMCR). When this bit is set, the corresponding I/O pin is configured as output push-pull alternate function. The PWM signals all have the same frequency which is controlled by the counter period and the ARTARR register value. fPWM = fCOUNTER / (256 - ARTARR) When a counter overflow occurs, the PWMx pin level is changed depending on the corresponding OPx (output polarity) bit in the PWMCR register. Figure 33. PWM Auto-reload Timer Function
255 DUTY CYCLE R EGIST ER (PWMDCRx)
When the counter reaches the value contained in one of the output compare register (OCRx) the corresponding PWMx pin level is restored. It should be noted that the reload values will also affect the value and the resolution of the duty cycle of the PWM output signal. To obtain a signal on a PWMx pin, the contents of the OCRx register must be greater than the contents of the ARTARR regis ter. The maximum available resolution for the PWMx duty cycle is: Resolution = 1 / (256 - ARTARR) Note: To get the maximum resolution (1/256), the ARTARR register must be 0. With this maximum resolution, 0% and 100% can be obtained by changing the polarity.
COUNTER
AUT O-RELO A D RE GISTER (ARTARR) 000
t
PWMx OUTPUT
WITH OEx=1 AND OPx=0 WITH OEx=1 AND OPx=1
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PWM AUTO-RELOAD TIMER (Cont'd) Figure 34. PWM Signal from 0% to 100% Duty Cycle
fCOUNTER ARTARR=FDh COUNTER FDh F Eh FFh FDh FEh FFh FDh F Eh
OCRx=FCh PWMx OUTPUT WITH OEx=1 AND OPx=0 OCRx=FDh OCRx=FEh OCRx=FFh
t
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PWM AUTO-RELOAD TIMER (Cont'd) Output compare and Time base interrupt On overflow, the OVF flag of the ARTCSR register is set and an overflow interrupt request is generated if the overflow interrupt enable bit, OIE, in the ARTCSR register, is set. The OVF flag must be reset by the user software. This interrupt can be used as a time base in the application. External clock and event detector mode Using the fEXT external prescaler input clock, the auto-reload timer can be used as an external clock event detector. In this mode, the ARTARR register is used to select the nEVENT number of events to be counted before setting the OVF flag. nEVENT = 256 - ARTARR When entering HALT mode while fEXT is selected, all the timer control registers are frozen but the counter continues to increment. If the OIE bit is set, the next overflow of the counter will generate an interrupt which wakes up the MCU. Caution: If HALT mode is used in the application, prior to executing the HALT instruction, the counter must be disabled by clearing the TCE bit in the ARTCSR register to avoid spurious counter increments.
Figure 35. External Event Detector Example (3 counts)
fEXT=fCOUNTER AR TAR R =FD h
COUNTER
FDh
F Eh
FFh
FDh
FEh
FFh
FDh
OVF
ARTCSR READ INTERRUPT IF OIE=1 INTERRUPT IF OIE=1
ARTCSR READ
t
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PWM AUTO-RELOAD TIMER (Cont'd) Input capture function This mode allows the measurement of external signal pulse widths through ICRx registers. Each input capture can generate an interrupt independently on a selected input signal transition. This event is flagged by a set of the corresponding CFx bits of the Input Capture Control/Status register (ICCSR). These input capture interrupts are enabled through the CIEx bits of the ICCSR register. The active transition (falling or rising edge) is software programmable through the CSx bits of the ICCSR register. The read only input capture registers (ICRx) are used to latch the auto-reload counter value when a transition is detected on the ARTICx pin (CFx bit set in ICCSR register). After fetching the interrupt vector, the CFx flags can be read to identify the interrupt source. Note: After a capture detection, data transfer in the ICRx register is inhibited until the ARTICCSR register is read (clearing the CFx bit). The timer interrupt remains pending while the CFx flag is set when the interrupt is enabled (CIEx bit set). This means, the ARTICCSR register has to be read at each capture event to clear the CFx flag. The timing resolution is given by auto-reload counter cycle time (1/fCOUNTER). Figure 37. Input Capture Timing Diagram
fCOUNTER
During HALT mode, input capture is inhibited (the ICRx is never re-loaded) and only the external interrupt capability can be used.
External interrupt capability This mode allows the Input capture capabilities to be used as external interrupt sources. The edge sensitivity of the external interrupts is programmable (CSx bit of ICCSR register) and they are independently enabled through CIEx bits of the ICCSR register. After fetching the interrupt vector, the CFx flags can be read to identify the interrupt source. The interrupts are synchronized on the counter clock rising edge (Figure 36). During HALT mode, the external interrupts can still be used to wake up the micro (if CIEx bit is set). Figure 36. ART External Interrupt
fCOUNTER
ARTICx PIN CFx FLAG
INTERRUPT
t
COUNTER
01h
02h
03h
04h
05h
06h
07h
ARTICx PIN CFx FLAG xxh IC R x R E GIS T E R
INTERRUPT
04h
t
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PWM AUTO-RELOAD TIMER (Cont'd) 10.2.3 Register Description CONTROL / STATUS REGISTER (CSR) Read / Write Reset Value: 0000 0000 (00h)
7 EXCL CC2 CC1 CC0 TCE FCRL OIE 0 OVF
COUNTER ACCESS REGISTER (CAR) Read / Write Reset Value: 0000 0000 (00h)
7 CA7 CA6 CA5 CA4 CA3 CA2 CA1 0 CA0
Bit 7 = EXCL External Clock This bit is set and cleared by software. It selects the input clock for the 7-bit prescaler. 0: CPU clock. 1: External clock. Bit 6:4 = CC[2:0] Counter Clock Control These bits are set and cleared by software. They determine the prescaler division ratio from fINPUT.
f COUNTER fINPUT fINPUT / 2 fINPUT / 4 fINPUT / 8 fINPUT / 16 fINPUT / 32 fINPUT / 64 fINPUT / 128 With fINPUT=8 MHz CC2 CC1 CC0 8 MHz 4 MHz 2 MHz 1 MHz 500 KHz 250 KHz 125 KHz 62.5 KHz 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Bit 7:0 = CA[7:0] Counter Access Data These bits can be set and cleared either by hardware or by software. The CAR register is used to read or write the auto-reload counter "on the fly" (while it is counting).
AUTO-RELOAD REGISTER (ARR) Read / Write Reset Value: 0000 0000 (00h)
7 AR7 AR6 AR5 AR4 AR3 AR2 AR1 0 AR0
Bit 3 = TCE Timer Counter Enable This bit is set and cleared by software. It puts the timer in the lowest power consumption mode. 0: Counter stopped (prescaler and counter frozen). 1: Counter running. Bit 2 = FCRL Force Counter Re-Load This bit is write-only and any attempt to read it will yield a logical zero. When set, it causes the contents of ARR register to be loaded into the counter, and the content of the prescaler register to be cleared in order to initialize the timer before starting to count. Bit 1 = OIE Overflow Interrupt Enable This bit is set and cleared by software. It allows to enable/disable the interrupt which is generated when the OVF bit is set. 0: Overflow Interrupt disable. 1: Overflow Interrupt enable. Bit 0 = OVF Overflow Flag This bit is set by hardware and cleared by software reading the CSR register. It indicates the transition of the counter from FFh to the ARR value. 0: New transition not yet reached 1: Transition reached
Bit 7:0 = AR[7:0] Counter Auto-Reload Data These bits are set and cleared by software. They are used to hold the auto-reload value which is automatically loaded in the counter when an overflow occurs. At the same time, the PWM output levels are changed according to the corresponding OPx bit in the PWMCR register. This register has two PWM management functions: Adjusting the PWM frequency Setting the PWM duty cycle resolution PWM Frequency vs. Resolution:
ARR value 0 [ 0..127 ] [ 128..191 ] [ 192..223 ] [ 224..239 ] Resolution Min 8 -bit > 7-bit > 6-bit > 5-bit > 4-bit ~0.244-KHz ~0.244-KHz ~0.488-KHz ~0.977-KHz ~1.953-KHz fPWM Ma x 31.25-KHz 62.5-KHz 125-KH z 250-KH z 500-KH z
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PWM AUTO-RELOAD TIMER (Cont'd) PWM CONTROL REGISTER (PWMCR) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 OE1 OE0 0 0 OP1 0 OP0
DUTY CYCLE REGISTERS (DCRx) Read / Write Reset Value: 0000 0000 (00h)
7 DC7 DC6 DC5 DC4 DC3 DC2 DC1 0 DC0
Bit 7:6 = Reserved. Bit 5:4 = OE[1:0] PWM Output Enable These bits are set and cleared by software. They enable or disable the PWM output channels independently acting on the corresponding I/O pin. 0: PWM output disabled. 1: PWM output enabled. Bit 3:2 = Reserved. Bit 1:0 = OP[1:0] PWM Output Polarity These bits are set and cleared by software. They independently select the polarity of the two PWM output signals.
PWMx output level O Px Counter <= OCRx 1 0 Counter > OCRx 0 1 0 1
Bit 7:0 = DC[7:0] Duty Cycle Data These bits are set and cleared by software. A DCRx register is associated with the OCRx register of each PWM channel to determine the second edge location of the PWM signal (the first edge location is common to all channels and given by the ARR register). These DCR registers allow the duty cycle to be set independently for each PWM channel.
Notes: When an OPx bit is modified, the PWMx output signal polarity is immediately reversed. If DCRx=FFh then the output level is always 0. If DCRx=00h then the output level is always 1.
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PWM AUTO-RELOAD TIMER (Cont'd) INPUT CAPTURE CONTROL / STATUS REGISTER (ARTICCSR) Read / Write (except bits 1:0 read and clear) Reset Value: 0000 0000 (00h)
7 0 0 CS2 CS1 CIE2 CIE1 CF2 0 IC7 CF1 IC6 IC5 IC4 IC3 IC2 IC1 IC0
INPUT CAPTURE REGISTERS (ARTICRx) Read only Reset Value: 0000 0000 (00h)
7 0
Bit 7:6 = Reserved, always read as 0. Bit 5:4 = CS[2:1] Capture Sensitivity These bits are set and cleared by software. They determine the trigger event polarity on the corresponding input capture channel. 0: Falling edge triggers capture on channel x. 1: Rising edge triggers capture on channel x. Bit 3:2 = CIE[2:1] Capture Interrupt Enable These bits are set and cleared by software. They enable or disable the Input capture channel interrupts independently. 0: Input capture channel x interrupt disabled. 1: Input capture channel x interrupt enabled. Bit 1:0 = CF[2:1] Capture Flag These bits are set by hardware when a capture occurs and cleared by hardware when software reads the ARTICCSR register. Each CFx bit indicates that an input capture x has occurred. 0: No input capture on channel x. 1: An input capture has occured on channel x.
Bit 7:0 = IC[7:0] Input Capture Data These read only bits are set and cleared by hardware. An ARTICRx register contains the 8-bit auto-reload counter value transferred by the input capture channel x event.
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PWM AUTO-RELOAD TIMER (Cont'd) Table 16. PWM Auto-Reload Timer Register Map and Reset Values
Address (Hex.) 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch Register Label PW MDCR1 Reset Value PW MDCR0 Reset Value PW MCR Reset Value ARTCSR Reset Value ARTCAR Reset Value ARTARR Reset Value ARTICCSR Reset Value ARTICR 1 Reset Value ARTICR 2 Reset Value 7 D C7 0 D C7 0 0 0 EXCL 0 C A7 0 A R7 0 0 IC7 0 IC7 0 6 DC6 0 DC6 0 0 0 CC2 0 CA6 0 AR6 0 0 IC6 0 IC6 0 5 DC5 0 DC5 0 OE1 0 CC1 0 CA5 0 AR5 0 CS2 0 IC5 0 IC5 0 4 DC4 0 DC4 0 OE0 0 CC0 0 CA4 0 AR4 0 CS1 0 IC4 0 IC4 0 3 D C3 0 D C3 0 0 0 TC E 0 C A3 0 A R3 0 CIE2 0 IC3 0 IC3 0 2 D C2 0 D C2 0 0 0 FCRL 0 C A2 0 A R2 0 CIE1 0 IC2 0 IC2 0 1 DC1 0 DC1 0 OP1 0 OIE 0 CA1 0 AR1 0 CF2 0 IC1 0 IC1 0 0 DC 0 0 DC 0 0 OP 0 0 OV F 0 CA 0 0 AR 0 0 CF1 0 IC0 0 IC0 0
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10.3 TIMEBASE UNIT (TBU) 10.3.1 Introduction The Timebase unit (TBU) can be used to generate periodic interrupts. 10.3.2 Main Features 8-bit upcounter Programmable prescaler Period between interrupts: max. 8.1ms (at 8 MHz fCPU ) Maskable interrupt Cascadable with PWM/ART TImer 10.3.3 Functional Description The TBU operates as a free-running upcounter. When the TCEN bit in the TBUCSR register is set by software, counting starts at the current value of the TBUCV register. The TBUCV register is incremented at the clock rate output from the prescaler selected by programming the PR[2:0] bits in the TBUCSR register. When the counter rolls over from FFh to 00h, the OVF bit is set and an interrupt request is generated if ITE is set. The user can write a value at any time in the TBUCV register. Figure 38. TBU Block Diagram
ART TIMER CARRY BIT
If the cascading option is selected (CAS bit=1 in the TBUCSR register), the TBU and the the ART TImer counters act together as a 16-bit counter. In this case, the TBUCV register is the high order byte, the ART counter (ARTCAR register) is the low order byte. Counting is clocked by the ART timer clock (Refer to the description of the ART Timer ARTCSR register). 10.3.4 Programming Example In this example, timer is required to generate an interrupt after a delay of 1 ms. Assuming that fCPU is 8 MHz and a prescaler division factor of 256 will be programmed using the PR[2:0] bits in the TBUCSR register, 1 ms = 32 TBU timer ticks. In this case, the initial value to be loaded in the TBUCV must be (256-32) = 224 (E0h).
ld ld ld ld A, E0h TBUCV, A ; Initialize counter value A 1Fh ; TBUCSR, A ; Prescaler factor = 256, ; interrupt enable, ; TBU enable
1
MSB LSB MSB LSB
0
TBU 8-BIT UPCOUNTER (TBUCV REGISTER) ART PWM TIMER 8-BIT COUNTER
TBU PRESCALER
fCPU
0
CAS OVF
ITE TCEN PR2 PR1 PR0
TBUCSR REGISTER INTERRUPT REQUEST
TBU
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TIMEBASE UNIT (Cont'd) 10.3.5 Low Power Modes Mode WAIT HALT Description No effect on TBU TBU halted. Bit 6 = CAS Cascading Enable This bit is set and cleared by software. It is used to cascade the TBU and the PWM/ART timers. 0: Cascading disabled 1: Cascading enabled Bit 5 = OVF Overflow Flag This bit is set only by hardware, when the counter value rolls over from FFh to 00h. It is cleared by software reading the TBUCSR register. Writing to this bit does not change the bit value. 0: No overflow 1: Counter overflow Bit 4 = ITE Interrupt enabled. This bit is set and cleared by software. 0: Overflow interrupt disabled 1: Overflow interrupt enabled. An interrupt request is generated when OVF=1. Bit 3 = TCEN TBU Enable. This bit is set and cleared by software. 0: TBU counter is frozen and the prescaler is reset. 1: TBU counter and prescaler running. Bit 2:0 = PR[2:0] Prescaler Selection These bits are set and cleared by software to select the prescaling factor.
PR 2 PR1 PR0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Prescaler Division Factor 2 4 8 16 32 64 128 256
10.3.6 Interrupts
Interrupt Event Counter Overflow Event Event Flag OVF Enable Control Bit I TE Exit from Wait Y es Exit from Halt No
Note: The OVF interrupt event is connected to an interrupt vector (see Interrupts chapter). It generates an interrupt if the ITE bit is set in the TBUCSR register and the I-bit in the CC register is reset (RIM instruction). 10.3.7 Register Description TBU COUNTER VALUE REGISTER (TBUCV) Read/Write Reset Value: 0000 0000 (00h)
7 CV 7 CV 6 CV 5 C V4 C V3 C V2 CV1 0 CV0
Bit 7:0 = CV[7:0] Counter Value This register contains the 8-bit counter value which can be read and written anytime by software. It is continuously incremented by hardware if TCEN=1. TBU CONTROL/STATUS REGISTER (TBUCSR) Read/Write Reset Value: 0000 0000 (00h)
7 0 CAS O VF ITE TCEN PR2 PR 1 0 PR0
Bit 7 = Reserved. Forced by hardware to 0.
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TIMEBASE UNIT (Cont'd) Table 17. TBU Register Map and Reset Values
Address (Hex.) 0036h 0037h Register Label TB UCV Reset Value TB USR Reset Value 7 C V7 0 0 6 CV6 0 CAS 0 5 CV5 0 OVF 0 4 CV4 0 ITE 0 3 CV3 0 TCE N 0 2 CV 2 0 PR 2 0 1 CV1 0 PR1 0 0 CV0 0 PR0 0
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10.4 SERIAL PERIPHERAL INTERFACE (SPI) 10.4.1 Introduction The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves however the SPI interface can not be a master in a multi-master s yst em. 10.4.2 Main Features Full duplex synchronous transfers (on 3 lines) Simplex synchronous transfers (on 2 lines) Master or slave operation Six master mode frequencies (fCPU/4 max.) fCPU/2 max. slave mode frequency (see note) SS Management by software or hardware Programmable clock polarity and phase End of transfer interrupt flag Write collision, Master Mode Fault and Overrun flags Note: In slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence. 10.4.3 General Description Figure 39 shows the serial peripheral interface (SPI) block diagram. There are 3 registers: SPI Control Register (SPICR) SPI Control/Status Register (SPICSR) SPI Data Register (SPIDR) The SPI is connected to external devices through 3 pins: MISO: Master In / Slave Out data MOSI: Master Out / Slave In data SCK: Serial Clock out by SPI masters and input by SPI slaves SS: Slave select: This input signal acts as a `chip select' to let the SPI master communicate with slaves individually and to avoid contention on the data lines. Slave SS inputs can be driven by standard I/O ports on the master MCU.
Figure 39. Serial Peripheral Interface Block Diagram
Data/Address Bus SPIDR Read Read Buffer Interrupt request
MOSI MISO
8-Bit Shift Register
7 SPIF WCOL OVR MODF 0
SPICSR
SOD SSM
0 SSI
SOD bit
Write
SS
SPI STATE CONTROL
7 SPIE
1 0
SCK
SPICR
0
SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
MAS T ER C ON T R O L SERIAL CLOCK GENER ATOR
SS
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SERIAL PERIPHERAL INTERFACE (Cont'd) 10.4.3.1 Functional Description A basic example of interconnections between a single master and a single slave is illustrated in Figure 40. The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first). The communication is always initiated by the master. When the master device transmits data to a slave device via MOSI pin, the slave device reFigure 40. Single Master/ Single Slave Application
sponds by sending data to the master device via the MISO pin. This implies full duplex communication with both data out and data in synchronized with the same clock signal (which is provided by the master device via the SCK pin). To use a single data line, the MISO and MOSI pins must be connected at each node ( in this case only simplex communication is possible). Four possible data/clock timing relationships may be chosen (see Figure 43) but master and slave must be programmed with the same timing mode.
MAS T ER M SBit L SBit MISO MISO MSBit
SLAV E L SB it
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
M OS I
MOS I
SPI CLOCK G ENERATO R
SCK SS +5V
SC K SS
Not used if SS is managed by software
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SERIAL PERIPHERAL INTERFACE (Cont'd) 10.4.3.2 Slave Select Management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM bit in the SPICSR register (see Figure 42) In software management, the external SS pin is free for other application uses and the internal SS signal level is driven by writing to the SSI bit in the SPICSR register. In Master mode: SS internal must be held high continuously
In Slave Mode: There are two cases depending on the data/clock timing relationship (see Figure 41): If CPHA=1 (data latched on 2nd clock edge): SS internal must be held low during the entire transmission. This implies that in single slave applications the SS pin either can be tied to VSS, or made free for standard I/O by managing the SS function by software (SSM= 1 and SSI=0 in the in the SPICSR register) If CPHA=0 (data latched on 1st clock edge): SS internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. If SS is not pulled high, a Write Collision error will occur when the slave writes to the shift register (see Section 10.4.5.3).
Figure 41. Generic SS Timing Diagram
MOSI/MISO Master SS Slave SS (if CPHA=0) Slave SS (if CPHA=1)
Byte 1
Byte 2
Byte 3
Figure 42. Hardware/Software Slave Select Management SSM bit
SSI bit SS external pin
1 0
SS internal
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SERIAL PERIPHERAL INTERFACE (Cont'd) 10.4.3.3 Master Mode Operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0). To operate the SPI in master mode, perform the following two steps in order (if the SPICSR register is not written first, the SPICR register setting (MSTR bit) may be not taken into account): 1. Write to the SPICR register: Select the clock frequency by configuring the SPR[2:0] bits. Select the clock polarity and clock phase by configuring the CPOL and CPHA bits. Figure 43 shows the four possible configurations. Note: The slave must have the same CPOL and CPHA settings as the master. 2. Write to the SPICSR register: Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin high for the complete byte transmit sequence. 3. Write to the SPICR register: Set the MSTR and SPE bits Note: MSTR and SPE bits remain set only if SS is high). The transmit sequence begins when software writes a byte in the SPIDR register. 10.4.3.4 Master Mode Transmit Sequence When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most significant bit first. When data transfer is complete: The SPIF bit is set by hardware An interrupt request is generated if the SPIE bit is set and the interrupt mask in the CCR register is cleared. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SPICSR register while the SPIF bit is set 2. A read to the SPIDR register.
Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. 10.4.3.5 Slave Mode Operation In slave mode, the serial clock is received on the SCK pin from the master device. To operate the SPI in slave mode: 1. Write to the SPICSR register to perform the following actions: Select the clock polarity and clock phase by configuring the CPOL and CPHA bits (see Figure 43). Note: The slave must have the same CPOL and CPHA settings as the master. Manage the SS pin as described in Section 10.4.3.2 and Figure 41. If CPHA=1 SS must be held low continuously. If CPHA=0 SS must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI I/O functions. 10.4.3.6 Slave Mode Transmit Sequence When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MISO pin most significant bit first. The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin. When data transfer is complete: The SPIF bit is set by hardware An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR register is cleared. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SPICSR register while the SPIF bit is set. 2. A write or a read to the SPIDR register. Notes: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see Section 10.4.5.2).
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SERIAL PERIPHERAL INTERFACE (Cont'd) 10.4.4 Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See Figure 43). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0). The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data capture clock edge Figure 43. Data Clock Timing Diagram
Figure 43, shows an SPI transfer with the four combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly connected between the master and the slave device. Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit.
CPHA =1
SCK (CPOL = 1) SCK (CPOL = 0)
MISO (from master) MOSI (from slave) SS (to slave)
CAPTURE STROBE
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
CPHA =0
SCK (CPOL = 1) SCK (CPOL = 0)
MISO (from master) MOSI (from slave) SS (to slave)
CAPTURE STROBE
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bi t 6
Bit 5
Bit 4
Bit3
Bi t 2
Bit 1
LSBit
Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter.
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SERIAL PERIPHERAL INTERFACE (Cont'd) 10.4.5 Error Flags 10.4.5.1 Master Mode Fault (MODF) Master mode fault occurs when the master device has its SS pin pulled low. When a Master mode fault occurs: The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set. The SPE bit is reset. This blocks all output from the device and disables the SPI peripheral. The MSTR bit is reset, thus forcing the device into slave mode. Clearing the MODF bit is done through a software sequence: 1. A read access to the SPICSR register while the MODF bit is set. 2. A write to the SPICR register. Notes: To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their original state during or after this clearing sequence. Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence. In a slave device, the MODF bit can not be set, but in a multi master configuration the device can be in slave mode with the MODF bit set. The MODF bit indicates that there might have been a multi-master conflict and allows software to handle this using an interrupt routine and either perform to a reset or return to an application default state.
10.4.5.2 Overrun Condition (OVR) An overrun condition occurs, when the master device has sent a data byte and the slave device has not cleared the SPIF bit issued from the previously transmitted byte. When an Overrun occurs: The OVR bit is set and an interrupt request is generated if the SPIE bit is set. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the SPIDR register returns this byte. All other bytes are lost. The OVR bit is cleared by reading the SPICSR register. 10.4.5.3 Write Collision Error (WCOL) A write collision occurs when the software tries to write to the SPIDR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and the software write will be unsuccessful. Write collisions can occur both in master and slave mode. See also Section 10.4.3.2 Slave Select Management. Note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the MCU operation. The WCOL bit in the SPICSR register is set if a write collision occurs. No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only). Clearing the WCOL bit is done through a software sequence (see Figure 44).
Figure 44. Clearing the WCOL bit (Write Collision Flag) Software Sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) 1st Step Read SPICSR
RES ULT
2nd Step
Read SPIDR
SPIF =0 WC OL=0
Clearing sequence before SPIF = 1 (during a data byte transfer) 1st Step 2nd Step Read SPICSR
RES ULT
Read SPIDR
WC OL=0
Note: Writing to the SPIDR register instead of reading it does not reset the WCOL bit
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SERIAL PERIPHERAL INTERFACE (Cont'd) 10.4.5.4 Single Master System A typical single master system may be configured, using an MCU as the master and four MCUs as slaves (see Figure 45). The master device selects the individual slave devices by using four pins of a parallel port to control the four SS pins of the slave devices. The SS pins are pulled high during reset since the master device ports will be forced to be inputs at that t |
