ST7265x
LOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC, I2C, SPI
Memories Up to 32K of ROM or High Density Flash (HDFlash) program memory with read/write protection For HDFlash devices, In-Application Programming (IAP) via USB and In-Circuit programming (ICP) Up to 5 Kbytes of RAM with up to 256 bytes stack Clock, Reset and Supply Management PLL for generating 48 MHz USB clock using a 12 MHz crystal Low Voltage Reset (except on E suffix devices) Dual supply management: analog voltage detector on the USB power line to enable smart power switching from USB power to battery (on E suffix devices). Programmable Internal Voltage Regulator for Memory cards (2.8V to 3.5V) supplying: Flash Card I/O lines (voltage shifting) Up to 50 mA for Flash card supply Clock-out capability 47 programmable I/O lines 15 high sink I/Os (8mA@0.6V / 20mA@1.3V) 5 true open drain outputs 24 lines programmable as interrupt inputs USB (Universal Serial Bus) Interface with DMA for full speed bulk applications compliant with USB 12 Mbs specification (version 2.0 compliant) On-Chip 3.3V USB voltage regulator and transceivers with software power-down 5 USB endpoints: 1 control endpoint 2 IN endpoints supporting interrupt and bulk 2 OUT endpoints supporting interrupt and bulk Hardware conversion between USB bulk packets and 512-byte blocks Device Summary
LQFP64 10x10
LQFP48
Mass Storage Interface DTC (Data Transfer Coprocessor): Universal Serial/Parallel communications interface, with software plug-ins for current and future protocol standards: Compact Flash - Multimedia Card Secure Digital Card - SmartMediaCard Sony Memory Stick - NAND Flash ATA Peripherals 2 Timers Configurable Watchdog for system reliability 16-bit Timer with 2 output compare functions. 2 Communication Interfaces SPI synchronous serial interface I2C Single Master Interface up to 400 KHz D/A and A/D Peripherals PWM/BRM Generator (with 2 10-bit PWM/ BRM outputs) 8-bit A/D Converter (ADC) with 8 channels Instruction Set 8-bit data manipulation 63 basic instructions 17 main addressing modes 8 x 8 unsigned multiply instruction True bit manipulation Development Tools Full hardware/software development package
Features Program memory User RAM (stack) - bytes Peripherals Operating Supply Package Operating Temperature Sep 2006
ST72651 32K ROM 5K (256)
ST72F651 32K FLASH
2
ST72652 16K ROM 512 (256) USB, DTC, WDT Single 4.0V to 5.5V LQFP64 (10 x10) / LQFP48 (7x7)
USB, DTC, Timer, ADC, SPI, I C, PWM, WDT Dual 2.7V to 5.5V or Dual 3.0V to 5.5V or 4.0V to 5.5V (for USB) 4.0V to 5.5V (for USB) LQFP64 (10 x10) 0C to +70C
Rev. 3.0
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Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4 READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.5 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.6 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.7 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.8 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.9 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.4 POWER SUPPLY MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.2 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.3 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.4 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.2 DATA TRANSFER COPROCESSOR (DTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.3 USB INTERFACE (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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11.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 11.5 PWM/BRM GENERATOR (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11.6 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.7 I²C SINGLE MASTER BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 11.8 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 13.10TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 13.11COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 144 13.128-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 14.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 14.3 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 154 15.1 OPTION BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . 155 15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 16 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 16.1 SPI MULTIMASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 16.2 IN-CIRCUIT PROGRAMMING OF DEVICES PREVIOUSLY PROGRAMMED WITH HARDWARE WATCHDOG OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 16.3 UNEXPECTED RESET FETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 16.4 I2C MULTIMASTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 17 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
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ST7265x
1 INTRODUCTION
The ST7265x MCU supports volume data exchange with a host (computer or kiosk) via a full speed USB interface. The MCU is capable of handling various transfer protocols, with a particular emphasis on mass storage applications. ST7265x is compliant with the USB Mass Storage Class specifications, and supports related protocols such as BOT (Bulk Only Transfer) and CBI (Control, Bulk, Interrupt). It is based on the ST7 standard 8-bit core, with specific peripherals for managing USB full speed data transfer between the host and most types of FLASH media card: A full speed USB interface with Serial Interface Engine, and on-chip 3.3V regulator and transceivers. A dedicated 24 MHz Data Buffer Manager state machine for handling 512-byte data blocks (this Figure 1. USB Data Transfer Block Diagram USB SIE DATA TRANSFER BU FFER 512-byte RAM Buffer 512-byte RAM Buffer D AT A TRANSFER COPROCESSOR (DTC) LEVEL SHIFTERS MASS STORAGE DEVICE size corresponds to a sector both on computers and FLASH media cards). A Data Transfer Coprocessor (DTC), able to handle fast data transfer with external devices. This DTC also computes the CRC or ECC required to handle Mass storage media. An Arbitration block gives the ST7 core priority over the USB and DTC when accessing the Data Buffer. In USB mode, the USB interface is serviced before the DTC. A FLASH Supply Block able to provide programmable supply voltage and I/O electrical levels to the FLASH media. Related Documentation AN1475: Developing an ST7265x Mass Storage Application
USB DATA TRANSFER BUFFER ACCESS ARBITR ATION
ST7 CORE
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INTRODUCTION (Cont'd) In addition to the peripherals for USB full speed data transfer, the ST7265x includes all the necessary features for stand-alone applications with FLASH mass storage. Low voltage reset ensuring proper power-on or power-off of the device (not on all products) Digital Watchdog 16-bit Timer with 2 output compare functions (not on all products - see device summary). Two 10-bit PWM outputs (not on all products see device summary)
Serial Peripheral interface (not on all products see device summary) Fast I2C Single Master interface (not on all products - see device summary) 8-bit Analog-to-Digital converter (ADC) with 8 multiplexed analog inputs (not on all products see device summary) The ST72F65x are the Flash versions of the ST7265x in a LQFP64 package. The ST7265x are the ROM versions in a LQFP64 package.
Figure 2. Digital Audio Player Application Example in Play Mode DATA TRANSFER BUFFER 512-byte RAM Buffer 512-byte RAM Buffer
BUFFER ACCESS AR BITRATION
ST7 CORE
DATA TRANSFER COPROCESSOR (DTC)
I2C
LEVEL SHIFTERS
MASS STORAGE DEVICE
DIGITAL AUDIO DEVICE
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INTRODUCTION (Cont'd) Figure 3. ST7265x Block Diagram
OSCIN OSCOUT
12MHz OSC 48MHz PLL
CLOCK DIVIDER f CPU
PORT A PORT B SPI * PORT C
PA[7:0] (8 bits) PB[7:0] (8 bits)
PC[7:0] (8 bits)
ARBITRATION
DATA TRANSFER BUFFER (1280 bytes)
DATA TRANSFER COPROCESSOR DTC S/W RAM (256 Bytes) PORT E PWM* PORT F I2C* 8-BIT ADC* VDDF VSSF VDDA VSSA VDD1,VDD2 DUAL SUPPLY MANAGER * VSS1, VSS2 USBVDD USBVSS PF[6:0] (7 bits) PE[7:0] (8 bits)
ADDRESS AND DATA BUS
USBDP USBDM USBVCC PD[7:0] (8 bits)
USB PORT D 16-BIT TIMER* WATCHDOG
RESET
CONTROL 8-BIT CORE ALU LVD* RAM (0.5/5 KBytes) PROGRAM MEMORY (16/32 Kbytes)
FLASH SUPPLY BLOCK POWER SUPPLY REGULATOR
VPP
* not available on all products (refer to Table 1: Device Summary)
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2 PIN DESCRIPTION
Figure 4. 48-Pin LQFP Package Pinout
USBVSS USBDM USBDP USBVCC USBVDD VDDF VSSF DTC/PB0 DTC/PB1 DTC/PB2 DTC/PB3 DTC/PB4
48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 3 34 33 4 32 5 31 6 30 7 ei1 29 8 28 9 27 10 ei0 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 DTC/PB5 DTC/PB6 DTC/PB7 DTC / PA0 DTC / PA1 DTC / PA2 DTC / PA3 DTC / PA4 DTC / PA5 DTC / PA6 DTC / PA7 VDD1
PF6 (HS) / ICCDATA PF5 (HS)/ICCCLK RESET VPP/ICCSEL PE4 PE3/DTC
OSCOUT OSCIN
VS S 2 VS S A VDDA VDD2
PE2 (HS) / DTC PE1 (HS) / DTC PE0 (HS) / DTC PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 VSS1
I/O pin supplied by VDDF / VSSF (HS) high sink capability eix associated external interrupt vector
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PIN DESCRIPTION (Cont'd) Figure 5. 64-Pin LQFP Package Pinout
O S C OU T OSCIN VSS2 VSSA VDDA VDD2 PF6 (HS)/ICCDATA PF5 (HS)/ICCCLK PF4 (HS) / USBEN PF3 / AIN1 PF2 / AIN0 PF1 (HS) / SDA PF0 (HS) / SCL RESET VPP/ICCSEL PE4 / PWM1 USBVS S USBDM USBD P USBVC C USBVDD VDDF VS S F DTC / PE5 (HS) DTC / PE6 (HS) DTC / PE7 (HS) DTC / PB0 DTC / PB1 DTC / PB2 DTC / PB3 DTC / PB4 DTC / PB5
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 ei1 40 9 39 10 38 11 37 12 36 13 35 14 ei0 ei2 ei2 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PE3 / PWM0 / AIN7 / DTC PE2 (HS) / AIN6 / DTC PE1 (HS) / AIN5 / DTC PE0 (HS) / AIN4 / DTC PD7 / AIN3 PD6 / AIN2 PD5/O C MP2 PD4/O C MP1 PD3 PD2 PD1 PD0 PC7 PC6 PC5 PC4
DTC / PB6 DTC / PB7 DTC / PA0 DTC / PA1 DTC / PA2 DTC / PA3 DTC / PA4 DTC / PA5 DTC / PA6 DTC / PA7 SS / MCO / (HS) PC0 MISO / DTC / (HS) PC1 MOSI / DTC / (HS) PC2 SCK / DTC / (HS) PC3 VD D1 VS S 1 8/163
I/O pin supplied by VDDF / VSSF (HS) high sink capability eix associated external interrupt vector
1
ST7265x
PIN DESCRIPTION (Cont'd) Legend / Abbreviations: Type: I = input, O = output, S = supply VDDF powered: I/O powered by the alternate supply rail, supplied by VDDF and VSSF. In/Output level: CT = CMOS 0.3VDD/0.7VDD with input trigger Output level: HS = High Sink (on N-buffer only)
Port and control configuration: Input:float = floating, wpu = weak pull-up, int = interrupt Output: OD = open drain, T = true open drain, PP = push-pull, OP = pull-up enabled by option byte. Refer to "I/O PORTS" on page 46 for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold.
Table 1. Device Pin Description
VDDF Powered Pin LQ FP48 LQ FP64 Type Pin Name Level O u tput Input Port / Control Input fl oat wpu int Output OD PP Main Function (after reset) Alternate Function
1 2 3
1 2 3
USBVSS USB DM USB DP
S I/O I/O
USB Digital ground USB bidirectional data (data -) USB bidirectional data (data +) USB power supply, output by the on-chip USB 3.3V linear regulator. Note: An external decoupling capacitor (typ. 100nF, min 47nF) must be connected between this pin and USBVSS. USB Power supply voltage (4V - 5.5V) also used by the regulator and PLL Note: External decoupling capacitors (typ. 4.7F+100nF, min 2.2F+100nFmust be connected between this pin and USBVSS. Power Line for alternate supply rail. Can be used as input (with external supply) or output (when using the on-chip voltage regulator). Note: An external decoupling capacitor (min. 20nF) must be connected to this pin to stabilize the regulator. Ground Line for alternate supply rail. Can be used as input (with external supply) or output (when using the on-chip voltage regulator) DTC I/O with serial capability Port E5 (MMC_CMD) DTC I/O with serial capability Port E6 (MMC_DAT) DTC I/O with serial capability Port E7 (MMC_CLK) Port B0 Port B1 Port B2 Port B3 DTC DTC DTC DTC
4
4
USB VCC
O
5
5
USB VDD
S
6
6
V DDF
S
X
7 8 9 10 11
7 8 9 10 11 12 13 14
V SSF PE5/DTC PE6/DTC PE7/DTC PB0/DTC PB1/DTC PB2/DTC PB3/DTC
S I/O I/O I/O I/O I/O I/O I/O
X X X X X X X X CT H S X2 ) CT H S X CT H S X CT CT CT CT X X X X X2 ) X X X X X X X X X
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VDDF Powered
Pin LQFP48 LQFP64 Type Pin Name
Level O u tput Input
Port / Control Input fl oat wpu int Output OD PP Main Function (after reset) Alternate Function
12 13 14 15 16 17 18 19 20 21 22 23 -
15 16 17 18 19 20 21 22 23 24 25 26 27 28
PB4/DTC PB5/DTC PB6/DTC PB7/DTC PA0/DTC PA1/DTC PA2/DTC PA3/DTC PA4/DTC PA5/DTC PA6/DTC PA7/DTC PC0/MCO /SS PC1/DTC/MIS0
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
X X X X X X X X X X X X X X
CT CT CT CT CT CT CT CT CT CT CT CT
X X X X X X X X ei0 X X X X X X X X X X X X
X X X X X X X X X X X X X X ei2
Port B4 Port B5 Port B6 Port B7 Port A0 Port A1 Port A2 Port A3 Port A4 Port A5 Port A6 Port A7 Port C0 Port C1
DTC DTC DTC DTC DTC DTC DTC DTC DTC DTC DTC DTC Main Clock Output / SPI Slave Select1) DTC I/O with serial capability (DATARQ) / SPI Master In Slave Out1) DTC I/O with serial capability (SDAT) / SPI Master Out Slave In1) DTC I/O with serial capability (SCLK) / SPI Serial Clock1)
CT HS X CT H S X
24 25 26 27 28 29 30 31 32 33
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
PC 2 / D T C / M O S I PC 3 / D T C / S C K V DD1 V SS1 PC4/ DT C PC5/ DT C PC6/ DT C PC7/ DT C PD0 PD1 PD2 PD3 PD4/OCM P1 PD5/OCM P2 PD6/AIN2 PD7/AIN3
I/O I/O S S I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
X X
CT HS X CT H S X
X X
Port C2 Port C3
Power supply voltage (2.7V - 5.5V) Digital ground CT CT CT CT CT CT CT CT CT CT CT CT X X ei2 X X X X X X ei1 X X X X X X X X X X X X Port D4 Port D5 Port D6 Port D7 X X X X X X X X X X Port C6 Port C7 Port D0 Port D1 Port D2 Port D3 Timer Output Compare 11) Timer Output Compare 21) Analog Input 21) Analog Input 31) DTC DTC X X Port C4 Port C5 DTC DTC
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VDDF Powered
Pin LQFP48 LQFP64 Type Pin Name
Level O u tput Input
Port / Control Input fl oat wpu int Output OD PP Main Function (after reset) Alternate Function
34 35 36 37 38 39
45 46 47 48 49 50
PE0/DTC/AIN4 PE1/DTC/AIN5 PE2/DTC/AIN6 PE3/AIN7/DTC/ PW M0 P E 4 / P W M1 VPP /ICCSEL
I/O I/O I/O I/O I/O S
CT H S X CT H S X CT H S X CT CT X X
X X X X X
X X X X X
Port E0 Port E1 Port E2 Port E3 Port E4
Analog Input 41)/ DTC Analog Input 51)/ DTC Analog Input 61)/ DTC Analog Input 71)/ DTC / PWM Output 01) PWM Output 11)
40
51
RES ET
I/O
X
X
Flash programming voltage. Must be held low in normal operating mode. Bidirectional. This active low signal forces the initialization of the MCU. This event is the top priority non maskable interrupt. This pin is switched low when the Watchdog has triggered or VDD is low. It can be used to reset external peripherals. Port F0 Port F1 X X Port F2 Port F3 Port F4 Port F5 Port F6 I2C Serial Clock1) I2C Serial Data1) Analog Input 01) Analog Input 11) USB Power Management USB Enable (alternate function selected by option bit) ICC Clock Output ICC Data Input
41 42 43 44 45 46 47 48
52 53 54 55 56 57 58 59 60 61 62 63 64
PF0 / SCL PF1 / SDA PF2 / AIN0 PF3 / AIN1 PF4 / USBEN PF5 / ICCCLK PF6 / ICCDATA V DD2 V DDA V SSA V SS2 O SCIN O SCOUT
I/O I/O I/O I/O I/O I/O I/O S S S S I O
CT HS X CT HS X CT CT X X
T T
CT H S X CT H S X CT H S X
T T T
Main Power supply voltage (2.7V - 5.5V on devices without LVD, otherwise 4V - 5.5V). Analog supply voltage Analog ground Digital ground Input/Output Oscillator pins. These pins connect a 12 MHz parallel-resonant crystal, or an external source to the on-chip oscillator.
Notes: 1. If the peripheral is present on the device (see Device Summary on page 1) 2. A weak pull-up can be enabled on PE5 input and open drain output by configuring the PEOR register and depending on the PE5PU bit in the option byte.
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Figure 6. Multimedia Card Or Secure Digital Card Writer Application Example
4.7F 100nF
V DD
USBVDD =4.0-5.5V USB Port
5V
USBVDD
1.5K USB
VCC
100nF
DP DM GND DP DM USB GND
USB
POWER MANAGEMENT (2)
I/O LOGIC
LED1
LED2 DTC REGULATOR FLASH level translator
PE7 PE6 PE5 VPP
VDDF
12V for Flash prog. (connect to GND if not used)
CLK DAT CMD
100nF
VDD
UP TO 5 MULTIMEDIA
OR SD CARDS
MultiMedia Card Pin ST72F65 pin ST7 / DTC (1) (1) This line shows if the ST72F65 pin is controlled by the ST7 core or by the DTC. (2) As this is a single power supply application, the USBEN function in not needed. Thus PF4/USBEN pin can be
C MD PE5 DTC
DAT P E6 D TC
CLK PE7 DTC
used as a normal I/O by configuring it as such by the option byte.
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Figure 7. Smartmedia Card Writer Or Flash Drive Application Example
4.7F 100nF
V DD
USBVDD =4.0-5.5V USB Port
5V
USBVDD
1.5K USB
VCC
100nF
DP DM GND DP DM USB GND
USB
POWER MANAGEMENT (4) I/O LOGIC REGULATOR
LED1
DTC
LED2
5 level translator VDDF
PB PA PE
1
FLASH
VPP
12V for Flash prog. (connect to GND if not used)
8
100nF
I/O
6
2
CTRL
0~7
VDD
UP TO 2 SMARTMEDIA
CARDS
Table 2. SmartMedia Interface Pin Assignment
SmartMedia Pin ST72F65 pin ST7 / DTC (1) I /O0~7 P B0-7 DTC CLE PA0 DTC WE PA1 DTC ALE PA 2 DTC RE PA3 DTC R/B PA4 DTC WP(2) PA7 ST7 CE1(2) PE1 ST 7 CE2(2)(3) PE0 ST7
(1): This line shows if the ST72F65 pin is controlled by the ST7 core or the DTC. (2): These lines are not controlled by the DTC but by the user software running on the ST7 core. The ST72F65 pin choice is at customer discretion. The pins shown here are only shown as an example. (3): When a single card is to be handled, PA7 is free for other functions. When 2 Smartmedia are to be handled, pins from both cards should be tied together (i.e. CLE1
with CLE2...) except for the CE pins. CE pin from card 1 should be connected to PA6 and CE pin from card 2 should be connect to PA7. Selection of the operating card is done by ST7 software. (4) As this is a single power supply application, the USBEN function in not needed. Thus PF4/USBEN pin can be used as a normal I/O by configuring it as such by the option byte.
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Figure 8. Compact Flash Card Writer Application Example
4.7F 100nF
VD D
USBVDD =4.0-5.5V USB Port
5V
USBVDD
1.5K USB
VCC
100nF
DP DM GND DP DM USB GND
USB
POWER MANAGEMENT 3)
I/O LOGIC
REGULATOR LED1
LED2 DTC FLASH 5 level translator
PA PB PE [2]
4.7K
1 VDDF
VPP
12V for Flash prog. (connect to GND if not used)
6
8
4.7F
CF 8-BIT MEMORY MODE
100nF
Table 3. Compact Flash Card Writer Pin Assignment
IORD, Compact Flash RESET, D0-7 D8-15 CS1, INPACK, IOWR, REG, A0-2 GND, Card Pin CE2, VCC BVD1, BVD2 A3-10 VS1, VS2, WAIT, CSEL,
CE1
RE WE
CD1
CD 2, RDY/BSY, WP NC -
ST72F65 pin ST7 / DTC 1)
PB0-7 NC D TC -
NC -
V DDF Power
PE2 PA6 VSSF PA0-2 +pull-up PA3 PA5 +pull-up 4.7k 100k Power DTC ST7 DTC DTC ST7
Notes: 1. This line shows if the ST72F65 pin is controlled by the ST7 core or by the DTC. 2. These lines are not controlled by the DTC but by the user software running on the ST7 core. The choice of
ST72F65 pin is at the customer's discretion. The pins shown here are given only as an example. 3. As this is a single power supply application, the USBEN function in not needed. Thus PF4/USBEN pin can be used as a normal I/O by configuring it as such by the option byte.
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Figure 9. Sony Memory Stick Writer Ap3plication Example
4.7F 100nF
V DD
USBVDD =4.0-5.5V USB Port
5V
USBVDD
1.5K USB
VCC
100nF
DP DM GND DP DM USB GND
USB
POWER MANAGEMENT 2)
I/O LOGIC
LED1
LED2 DTC REGULATOR FLASH level translator
PC0 PC3 PC1 PC2 VPP
VDDF
12V for Flash prog. (connect to GND if not used)
CD CLK BS DAT 4.7F 100nF
VDD
SONY MEMORY STICK
MultiMedia Card Pin ST72F65 pin ST7 / DTC (1) (1) This line shows if the ST72F65 pin is controlled by the ST7 core or by the DTC. (2) As this is a single power supply application, the USBEN function in not needed. Thus PF4/USBEN pin can be
C MD PE5 DTC
DAT P E6 D TC
CLK PE7 DTC
used as a normal I/O by configuring it as such by the option byte.
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3 REGISTER & MEMORY MAP
As shown in Figure 10, the MCU is capable of addressing 64 Kbytes of memories and I/O registers. The available memory locations consist of 80 bytes of register locations, up to 5 Kbytes of RAM and up to 32 Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh. The highest address bytes contain the user reset and interrupt vectors. IMPORTANT: Memory locations noted "Reserved" must never be accessed. Accessing a reserved area can have unpredictable effects on the device. Related Documentation AN985: Executing Code in ST7 RAM
Figure 10. Memory Map
0050h 0000h 004Fh 0050h
HW Registers (see Table 4) 512 Bytes RAM*
00FFh 0100h 01FFh 0200h
Short Addressing RAM (176 Bytes) Stack (256 Bytes)
5 KBytes RAM* 144Fh 1450h DTC RAM (Write protected)
154Fh
256 Bytes USB Data Buffer** 1280 Bytes Reserved
16-bit Addressing RAM (80 Bytes)
024Fh
1A4Fh 7FFFh 8000h
0050h 00FFh 0100h 01FFh 0200h
Short Addressing RAM (176 Bytes) Stack (256 Bytes)
Program Memory* 32 Kbytes
C000h
16 Kbytes
144Fh FFDFh FFE0h
16-bit Addressing RAM (4688 Bytes)
FFFFh
Interrupt & Reset Vectors (see Table 10)
* Program memory and RAM sizes are product dependent (see Table ) ** The ST7 core is not able to read or write in the USB data buffer if the ST7265x is running at 6Mz in standalone mode.
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Table 4. Hardware Register Memory Map
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h to 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh DTC DSM SPI PC R SPIDR SPICR SPICSR DTCCR DTCSR Reserved DTCPR DTC Pointer Register 00h R/W Power Control Register SPI Data I/O Register SPI Control Register SPI Control/Status Register DTC Control Register DTC Status Register 00h 00h 00h xxh 0xh 00h R/W R/W R/W R/W R/W R/W Reserved Area (3 bytes) A D C1 WDG ADCDR ADCCS R WD G C R PCDR PCDDR PCOR PDDR PDDDR PDOR PEDR PEDDR PEOR PFDR PFDDR Block Register Label PADR PADDR PAOR PBDR PBDDR Register name Port A Data Register Port A Data Direction Register Port A Option Register Port B Data Register Port B Data Direction Register Reserved Area (1 byte) Port C Data Register Port C Data Direction Register Port C Option Register Port D Data Register Port D Data Direction Register Port D Option Register Port E Data Register Port E Data Direction Register Port E Option Register Port F Data Register Port F Data Direction Register Reserved Area (1 byte) ADC Data Register ADC Control Status Register Watchdog Control Register 00h 00h 7Fh Read only R/W R/W 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Status 00h 00h 00h 00h 00h Remarks R/W R/W R/W R/W R/W
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Address 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh
Block
Register Label TCR1 TCR2 TSR CHR CLR
Register name Timer Control Register 1 Timer Control Register 2 Timer Status Register Timer Counter High Register Timer Counter Low Register Timer Alternate Counter High Register Timer Alternate Counter Low Register Timer Output Compare 1 High Register Timer Output Compare 1 Low Register Timer Output Compare 2 High Register Timer Output Compare 2 Low Register Flash Control Status Register
Reset Status 00h 00h 00h FFh FCh FFh FCh 80h 00h 80h 00h 00h FFh FFh FFh FFh 00h 00h 06h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
Remarks R/W R/W Read Only Read Only Read Only Read Only Read Only R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Read only Read only R/W
TIM
ACHR ACLR OC1HR OC1LR OC2HR OC2LR
Flash ITSP R0 ITC ITSP R1 ITSP R2 ITSP R3 USBISTR USBIMR USBCTLR DADDR USBSR EP0R CNT0RXR USB CNT0TXR EP1RXR CNT1RXR EP1TXR CNT1TXR EP2RXR CNT2RXR EP2TXR CNT2TXR I2CC R I2CS R1 I2CS R2 I2C 1 I2CC CR Not used Not used I2CD R USB BUFCSR
Interrupt Software Priority Register 0 Interrupt Software Priority Register 1 Interrupt Software Priority Register 2 Interrupt Software Priority Register 3 USB Interrupt Status Register USB Interrupt Mask Register USB Control Register Device Address Register USB Status Register Endpoint 0 Register EP 0 Reception Counter Register EP 0 Transmission Counter Register Endpoint 1 Register EP 1 Reception Counter Register Endpoint 1 Register EP 1 Transmission Counter Register Endpoint 2 Register EP 2 Reception Counter Register Endpoint 2 Register EP 2 Transmission Counter Register I2C I2C Control Register Status Register 2 I2C Status Register 1 I2C Clock Control Register
I2C Data Register Buffer Control/Status Register Reserved Area (1 Byte)
00h 00h
R/W R/W
MISCR1 MISCR2
Miscellaneous Register 1 Miscellaneous Register 2 Reserved Area (1 Byte)
00h 00h
R/W R/W
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Address 004Ch 004Dh 004Eh 004Fh
Block
Register Label MISCR3 PWM 0
Register name Miscellaneous Register 3 10-bit PWM/BRM registers
Reset Status 00h 80h 00h 80h
Remarks R/W R/W R/W R/W
PWM1)
BRM10 PWM 1
Note 1. If the peripheral is present on the device (see Device Summary on page 1)
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4 FLASH PROGRAM MEMORY
4.1 Introduction The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external VPP supply. The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming). The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 Main Features
Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (see Table 5). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required. The first two sectors have a fixed size of 4 Kbytes (see Figure 11). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000hFFFFh). Table 5. Sectors available in Flash devices
Flash Memory Size (bytes) 4K Available Sectors Sector 0 Sectors 0,1 Sectors 0,1, 2
Three Flash programming modes: Insertion in a programming tool. In this mode, all sectors including option bytes can be programmed or erased. ICP (In-Circuit Programming). In this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board. IAP (In-Application Programming) In this mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board and while the application is running. ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM Read-out protection Register Access Security System (RASS) to prevent accidental programming or erasing
8K > 8K
4.4 Read-out Protection Read-out protection, when selected, provides a protection against Program Memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. In Flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased and the device can be reprogrammed. Read-out protection selection depends on the device type: In Flash devices it is enabled and removed through the FMP_R bit in the option byte. In ROM devices it is enabled by mask option specified in the Option List.
4.3 Structure The Flash memory is organised in sectors and can be used for both code and data storage.
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Figure 11. Memory Map and Sector Address
4K
1000h 3FFFh 7FFFh 9FFFh BFFFh D7FFh DFFFh EFFFh FFFFh
8K
10K
16K
24K
32K
48K
60K
DV FLASH MEMORY SIZE
SECTOR 2 2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes 52 Kbytes 4 Kbytes 4 Kbytes SECTOR 1 SECTOR 0
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FLASH PROGRAM MEMORY (Cont'd) 4.5 ICC Interface ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see Figure 12). These pins are: RESET: device reset VSS: device power supply ground Figure 12. Typical ICC Interface
PROGRAMMING TOOL ICC CONNECTOR ICC Cable APPLICATION BOARD (See Note 3) OPTIONAL (See Note 4) ICC CONNECTOR HE10 CONNECTOR TYPE 9 10 7 8 5 6 3 4 1 2 APPLICATION RESET SOURCE See Note 2 10k APPLICATION POWER SUPPLY CL2 CL1 See Note 1 APPLICATION I/O
ICCCLK: ICC output serial clock pin ICCDATA: ICC input/output serial data pin ICCSEL/VPP: programming voltage OSC1(or OSCIN): main clock input for external source (optional) VDD: application board power supply (see Figure 12, Note 3)
ST7
Notes: 1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values. 2. During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset man-
agement IC with open drain output and pull-up resistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session. 3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual. 4. Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case.
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ICCSEL/VPP
ICCDATA
RESET
ICCCLK
OSC2
OSC1
VDD
VSS
ST7265x
FLASH PROGRAM MEMORY (Cont'd) 4.6 ICP (In-Circuit Programming) To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool. Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 12). For more details on the pin locations, refer to the device pinout description. 4.7 IAP (In-Application Programming) This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool). This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). For example, it is possible to download code from the SPI, SCI, USB or CAN interface and program it in the Flash. IAP mode can be used to program any of the Flash Table 6. FLASH Register Map and Reset Values
Address (Hex.) 002Bh Register Label FC SR Reset Value 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0
7 0 0 0 0 0 0 0 0 0
sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.
4.8 Related Documentation For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual. 4.9 Register Description FLASH CONTROL/STATUS REGISTER (FCSR) Read / Write Reset Value: 0000 0000 (00h)
This register is reserved for use by Programming Tool software. It controls the Flash programming and erasing operations.
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5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES
5.3 CPU REGISTERS The six CPU registers shown in Figure 13 are not present in the memory mapping and are accessed by specific instructions. Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures. Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
Enable executing 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) Two 8-bit index registers 16-bit stack pointer Low power HALT and WAIT modes Priority maskable hardware interrupts Non-maskable software/hardware interrupts
Figure 13. CPU Registers
7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 0 CONDITION CODE REGISTER 1 1 I1 H I0 N Z C RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value 0 Y INDEX REGISTER 0 X INDEX REGISTER 0 ACCUMULATOR
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CENTRAL PROCESSING UNIT (Cont'd) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx
7
1 1 I1 H I0 N Z
Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test inst ructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions. Interrupt Management Bits Bit 5,3 = I1, I0 Interrupt The combination of the I1 and I0 bits gives the current interrupt software priority.
Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) I1 1 0 0 1 I0 0 1 0 1
0 C
The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Arithmetic Management Bits Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It's a copy of the result 7th bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions.
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See the interrupt management chapter for more details.
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CENTRAL PROCESSING UNIT (Cont'd) Stack Pointer (SP) Read/Write Reset Value: 01 FFh
15 0 7
SP7 SP6 SP5 SP4 SP3 SP2 SP1
8 0 0 0 0 0 0 1 0 SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 14). Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address. Figure 14. Stack Manipulation Example
CALL Subroutine @ 0100h Interrupt Event P USH Y
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 14. When an interrupt is received, the SP is decremented and the context is pushed on the stack. On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area.
PO P Y
IRET
RET or RSP
SP SP CC A X PC H SP PCH @ 01FFh PCL P CL PCH PCL Y CC A X PCH PCL PCH PC L SP CC A X PCH PCL PCH PCL SP PCH PCL SP
Stack Higher Address = 01FFh Stack Lower Address = 0100h
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6 SUPPLY, RESET AND CLOCK MANAGEMENT
6.1 CLOCK SYSTEM 6.1.1 General Description The MCU accepts either a 12 MHz crystal or an external clock signal to drive the internal oscillator. The internal clock (fCPU) is derived from the internal oscillator frequency (fOSC), which is 12 Mhz in Stand-alone mode and 48Mhz in USB mode. The internal clock (fCPU) is software selectable using the CP[1:0] and CPEN bits in the MISCR1 regis ter. In USBVDD power supply mode, the PLL is active, generating a 48MHz clock to the USB. In this mode, fCPU can be configured to be up to 8 MHz. In VDD mode the PLL and the USB clock are disabled, and the maximum frequency of fCPU is 6 MHz. The internal clock signal (fCPU) is also routed to the on-chip peripherals. The CPU clock signal consists of a square wave with a duty cycle of 50%. The internal oscillator is designed to operate with an AT-cut parallel resonant quartz in the frequency range specified for fosc. The circuit shown in Figure 16 is recommended when using a crystal, and Table 7 lists the recommended capacitance. The crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilisation time. Table 7. Recommended Values for 12-MHz Crystal Resonator
RSMAX COSCIN C OSCOUT 20 56pF 56pF 25 47pF 47pF 70 22pF 22pF
6.1.2 External Clock An external clock may be applied to the OSCIN input with the OSCOUT pin not connected, as shown on Figure 15. The tOXOV specifications does not apply when using an external clock input. The equivalent specification of the external clock source should be used instead of tOXOV (see Section 6.5 CONTROL TIMING). Figure 15. External Clock Source Connections
OSCIN
OSCOUT NC
EXTERNAL CLOCK
Figure 16. Crystal Resonator
OSCIN
OSCOUT
COSCIN
COSCOUT
Note: RSMAX is the equivalent serial resistor of the crystal (see crystal specification).
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6.2 RESET SEQUENCE MANAGER (RSM) 6.2.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 6.2.2: External RESET source pulse Internal LVD RESET (Low Voltage Detection) Internal WATCHDOG RESET These sources act on the RESET pin and it is always kept low during the delay phase. Figure 17. RESET Sequences VDD
VIT+(LVD) VIT-(LVD)
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases as shown in Figure 17: Active Phase depending on the RESET source Min 512 CPU clock cycle delay (see Figure 19 and Figure 20 RESET vector fetch
LVD RESET
SHORT EXT. RESET
LONG EXT. RESET
WATCHDOG RESET
RUN
ACTIVE PHASE
RUN
ACTIVE PHASE
RUN
ACTIVE PHASE
RUN
ACTIVE PHASE
RUN
tw(RSTL)out th(RSTL)in
EXTERNAL RESET SOURCE
tw(RSTL)out th(RSTL)in
DELAY
tw(RSTL)out
RESET PIN
WATCHDOG RESET WATCHDOG UNDERFLOW INTERNAL RESET (min 512 TCPU) VECTOR FETCH
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RESET SEQUENCE MANAGER (Cont'd) 6.2.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See electrical characteristics section for more details. A RESET signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized. This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode. The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. If the external RESET pulse is shorter than tw(RSTL)out (see short ext. Reset in Figure 17), the signal on the RESET pin will be stretched. Otherwise the delay will not be applied (see long ext. Reset in Figure 17). Figure 18. Reset Block Diagram Starting from the external RESET pulse recognition, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out. 6.2.3 Internal Low Voltage Detection RESET Two different RESET sequences caused by the internal LVD circuitry can be distinguished: Power-On RESET Voltage Drop RESET The device RESET pin acts as an output that is pulled low when VDD
VDD
f CPU
COUNTER
INTERNAL RESET
RON
RESET
PULSE GENERATOR
WATCHDOG RESET LVD RESET
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RESET SEQUENCE MANAGER (Cont'd) In stand-alone mode, the 512 CPU clock cycle delay allows the oscillator to stabilize and ensures that recovery has taken place from the Reset state. Figure 19. Reset Delay in Stand-alone Mode
RESET
In USB mode the delay is 256 clock cycles counted from when the PLL LOCK signal goes high. The RESET vector fetch phase duration is 2 clock c ycles.
DELAY
512 x tCPU(STAND-ALONE)
FETCH VECTOR
Figure 20. Reset Delay in USB Mode
RESE T
DELAY
256 x tCPU(STAND-ALONE) PLL Startup time (undefined) 400 s typ.
256 x tCPU(USB) FETCH VECTOR
Note: For a description of Stand-alone mode and USB mode refer to Section 6.4.
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6.3 LOW VOLTAGE DETECTOR (LVD) To allow the integration of power management features in the application, the Low Voltage Detector function (LVD) generates a static reset when the VDDA supply voltage is below a VIT- reference value. This means that it secures the power-up as well as the power-down, keeping the ST7 in reset. The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD Reset circuitry generates a reset when VDDA is below: VIT+ when VDDA is rising VIT- when VDDA is falling The LVD function is illustrated in Figure 21. During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Note: It is recommended to make sure that the VDDA supply voltage rises monotonously when the device is exiting from Reset, to ensure the application functions properly.
Figure 21. Low Voltage Detector vs Reset VDDA
V hyst VIT+(LVD) VIT-(LVD)
RESET
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6.4 POWER SUPPLY MANAGEMENT 6.4.1 Single Power Supply Management In applications operating only when connected to the USB (Flash writers, Backup systems), the microcontroller must operate from a single power supply (i.e. USB bus power supply or the local power source in the case of self-powered devices). Devices with LVD (no E suffix) or without LVD (E suffix) can support this configuration. In order to enable the Single Power Supply Management, the PLGIE bit in the PCR register should kept cleared by software (reset default value). In this case, pin VDD and USBVDD of the microcontroller must be connected together and supplied by a 4.0 to 5.5V voltage supply, either from the USB cable or from the local power source. See Figure 22. F . igure 22. Single Power Supply Mode Stand-alone Mode and USB Mode. This configuration is only available on devices without LVD (E suffix). Devices with LVD are kept under reset when the power supply drops below the LVD threshold voltage and thus Stand-Alone mode can not be entered. In order to enable Dual Power Supply Management: the USBEN pin function must be selected by programming the option byte. the user software must set the PLGIE bit in the PCR register in the initialization routine. Stand-Alone Mode This mode is to be used when no USB communication is needed. The microcontroller in this mode can run at very low voltage, making the design of low power / battery supplied systems easy. In this mode: The USB cable is unplugged (no voltage input on USBVDD pin) The PLL is off The on-chip USB interface is disabled The core can run at up to 6 MHz internal frequency The DTC operates at a frequency of 6MHz USBEN is kept floating by H/W. The microcontroller is supplied through the VDD pin USB Mode When connected to the USB, the microcontroller can run at full speed, still saving battery power by using USB power or self power source. To go into USB mode, a voltage from 4.0V to 5.5V must be provided to the USBVDD pin. In this mode: The USB cable is plugged in USBVDD pin is supplied by a 4.0 to 5.5V supply voltage, either from the USB cable or from the self powering source The PLL is running at 48 MHz The on-chip USB interface is enabled The core can run at up to 8 MHz internal frequency The DTC operates at a frequency of 24MHz USBEN is set to output low level by hardware. This signal can be used to control an external transistor (USB SWITCH) to change the power supply configuration (see Figure 23). The microcontroller can be USB bus powered
VDD1 VDD2 VDDA
USBVDD 4.0 - 5.5 V Note: Ground lines not shown In this mode: The PLL is running at 48 MHz The on-chip USB interface is enabled The core can run at up to 8MHz internal frequency The microcontroller can be either USB bus powered or supplied by the local power source (self powered) The USBEN function is not used. The PF4 pin can be configured to work as a normal I/O by programming the Option Byte. 6.4.2 Dual Power Supply Management In case of a device that can be used both when powered by the USB or from a battery (Digital Audio Player, Digital Camera, PDA), the microcontroller can operate in two power supply modes: ST7
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POWER SUPPLY MANAGEMENT (Cont'd) 6.4.2.1 Switching from Stand-Alone Mode to USB Mode In Stand-Alone Mode, when the user plugs in the USB cable, 4V min. is input to USBVDD. The onchip power Supply Manager generates an internal interrupt when USBVDD reaches USBVIT+ (if the PLGIE bit in the PCR register is set). The user program then can finish the current processing, and MUST generate a software RESET afterwards. This puts the microcontroller into reset state and all I/O ports go into input high impedance mode. Figure 23. External Power Supply Switch
Step-up converter (Note 3)
During and after this (software induced) reset phase, the USBEN pin is set to output low level by hardware. This causes the USB SWITCH to be turned ON. Consequently, VDD pin is powered by USBVDD supply. See Figure 23. Once in USB mode, no power is drawn from the step-up converter output. For more details, refer to Figure 24.
VDD1
PMOS
(Note 2) USB SWITCH
VDD2 VDDA USBEN
Option bit
General Purpose I/O (I/O port DR, DDR) Alternate Function (USBEN)
EDGE DETECTOR WITH LATCH Interrupt Request
(True OD, H/W ctrl) USBVDD
PLL
USB VOLTAGE DETECTOR
VITPF VITMF PLG PLGIE
DETEN
PCR REGISTER
S/W RESET
4V min. from USB
USBVIT+ USBVIT-
RESET LOGIC
USBEN H/W CONTROL
USBVIT+ USBVITUSBVDD PLG bit
VDDF ST7 Note 1: Ground lines not shown
REGULATOR
VITMF Bit VITPF Bit
Note 2: Suggested device: STN3PF06 (STMicroelectronics) Note 3: To allow USB cable unplug detection, output voltage of step-up converter should be low enough to not enduce (through PMOS substrate diode) voltage greater than USBVITon USBVDD pin
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POWER SUPPLY MANAGEMENT (Cont'd) 6.4.2.2 Switching from USB Mode to StandAlone Mode In USB Mode, when the user unplugs the USB cable, the voltage level drops on the USBVDD line. The on-chip Power Supply Manager generates a PLG interrupt when USBVDD reaches USBVIT-. The user program then can finish the current processing, and MUST generate a software RESET. Caution: Care should be taken as during this period the microcontroller clock is provided from the PLL output. Functionality in this mode is not guaranteed for voltages below VPLLmin. Caution: When the VDDF is supplied externally by a voltage higher than the detector thresholds, the USBVDD voltage continues to be driven by the protection diode between VDDF and USBVDD. In this configuration, the detector will not detect a voltage drop and can not be used. Software must ensure that the software RESET is generated before VDD. drops below VPLLmin. Failing to do this will cause the clock circuitry to stop, freezing the microcontroller operations.
Once the user program has executed the software reset, the microcontroller goes into reset state and all I/O ports go into floating input mode. During and after this (software induced) reset phase, the USBEN pin is put in high impedance by hardware. It causes the USB SWITCH to be turned OFF, so USBVDD is disconnected from VDD. The PLL is automatically stopped and the internal frequency is provided by a division of the crystal frequency. Refer to Figure 24. The microcontroller is still powered by the residual USBVDD voltage (higher than step-up converter set output level). This VDD voltage decreases during the reset phase until it reaches the step-up converter set output voltage. At that time, step-up converter resumes operation, and powers the application. Caution: In order to avoid applying excessive voltage to the Storage Media, a minimum delay must be ensured during (and after if needed) the reset phase, prior to switching ON the external STORAGE switch.
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POWER SUPPLY MANAGEMENT (Cont'd) Figure 24. Power Supply Management: Dual Power Supply
STAND-ALONE SUPPLY S UPPLY V OL T A G E S USBVIT+ USBVITVPLLmin48
USBVDD
PLG INTERRUPT R EQUEST R ESET S/W STATUS
RE SET
STAND-ALONE PROCESSING
1
2
RESE T
USB MODE PROCESS.
1 2 RST STAND-ALONE MODE RESET PROCESSING
S/W Reset
S/W Reset
U SBEN
HI-Z
ON
HI-Z
USB MODE VIT+(LVD) STAND-ALONE STAND-ALONE VIT-(LVD)
VDD pin
voltage PLL ON/OFF 48 MHz SIGNAL CLOCK S OU R C E
PLL OFF
PLL ON
PLL OFF
NO CLOCK
UND E 3 FINED
STABLE 48 MHz 4
NO CLOCK
CRYSTAL (12MHz)
PLL
CRYSTAL (12MHz)
1. Interrupt processing 2. Finish current processing 3. PLL start-up time (automatically controlled by hardware following a software reset) 4. PLL running with frequency in the range of 48 to 24 MHz (see section 13.3.3 on page 128)
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POWER SUPPLY MANAGEMENT (Cont'd) 6.4.3 Storage Media Interface I/Os The microcontroller is able to drive Storage Media through an interface operating at a different voltage from the rest of the circuit. This is achieved by powering the Storage Media interface I/O circuitry through a specific supply rail connected to VDDF pin. The VDDF pin can be used either as an input or output. If the on-chip voltage regulator is off, power to the interface I/Os should be provided externally to the VDDF pin. This should be the case when in StandAlone Mode, or in USB mode when the current required to power the Storage Media is above the current capacity of the on-chip regulator. If the on-chip voltage regulator is on, it powers the interface I/Os, and VDDF pin can supply the Storage Media. This is recommended in USB Mode, when the current required to power the Storage Media is within the capacity of the on-chip regulator. Caution: If VDDF is supplied externally, the regulator must not be enabled. Important Note: If VDDF is not present, all VDDF-driven I/Os cannot be used and are tied to ground. Refer to Section 9.2.4 for more details. Application Example: Stand-Alone Mode The Storage Media interface supply is powered by VDD enabled by an external switch which connects VDD to VDDF. This switch can be driven by any True Open Drain I/O pin and controlled by user software.
The on-chip voltage regulator must be disabled to avoid any conflict and to decrease consumption (reset the REGEN bit in the PCR register). USB Mode In this case the core of the microcontroller is running from the USB bus power or the self power supply. VDD and USBVDD pins are supplied with a voltage from 4.0 to 5.5V. The Storage Media Interface can be powered through the on-chip regulator (providing power to the I/O pins and output on pin VDDF) if the current requirement is within the output capacity of the on chip regulator. The regulator output voltage can be programmed to 2.8V, 3.3V, 3.4V or 3.5 Volts, depending on the Storage Media specifications. (see VSET[1:0] bits in PCR register description) Should the current requirement for the Storage Media be higher than the current capacity of the on chip regulator, an external regulator should be used. Thus the on-chip voltage regulator must be disabled to avoid any conflict (reset the REGEN bit in the PCR register). Caution: The user should ensure that VDD does not exceed the maximum rating specified for the Storage Media VDDF max when switching STORAGE switch on.
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POWER SUPPLY MANAGEMENT (Cont'd) 6.4.4 Register Description POWER CONTROL REGISTER (PCR) Reset Value: 0000 0000 (00h)
7 ITPF ITM F PLG PLG IE V SE T1 VSE T0 DET EN 0 REG EN
Bit 3:2 = VSET[1:0] Voltage Regulator Output Voltage. These bits are set and cleared by software to select the output voltage of the on-chip voltage regulator (for the VDDF output).
VSE VSE T1 T0 0 0 0 1 1 0 1 1 Voltage output of the regulator 3.5V 3.4V 3.3V 2.8V
Bit 7 = ITPF Voltage Input Threshold Plus Flag This bit is set by hardware when USBVDD rises over USBVIT+ and cleared by hardware when USBVDD drops below USBVIT+. 0: USBVDD < USBVIT+ 1:USBVDD > USBVIT+ Bit 6 = ITMF Voltage Input Threshold Minus Flag This bit is set by hardware when USBVDD rises over USBVIT- and cleared by hardware when USBVDD drops below USBVIT-. 0: USBVDD < USBVIT1:USBVDD > USBVITBit 5 = PLG USB Plug/Unplug detection. This bit is set by hardware when it detects that the USB cable has been plugged in. It is cleared by hardware when the USB cable is unplugged. (Detection happens when USBVDD rises over USBVIT+ or when USBVDD drops below USBVIT-). If the PLGIE bit is set, the rising/falling edge of the PLG bit also generates an interrupt request. This interrupt is able to wake up the ST7 core from Halt mode. 0: USB cable unplugged 1: USB cable plugged in Bit 4 = PLGIE USB Plug/Unplug Interrupt Enable. This bit is set and cleared by software. 0: Single supply mode: PLG interrupt disabled. 1: Dual supply mode: PLG interrupt enabled (generates an interrupt on the rising/falling edge of PLG).
Bit 1 = DETEN USB Voltage Detector Enable. This bit is set and cleared by software. It is used to power-off the USB voltage detector in Stand-alone mode to reduce unnecessary power consumption, especially in HALT mode. 0: The USB voltage detector is enabled. 1: The USB voltage detector disabled (ITPF, ITMF and PLG bits are forced high) Bit 0 = REGEN Voltage Regulator Enable. This bit is set and cleared by software. 0: The regulator is completely shutdown and no current is drawn from the power supply by the voltage reference. 1: The on-chip voltage regulator is powered-on. Related Documentation AN1529: Extending the current & voltage capability on the ST7265 VDDF Supply
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7 INTERRUPTS
7.1 INTRODUCTION The CPU enhanced interrupt management provides the following features: Hardware interrupts Software interrupt (TRAP) Nested or concurrent interrupt management with flexible interrupt priority and level management: Up to 4 software programmable nesting levels Up to 16 interrupt vectors fixed by hardware 3 non maskable events: RESET, TRAP, TLI This interrupt management is based on: Bit 5 and bit 3 of the CPU CC register (I1:0), Interrupt software priority registers (ISPRx), Fixed interrupt vector addresses located at the high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order. This enhanced interrupt controller guarantees full upward compatibility with the standard (not nested) CPU interrupt controller. 7.2 MASKING AND PROCESSING FLOW The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector (see Table 8). The processing flow is shown in Figure 25. Figure 25. Interrupt Processing Flowchart
RESET PENDING INTERRUPT N Y TLI Interrupt has the same or a lower software priority than current one N I1:0 Interrupt has a higher software priority than current one Y
When an interrupt request has to be serviced: Normal processing is suspended at the end of the current instruction execution. The PC, X, A and CC registers are saved onto the stack. I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx registers of the serviced interrupt vector. The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to "Interrupt Mapping" table for vector addresses). The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume. Table 8. Interrupt Software Priority Levels
Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) Level Low I1 1 0 0 1 I0 0 1 0 1
High
FETCH NEXT INSTRUCTION
THE INTERRUPT STAYS PENDING
Y
"IRET" N
RESTORE PC, X, A, CC FROM STACK
EXECUTE INSTRUCTION
STACK PC, X, A, CC LOAD I1:0 FROM INTERRUPT SW REG. LOAD PC FROM INTERRUPT VECTOR
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INTERRUPTS (Cont'd) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: the highest software priority interrupt is serviced, if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first. Figure 26 describes this decision process. Figure 26. Priority Decision Process
PENDING INTERRUPTS
TLI (Top Level Hardware Interrupt) This hardware interrupt occurs when a specific edge is detected on the dedicated TLI pin. Caution: A TRAP instruction must not be used in a TLI service routine. TRAP (Non Maskable Software Interrupt) This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the flowchart in Figure 25 as a TLI. Caution: TRAP can be interrupted by a TLI. RESET The RESET source has the highest priority in the CPU. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See the RESET chapter for more details.
Same
SOFTWARE PRIORITY
Different
HIGHEST SOFTWARE PRIORITY SERVICED HIGHEST HARDWARE PRIORITY SERVICED
When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. Note 1: The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt. Note 2: RESET, TRAP and TLI can be considered as having the highest software priority in the decision process. Different Interrupt Vector Sources Two interrupt source types are managed by the CPU interrupt controller: the non-maskable type (RESET, TRAP, TLI) and the maskable type (external or from internal peripherals). Non-Maskable Sources These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see Figure 25). After stacking the PC, X, A and CC registers (except for RESET), the corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level 3). These sources allow the processor to exit HALT mode.
Maskable Sources Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending. External Interrupts External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitivity is software selectable through the ISx bits in the MISCR1 and MISCR3 registers. External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically NANDed. Peripheral Interrupts Usually the peripheral interrupts cause the Device to exit from HALT mode except those mentioned in the "Interrupt Mapping" table. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear sequence is executed.
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INTERRUPTS (Cont'd) 7.3 INTERRUPTS AND LOW POWER MODES All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT modes (see column "Exit from HALT" in "Interrupt Mapping" table). When several pending interrupts are present while exiting HALT mode, the first one serviced can only be an interrupt with exit from HALT mode capability and it is selected through the same decision process shown in Figure 26. Note: If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced. Figure 27. Concurrent Interrupt Management
SOFTW ARE PRIORITY LEVEL IT2 IT1 IT4 IT3 TLI IT0 I1 I0
7.4 CONCURRENT & NESTED MANAGEMENT The following Figure 27 and Figure 28 show two different interrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in Figure 28. The interrupt hardware priority is given in this order from the lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0, TLI. The software priority is given for each interrupt. Warning: A stack overflow may occur without notifying the software of the failure.
HARDWARE PRIORITY
TLI IT0 IT1 IT2 IT3 RIM IT4 MAIN MAIN IT1
3 3 3 3 3 3 3/0 10
11 11 11 11 11 11
11 / 10 Figure 28. Nested Interrupt Management
SOFTW ARE PRIORITY LEVEL
TLI
IT0
IT2
IT1
IT4
IT3
I1
I0
HARDWARE PRIORITY
TLI IT0 IT1 IT2 IT3 RIM IT4 MAIN IT4 MAIN IT1 IT2
3 3 2 1 3 3 3/0 10
11 11 00 01 11 11
11 / 10
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USED STACK = 20 BY TES
USED STACK = 10 BYTES
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INTERRUPTS (Cont'd) 7.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read / Write Reset Value: 111x 1010 (xAh)
7 1 1 I1 H I0 N Z 0 C ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I0_9 I1_4 I1_8 I0_4 I0_8
INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX) Read/Write (bit 7:4 of ISPR3 are read only) Reset Value: 1111 1111 (FFh)
7 ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 0 I0_0
Bit 5, 3 = I1, I0 Software Interrupt Priority These two bits indicate the current interrupt software priority.
Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable*) Level Low I1 1 0 0 1 I0 0 1 0 1
ISPR2 ISPR3
I1_11 I0_11 I1_10 I0_10 I1_9 1 1 1 1
I1_13 I0_13 I1_12 I0_12
High
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see "Interrupt Dedicated Instruction Set" table). *Note: TLI, TRAP and RESET events can interrupt a level 3 program.
These four registers contain the interrupt software priority of each interrupt vector. Each interrupt vector (except RESET and TRAP) has corresponding bits in these registers where its own software priority is stored. This correspondance is shown in the following table.
Vector address FFFBh-FFFAh FFF9h-FFF8h ... FFE1h-FFE0h ISPRx bits I1_0 and I0_0 bits* I1_1 and I0_1 bits ... I1_13 and I0_13 bits
Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits in the CC register. Level 0 can not be written (I1_x=1, I0_x=0). In this case, the previously stored value is kept. (example: previous=CFh, write=64h, result=44h) The RESET, TRAP and TLI vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set. *Note: Bits in the ISPRx registers which correspond to the TLI can be read and written but they are not significant in the interrupt process management. Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behaviour has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x).
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INTERRUPTS (Cont'd) Table 9. Dedicated Interrupt Instruction Set
Instruction H ALT IRET JRM JRNM POP CC RIM SIM TR AP W FI New Description Entering Halt mode Interrupt routine return Jump if I1:0=11 Jump if I1:0<>11 Pop CC from the Stack Enable interrupt (level 0 set) Disable interrupt (level 3 set) Software trap Wait for interrupt Function/Example Pop CC, A, X, PC I 1:0=11 ? I 1:0<>11 ? Mem => CC Load 10 in I1:0 of CC Load 11 in I1:0 of CC Software NMI I1 1 I1 H H I0 0 I0 N N Z Z C C
I1 1 1 1 1
H
I0 0 1 1 0
N
Z
C
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned inst ructions. In order not to lose the current software priority level, the RIM, SIM, HALT, WFI and POP CC instructions should never be used in an interrupt routine. Table 10. Interrupt Mapping
N Source Block R ESET TRAP ICP PLG EI0 DTC USB E SUSP EI 1 I2C T IM EI2 SPI Description Reset Software Interrupt Flash Start Programming NMI Interrupt (TLI) Power Management USB Plug/Unplug External Interrupt Port A DTC Peripheral Interrupt USB Peripheral Interrupt USB End Suspend Interrupt External Interrupt Port D I2C Interrupt Timer interrupt External Interrupt Port C SPI interrupt Register Label Priority Order Highest Priority Exit from HALT yes no y es y es yes no no y es y es no no yes y es Address Vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFE Fh FFECh-FFED h FFEAh-FFEB h FFE8h-FFE9h FFE6h-FFE7h
N/A PC R N/A DTC SR USBISTR USBISTR N /A I2CSRx TS R N/A SPICSR
0 1 2 3 4 5 6 7 8 9 10
Lowest Priority
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INTERRUPTS (Cont'd) Table 11. Nested Interrupts Register Map and Reset Values
Address (Hex.) 002Ch Register Label ISPR0 Reset Value ISPR1 Reset Value ISPR2 Reset Value ISPR3 Reset Value 7 DTC I1_3 1
2
6
5 EI 0
4
3 P LG
2
1 ISP 1 US B I1_4 1
0
I0_3 1
I1_2 1 EI 1 I1_6 1 SPI I1_10 1
I0_2 1 I0_6 1 I0_10 1
002Dh
002Eh
IC I1_7 I0_7 1 1 Not used I1_11 I0_11 1 1
002Fh
1
1
1
1
I1_1 I0_1 1 1 ES USP I1_5 I0_5 1 1 EI2 I1_9 I0_9 1 1 Not used I1_13 I0_13 1 1
1 I0_4 1
TIM I1_8 I0_8 1 1 Not used I1_12 I0_12 1 1
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8 POWER SAVING MODES
8.1 INTRODUCTION To give a large measure of flexibility to the application in terms of power consumption, two main power saving modes are implemented in the ST7. After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (fCPU). From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. The user can also switch off any unused on-chip peripherals individually by programming the MISCR2 register. 8.2 WAIT MODE WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the "WFI" ST7 software instruction. All peripherals remain active. During WAIT mode, the I1:0] bits in the CC register are forced to 0, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 29.
N INTERRUP T
Figure 29. WAIT Mode Flow Chart
WFI INSTRUCTION
OSCILLATOR PERIPH. CLOCK CPU CLOCK I1:0] BITS
ON ON OFF CLEAR ED
N RESET
Y
Y
OSCILLATOR PERIPH. CLOCK CPU CLOCK I1:0] BITS
ON ON ON SET
IF RESET DELA Y (Refer to Figure 19 and Figure 20)
FETCH RESET VECTOR OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is pushed on the stack. The I1:0] bits are set during the interrupt routine and cleared when the CC register is popped.
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POWER SAVING MODES (Cont'd) 8.3 HALT MODE The HALT mode is the MCU lowest power consumption mode. The HALT mode is entered by executing the HALT instruction. The internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals. When entering HALT mode, the I[1:0] bits in the Condition Code Register are cleared. Thus, any of the external interrupts (ITi or USB end suspend mode), are allowed and if an interrupt occurs, the CPU clock becomes active. The MCU can exit HALT mode on reception of either an external interrupt on ITi, a plug/unplug interrupt, an end suspend mode interrupt coming from USB peripheral, an SPI interrupt or a reset. The oscillator is then turned on and a stabilization time is provided before releasing CPU operation. The stabilization time is 512 CPU clock cycles. After the start up delay, the CPU continues operation by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up. Related Documentation AN980: ST7 Keypad Decoding Techniques, Implementing Wake-Up on Keystroke AN1014: How to Minimize the ST7 Power Consumption AN1605: Using an active RC to wakeup the ST7LITE0 from power saving mode Figure 30. HALT Mode Flow Chart
HALT INSTRUCTION
OSCILLATOR PERIPH. CLOCK CPU CLOCK I1:0] BITS
OFF OFF OFF CLEARED
N RE SET N
EXTERNAL INTERRUPT*
Y
Y OSCILLATOR PERIPH. CLOCK CPU CLOCK I1:0] BITS ON ON ON SET
D EL AY (Refer to Figure 19 and Figure 20)
FETCH RESET VECTOR OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is pushed on the stack. TheI1:0] bits are set during the interrupt routine and cleared when the CC register is popped.
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9 I/O PORTS
9.1 INTRODUCTION Important note: Please note that the I/O port configurations of this device differ from those of the other ST7 devices. The I/O ports offer different functional modes: transfer of data through digital inputs and outputs and for specific pins: external interrupt generation alternate signal input/output for the on-chip peripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 9.2 FUNCTIONAL DESCRIPTION Each port has 2 main registers: Data Register (DR) Data Direction Register (DDR) and one optional register: Option Register (OR) Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is shown in Figure 31 9.2.1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Notes: 1. Writing the DR register modifies the latch value but does not affect the pin status. 2. When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. External interrupt function When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the Miscellaneous register. Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt source, these are logically NANDed and inverted. For this reason if one of the interrupt pins is tied low, it masks the other ones. In case of a floating input with interrupt configuration, special care must be taken when changing the configuration (see Figure 32). When enabling/disabling an external interrupt by changing port configuration (OR, DDR, control by DTC), a spurious interrupt is generated if the pin level is low and its edge sensitivity includes falling/ rising edge. This is due to the edge detector input which is switched to '1' when the external interrupt is disabled by port configuration. To avoid this unwanted interrupt, a "safe" edge sensitivity (rising edge for enabling and falling edge for disabling) has to be selected before changing the port configuration and configuring the appropriate sensitivity again. The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched.
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I/O PORTS (Cont'd) 9.2.2 Output Modes Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status:
DR 0 1 Push-pull VS S VDD Open-drain Vss Floating
The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Reading the DR register returns the digital value present on the external I/O pin. Consequently even in output mode a value written to an open drain port may differ from the value read from the port. For example, if software writes a `1' in the latch, this value will be applied to the pin, but the pin may stay at `0' depending on the state of the external circuitry. For this reason, bit manipulation even using instructions like BRES and BSET must not be used on open drain ports as they work by reading a byte, changing a bit and writing back a byte. A workaround for applications requiring bit manipulation on Open Drain I/Os is given in Section 9.2.5. 9.2.3 Alternate Functions When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming. When the signal comes from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal goes to an on-chip peripheral, the I/O pin must be configured in input mode. In this
case, the pin state is also digitally readable by addressing the DR register. Note: Input pull-up configuration can cause unexpected values at the input of the alternate peripheral input. When an on-chip peripheral uses a pin as input and output, this pin has to be configured in input floating mode. CAUTION: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin. WARNING: The analog input voltage level must be within the limits stated in the absolute maximum ratings. 9.2.4 VDDF-Powered I/Os The microcontroller is able to power the I/O pins from a specific supply rail connected to the VDDF pin. If VDDF is not present, all VDDF-driven I/Os cannot be used and are tied to ground. Furthermore, this is also true in an application where the internal regulator is used but not yet enabled (this is at least the case during the reset stage).
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I/O PORTS (Cont'd) Figure 31. I/O Port General Block Diagram
REGISTER ACCESS ALTERNATE OUTP UT 1 0 ALTERNATE ENABLE DR
VDD/VDDF
P-BUFFER (see table below) PULL-UP (see table below) VDD/VDDF
D DR PULL-UP CONFIGURATION If implemented OR SEL N-BUFFER DDR SEL CMOS SCHMITT TR IGG E R ANALOG INPUT DIODE S (see table below) PAD
OR
EXTERNA L INTERR UPT SOURCE (eix)
Table 12. I/O Port Mode Options
Configuration Mode Input Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) True Open Drain Pull-Up Off On Off NI P-Buffer Off On Off NI On On Diodes to VDD t o VS S
O u tput
Legend: NI - not implemented Off - implemented not activated On - implemented and activated Note: The diode to VDD/VDDF is not implemented in the true open drain pads. A local protection between the pad and VSS is implemented to protect the device against positive stress.
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DATA BUS
DR SEL
ALTERNATE INPUT FROM OTHER BITS
POLARITY SELECTION
NI (see note)
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I/O PORTS (Cont'd) Table 13. I/O Port Configurations
Hardware Configuration
NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS VDD/VDDF RPU PAD PULL-UP CONFIGURATION DR REGISTER ACCESS
DR REGISTER
W DATA BUS R
INPUT 1 )
ALTERNATE INPUT FROM OTHER PINS INTERRUPT CONFIGURATION POLARITY SELECTION ANALOG INPUT NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS EXTERNAL INTERRUPT SOURCE (eix)
O PEN-DRAIN OUTPU T 2 )
VDD/VDDF
DR REGISTER ACCESS
RPU PAD DR REGISTER
R W
DATA BUS
ALTERNATE ENABLE NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS
ALTERNATE OUTPUT DR REGISTER ACCESS
VDD/VDDF
P U SH-P ULL OUTPU T 2 )
RPU PAD DR REGISTER
R W
DATA BUS
ALTERNATE ENABLE
ALTERNATE OUTPUT
Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.
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I/O PORTS (Cont'd) 9.2.5 Bit manipulation on Open Drain Outputs As mentioned in Section 9.2.2, software should avoid using bit manipulation instructions on the DR register in open drain output mode, but must always access it using byte instructions. If bit manipulation is needed, the solution is to use a copy of the DR register in RAM, change the bits (using BRES or BCLR instructions for example) and copy the whole byte into the DR register each time the value has to be output on a port. This way, no bit manipulation is performed on the DR register but each bit of the DR register can be controlled separately. 9.3 I/O PORT IMPLEMENTATION The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain. Port B (without Option Register) PB[7:0]
MODE floating input push-pull output DDR 0 1
Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 32 Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. Figure 32. Interrupt I/O Port State Transitions
01
INPUT floating/pull-up interrupt
00
INPUT floating (reset state)
10
OUTPUT open-drain
11
OUTPUT push-pull
XX
= DDR, OR
The I/O port register configurations are summarized as follows.
Table 14. Port Configuration (with Option Register)
Port Port A Pin name PA7:0 PC7:4 Port C PC3:0 Port D PD7:0 PE7:6 PE5 PE4:3 PE2:0 PF6:4 PF3:2 PF1:0 floating floating floating Input OR = 0 floating floating OR = 1 floating with interrupt floating with interrupt floating with interrupt floating with interrupt floating with pull-up, if selected by option byte see Section 15.1) floating floating floating floating floating OR = 0 open drain push-pull push-pull open drain push-pull Output OR = 1 push-pull High-Sink No No Yes No Yes Yes No Yes Yes No Yes
Port E
Port F
open drain push-pull open drain (with pull-up, if selectpush-pull ed by option byte see Section 15.1) open drain push-pull open drain push-pull True open drain push-pull True open drain
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I/O PORTS (Cont'd) 9.4 Register Description DATA REGISTER (DR) Port x Data Register PxDR with x = A, B, C, D, E or F. Read / Write Reset Value: 0000 0000 (00h)
7 D7 D6 D5 D4 D3 D2 D1 0 D0
OPTION REGISTER (OR) Port x Option Register PxOR with x = A, C, D, or E Read/Write Reset Value: 0000 0000 (00h)
7 O7 O6 O5 O4 O3 O2 O1 0 O0
Bits 7:0 = D[7:0] Data register 8 bits. The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken into account even if the pin is configured as an input; this allows to always have the expected level on the pin when toggling to output mode. Reading the DR register always returns the digital value applied to the I/O pin (pin configured as input). DATA DIRECTION REGISTER (DDR) Port x Data Direction Register PxDDR with x = A, B, C, D, E or F. Read / Write Reset Value: 0000 0000 (00h)
7 DD7 DD6 DD 5 DD4 D D3 DD2 DD1 0 DD 0
Bits 7:0 = O[7:0] Option register 8 bits. For specific I/O pins, this register is not implemented. In this case the DDR register is enough to select the I/O pin configuration. The OR register allows to distinguish: in input mode if the interrupt capability or the basic configuration is selected, in output mode if the push-pull or open drain configuration is selected. Each bit is set and cleared by software. Input mode: 0: Floating input 1: Floating input with interrupt (ports A, C and D). For port E configuration, refer to Table 14. Output mode: 0: Output open drain (with P-Buffer deactivated) 1: Output push-pull
Bits 7:0 = DD[7:0] Data direction register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bit is set and cleared by software. 0: Input mode 1: Output mode
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I/O PORTS (Cont'd) Table 15. I/O Port Register Map and Reset Values
Register Label (Hex.) Reset Value of all I/O port registers 0000h P ADR 0001h P ADDR 0002h P AOR 0003h P BDR 0004h P BDDR 0005h 0006h P CDR 0007h P CDDR 0008h P COR 0009h P DDR 000Ah P DDDR 000Bh P DOR 000Ch P EDR 000Dh P EDDR 000Eh P EOR 000Fh P FDR 0010h P FDDR Address 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
MSB
LSB
MSB Unused MSB
LSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
Related Documentation AN970: SPI Communication between ST7 and E EPROM
AN1045: S/W implementation of I2C bus master AN1048: Software LCD driver
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10 MISCELLANEOUS REGISTERS
MISCELLANEOUS REGISTER 1 (MISCR1) Read / Write Reset Value: 0000 0000 (00h)
7 IS11 IS10 MC O I S21 I S20 CP1 0 Operating Mode CP0 CPEN Stand-alone mode (fOSC = 12 MHz) fCPU 3 MHz 6 MHz* 1.5 MHz 750 KHz 375 KHz 6 MHz 8 MHz 2 MHz 1 MHz 250 KHz CP1 C P0 CPEN x x 0 0 0 1 1 0 1 0 1 1 1 1 1 x x 0 0 0 1 1 0 1 0 1 1 1 1 1
Bits 2:1 = CP[1:0] CPU clock prescaler These bits select the CPU clock prescaler which is applied in the different slow modes. Their action is conditioned by the setting of the CPEN bit. These two bits are set and cleared by software
Bits 7:6 = IS1[1:0] ei0 Interrupt sensitivity Interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the ei0 interrupts (Port A):
I S 11 IS10 0 0 0 1 1 0 1 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
USB mode (48 MHz PLL)
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bit 5 = MCO Main clock out selection This bit enables the MCO alternate function on the I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for general-purpose I/O) 1: MCO alternate function enabled (fCPU output on I/O port) Bits 4:3 = IS2[1:0] ei1 Interrupt sensitivity Interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the ei1 external interrupts (Port D):
IS21 IS20 0 0 0 1 1 0 1 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
Caution: The ST7 core is not able to read or write in the USB data buffer if the ST7265x is configured at 6 MHz in standalone mode. In USB mode, with fCPU 2 MHz, if the ST7 core accesses the USB data buffer, this may prevent the USB interface from accessing the buffer, resulting in a USB buffer overrun error. This is because an access to memory lasts one cycle and the USB has to send/receive at a fixed baud rate. Note: A frequency change of the ST7 core does not affect the frequency of the Data Transfer Coprocessor (DTC). Bit 0 = CPEN Clock Prescaler Enable This bit is set and cleared by software. It is used with the CP[1:0] bits to configure the internal clock frequency. 0: Default fCPU used (3 or 6 MHz) 1: fCPU determined by CP[1:0] bits
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3).
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MISCELLANEOUS REGISTERS (Cont'd) MISCELLANEOUS REGISTER 2 (MISCR2) Reset Value: 0000 0000 (00h)
7 0 0 0 P4 P3 P2 P1 0 P0
Bits 7:5 = Reserved. Bits 4:0 = P[4:0] Power Management Bits These bits are set and cleared by software. They can be used to switch the on-chip peripherals of the microcontroller ON or OFF. The registers are not changed by switching the peripheral OFF and then ON (contents are frozen while OFF). 0: Peripheral ON (running) 1: Peripheral OFF
Bit P0 P1 P2 P3 P4 Peripheral PW M Tim e r I2C USB DTC
In either case, the Watchdog will not reset the MCU if a HALT instruction is executed while the USB is in Suspend mode. 0: If the Watchdog is active, it will reset the MCU if a HALT instruction is executed (unless the USB is in Suspend mode) 1: When a HALT instruction is executed, the MCU will enter Halt mode (without generating a reset) even if the Watchdog is active. Bits 6:4 = Reserved, forced by hardware to 0. Bits 3:2= IS3[1:0] ei2 Interrupt sensitivity Interrupt sensitivity, defined using the IS3[1:0] bits, is applied to the ei2 interrupts (Port C):
I S 31 IS30 0 0 0 1 1 0 1 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
These 2 bits must be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bit 1 = PWM1 PWM1 Output Control 0: PWM1 Output alternate function disabled (I/O pin free for general purpose I/O). 1: PWM1 Output alternate function enabled
0
MISCELLANEOUS REGISTER 3 (MISCR3) Read / Write Reset Value: 0000 0000 (00h)
7 WD G HALT 0 0 0 IS31
I S30 P WM1 P WM0
Bit 7 = WDGHALT Watchdog and HALT Mode This bit is set and cleared by software. It determines if a RESET is generated when entering Halt mode while the Watchdog is active (WDGA bit =1 in the WDGCR register).
Bit 0 = PWM0 PWM0 Output Control 0: Output alternate function disabled (I/O pin free for general purpose I/O). 1: PWM0 Output alternate function enabled
Table 16. Miscellaneous Register Map and Reset Values
Address (Hex.) 49 4A 4C Register Label MISC R1 Reset Value MISC R2 Reset Value MISC R3 Reset Value 7 IS11 0 0 0 WDG HALT 0 6 IS 10 0 0 0 0 0 5 MCO 0 0 0 0 0 4 IS21 0 P4 0 0 0 3 IS20 0 P3 0 IS31 0 2 CP1 0 P2 0 IS30 0 1 CP0 0 P1 0 PW M1 0 0 CPEN 0 P0 0 PWM 0 0
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11 ON-CHIP PERIPHERALS
11.1 WATCHDOG TIMER (WDG) 11.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter's contents before the T6 bit becomes cleared. 11.1.2 Main Features Programmable free-running downcounter (64 increments of 65536 CPU cycles) Programmable reset Reset (if watchdog activated) when the T6 bit reaches zero Hardware Watchdog selectable by option byte 11.1.3 Functional Description The counter value stored in the CR register (bits T[6:0]), is decremented every 65,536 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments. Figure 33. Watchdog Block Diagram
RESET
If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. This downcounter is freerunning: it counts down even if the watchdog is disabled. The value to be stored in the CR register must be between FFh and C0h (see Table 17): The WDGA bit is set (watchdog enabled) The T6 bit is set to prevent generating an immediate reset The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. Table 17.Watchdog Timing (fCPU = 8 MHz)
CR Register initial value Max Min FFh C0 h WDG timeout period (ms) 524.288 8.192
WATCHDOG CONTROL REGISTER (CR) WDG A T6 T5 T4 T3 T2 T1 T0
7-BIT DOWNCOUNTER
fCPU
CLOCK DIVIDER ÷65536
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WATCHDOG TIMER (Cont'd) 11.1.4 Software Watchdog Option If Software Watchdog is selected by option byte, the watchdog is disabled following a reset. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). 11.1.6 Low Power Modes
Mode WAIT
11.1.5 Hardware Watchdog Option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used.
Description
HALT
No effect on Watchdog. If the WDGHALT bit in the MISCR3 register is set, Halt mode can be used when the watchdog is enabled. When the oscillator is stopped, the WDG stops counting and is no longer able to generate a reset until the microcontroller receives an external interrupt or a reset. If an external interrupt is received, the WDG restarts counting after 514 CPU clocks. In the case of the Software Watchdog option, if a reset is generated, the WDG is disabled (reset state). Note: In USB mode, and in Suspend mode, a reset is not generated by entering Halt mode
Recommendations Make sure that an external event is available to wake up the microcontroller from Halt mode. Before executing the HALT instruction, refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller. When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as Input before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. 11.1.7 Interrupts None.
The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E. As the HALT instruction clears the I bits in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt).
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WATCHDOG TIMER (Cont'd) 11.1.8 Register Description CONTROL REGISTER (CR) Read / Write Reset Value: 0111 1111 (7Fh)
7 WDGA T6 T5 T4 T3 T2 T1 0 T0
hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watchdog option is enabled by option byte. Bits 6:0 = T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).
Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by
Table 18. Watchdog Timer Register Map and Reset Values
Address (Hex.) 14 Register Label WDGC R Reset Value 7 W D GA 0 6 T6 1 5 T5 1 4 T4 1 3 T3 1 2 T2 1 1 T1 1 0 T0 1
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11.2 DATA TRANSFER COPROCESSOR (DTC) 11.2.1 Introduction The Data Transfer Coprocessor is a Universal Serial/Parallel Communications Interface. By means of software plug-ins provided by STMicroelectronics, the user can configure the ST7 to handle a wide range of protocols and physical interfaces such as: 8 or 16-bit IDE mode Compact Flash Multimedia Card (MMC protocol) SmartMediaCard Secure Digital Card Support for different devices or future protocol standards does not require changing the microcontroller hardware, but only installing a different software plug-in. Once the plug-in (up to 256 bytes) stored in the ROM or FLASH memory of the ST7 device is loaded in the DTC RAM, and that the DTC operation is Figure 34. DTC Block Diagram
ST7 DATA/ADDRESS BUS
started, the I/O ports mapped to the DTC assume specific alternate functions. Main Features Full-Speed data transfer from USB to I/O ports without ST7 core intervention Protocol-independency Support for serial and parallel devices Maskable Interrupts 11.2.2 Functional Description The block diagram is shown in Figure 34. The main function of the DTC is to quickly transfer data between : USB and ST7 I/O ports in between ST7 I/O ports The protocol used to read or write from the I/O port is defined by the S/W plug-in in the DTC RAM.
DTCPR
MSB LSB
I/O PORTS
DATA TRANSFER COPROCESSOR
DATA TRANSFER BUFFER
TO USB INTERFACE
DTC RAM DTCCR
0 0 0
ERR STOP EN EN LOAD INIT RUN
DTC SR
0 0 0 0 0 0
ERROR STOP
INTERRUPT REQUEST
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Data Transfer Coprocessor (Cont'd) When the USB interface is used, data transfer is typically controlled by a host computer. The ST7 core can also read from and write to the data buffer of the DTC. Typically, the ST7 controls the application when the USB not used (autonomous mode). The buffer can potentially be accessed by any one of three requestors, the ST7, the DTC and the USB. Mastership of the buffer is not time limited. While a master is accessing the buffer, other requests will not be acknowleged until the buffer is freed by the master. If several requests are pending, when the buffer is free it is granted to the source with the highest priority in the daisy-chain (fixed by hardware), first the ST7, secondly the USB and finally the DTC. Note: Any access by the ST7 to the buffer requires more cycles than either a DTC or USB access. For performance reasons, when the USB interface is exchanging data with the DTC, ST7 accesses should be avoided if possible. 11.2.3 Loading the Protocol Software The DTC must first be initialized by loading the protocol-specific software plug-in (provided by STMicroelectronics) into the DTC RAM. To do this: 1. Stop the DTC by clearing the RUN bit in the DTCCR register 2. Remove the write protection by setting the LOAD bit in the DTCCR register 3. Load the (null-terminated) software plug-in in the DTC RAM. Figure 35. State Diagram of DTC Operations
RU N=0 INIT=0 LOAD=1
4. Restore the write protection by clearing the LOAD bit in the DTCCR register The DTC is then ready for operation. 11.2.4 Executing the Protocol Functions To execute any of the software plug-in functions follow the procedure below: 1. Clear the RUN bit to stop the DTC 2. Select the function by writing its address in the DTCPR register (refer to the separate document for address information). 3. Set the INIT bit in the DTCCR register to copy the DTCPR pointer to the DTC. 4. Clear the INIT bit to return to idle state. 5. Set the RUN bit to start the DTC. 11.2.5 Changing the DTCPR pointer on the fly As shown in Figure 35, the pointer can be changed by writing INIT=1 while the DTC is running (RUN=1), however if the DTC is executing an internal interrupt routine, there will be a delay until interrupt handling is completed. 11.2.6 Low Power Modes Mode WAIT H ALT Description No effect on DTC DTC halted.
DTC RAM LOAD
LOAD=0
RUN=0 IN IT=0 LO AD=0
RU N=1 INIT=0 LOAD=0 RU N=0
LOA D=1 IN IT=1
DTC IDLE
INIT=0
DTC R UNN ING
RUN=1 IN IT=0 INIT=1
POINTER CH ANGE
R UN=0 INI T =1 LOAD=0
ON-THE-FLY POINTER CHANGE
RUN =1 INIT=1 LOAD=0
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