ST7263BDx ST7263BHx ST7263BKx ST7263BE
Low speed USB 8-bit MCU family with up to 32K Flash/ROM, DFU capability, 8-bit ADC, WDG, timer, SCI & I²C
Memories 4, 8, 16 or 32 Kbytes program memory: high density Flash (HDFlash), FastROM or ROM with Read-Out and Write protection In-application programming (IAP) and in-circuit programming (ICP) 384, 512 or 1024 bytes RAM memory (128byte stack) Clock, reset and supply management Run, Wait, Slow and Halt CPU modes 12 or 24 MHz oscillator RAM Retention mode Optional low voltage detector (LVD) USB (universal serial bus) Interface DMA for low speed applications compliant with USB 1.5 Mbs (version 2.0) and HID specifications (version 1.0) Integrated 3.3 V voltage regulator and transceivers Supports USB DFU class specification Suspend and Resume operations 3 endpoints with programmable Input/Output configuration Up to 27 I/O ports Up to 8 high sink I/Os (10 mA at 1.3 V) 2 very high sink true open drain I/Os (25 mA at 1.5 V) Up to 8 lines individually programmable as interrupt inputs 1 analog peripheral 8-bit A/D converter with 8 or 12 channels
PSDIP32
LQFP48 (7x7)
SO34(Shrink)
SO24
QFN40 (6x6)
2 timers Programmable watchdog 16-bit timer with 2 Input Captures, 2 Output Compares, PWM output and clock input 2 communication Interfaces Asynchronous serial communications Interface I²C multimaster Interface up to 400 kHz Instruction Set 63 basic instructions 17 main addressing modes 8 x 8 unsigned multiply instruction True bit manipulation Development tools Versatile development tools (under Windows) including assembler, linker, C-compiler, archiver, source level debugger, software library, hardware emulator, programming boards and gang programmers, HID and DFU software layers
ST7263BE1, ST7263BE2, ST7263BE4, ST7263BE6 32K 16K 512 (128) 8K 4K
Table 1. Device summary
Features Program memory (Flash / ROM) - bytes RAM (stack) - bytes Standard peripherals Other peripherals I/Os (high current) Operating supply CPU frequency Operating temp. Packages LQFP48 (7x7) QFN40 (6x6) 27 (10) SCI, I²C, ADC ST7263BH2, ST7263BH6 32K 1024 (128) 16K 8K ST7263BD6 32K 1024 (128) ST7263BK1, ST7263BK2, ST7263BK4, ST7263BK6 32K 16K 8K 384 (128) 4K
512 384 (128) (128)
1024 512 (128) (128)
384 1024 (128) (128)
384 384 (128) (128)
Watchdog timer, 16-bit timer, USB SCI, ADC ADC 19 (10) 4.0 V to 5.5 V 8 MHz (with 24 MHz oscillator) or 4 MHz (with 12 MHz oscillator) 0 C to +70 C SDIP32/ SO34 QFN40 (6x6) SDIP32/SO34 SO24 SCI, I²C 14 (6)
Rev. 7.0
August 2007 1/145
1
Table of Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2.1 Read-Out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3 ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.4 ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.5 IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.6 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 CPU registers (Cont'd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 Reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1.1 Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.2 Watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.3 External reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 24 24 26 26 26 27 29
9 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.2 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.3 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.4 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.3.1 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.2 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.3 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.4 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Miscellaneous register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 . ... 12 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 36 38 39 40 41 42 42
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12.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.4 Software Watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.5 Hardware Watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.8 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4 USB interface (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4.5 Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5 I²C bus interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 8-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 42 42 43 43 43 43 44 45 45 45 45 57 57 57 58 64 64 64 64 66 72 72 73 78 78 78 78 79 84 86 86 86 86 88 92 92 93 98
12.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 12.6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 12.6.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 12.6.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 12.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 12.6.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 13 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 102 ... 13.1 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 13.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
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13.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 insTruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 103 103 103 104 104 105
14 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 14.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 14.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.1 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.2 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 108 108 108 108 109 109 109 109 110
14.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 14.3.2 Operating conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . 110 14.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 14.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 14.5.1 General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.2 Control timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.3 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 112 113 114
14.6.1 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 14.6.2 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 14.7 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 14.7.1 Functional EMS (Electromagnetic susceptibility) . . . . . . . . . . . . . . . . . . . . . . . . . 14.7.2 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.7.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . . . . . . . . 14.8 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 115 116 117
14.8.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 14.8.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 14.9 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 14.9.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 14.10Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 14.10.1 USB - universal bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.10.2 SCI - serial communication interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.10.3 I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.118-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 124 124 126
15 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 15.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 128 ... 15.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
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15.3 Soldering and glueability information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 16 Device configuration and ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 16.1 Option Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 16.2 Device ordering information and transfer of customer code . . . . . . . . . . . . . . . . . . . . . . . 134 16.3 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 16.3.1 Evaluation tools and starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.4 Order codes for ST7263B development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 137 137 137 139
17 Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 17.1 PA2 limitation with OCMP1 enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 17.2 Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 17.3 USB behavior with LVD disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 17.4 I2C multimaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 17.5 Halt mode power consumption with ADC on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 17.6 SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
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1 Introduction
The ST7263B microcontrollers form a sub-family of the ST7 MCUs dedicated to USB applications. The devices are based on an industry-standard 8bit core and feature an enhanced instruction set. They operate at a 24 MHz or 12 MHz oscillator frequency. Under software control, the ST7263B MCUs may be placed in either Wait or Halt modes, thus reducing power consumption. The enhanced instruction set and addressing modes afford real programming potential. In addition to standard 8bit data management, the ST7263B MCUs feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. The devices include an ST7 Core, up to 32Kbytes of program memory, up to 1024 bytes of RAM, 27 I/O lines and the following on-chip peripherals: USB low speed interface with 3 endpoints with programmable in/out configuration using the DMA architecture with embedded 3.3V voltage Figure 1. General block diagram
INTERNAL CLOCK OSC/3 OSCILLATOR OSC/4 or OSC/2 for USB2) VDD VSS POWER SUPPLY WATCHDOG PORT B ADC1) PORT D
ADDRESS AND DATA BUS
regulator and transceivers (no external components are needed). 8-bit analog-to-digital converter (ADC) with 12 multiplexed analog inputs Industry standard asynchronous SCI serial interface Watchdog 16-bit timer featuring an external clock input, 2 Input Captures, 2 Output Compares with Pulse Generator capabilities Fast I²C multimaster interface Low voltage reset (LVD) ensuring proper poweron or power-off of the device The ST72F63B devices are Flash versions. They support programming in IAP mode (in-application programming) via the on-chip USB interface.
OSCIN OSCOUT
I²C PORT A 16-BIT TIMER PA[7:0] (8 bits)
RESET
CONTROL 8-BIT CORE ALU LVD USB DMA
PB[7:0] (8 bits) PD[7:0] (8 bits)
PORT C SCI PC[2:0] (3 bits)
VPP/TEST VDDA VSSA
PROGRAM MEMORY (32K bytes) RAM (1024 bytes)
(UART) USB SIE
USBDP USBDM USBVCC
ADC channels: 12 on 48-pin devices (Port B and Port D[3:0]) 8 on 34 and 32-pin devices (Port B) None on 24-pin devices 2) 12 or 24 MHz OSCIN frequency required to generate 6 MHz USB clock. 3) The drive from USBVCC is sufficient to only drive an external pull-up in additoin to the internal transceiver
1)
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2 Pin description
Figure 2. 48-pin LQFP package pinout
PA0/MCO PA1(25mA)/SDA/ICCDATA PD7 PD6 PD5 PD4 PD3/AIN11 PD2/AIN10 PD1/AIN9 PD0/AIN8 PA2(25mA)/SCL/ICCCLK NC
48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24
VSSA USBDP USBDM USBVCC VDDA VDD OSCO UT OSCIN VSS USBO E/P C 2 NC NC
P A 3/EXTC L K PA4/ICAP1/IT1 PA5/ICAP2/IT2 P A 6/O C MP1/IT3 P A 7/O C MP2/IT4 PB0(10mA)/AIN0 PB1(10mA)/AIN1 PB2(10mA)/AIN2 PB3(10mA)/AIN3 PB4(10mA)/AIN4/IT5 PB5(10mA)/AIN5/IT6 VPP/TEST
AIN7/IT8/PB7(10mA) AIN6/IT7/PB6(10mA)
RESET
TDO/PC1 RDI/PC0
NC NC NC NC NC NC NC
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Figure 3. 40-lead QFN package pinout
PA1(25mA)/SDA/ICCDATA PA2(25mA)/SCL/ICCCLK
31 30 29 28 27 26 25 24 23 22 21 11 12 13 14 RESET 15 16 17 18 19 20
PD31)/AIN11
PD21)/AIN10
PD11)/AIN9
33
40
39
38
37
36
35
34
PA0/MCO VSSA USBDP USBDM USBVCC VDDA VDD OSCOU T OSCIN VSS
PD01)/AIN8
32
PD71)
PD61)
PD51)
PD41)
1 2 3 4 5 6 7 8 9 10
PA3/EXTCLK PA4/ICA P1/IT1 PA5/ICA P2/IT2 PA6/OCMP 1/IT3 PA7/OCMP 2/IT4 PB0(10mA)/AIN0 PB1(10mA)/AIN1 PB2(10mA)/AIN2 PB3(10mA)/AIN3 PB4(10mA)/AIN4/IT5
VPP/TEST
Note: 1. Port D functions are not available on the 8K version of the QFN40 package (ST7263BK2) and should not be connected.
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IT8/AIN7/PB7(10mA)
IT7/AIN6/PB6(10mA)
IT6/AIN5/PB5(10mA)
RD I/P C0
NC
USBOE/PC2
TDO/P C 1
NC
ST7263BDx ST7263BHx ST7263BKx ST7263BE
Pin description (Cont'd) Figure 4. 34-pin SO package pinout
VDDA USBVCC USBDM USBDP VSSA PA0/MCO PA1(25mA)/SDA/ICCDATA NC NC NC PA2(25mA)/SCL/ICCCLK PA3/EXTCLK PA4/ICAP1/IT1 PA5/ICAP2/IT2 PA6/OCMP1/IT3 PA7/OCMP2/IT4 PB0(10mA)/AIN0
VDD OSCOUT OSCIN V SS PC2/USBOE PC1/TDO PC0/RDI RESET NC AIN7/IT8/PB7(10mA) AIN6/PB6/IT7(10mA) VPP/TEST AIN5/IT6/PB5(10mA) AIN4/IT5/PB4(10mA) AIN3/PB3(10mA) AIN2/PB2(10mA) AIN1/PB1(10mA)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18
Figure 5. 32-pin SDIP package pinout
VDD OSCOUT OSCIN VSS PC2/USBOE PC1/TDO PC0/RDI RESET AIN7/IT8/PB7(10mA) AIN6/IT7/PB6(10mA) VPP/TEST AIN5/IT6/PB5(10mA) AIN4/IT5/PB4(10mA) AIN3/PB3(10mA) AIN2/PB2(10mA) AIN1/PB1/(10mA)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VDDA USBVCC USBDM USBDP VSSA PA0/MCO PA1(25mA)/SDA/ICCDATA NC NC PA2(25mA)/SCL/ICCCLK PA3/EXTCLK PA4/ICAP1/IT1 PA5/ICAP2/IT2 PA6/OCMP1/IT3 PA7/OCMP2/IT4 PB0(10mA)/AIN0
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Figure 6. 24-pin SO package pinout
V DD OS COUT OSCIN VSS TDO/PC1 RDI/PC0 RESET/ IT7/PB6(10mA) VPP/TEST PB3(10mA) PB2(10mA) USBOE/PB1(10mA)
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
USBVcc US BDM USBDP VSSA PA0/MCO PA1(25mA)/SDA/ICCDATA PA2(25mA)/SCL/ICCCLK PA3/EXTCLK PA4/ICAP1/IT1 PA5/ICAP2/IT2 PA7/OCMP2/IT4 PB0(10mA)
RESET (see Note 1): bidirectional. This active low signal forces the initialization of the MCU. This event is the top priority non maskable interrupt. This pin is switched low when the Watchdog is triggered or the VDD is low. It can be used to reset external peripherals. OSCIN/OSCOUT: input/output oscillator pin. These pins connect a parallel-resonant crystal, or an external source, to the on-chip oscillator. VDD/VSS (see Note 2): main power supply and Ground voltages. VDDA/VSSA (see Note 2): power supply and ground voltages for analog peripherals. Alternate Functions: Several pins of the I/O ports assume software programmable alternate functions as shown in the pin description.
Note 1: Adding two 100 nF decoupling capacitors on the Reset pin (respectively connected to VDD and VSS) will significantly improve product electromagnetic susceptibility performance. Note 2: To enhance the reliability of operation, it is recommended that VDDA and VDD be connected together on the application board. This also applies to VSSA and VSS. Note 3: The USBOE alternate function is mapped on port C2 in 32/34/48 pin devices. In SO24 devices it is mapped on Port B1. Note 4: The timer OCMP1 alternate function is mapped on Port A6 in 32/34/48 pin devices. In SO24 devices it is not available.
Legend / Abbreviations for Table 2 and Table 3: Type: I = input, O = output, S = supply In/Output level: CT = CMOS 0.3VDD/0.7VDD with input trigger Output level: 10mA = 10mA high sink (Fn N-buffer only) 25mA = 25mA very high sink (on N-buffer only) Port and control configuration: Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog Output: OD = open drain, PP = push-pull, T = True open drain The RESET configuration of each pin is shown in bold. This configuration is kept as long as the device is under reset state.
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Table 2. Device pin description (QFN40, LQFP48, SO34 and SDIP32)
Pin n LQFP48 Type SDIP32 Q F N40 SO34 Pin name Level O u tput Input Port / Control Input float wpu ana int Output OD PP Main function (after reset)
Alternate function
1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 9 -
7 8 9 10
6 7 8 9
VDD OS C O U T OS C I N VSS
S O I S I /O I /O I /O C T I/O -------I /O C T 1 0 m A X I /O C T 10mA X S I /O C T 10mA X I /O C T 10mA X I /O CT 10mA X I /O CT 10mA X I /O CT 10mA X I /O CT 10mA X I/O I/O I/O I/O I /O CT CT CT CT CT X X X X X T X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X CT CT X X X X X X X X
Power supply voltage (4V - 5.5V) Oscillator output Oscillator input Digital ground Port C2 Port C1 Port C0 Reset Not connected Not connected Not connected Not connected Not connected Not connected Not connected Port B7 Port B6 ADC analog input 7 ADC analog input 6 USB Output Enable SCI Transmit Data Output SCI Receive Data Input
11 10 PC2/U SBOE 12 13 PC1/TDO 13 14 PC0/R D I 14 15 RESET 15 16 NC 16 17 NC 18 NC 19 NC 20 NC 21 NC 22 NC
1 0 1 7 2 3 PB7/AI N 7/ IT8
10 11 18 24 PB6/AIN6/IT7 11 12 19 25 VPP/TEST 12 13 20 26 PB5/AIN5/IT6 13 14 21 27 PB4/AIN4/IT5 14 15 22 28 PB3/AIN3 15 16 23 29 PB2/AIN2 16 17 24 30 PB1/AIN1 17 18 25 31 PB0/AIN0 18 19 26 32 PA7/O CMP2/IT4 19 20 27 33 PA6/O CMP1/IT3 20 21 28 34 PA5/ICAP2/IT2 21 22 29 35 PA4/ICAP1/IT1 22 23 30 36 PA3/EX T CLK 23 24 31 38 PA2/SC L /ICCCLK 32 39 PD01)/AIN8
Programming supply Port B5 Port B4 Port B3 Port B2 Port B1 Port B0 Port A7 Port A6 Port A5 Port A4 Port A3 Port A2 Port D0 ADC analog input 5 ADC analog input 4 ADC analog input 3 ADC analog input 2 ADC analog input 1 ADC analog Input 0 Timer Output Compare 2 Timer Output Compare 1 Timer Input Capture 2 Timer Input Capture 1 Timer External Clock I²C serial clock, ICC Clock ADC analog Input 8
I/O CT 25mA X I/O CT X
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Pin n LQFP48 Type SDIP32 Q F N40 SO34 Pin name
Level O u tput Input
Port / Control Input float wpu ana int Output OD PP
Main function (after reset) Port D1 Port D2 Port D3 Port D4 Port D5 Port D6 Port D7
Alternate function
-
25
33 40 PD11)/AIN9 34 41 PD21 ) /AIN10
I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT ----
X X X X X X X
X X X
X X X X X X X
ADC analog Input 9 ADC analog Input 10 ADC analog Input 11
35 42 PD31)/AIN11 36 43 PD4 37 44
1)
PD51 )
1)
38 45 PD6 39 46 -
PD71 ) NC NC NC
Not connected Not connected Not connected T X X Port A1 Port A0 I²C serial data, ICC Data Main Clock Output
24 26 25 27
26 28 40 47 PA1/SD A/ICCDATA 27 29 28 30 29 31 30 32 31 33 32 34 1 2 3 4 5 6 4 8 PA0/M CO 1 2 3 4 5 VSSA USBDP USBDM USBVCC VDDA
2)
I/O CT 25mA X I/O S I /O I /O O S CT
Analog ground USB bidirectional data (data +) USB bidirectional data (data -) USB power supply 2) Analog supply voltage
Note: 1. Port D functions are not available on the 8K version of the QFN40 package (ST7263BK2) and should not be connected. 2. The drive from USBVcc is sufficient to only drive an external pull-up in addition to the internal transceiver.
Table 3. Device pin description (SO24)
Pin n Type SO24 Pin Name Level Output Input Port / Control Input float wpu ana int Output OD PP Main Function (after reset) Alternate Function
1 2 3 4 5 6 7
VDD OSCO U T OS C I N VSS PC1/TDO P C0/R DI RESET
S O I S I/O I/O I/O CT CT X X X X X X
Power supply voltage (4V - 5.5V) Oscillator output Oscillator input Digital ground Port C1 Port C0 Re s e t SCI Transmit Data Output SCI Receive Data Input
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Pin n Type SO24 Pin Name
Level O u tput Input
Port / Control Input float wpu ana int Output OD PP Main Function (after reset) Port B6 Programming supply Alternate Function
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
PB6/IT7 VPP/TEST PB3 PB2 PB1/U SBOE PB0 PA7/O CMP2/IT4 PA5/ICAP2/IT2 PA4/ICAP1/IT1 PA3/E XTCLK PA2/S CL/ ICCC LK PA1/S DA/ICCDATA PA0/M CO VSSA USBDP USBDM USBVCC
I/O S I/O I/O I /O I/O I/O I/O I/O I /O I/O I/O I/O S I /O I /O O
CT 10mA
X
X
X
X
CT 10mA CT 10mA CT 10mA CT 10mA CT CT CT CT CT 25mA CT 25mA CT
X X X X X X X X X X X X X X
X X X X
X X X X X X X X T T X
Port B3 Port B2 Port B1 Port B0 Port A7 Port A5 Port A4 Port A3 Port A2 Port A1 Port A0 Timer Output Compare 2 Timer Input Capture 2 Timer Input Capture 1 Timer External Clock I²C serial clock, ICC Clock I²C serial data, ICC Data Main Clock Output USB Output Enable
Analog ground USB bidirectional data (data +) USB bidirectional data (data -) USB power supply
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3 Register & memory map
As shown in Figure 7, the MCU is capable of addressing 32 Kbytes of memories and I/O registers. The available memory locations consist of up to 1024 bytes of RAM including 64 bytes of register locations, and up to 32K bytes of user program memory in which the upper 32 bytes are reserved for interrupt vectors. The RAM space includes up to 128 bytes for the stack from 0100h to 017Fh. Figure 7. Memory map
0040h 0000h 003Fh 0040h
The highest address bytes contain the user reset and interrupt vectors. IMPORTANT: Memory locations noted "Reserved" must never be accessed. Accessing a reserved area can have unpredictable effects on the device.
HW Registers (See Table 5) RAM (384 / 512 / 1024 bytes)
00FFh 0100h 017Fh 0180h
Short Addressing RAM (192 bytes) Stack (128 bytes) 16-bit Addressing RAM
01BF / 023F / 043Fh 01C0 / 0240 / 0440h
Reserved
7FFFh 8000h
01BF / 023F / 043Fh 8000h
Program Memory (4 / 8 / 16 / 32 Kbytes)
FFDFh FFE0h FFFFh C000h
32 Kbytes
Interrupt & Reset Vectors (See Table 4)
16 Kbytes E000h 8 Kbytes F000h FFDFh 4 Kbytes
Table 4. interrupt vector map
Vector address FFE0h-FFEDh FFEEh-FFEFh FFF0h-FFF1h FFF2h-FFF3h FFF4h-FFF5h FFF6h-FFF7h FFF8h-FFF9h FFFAh-FFFBh FFFCh-FFFDh FFFEh-FFFFh Description Reserved Area USB Interrupt Vector SCI Interrupt Vector I²C Interrupt Vector TIMER Interrupt Vector IT1 to IT8 Interrupt Vector USB End Suspend mode Interrupt Vector Flash Start Programming Interrupt Vector TRAP (software) Interrupt Vector RESET Vector I- bit I- bit I- bit I- bit I- bit I- bit I- bit None None Internal Interrupt Internal Interrupt Internal Interrupt Internal Interrupt External Interrupt External Interrupts Internal Interrupt CPU Interrupt No No No No Yes Yes Yes No Yes Masked by R emarks Exit from Halt mode
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Table 5. Hardware register memory map
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh to 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h SC I TIM TCR2 TCR1 TCSR TIC1H R TIC1LR TOC1HR TOC1LR TCHR TCLR TACHR TACLR TIC2H R TIC2LR TOC2HR TOC2LR SCISR SCIDR SCIBRR SCICR1 SCICR2 Timer Control Register 2 Timer Control Register 1 Timer Control/Status Register Timer Input Capture High Register 1 Timer Input Capture Low Register 1 Timer Output Compare High Register 1 Timer Output Compare Low Register 1 Timer Counter High Register Timer Counter Low Register Timer Alternate Counter High Register Timer Alternate Counter Low Register Timer Input Capture High Register 2 Timer Input Capture Low Register 2 Timer Output Compare High Register 2 Timer Output Compare Low Register 2 SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 00h 00h 00h xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h C0h xxh 00h x000 0000b 00h R/W R/W R/W Read only Read only R/W R/W Read only R/W Read only R/W Read only Read only R/W R/W Read only R/W R/W R/W R/W Block Port A Port B Port C Port D ITC MIS C ADC WDG Register label PADR PADDR PBDR PBDDR PCDR PCDDR PDDR PDDDR ITIFRE MISCR ADCDR ADCCS R WD G C R Register name Port A Data Register Port A Data Direction Register Port B Data Register Port B Data Direction Register Port C Data Register Port C Data Direction Register Port D Data Register Port D Data Direction Register Interrupt Register Miscellaneous Register ADC Data Register ADC control Status register Watchdog Control Register Reserved (4 bytes) Reset status 00h 00h 00h 00h 1111 x000b 1111 x000b 00h 00h 00h 00h 00h 00h 7Fh Remarks R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Read only R/W R/W
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Address 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h to 0036h 0032h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh
Block
Register label USBPIDR USBDM AR USBIDR USBISTR USBIMR USBCTLR
Register name USB PID Register USB DMA address Register USB Interrupt/DMA Register USB Interrupt Status Register USB Interrupt Mask Register USB Control Register USB Device Address Register USB Endpoint 0 Register A USB Endpoint 0 Register B USB Endpoint 1 Register A USB Endpoint 1 Register B USB Endpoint 2 Register A USB Endpoint 2 Register B Reserved (5 bytes) Reserved (5 bytes)
Reset status x0h xxh x0h 00h 00h 06h 00h 0000 xxxxb 80h 0000 xxxxb 0000 xxxxb 0000 xxxxb 0000 xxxxb
Remarks Read only R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
USB
USBDA DDR USBEP0R A USBEP0R B USBEP1R A USBEP1R B USBEP2R A USBEP2R B
Flash
F CSR
Flash Control /Status Register Reserved (1 byte)
00h
R/W
I2CD R I2CO AR I²C I2CC CR I2CS R2 I2CS R1 I2CC R
I²C Data Register Reserved I²C (7 Bits) Slave Address Register I²C Clock Control Register I²C 2nd Status Register I²C 1st Status Register I²C Control Register
00h 00h 00h 00h 00h 00h
R/W R/W R/W Read only Read only R/W
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4 Flash program memory
4.1 Introduction The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a byte-by-byte basis using an external VPP supply. The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (in-circuit programming) or IAP (in-application programming). The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors.Main features 3 Flash programming modes: Insertion in a programming tool. In this mode, all sectors including option bytes can be programmed or erased. ICP (in-circuit programming). In this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board. IAP (in-application programming) In this mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board and while the application is running. ICT (in-circuit testing) for downloading and executing user application test patterns in RAM Read-Out protection Register access security system (RASS) to prevent accidental programming or erasing 4.2 Structure The Flash memory is organised in sectors and can be used for both code and data storage. Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (see Table 6). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required. The first two sectors have a fixed size of 4 Kbytes (see Figure 8). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000hFFFFh). Table 6. Sectors available in Flash devices
Flash size (bytes) 4K 8K > 8K Available sectors Sector 0 Sectors 0,1 Sectors 0,1, 2
4.2.1 Read-Out protection Read-Out protection, when selected, provides a protection against Program Memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. In Flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased and the device can be reprogrammed. Read-Out protection selection depends on the device type: In Flash devices it is enabled and removed through the FMP_R bit in the option byte. In ROM devices it is enabled by mask option specified in the Option List.
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Figure 8. Memory map and sector address
4K
1000h 3FFFh 7FFFh 9FFFh BFFFh D7FFh DFFFh EFFFh FFFFh
8K
10K
16K
24K
32K
48K
60K
FLASH MEMORY SIZE
SECTOR 2 2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes 52 Kbytes 4 Kbytes 4 Kbytes SECTOR 1 SECTOR 0
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Flash program memory (Cont'd) 4.3 ICC interface ICC (in-circuit communication) needs a minimum of four and up to six pins to be connected to the programming tool (see Figure 9). These pins are: RESET: device reset VSS: device power supply ground ICCCLK: ICC output serial clock pin Figure 9. Typical ICC interface
PROGRAMMING TOOL ICC CONNECTOR ICC Cable APPLICATION BOARD (See Note 3) OPTIONAL (See Note 4) ICC CONNECTOR HE10 CONNECTOR TYPE 9 10 7 8 5 6 3 4 1 2 APPLICATION RESET SOURCE See Note 2 10k APPLICATION POWER SUPPLY CL2 CL1 See Note 1 APPLICATION I/O
ICCDATA: ICC input/output serial data pin ICCSEL/VPP: programming voltage OSC1(or OSCIN): main clock input for external source (optional) VDD: application board power supply (see Figure 9, Note 3)
RESET
ST7
Notes: 1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values. 2. During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R > 1K or a reset man-
agement IC with open drain output and pull-up resistor > 1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session. 3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual. 4. Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multioscillator capability need to have OSC2 grounded in this case.
ICCSEL/VPP
ICCDATA
ICCCLK
OSC2
OSC1
VDD
VSS
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Flash program memory (Cont'd) 4.4 ICP (in-circuit programming) To perform ICP the microcontroller must be switched to ICC (in-circuit communication) mode by an external controller or programming tool. Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 9). For more details on the pin locations, refer to the device pinout description. 4.5 IAP (in-application programming) This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool). This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). For example, it is possible to download code from the SPI, SCI or other type of serial interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/ erase protected to allow recovery in case errors occur during the programming operation. 4.6 Related documentation For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual. 4.7 Register description Flash Control/Status register (FCSR) Read / Write Reset value: 0000 0000 (00h)
7 0 0 0 0 0 0 0 0 0
This register is reserved for use by programming tool software. It controls the Flash programming and erasing operations.
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5 Central processing unit
5.1 Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 Features
63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit index registers 16-bit stack pointer Low power modes Maskable hardware interrupts Non-maskable software interrupt
5.3 CPU registers The six CPU registers shown in Figure 10 are not present in the memory mapping and are accessed by specific instructions. Figure 10. CPU registers
7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 0 0 0
Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The cross-assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 111HI 0 NZC CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined value
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CPU registers (cont'd) Condition Code register (CC) Read/Write Reset value: 111x1xxx
7 1 1 1 H I N Z 0 C
because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. Bit 2 = N Negative This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions. Bit 1 = Z Zero This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test inst ructions. Bit 0 = C Carry/borrow This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions.
The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Bit 4 = H Half carry This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 3 = I Interrupt mask This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible
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6 CPU registers (Cont'd)
Stack Pointer (SP) Read/Write Reset value: 017Fh
15 0 7 0 SP6 SP5 S P4 SP3 SP2 SP 1 0 0 0 0 0 0 8 1 0 SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 11). Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP6 to SP0 bits are set) which is the stack higher address. Figure 11. Stack manipulation example
CALL Subroutine @ 0100h Interrupt Event P USH Y
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 11. When an interrupt is received, the SP is decremented and the context is pushed on the stack. On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area.
PO P Y
IRET
RET or RSP
SP SP CC A X PC H SP PCH @ 017Fh PCL P CL PCH PCL Y CC A X PCH PCL PCH PC L SP CC A X PCH PCL PCH PCL SP PCH PCL SP
Stack Higher Address = 017Fh Stack Lower Address = 0100h
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7 Reset and clock management
7.1 Reset The Reset procedure is used to provide an orderly software start-up or to exit low power modes. Three reset modes are provided: a low voltage (LVD) reset, a watchdog reset and an external reset at the RESET pin. A reset causes the reset vector to be fetched from addresses FFFEh and FFFFh in order to be loaded into the PC and with program execution starting from this point. An internal circuitry provides a 4096 CPU clock cycle delay from the time that the oscillator becomes a c t iv e . 7.1.1 Low voltage detector (LVD) Low voltage reset circuitry generates a reset when VDD is: below VIT+ when VDD is rising, below VIT- when VDD is falling. During low voltage reset, the RESET pin is held low, thus permitting the MCU to reset other devices. It is recommended to make sure that the VDD supply voltage rises monotonously when the device is exiting from Reset, to ensure the application functions properly. 7.1.2 Watchdog reset When a watchdog reset occurs, the RESET pin is pulled low permitting the MCU to reset other devices in the same way as the low voltage reset (Figure 12). 7.1.3 External reset The external reset is an active low input signal applied to the RESET pin of the MCU. As shown in Figure 15, the RESET signal must stay low for a minimum of one and a half CPU clock cycles. An internal Schmitt trigger at the RESET pin is provided to improve noise immunity.
Figure 12. Low voltage detector functional diagram
RESET
VDD
LOW VOLTAGE DETECTOR
INTERNAL RESET
FROM WATCHDOG RESET
Figure 13. Low voltage reset signal output
V I T+
VIT-
VDD
RESET
Note: Hysteresis (VIT+-VIT-) = Vhys
Figure 14. Temporization timing diagram after an internal Reset
VIT+
VDD
Temporization (4096 CPU clock cycles)
Addresses
$FFFE
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Reset (Cont'd) Figure 15. Reset timing diagram
t DDR VDD
OSCIN tOXOV f CPU
PC RE SET
FFFE
FFFF
WATCHDOG RESET
4096 CPU CLOCK CYCLES D EL AY
Note: Refer to Section 14, "Electrical characteristics" for values of tDDR, tOXOV, VIT+, VIT- and Vhys
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7.2 Clock system 7.2.1 General description The MCU accepts either a crystal or ceramic resonator, or an external clock signal to drive the internal oscillator. The internal clock (fCPU) is derived from the external oscillator frequency (fOSC), which is divided by 3 (and by 2 or 4 for USB, depending on the external clock used). The internal clock is further divided by 2 by setting the SMS bit in the Miscellaneous Register. Using the OSC24/12 bit in the option byte, a 12 MHz or a 24 MHz external clock can be used to provide an internal frequency of either 2, 4 or 8 MHz while maintaining a 6 MHz for the USB (refer to Figure 18). The internal clock signal (fCPU) is also routed to the on-chip peripherals. The CPU clock signal consists of a square wave with a duty cycle of 50%. The internal oscillator is designed to operate with an AT-cut parallel resonant quartz or ceramic resonator in the frequency range specified for fosc. The circuit shown in Figure 17 is recommended when using a crystal, and Table 7, "Recommended values for 24 MHz crystal resonator" lists the recommended capacitance. The crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilisation time. Table 7. Recommended values for 24 MHz crystal resonator
RSMAX COSCIN C OSCOUT 20 56pF 56pF 1-10 M 25 47pF 47pF 1-10 M 70 22pF 22pF 1-10 M 0
source should be used instead of tOXOV (see Section 6.5 CONTROL TIMING). Figure 16. External clock source connections
OSCIN
OSCOUT NC
EXTERNAL CLOCK
Figure 17. Crystal/ceramic resonator
OSCIN
RP
OSCOUT
COSCIN
COSCOUT
Figure 18. Clock block diagram
8, 4 or 2 MHz CPU and peripherals)
RP
%3
%2
1 SM S
Note: RSMAX is the equivalent serial resistor of the crystal (see crystal specification). 7.2.2 External clock An external clock may be applied to the OSCIN input with the OSCOUT pin not connected, as shown on Figure 16. The tOXOV specifications do not apply when using an external clock input. The equivalent specification of the external clock
1 24 or 12 MHz Crystal
%2 %2
6 MHz (USB)
%2
0 OSC24/12
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8 Interrupts
The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in Table 8, "Interrupt mapping" and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 19. The maskable interrupts must be enabled clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). When an interrupt has to be serviced: Normal processing is suspended at the end of the current instruction execution. The PC, X, A and CC registers are saved onto the stack. The I bit of the CC register is set to prevent additional interrupts. The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to Table 8, "Interrupt mapping" for vector addresses). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume. Priority management By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine. In the case several interrupts are simultaneously pending, a hardware priority defines which one will be serviced first (see Table 8, "Interrupt mapping"). Non-maskable software interrupts This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. It will be serviced according to the flowchart on Figure 19. Interrupts and low power mode All interrupts allow the processor to leave the Wait low power mode. Only external and specific mentioned interrupts allow the processor to leave the Halt low power mode (refer to the "Exit from Halt" column in Table 8, "Interrupt mapping"). External interrupts The pins ITi/PAk and ITj/PBk (i=1,2; j= 5,6; k=4,5) can generate an interrupt when a rising edge occurs on this pin. Conversely, the ITl/PAn and ITm/ PBn pins (l=3,4; m= 7,8; n=6,7) can generate an interrupt when a falling edge occurs on this pin. Interrupt generation will occur if it is enabled with the ITiE bit (i=1 to 8) in the ITRFRE register and if the I bit of the CCR is reset. Peripheral interrupts Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: The I bit of the CC register is cleared. The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by one of the two following operations: Writing "0" to the corresponding bit in the status register. Accessing the status register while the flag is set followed by a read or write of an associated register. Notes: 1. The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting to be enabled) will therefore be lost if the clear sequence is executed. 2. All interrupts allow the processor to leave the Wait low power mode. 3. Exit from Halt mode may only be triggered by an External Interrupt on one of the ITi ports (PA4-PA7 and PB4-PB7), an end suspend mode Interrupt coming from USB peripheral, or a reset.
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Interrupts (Cont'd) Figure 19. Interrupt processing flowchart
FROM RESET BIT I SET Y N N
INTERRUPT Y
FETCH NEXT INSTRUCTION
N
IRET Y STACK PC, X, A, CC SET I BIT LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK THIS CLEARS I BIT BY DEFAULT
Table 8. Interrupt mapping
N Source block RESET TRAP FLASH USB 1 2 3 4 5 ITi T IMER I²C S CI USB Reset Software Interrupt Flash Start Programming Interrupt End Suspend mode External Interrupts Timer Peripheral Interrupts I²C Peripheral Interrupts SCI Peripheral Interrupts USB Peripheral Interrupts ISTR ITRFRE T IMSR I²CSR1 I²CSR2 SCISR ISTR Lowest Priority no Description Register label N/A Priority order Highest Priority Exit from Halt yes no yes yes Vector address FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh
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Interrupts (Cont'd) 8.1 Interrupt register Interrupt register (ITRFRE) Address: 0008h -- Read/Write Reset value: 0000 0000 (00h)
7
IT8E IT7E IT6E IT5E IT4E IT3E IT2E
0
IT1E
Bit 7:0 = ITiE (i=1 to 8). Interrupt Enable Control Bits.
If an ITiE bit is set, the corresponding interrupt is generated when a rising edge occurs on the pin PA4/IT1 or PA5/ IT2 or PB4/IT5 or PB5/IT6 or a falling edge occurs on the pin PA6/IT3 or PA7/ IT4 or PB6/IT7 or PB7/IT8 No interrupt is generated elsewhere. Note: Analog input must be disabled for interrupts coming from port B.
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9 Power saving modes
9.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, two main power saving modes are implemented in the ST7. After a RESET, the normal operating mode is selected by default (Run mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 3 (fCPU). From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. Figure 20. Halt mode flowchart
HALT INSTRUCTION
OSCILLATOR PERIPH. CLOCK CPU CLOCK I- BIT
OFF OFF OFF CLEARED
9.2 Halt mode The MCU consumes the least amount of power in Halt mode. The Halt mode is entered by executing the HALT instruction. The internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals. When entering Halt mode, the I bit in the Condition Code Register is cleared. Thus, all external interrupts (ITi or USB end suspend mode) are allowed and if an interrupt occurs, the CPU clock becomes a c t iv e . The MCU can exit Halt mode on reception of either an external interrupt on ITi, an end suspend mode interrupt coming from USB peripheral, or a reset. The oscillator is then turned on and a stabilization time is provided before releasing CPU operation. The stabilization time is 4096 CPU clock cycles. After the start up delay, the CPU continues operation by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up.
N
EXTERNAL INTERRUPT*
N RESET
Y
Y OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT ON ON ON SET
4096 CPU CLOCK CYCLES DELAY
FETCH RESET VECTOR OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped.
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Power saving modes (Cont'd) 9.3 Slow mode In Slow mode, the oscillator frequency can be divided by 2 as selected by the SMS bit in the Miscellaneous Register. The CPU and peripherals are clocked at this lower frequency. Slow mode is used to reduce power consumption, and enables the user to adapt the clock frequency to the available supply voltage. 9.4 Wait mode Wait mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the "WFI" ST7 software instruction. All peripherals remain active. During Wait mode, the I bit of the CC register is forced to 0 to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in Wait mode until an interrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 21. Related documentation AN 980: ST7 Keypad Decoding Techniques, Implementing Wake-Up on Keystroke AN1014: How to Minimize the ST7 Power Consumption AN1605: Using an active RC to wakeup the ST7LITE0 from power saving mode Figure 21. Wait mode flowchart
WFI INSTRUCTION
OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT
ON ON OFF CLEAR ED
N R ESET N INTERRUP T
Y
Y
OSCILLATOR PERIPH. CLOCK CPU CLOCK I- BIT
ON ON ON SET
IF RESET 4096 CPU CLOCK CYCLES DELAY
FETCH RESET VECTOR OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped.
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10 I/O ports
10.1 Introduction The I/O ports offer different functional modes: Transfer of data through digital inputs and outputs and for specific pins Analog signal input (ADC) Alternate signal input/output for the on-chip peripherals External interrupt generation An I/O port consists of up to 8 pins. Each pin can be programmed independently as a digital input (with or without interrupt generation) or a digital output. 10.2 Functional description Each port is associated to 2 main registers: Data Register (DR) Data Direction Register (DDR) Each I/O pin may be programmed using the corresponding register bits in DDR register: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. Table 9. I/O pin functions
D DR 0 1 M OD E Input Ou t p u t
tivity is given independently according to the description mentioned in the ITRFRE interrupt register. Each pin can independently generate an Interrupt request. Each external interrupt vector is linked to a dedicated group of I/O port pins (see Interrupts section). If more than one input pin is selected simultaneously as an interrupt source, this is logically ORed. For this reason if one of the interrupt pins is tied low, the other ones are masked. Output mode The pin is configured in output mode by setting the corresponding DDR register bit (see Table 7). In this mode, writing "0" or "1" to the DR register applies this digital value to the I/O pin through the latch. Therefore, the previously saved value is restored when the DR register is read. Note: The interrupt function is disabled in this mode. Digital alternate function When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin has to be configured in input mode. In this case, the pin's state is also digitally readable by addressing the DR register. Notes: 1. Input pull-up configuration can cause an unexpected value at the input of the alternate peripheral input. 2. When the on-chip peripheral uses a pin as input and output, this pin must be configured as an input (DDR = 0). Warning: The alternate function must not be activated as long as the pin is configured as an input with interrupt in order to avoid generating spurious interrupts.
Input modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Note 1: All the inputs are triggered by a Schmitt trigger. Note 2: When switching from input mode to output mode, the DR register should be written first to output the correct value as soon as the port is configured as an output. Interrupt function When an I/O is configured as an Input with Interrupt, an event on this I/O can generate an external Interrupt request to the CPU. The interrupt sensi-
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I/O ports (Cont'd) Analog alternate function When the pin is used as an ADC input the I/O must be configured as a floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to
have clocking pins located close to a selected analog pin. Warning: The analog input voltage level must be within the limits stated in the Absolute Maximum Ratings. 10.3 I/O port implementation The hardware implementation on each I/O port depends on the settings in the DDR register and specific feature of the I/O port such as ADC Input or true open drain.
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I/O ports (Cont'd) 10.3.1 Port A Table 10. Port A0, A3, A4, A5, A6, A7 description
PORT A PA0 PA3 PA4 I/O Input1 with pull-up with pull-up with pull-up Output push-pull push-pull Signal MCO (Main Clock Output) Timer EXTCLK Timer ICAP1 push-pull IT1 Schmitt triggered input Timer ICAP2 push-pull IT2 Schmitt triggered input Timer OCMP1 push-pull IT3 Schmitt triggered input Timer OCMP2 push-pull IT4 Schmitt triggered input IT2E = 1 (ITIFRE) O C1E = 1 IT3E = 1 (ITIFRE) O C2E = 1 IT4E = 1 (ITIFRE) IT1E = 1 (ITIFRE) Alternate function Condition MCO = 1 (MISCR) CC1 =1 CC0 = 1 (Timer CR2)
PA5 PA62
with pull-up
with pull-up
PA7
1 2
with pull-up
Reset State Not available on SO24
Figure 22. PA0, PA3, PA4, PA5, PA6, PA7 and PD[7:4] configuration
ALTERNATE ENABLE ALTERNATE 1 OUTPUT 0 VDD
P-BUFFER
DR LATCH ALTERNATE ENABLE DDR LATCH DDR SEL
DATA BUS
VDD
PULL-UP
PAD
N-BUFFER DR SEL 1 DIODES ALTERNATE ENABLE VSS
ALTERNATE INPUT
0
CMOS SCHMITT TRIGGER
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I/O ports (Cont'd) Table 11. PA1, PA2 description
P OR T A PA1 PA2
1
I/O Input 1 without pull-up without pull-up Output Very High Current open drain Very High Current open drain
Alternate function Signal SDA (I²C data) SCL (I²C clock) Co n d i t i o n I²C enable I²C enable
Reset State
Figure 23. PA1, PA2 configuration
ALTERNATE ENABLE ALTERNATE 1 OUTPUT 0 DR LATCH
DDR LATCH
DATA BUS
PAD
DDR SEL
N-BUFFER
DR SEL
1 0
ALTERNATE ENABLE VSS CMOS SCHMITT TRIGGER
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I/O ports (Cont'd) 10.3.2 Port B Table 12. Port B description
POR T B Input1 PB0 without pull-up I /O Output push-pull Signal Analog input (ADC) Analog input (ADC) PB1 without pull-up push-pull USBOE (USB output enable)2 Analog input (ADC) Analog input (ADC) Analog input (ADC) PB4 without pull-up push-pull IT5 Schmitt triggered input Analog input (ADC) PB5 without pull-up push-pull IT6 Schmitt triggered input Analog input (ADC) PB6 without pull-up push-pull IT7 Schmitt triggered input Analog input (ADC) PB7
1Reset 2
Alternate function Co n d i t i o n CH[3:0] = 000 (ADCCSR) CH[3:0] = 001 (ADCCSR) USBOE =1 (MISCR) CH[3:0]= 010 (ADCCSR) CH[3:0]= 011 (ADCCSR) CH[3:0]= 100 (ADCCSR) IT4E = 1 (ITIFRE) CH[3:0]= 101 (ADCCSR) IT5E = 1 (ITIFRE) CH[3:0]= 110 (ADCCSR) IT6E = 1 (ITIFRE) CH[3:0]= 111 (ADCCSR) IT7E = 1 (ITIFRE)
PB2 PB3
without pull-up without pull-up
push-pull push-pull
without pull-up State
push-pull IT8 Schmitt triggered input
On SO24 only
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Figure 24. Port B and D[3:0] configuration
ALTERNATE ENABLE ALTERNATE OUTPUT DR LATCH ALTERNATE ENABLE DDR LATCH PAD ANALOG ENABLE (ADC) DDR SEL 1 0 P-BUFFER VDD
V DD
ALTERNATE INPUT
COMMON ANALOG RAIL
DATA BUS
ANALOG SWITCH N-BUFFER 1 ALTERNATE ENABLE 0 DIGITAL ENABLE VSS
DIODES
DR SEL
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I/O ports (Cont'd) 10.3.3 Port C Table 13. Port C description
I/O PO RT C Input PC0 PC1 PC 2 2
1 2 1
Alternate function Output Signal RDI (SCI input) TDO (SCI output) USBOE (USB output enable) SCI enable USBOE =1 (MISCR) Co n d i t i o n
with pull-up with pull-up with pull-up
push-pull push-pull push-pull
Reset State Not available on SO24
Figure 25. Port C configuration
ALTERNATE ENABLE ALTERNATE 1 OUTPUT 0 VDD
P-BUFFER
DR LATCH ALTERNATE ENABLE
DATA BUS
PULL-UP
VDD
DDR LATCH DDR SEL PAD
N-BUFFER 1
DR SEL
DIOD ES
ALTERNATE ENABLE
0 ALTERNATE INPUT
V SS
CMOS SCHMITT TRIGGER
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10.3.4 Port D Table 14. Port D description
I/O PORT D Input* PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 *Reset State without pull-up without pull-up without pull-up without pull-up with pull-up with pull-up with pull-up with pull-up Output push-pull push-pull push-pull push-pull push-pull push-pull push-pull push-pull Signal Analog input (ADC) Analog input (ADC) Analog input (ADC) Analog input (ADC) Condition CH[3:0] = 1000 (ADCCS R) CH[3:0] = 1001 (ADCCS R) CH[3:0] = 1010 (ADCCS R) CH[3:0] = 1011 (ADCCS R) Alternate function
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I/O ports (Cont'd) 10.3.5 Register description Data registers (PxDR) Port A Data Register (PADR): 0000h Port B Data Register (PBDR): 0002h Port C Data Register (PCDR): 0004h Port D Data Register (PDDR): 0006h Read / Write Reset value Port A: 0000 0000 (00h) Reset value Port B: 0000 0000 (00h) Reset value Port C: 1111 x000 (FXh) Reset value Port D: 0000 0000 (00h) Note: For Port C, unused bits (7-3) are not accessible.
7 D7 D6 D5 D4 D3 D2 D1 0
Data Direction Register (PxDDR) Port A Data Direction Register (PADDR): 0001h Port B Data Direction Register (PBDDR): 0003h Port C Data Direction Register (PCDDR): 0005h Port D Data Direction Register (PDDDR): 0007h Read/Write Reset value Port A: 0000 0000 (00h) Reset value Port B: 0000 0000 (00h) Reset value Port C: 1111 x000 (FXh) Reset value Port D: 0000 0000 (00h) Note: For Port C, unused bits (7-3) are not accessible
7 DD 7 DD6 DD5 DD4 DD 3 DD2 DD1 0 DD0
D0
Bit 7:0 = D[7:0] Data Register 8 bits. The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken into account even if the pin is configured as an input. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input). Note: When using open-drain I/Os in output configuration, the value read in DR is the digital value applied to the I/Opin. Table 15. I/O ports register map
Address (Hex.) 00 01 02 03 04 05 06 07 Register label PADR PADD R PBDR PBDD R PCDR PCDD R PDDR PDDD R 7 MS B MS B MS B MS B MS B MS B MS B MS B 6 5
Bit 7:0 = DD[7:0] Data Direction Register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bit is set and cleared by software. 0: Input mode 1: Output mode
4
3
2
1
0 LSB LSB LSB LSB LSB LSB LSB LSB
Related documentation AN 970: SPI communication between ST7 and EEPROM AN1045: S/W implementation of I2C bus master AN1048: Software LCD driver
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11 Miscellaneous register
Address: 0009h -- Read/Write Reset value: 0000 0000 (00h)
7
SMS USBOE
0
MCO
Bit 7:3 = Reserved Bit 2 = SMS Slow Mode Select. This bit is set by software and only cleared by hardware after a reset. If this bit is set, it enables the use of an internal divide-by-2 clock divider (refer to Figure 18 on page 26). The SMS bit has no effect on the USB frequency. 0: Divide-by-2 disabled and CPU clock frequency is standard
1: Divide-by-2 enabled and CPU clock frequency is halved. Bit 1 = USBOE USB enable. If this bit is set, the port PC2 (PB1 on SO24) outputs the USB output enable signal (at "1" when the ST7 USB is transmitting data). Unused bits 7-4 are set. Bit 0 = MCO Main Clock Out selection This bit enables the MCO alternate function on the PA0 I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for general-purpose I/O) 1: MCO alternate function enabled (fCPU on I/O port)
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12 On-chip peripherals
12.1 Watchdog timer (WDG) 12.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter's contents before the T6 bit becomes cleared. 12.1.2 Main features Programmable free-running counter (64 increments of 49,152 CPU cycles) Programmable reset Reset (if watchdog activated) when the T6 bit reaches zero Optional reset on HALT instruction (configurable by option byte) Hardware Watchdog selectable by option byte. 12.1.3 Functional description The counter value stored in the CR register (bits T6:T0), is decremented every 49,152 machine cyFigure 26. Watchdog block diagram cles, and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T6:T0) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 30s. The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. This downcounter is freerunning: it counts down even if the watchdog is disabled. The value to be stored in the CR register must be between FFh and C0h (see Table 16, ". Watchdog timing (fCPU = 8 MHz)"): The WDGA bit is set (watchdog enabled) The T6 bit is set to prevent generating an immediate reset The T5:T0 bits contain the number of increments which represents the time delay before the watchdog produces a reset.
RESET
WATCHDOG CONTROL REGISTER (CR) WDG A T6 T5 T4 T3 T2 T1 T0
7-BIT DOWNCOUNTER
fCPU
CLOCK DIVIDER ÷49152
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Watchdog timer (Cont'd) Table 16. Watchdog timing (fCPU = 8 MHz)
CR register initial value Max Min FFh C0 h WDG timeout period (ms) 393.216 6.144
Notes: Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). 12.1.4 Software Watchdog option If Software Watchdog is selected by option byte, the watchdog is disabled following a reset. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). 12.1.5 Hardware Watchdog option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used. 12.1.6 Low power modes WAIT instruction No effect on Watchdog. HALT instruction If the Watchdog reset on Halt option is selected by option byte, a HALT instruction causes an immediate reset generation if the Watchdog is activated (WDGA bit is set). 12.1.6.1 Using Halt mode with the WDG (option) If the Watchdog reset on Halt option is not selected by option byte, the Halt mode can be used when the watchdog is enabled.
In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the WDG stops counting and is no longer able to generate a reset until the microcontroller receives an external interrupt or a reset. If an external interrupt is received, the WDG restarts counting after 4096 CPU clocks. If a reset is generated, the WDG is disabled (reset state). Recommendations Make sure that an external event is available to wake up the microcontroller from Halt mode. Before executing the HALT instruction, refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller. When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as "Input Pull-up with Interrupt" before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure. The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E. As the HALT instruction clears the I bit in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). 12.1.7 Interrupts None.
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Watchdog timer (Cont'd) 12.1.8 Register description Control Register (CR) Read / Write Reset value: 0111 1111 (7Fh)
7 WDGA T6 T5 T4 T3 T2 T1 0 T0
hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).
Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by Table 17. Watchdog timer register map and reset values
Address (Hex.) 0Ch Register Label WDG C R Reset value 7 W D GA 0 6 T6 1 5 T5 1 4 T4 1 3 T3 1 2 T2 1 1 T1 1 0 T0 1
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12.2 16-bit timer 12.2.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler. Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequencies are not modified. This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B). 12.2.2 Main features Programmable prescaler: fCPU divided by 2, 4 or 8 Overflow status flag and maskable interrupt External clock input (must be at least four times slower than the CPU clock speed) with the choice of active edge 1 or 2 Output Compare functions each with: 2 dedicated 16-bit registers 2 dedicated programmable signals 2 dedicated status flags 1 dedicated maskable interrupt 1 or 2 Input Capture functions each with: 2 dedicated 16-bit registers 2 dedicated active edge selection signals 2 dedicated status flags 1 dedicated maskable interrupt Pulse width modulation mode (PWM) One Pulse mode Reduced Power mode 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)* The block diagram is shown in Figure 27. *Note: Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pin out description. When reading an input signal on a non-bonded pin, the value will always be `1'. 12.2.3 Functional description 12.2.3.1 Counter The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high and low. Counter Register (CR): Counter High Register (CHR) is the most significant byte (MS byte). Counter Low Register (CLR) is the least significant byte (LS byte). Alternate Counter Register (ACR) Alternate Counter High Register (ACHR) is the most significant byte (MS byte). Alternate Counter Low Register (ACLR) is the least significant byte (LS byte). These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register, (SR), (see note at the end of paragraph titled 16-bit read sequence). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode. The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 18, "Clock Control Bits". The value in the counter register repeats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be fCPU/2, fCPU/4, fCPU/8 or an external frequency.
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16-bit timer (Cont'd) Figure 27. Timer block diagram
ST7 INTERNAL BUS fCPU MCU-PERIPHERAL INTERFACE 8 low 8-bit buffer EXEDG 16 1/2 1/4 1/8 EX TCLK pin COUNTER REGISTER ALTERNATE COUNTER REGISTER 16 CC [1:0] TIMER INTERNAL BUS 16 16 OVERFLOW DE TECT CIRCUIT O UT PUT C OM P A R E REGISTER 1 O UT PUT COM PARE REGISTER 2 INPUT CAPTURE REGISTER 1 16 INPUT CAPTURE REGISTER 2 16 8 high low 8 high 8 low 8 high 8 low 8 high 8 low 8
8 high
OUTPUT COMPARE CIRCUIT 6
EDGE DETECT CIRCU IT1
IC AP1 pin
EDGE DETECT CIRCUIT2
IC AP2 pin
LATCH1
ICF1 OCF1 TOF ICF2 OCF2 TIMD
O C MP 1 pin O C MP 2 pin
0
0 LATCH2
(Control/Status Register) CSR
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
OC1E OC2E OPM PWM
CC1
CC0 IEDG2 EXEDG
(Control Register 1) CR1
(Control Register 2) CR2
(See note) TIMER INTERRUPT
Note: If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See device Interrupt Vector Table)
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16-bit timer (Cont'd) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence At t0 Read MS byte Other inst ructions Read At t0 +t LS byte Sequence completed The user must read the MS byte first, then the LS byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS byte of the count value at the time of the read. Whatever the timer mode used (input capture, output compare, One Pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: The TOF bit of the SR register is set. A timer interrupt is generated if: TOIE bit of the CR1 register is set and I bit of the CC register is cleared. If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true.
Returns the buffered
LS byte is buffered
LS byte value at t0
Clearing the overflow interrupt request is done in two steps: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. Notes: The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously. The timer is not affected by Wait mode. In Halt mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset). 12.2.3.2 External clock The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter. The counter is synchronized with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency.
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16-bit timer (Cont'd) Figure 28. Counter timing diagram, internal clock divided by 2
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFD FFFE FFFF 0000 0001 0002 0003
Figure 29. Counter timing diagram, internal clock divided by 4
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000 0001
Figure 30. Counter timing diagram, internal clock divided by 8
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000
Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
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16-bit timer (Cont'd) 12.2.3.3 Input Capture In this section, the index, i, may be 1 or 2 because there are two input capture functions in the 16-bit timer. The two 16-bit input capture registers (IC1R and IC2R) are used to latch the value of the free running counter after a transition is detected on the ICAPi pin (see Figure 31).
ICiR MS byte ICiHR LS byte ICiLR
ICiR register is a read-only register. The active transition is software programmable through the IEDGi bit of Control Registers (CRi). Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the input capture function select the following in the CR2 register: Select the timer clock (CC[1:0]) (see Table 18, "Clock Control Bits"). Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). And select the following in the CR1 register: Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1pin must be configured as floating input or input with pullup without interrupt if this configuration is available).
When an input capture occurs: ICFi bit is set. The ICiR register contains the value of the free running counter on the active transition on the ICAPi pin (see Figure 32). A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true. Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. Notes: 1. After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2. The ICiR register contains the free running counter value which corresponds to the most recent input capture. 3. The two input capture functions can be used together even if the timer also uses the two output compare functions. 4. In One Pulse mode and PWM mode only Input Capture 2 can be used. 5. The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any transitions on these pins activates the input capture function. Moreover if one of the ICAPi pins is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the ICiHR (see note 1). 6. The TOF bit can be used with interrupt generation in order to measure events that go beyond the timer range (FFFFh).
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16-bit timer (Cont'd) Figure 31. Input Capture block diagram
ICAP1 pin ICAP2 pin EDGE DETECT CIRC UIT2 EDGE DETECT CIRC UIT1
ICIE
(Control Register 1) CR1
IEDG1
(Status Register) SR IC2R Register IC1R Register
ICF1 ICF2 0 0 0
16-BIT 16-BIT FREE RUNNING CO UNTER
(Control Register 2) CR2
CC1 CC0 IEDG2
Figure 32. Input Capture timing diagram
TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER Note: The rising edge is the active edge. FF03 FF01 FF02 FF03
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16-bit timer (Cont'd) 12.2.3.4 Output Compare In this section, the index, i, may be 1 or 2 because there are two output compare functions in the 16bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Compare register and the free running counter, the output compare function: Assigns pins with a programmable value if the OCiE bit is set Sets a flag in the status register Generates an interrupt if enabled Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle.
OCiR MS byte OC i H R LS byte OCiLR
The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset). A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is cleared in the CC register (CC). The OCiR register value required for a specific timing application can be calculated using the following formula:
OCiR =
t * fCPU
PRESC
Where: t = Output compare period (in seconds) fCPU = CPU clock frequency (in hertz) = Timer prescaler factor (2, 4 or 8 dePRESC pending on CC[1:0] bits, see Table 18, "Clock Control Bits") If the timer clock is an external clock, the formula is :
These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OCiR value to 8000h. Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the output compare function, select the following in the CR2 register: Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output compare i signal. Select the timer clock (CC[1:0]) (see Table 18, "Clock Control Bits"). And select the following in the CR1 register: Select the OLVLi bit to applied to the OCMPi pins after the match occurs. Set the OCIE bit to generate an interrupt if it is needed. When a match is found between OCiR register and CR register: OCFi bit is set.
OCiR = t * fEXT
Where: t = Output compare period (in seconds) fEXT = External timer clock frequency (in hertz) Clearing the output compare interrupt request (that is, clearing the OCFi bit) is done by: 1. Reading the SR register while the OCFi bit is set. 2. An access (read or write) to the OCiLR register. The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OCiR register: Write to the OCiHR register (further compares are inhibited). Read the SR register (first step of the clearance of the OCFi bit, which may be already set). Write to the OCiLR register (enables the output compare function and clears the OCFi bit).
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16-bit timer (Cont'd) Notes: 1. After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set. 3. In both internal and external clock modes, OCFi and OCMPi are set while the counter value equals the OCiR register value (see Figure 34 on page 53 for an example with fCPU/2 and Figure 35 on page 53 for an example with fCPU/4). This behavior is the same in OPM or PWM mode. 4. The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also use |
