M41T81
Serial access real-time clock with alarm
Not For New Design
Features
For new designs use M41T81S Counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century 32 KHz crystal oscillator integrating load capacitance (12.5 pF) providing exceptional oscillator stability and high crystal series resistance operation Serial interface supports I2C bus (400 kHz protocol) Ultra-low battery supply current of 0.6 A (typ at 3 V) 2.0 to 5.5 V clock operating voltage Automatic switch-over and deselect circuitry (for 3V application select M41T81S datasheet) Power-down time stamp (HT bit) allowing determination of time elapsed in battery backup Programmable alarm and interrupt function (valid even during battery backup mode) Accurate programmable watchdog timer (from 62.5 ms to 128 s) Software clock calibration to compensate crystal deviation due to temperature Operating temperature of 40 to 85C ECOPACK package available
8 1
SO8 (M) 8-pin SOIC
May 2008
Rev 9
1/30
www.st.com 1
This is information on a product still in production but not recommended for new designs.
Contents
M41T81
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Star t data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 2.3 2.4
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 Power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Preferred initial power-on default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4 5 6 7 8
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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M41T81
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Clock register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Preferred default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SO8 8-lead plastic small outline (150 mils body width), package mechanical data. . . . . 27 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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List of figures
M41T81
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8-pin SOIC (M) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Alternative READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Backup mode alarm waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SO8 8-lead plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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M41T81
Description
1
Description
The M41T81 is a low power serial RTC with a built-in 32.768 kHz oscillator (external crystal controlled). Eight bytes of the SRAM (see Table 2: Clock register map on page 14) are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. An additional 12 bytes of SRAM provide status/control of Alarm, Watchdog and Square Wave functions. Addresses and data are transferred serially via a two line, bidirectional I2C interface. The built-in address register is incremented automatically after each WRITE or READ data byte. The M41T81 has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power failure occurs. The energy needed to sustain the SRAM and clock operations can be supplied by a small lithium button supply when a power failure occurs. Functions available to the user include a non-volatile, time-of-day clock/calendar, alarm interrupts, watchdog timer and programmable square wave output. The eight clock address locations contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24-hour BCD format. Corrections for 28, 29 (leap year valid until year 2100), 30 and 31 day months are made automatically. The M41T81 is supplied in an 8-pin SOIC. Figure 1. Logic diagram
VCC VB A T
XI XO M41T81 SCL SDA IRQ/FT/OUT/SQW
VSS
AI04613
5/30
Description Table 1. Signal names
XI XO IRQ/OUT/FT/SQW SDA SCL VBAT VCC VSS Oscillator input Oscillator output
M41T81
Interrupt / output driver / frequency test / square wave (open drain) Serial data input/output Serial clock input Battery supply voltage Supply voltage Ground
Figure 2.
8-pin SOIC (M) connections
XI XO VBAT VSS
1 2 3 4
M41T81
8 7 6 5
VCC IRQ/FT/OUT/SQW SCL SDA
AI04769
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M41T81 Figure 3. Block diagram
REAL TIME CLOCK CALENDAR 32KHz OSCILLATOR
Description
CRYSTAL
RTC W/ALARM & CALIBRATION
AFE
SDA
WATCHDOG IC INTERFACE
2
IRQ/FT/OUT/SQW SQWE
(1,2)
SCL WRITE PROTECT
SQUARE WAVE
FREQUENCY TEST FT OUTPUT DRIVER OUT
INTERNAL POWER VCC
VBAT VSO
(3)
COMPARE
AI04616
1. Open drain output 2. Square wave function has the highest priority on IRQ/FT/OUT/SQW output. 3. VSO = VBAT 0.5 V (typ)
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Operation
M41T81
2
Operation
The M41T81 clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 20 bytes contained in the device can then be accessed sequentially in the following order:
1st byte: tenths/hundredths of a second register 2nd byte: seconds register 3rd byte: minutes register 4th byte: century/hours register 5th byte: day register 6th byte: date register 7th byte: month register 8th byte: year register 9th byte: control register 10th byte: watchdog register 11th - 16th bytes: alarm registers 17th - 19th bytes: reserved 20th byte: square wave register
The M41T81 clock continually monitors VCC for an out-of-tolerance condition. Should VCC fall below VSO, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from a an out-of-tolerance system. The device also automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. For more information on battery storage life refer to Application Note AN1012.
2.1
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined:
Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line, while the clock line is high, will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
2.1.1
Bus not busy
Both data and clock lines remain high.
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M41T81
Operation
2.1.2
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the START condition.
2.1.3
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the STOP condition.
2.1.4
Data valid
The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition a device that gives out a message is called "transmitter," the receiving device that gets the message is called "receiver." The device that controls the message is called "master." The devices that are controlled by the master are called "slaves."
2.1.5
Acknowledge
Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the transmitter must leave the data line high to enable the master to generate the STOP condition.
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Operation Figure 4. Serial bus data transfer sequence
M41T81
DATA LINE STABLE DATA VALID
CLOCK
DATA
START CONDITION
CHANGE OF DATA ALLOWED
STOP CONDITION
AI00587
Figure 5.
Acknowledgement sequence
START CLOCK PULSE FOR ACKNOWLEDGEMENT 1 2 8 9
SCL FROM MASTER
DATA OUTPUT BY TRANSMITTER
MSB
LSB
DATA OUTPUT BY RECEIVER
AI00601
2.2
READ mode
In this mode the master reads the M41T81 slave after setting the slave address (see Figure 7 on page 11). Following the WRITE mode control bit (R/W=0) and the acknowledge bit, the word address 'An' is written to the on-chip address pointer. Next the START condition and slave address are repeated followed by the READ mode control bit (R/W=1). At this point the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. The address pointer is only incremented on reception of an acknowledge clock. The M41T81 slave transmitter will now place the data byte at address An+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to "An+2." This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume due to a stop condition or when the pointer increments to any non-clock address (08h-13h).
Note:
This is true both in READ mode and WRITE mode.
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M41T81
Operation An alternate READ mode may also be implemented whereby the master reads the M41T81 slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure 8 on page 11). Figure 6. Slave address location
R/W
START
SLAVE ADDRESS
A
MSB
1
1
0
1
0
0
LSB 0
AI00602
START
Figure 7.
READ mode sequence
START
R/W
BUS ACTIVITY: MASTER
SDA LINE
S
WORD ADDRESS (An)
ACK
S
R/W
DATA n
DATA n+1
ACK
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
SLAVE ADDRESS
STOP
DATA n+X
P
AI00899
Figure 8.
Alternative READ mode sequence
START R/W STOP DATA n ACK ACK DATA n+1 ACK ACK DATA n+X P NO ACK
AI00895
BUS ACTIVITY: MASTER SDA LINE
S
BUS ACTIVITY: SLAVE ADDRESS
NO ACK
ACK
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Operation
M41T81
2.3
WRITE mode
In this mode the master transmitter transmits to the M41T81 slave receiver. Bus protocol is shown in Figure 9 on page 12. Following the START condition and slave address, a logic '0' (R/W=0) is placed on the bus and indicates to the addressed device that word address "An" will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next address location on the reception of an acknowledge clock. The M41T81 slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address see Figure 6 on page 11 and again after it has received the word address and each data byte.
2.4
Data retention mode
With valid VCC applied, the M41T81 can be accessed as described above with READ or WRITE Cycles. Should the supply voltage decay, the power input will be switched from the VCC pin to the battery when VCC falls below the battery backup switchover voltage (VSO). At this time the clock registers will be maintained by the attached battery supply. On power-up, when VCC returns to a nominal value, write protection continues for trec (see Figure 10 on page 23, Table 11 on page 24). For a further, more detailed review of lifetime calculations, please see application note AN1012. Figure 9. WRITE mode sequence
START
START
R/W
BUS ACTIVITY: MMASTER ASTER SSA LINE D DA LINE
R/W
BUS ACTIVITY:
S
S
ACK
WORD ADDRESS DATA (An)
ACK
DA n DATA n DATA n+1TA n+1
ACK ACK
DATA n+X
DAP A n+X T
ACK
STOP
P NO ACK
ACK
ACK
ACK
BUS ACTIVITY:
BUS ACTIVITY:
SLAVE ADDRSSS VE E LA
AI00591
ADDRESS
ACK
AI00895
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STOP
M41T81
Clock operation
3
Clock operation
The 20-byte register map (see Table 2 on page 14) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers.
Note:
The Tenths/hundredths of seconds cannot be written to any value other than "00." Bits D6 and D7 of clock register 03h (century/hours register) contain the CENTURY ENABLE bit (CEB) and the CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of register 04h contain the day (day of week). Registers 05h, 06h, and 07h contain the date (day of month), month and Years. The ninth clock register is the control register (this is described in the clock calibration section). Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts within one second. The eight clock registers may be read one byte at a time, or in a sequential block. Provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of data during the READ.
3.1
Power-down time-stamp
When a power failure occurs, the HT bit will automatically be set to a '1.' This will prevent the clock from updating the TIMEKEEPER registers, and will allow the user to read the exact time of the power-down event. Resetting the HT bit to a '0' will allow the clock to update the TIMEKEEPER registers with the current time. For more information, see application note AN1572.
3.2
Clock registers
The M41T81 offers 20 internal registers which contain clock, alarm, watchdog, flag, square wave and control data. These registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORTTM cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. The internal divider (or clock) chain will be reset upon the completion of a WRITE to any clock address. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume either due to a stop condition or when the pointer increments to any non-clock address (08h-13h). Clock and alarm registers store data in BCD. Control, watchdog and square wave registers store data in binary format.
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Clock operation Table 2.
Addr D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h
1. Keys:
S = Sign bit FT = Frequency test bit ST = Stop bit 0 = Must be set to '0' BMB0-BMB4 = Watchdog multiplier bits CEB = Century enable bit CB = Century bit OUT = Output level ABE = Alarm in battery backup mode enable bit AFE = Alarm flag enable flag RB0-RB1 = Watchdog resolution bits RPT1-RPT5 = Alarm repeat mode bits WDF = Watchdog flag (read only) AF = Alarm flag (read only) SQWE = Square wave enable RS0-RS3 = SQW frequency HT = Halt update bit
M41T81
Clock register map(1)
Function/range BCD format Seconds Seconds Minutes Centur y/ hours Day Date Month Year Control RB1 RB0 Watchdog Al month Al date Al hour Al min Al sec 0 0 0 0 0 Flags Reserved Reserved Reserved SQW 01-12 01-31 00-23 00-59 00-59 00-99 00-59 00-59 0-1/00-23 01-7 01-31 01-12 00-99
D6
D5
D4
D3
D2
D1
D0
0.1 seconds ST 0 CEB 0 0 0 CB 0 0 0 0 10 years OUT 0 AFE RPT4 RPT3 RPT2 RPT1 WDF 0 0 0 RS3 AF 0 0 0 RS2 FT BMB4 SQWE RPT5 HT S BMB3 ABE BMB2 Al 10M BMB1 0 10 date 10M 10 seconds 10 minutes 10 hours 0 0
0.01 seconds Seconds Minutes Hours (24 hour format) Day of week Date: day of month Month Year Calibration BMB0
Alarm month Alarm date Alarm hour Alarm minutes Alarm seconds
AI 10 date AI 10 hour
Alarm 10 minutes Alarm 10 seconds 0 0 0 0 RS1 0 0 0 0 RS0 0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
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M41T81
Clock operation
3.3
Calibrating the clock
The M41T81 is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not exceed 35 ppm (parts per million) oscillator frequency error at 25oC, which equates to about +1.9 to 1.1 minutes per month (see Figure 10 on page 16). When the calibration circuit is properly employed, accuracy improves to better than 2 ppm at 25C. The oscillation rate of crystals changes with temperature. The M41T81 design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 11 on page 16. The number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the control register. Adding counts speeds the clock up, subtracting counts slows the clock down. The calibration bits occupy the five lower order bits (D4-D0) in the control register 08h. These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or 2.034 ppm of adjustment per calibration step in the calibration register (see Figure 11 on page 16). Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or 5.35 seconds per month which corresponds to a total range of +5.5 or 2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M41T81 may require. The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in application note AN934, "TIMEKEEPER calibration." This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of the IRQ/FT/OUT/SQW pin. The pin will toggle at 512Hz, when the stop bit (ST, D7 of 01h) is '0,' the frequency test bit (FT, D6 of 08h) is '1,' the alarm flag enable bit (AFE, D7 of 0Ah) is '0,' and the square wave enable bit (SQWE, D6 of 0Ah) is '0' and the watchdog register (09h = 0) is reset. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm oscillator frequency error, requiring a 10 (XX001010) to be loaded into the calibration byte for correction. Note that setting or changing the calibration byte does not affect the frequency test output frequency.
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Clock operation
M41T81
The IRQ/FT/OUT/SQW pin is an open drain output which requires a pull-up resistor to VCC for proper operation. A 500-10 k resistor is recommended in order to control the rise time. The FT bit is cleared on power-down. Figure 10. Crystal accuracy across temperature
Frequency (ppm) 20 0 20 40 60 80 100 120 140 160 40 30 20 10 0 10 20 30 40 50 60 70 80 F = K x (T T )2 O F K = 0.036 ppm/C 0.006 ppm/C TO = 25C 5C
2 2
Temperature C
AI07888
Figure 11. Clock calibration
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
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M41T81
Clock operation
3.4
Setting alarm clock registers
Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second or repeat every year, month, day, hour, minute, or second. It can also be programmed to go off while the M41T81 is in the battery backup mode to serve as a system wake-up call. Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Table 3 on page 18 shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. When the clock information matches the alarm clock settings based on the match criteria defined by RPT5-RPT1, the AF (alarm flag) is set. If AFE (alarm flag enable) is also set (and SQWE is '0.'), the alarm condition activates the IRQ/FT/OUT/SQW pin.
Note:
If the address pointer is allowed to increment to the flag register address, an alarm condition will not cause the interrupt/flag to occur until the address pointer is moved to a different address. It should also be noted that if the last address written is the "alarm seconds," the address pointer will increment to the flag address, causing this situation to occur. The IRQ/FT/OUT/SQW output is cleared by a READ to the flags register as shown in Figure 12. A subsequent READ of the flags register is necessary to see that the value of the alarm flag has been reset to '0.' The IRQ/FT/OUT/SQW pin can also be activated in the battery backup mode. The IRQ/FT/OUT/SQW will go low if an alarm occurs and both ABE (alarm in battery backup mode enable) and AFE are set. Figure 13 illustrates the backup mode alarm timing. Figure 12. Alarm interrupt reset waveform
0Eh 0Fh 10h
ACTIVE FLAG
IRQ/FT/OUT/SQW
HIGH-Z
AI04617
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Clock operation Figure 13. Backup mode alarm waveform
VCC
M41T81
VSO trec ABE and AFE Bits AF Bit in Flags Register IRQ/FT/OUT/SQW
HIGH-Z
AI05663
Table 3.
RPT5 1 1 1 1 1 0
Alarm repeat modes
RPT4 1 1 1 1 0 0 RPT3 1 1 1 0 0 0 RPT2 1 1 0 0 0 0 RPT1 1 0 0 0 0 0 Alarm setting Once per second Once per minute Once per hour Once per day Once per month Once per year
3.5
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (For example: writing 00001110 in the watchdog register = 3*1, or 3 seconds). If the processor does not reset the timer within the specified period, the M41T81 sets the WDF (watchdog flag) and generates a watchdog interrupt. The watchdog timer can be reset by having the microprocessor perform a WRITE of the watchdog register. The time-out period then starts over. Should the watchdog timer time-out, a value of 00h needs to be written to the watchdog register in order to clear the IRQ/FT/OUT/SQW pin. This will also disable the watchdog function until it is again programmed correctly. A READ of the flags register will reset the watchdog flag (Bit D7; register 0Fh). The watchdog function is automatically disabled upon power-up and the watchdog register is cleared. If the watchdog function is set, the frequency test function is activated, and the SQWE bit is '0,' the watchdog function prevails and the frequency test function is denied.
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M41T81
Clock operation
3.6
Square wave output
The M41T81 offers the user a programmable square wave function which is output on the SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These frequencies are listed in Table 4. Once the selection of the SQW frequency has been completed, the IRQ/FT/OUT/SQW pin can be turned on and off under software control with the square wave enable bit (SQWE) located in register 0Ah. Table 4. Square wave output frequency
Square wave bits RS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Square wave Frequency None 32.768 8.192 4.096 2.048 1.024 512 256 128 64 32 16 8 4 2 1 Units kHz kHz kHz kHz kHz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz
3.7
Century bit
Bits D7 and D6 of clock register 03h contain the CENTURY ENABLE bit (CEB) and the CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle.
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Clock operation
M41T81
3.8
Output driver pin
When the FT bit, AFE bit, SQWE bit, and watchdog register are not set, the IRQ/FT/OUT/SQW pin becomes an output driver that reflects the contents of D7 of the control register. In other words, when D7 (OUT bit) and D6 (FT bit) of address location 08h are a '0,' then the IRQ/FT/OUT/SQW pin will be driven low.
Note:
The IRQ/FT/OUT/SQW pin is an open drain which requires an external pull-up resistor.
3.9
Preferred initial power-on default
Upon initial application of power to the device, the following register bits are set to a '0' state: watchdog register; AFE; ABE; SQWE; and FT. The following bits are set to a '1' state: ST; OUT; and HT (see Table 5 on page 20). Table 5. Preferred default values
Condition Initial power-up(2) Subsequent power-up (with battery backup)(3)
1. 2. 3.
BMB0-BMB4, RB0, RB1. State of other control bits undefined. UC = unchanged
ST 1 UC
HT 1 1
Out 1 UC
FT 0 0
AFE 0 UC
SQWE 0 UC
ABE 0 UC
Watchdog register(1) 0 0
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M41T81
Maximum ratings
4
Maximum ratings
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 6.
Sym TSTG
VCC
Absolute maximum ratings
Parameter Storage temperature (VCC off, oscillator off) Supply voltage Lead solder temperature for 10 seconds Input or output voltages Output current Power dissipation Value 55 to 125 0.3 to 7 260 0.3 to VCC+0.3 20 1 Unit C V C V mA W
TSLD(1) VIO IO PD
1. Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds).
Caution:
Negative undershoots below 0.3 volts are not allowed on any pin while in the battery backup mode
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DC and AC parameters
M41T81
5
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 7. Operating and AC measurement conditions(1)
Parameter Supply voltage (VCC) Ambient operating temperature (TA) Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages
1.
Output Hi-Z is defined as the point where data is no longer driven.
M41T81 2.0 to 5.5 V 40 to 85C 100 pF 50 ns 0.2VCC to 0.8 VCC 0.3VCC to 0.7 VCC
Figure 14. AC measurement I/O waveform
0.8VCC
0.7VCC 0.3VCC
AI02568
0.2VCC
Table 8.
Symbol CIN COUT(3) tLP
1. 2. 3.
Capacitance
Parameter(1) (2) Input capacitance Output capacitance Low-pass filter input time constant (SDA and SCL) Min Max 7 10 50 Unit pF pF ns
Effective capacitance measured with power supply at 5V; sampled only, not 100% tested. At 25C, f = 1 MHz. Outputs deselected.
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M41T81 Table 9.
Sym ILI ILO ICC1 ICC2 VIL VIH
VOL
DC and AC parameters DC characteristics
Parameter Input leakage current Output leakage current Supply current Supply current (standby) Input low voltage Input high voltage Output low voltage Output low voltage (open drain)(2) Pull-up supply voltage (open drain) VBAT(3) Battery supply voltage IBAT
1. 2. 3. 4. 5.
Test condition(1) 0V VIN VCC 0V VOUT VCC Switch freq = 400 kHz SCL,SDA = VCC 0.3V
Min
Typ
Max 1 1 400 100
Unit A A A A V V V V V V A
0.3 0.7VCC IOL = 3.0 mA IOL = 10 mA IRQ/OUT/FT/SQW 2.5(4) TA = 25C, VCC = 0 V oscillator on, VBAT = 3 V 3 0.6
0.3VCC VCC + 0.3 0.4 0.4 5.5 3.5(5) 1
Battery supply current
Valid for ambient operating temperature: TA = 40 to 85C; VCC = 2.0 to 5.5 V (except where noted). For IRQ/FT/OUT/SQW pin (open drain) STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equivalent) as the battery supply. After switchover (VSO), VBAT (min) can be 2.0 V for crystal with RS = 40 K. For rechargeable back-up, VBAT (max) may be considered VCC.
Table 10.
Sym fO RS CL
1.
Crystal electrical characteristics
Parameter(1) (2) Resonant frequency Series resistance Load capacitance 12.5 Min Typ 32.768 60 Max Units kHz k pF
Externally supplied. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp for further information on this crystal type. Load capacitors are integrated within the M41T81. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account.
2.
Figure 15. Power down/up mode AC waveforms
VCC VSO tPD SDA SCL DON'T CARE
AI00596
trec
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DC and AC parameters Table 11.
Symbol tPD trec
1. 2.
M41T81 Power down/up AC characteristics
Parameter(1) (2) SCL and SDA at VIH before power down SCL and SDA at VIH after power Up Min 0 10 Typ Max Unit nS S
VCC fall time should not exceed 5 mV/s. Valid for ambient operating temperature: TA = 40 to 85C; VCC = 2.0 to 5.5 V (except where noted).
Table 12.
Sym VSO
1. 2.
Power down/up trip points DC characteristics
Parameter(1) (2) Min Typ Max Unit V
Battery backup switchover voltage
VBAT 0.80 VBAT 0.50 VBAT 0.30
All voltages referenced to VSS. Valid for ambient operating temperature: TA = 40 to 85C; VCC = 2.0 to 5.5 V (except where noted).
Figure 16. Bus timing requirements sequence
SDA tBUF tHD:STA tR SCL tHIGH P S tLOW tSU:DAT tHD:DAT tSU:STA SR P tSU:STO tF tHD:STA
AI00589
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M41T81 Table 13.
Sym fSCL tLOW tHIGH tR tF tHD:STA
DC and AC parameters AC characteristics
Parameter(1) SCL clock frequency Clock low period Clock high period SDA and SCL rise time SDA and SCL fall time START condition hold time (after this period the first clock pulse is generated) START condition setup time (only relevant for a repeated start condition) Data setup time Data hold time STOP condition setup time Time the bus must be free before a new transmission can start 600 Min 0 1.3 600 300 300 Typ Max 400 Units kHz s ns ns ns ns
tSU:STA tSU:DAT tHD:DAT
(2)
600 100 0 600 1.3
ns ns s ns s
tSU:STO tBUF
1. 2.
Valid for ambient operating temperature: TA = 40 to 85C; VCC = 2.0 to 5.5 V (except where noted). Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of SCL.
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Package mechanical information
M41T81
6
Package mechanical information
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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M41T81
Package mechanical information Figure 17. SO8 8-lead plastic small package outline
h x 45 A2 b e 0.25 mm GAUGE PLANE k
8
A ccc c
D
E1
1
E A1 L L1
SO-A
1. Drawing is not to scale.
Table 14.
SO8 8-lead plastic small outline (150 mils body width), package mechanical data
Millimeters inches Max 1.75 0.10 1.25 0.28 0.17 0.48 0.23 0.10 4.90 6.00 3.90 1.27 4.80 5.80 3.80 0.25 0 0.40 1.04 5.00 6.20 4.00 0.50 8 1.27 0.041 0.193 0.236 0.154 0.050 0.189 0.228 0.150 0.010 0 0.016 0.25 0.004 0.049 0.011 0.007 0.019 0.009 0.004 0.197 0.244 0.157 0.020 8 0.050 Typ Min Ma x 0.069 0.010
Symbol Typ A A1 A2 b c ccc D E E1 e h k L L1 Min
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Part numbering
M41T81
7
Part numbering
Table 15.
Example:
Ordering information scheme
M41T 81 M 6 E
Device type M41T
Supply voltage and write protect voltage 81 = VCC = 2.0 to 5.5 V
Package M = SO8
Temperature range 6 = 40C to 85C
Shipping method E = ECOPACK package, tubes F = ECOPACK package, tape & reel
For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you.
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M41T81
Revision history
8
Revision history
Table 16.
Date Dec-2001 21-Jan-2002 01-May-2002 05-Jun-2002 10-Jun-2002 03-Jul-2002 11-Oct-2002 21-Jan-2003 05-Mar-2003 12-Sep-2003 27-Apr-2004 17-Jun-2004 7-Sep-2004 13-Sep-2004 03-Jun-2005
Document revision history
Revision 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 2.0 3.0 4.0 5.0 6.0 7 First issue Fix table footnotes (Table 9, Table 10) Modify reflow time and temperature footnote (Table 6) Modify data retention text, trip points (Table 12) Corrected supply voltage values (Table 6, Table 7) Modify DC characteristics, crystal electrical table footnotes, preferred default values (Table 9, Table 10, Table 5) Add marketing status (Figure 2; Table 15); adjust footnotes (Figure 2; Table 9) Add embedded crystal package option (Figure 1, 3, 23; Table 16); modified pre-existing mechanical drawing (Figure 17; Table 14). Correct dimensions (Table 16); remove SNAPHAT package option Updated disclaimer, v2.2 template; add SOX18 package (Figure 2, 4; Table 15) Reformatted; update characteristics (Figure 4, 3, Figure 3, Figure 10, Figure 13, Table 1, Table 6, Table 9, Table 12, Table 15) Reformatted; add lead-free information; add dual footprint connections (Figure 5;Table 6, Table 15) Update footprint and maximum ratings (Figure 5; Table 6) Update max ratings (Table 6) Remove SOX18 and SOX28 references (Features summary, Figure 1; Table 1, Table 6, Table 10, Table 15) Changed document to new template; Updated package mechanical data in Section 6: Package mechanical information; small text changes for entire document; ecopack compliant. Datasheet status updated to "not for new design" (updated cover page); updated Table 1, 6, 15. Changes
22-Aug-2006
8
28-May-2008
9
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M41T81
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