M41T94
Serial real-time clock with 44 bytes NVRAM and reset
Features
Counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century 32KHz crystal oscillator integrating load capacitance (12.5pF) providing exceptional oscillator stability and high crystal series resistance operation Serial peripheral interface (2MHz SPI) Ultra-low battery supply current of 500nA (max) 2.7 to 5.5V operating voltage 2.5 to 5.5V oscillator operating voltage Battery low flag Automatic switchover and deselect circuitry 44 bytes of general purpose RAM Programmable alarm and interrupt function (valid even during battery back-up mode) Accurate programmable watchdog timer (from 62.5ms to 128s) Microprocessor power-on reset Choice of power-fail deselect voltages (VCC = 2.7 to 5.5V): THS = VSS; 2.55V VPFD 2.70V THS = VCC; 4.20V VPFD 4.50V Packaging includes a 28-lead SOIC and SNAPHAT top (to be ordered separately) or 16-lead SOIC 28-lead SOIC package provides direct connection for a SNAPHAT top which contains the battery and crystal RoHS compliant Lead-free second level interconnect SNAPHAT (SH) battery & crystal SO16 (MQ)
16 1
28 1
SOH28 (MH)
November 2007
Rev 5
1/41
www.st.com 1
Contents
M41T94
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 2.2 2.3 2.4 Serial data output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Serial data input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Serial clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chip enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 3.2 3.3 SPI bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Read and write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 Power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Reset inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 tREC bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5 6 7
2/41
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
M41T94
Contents
8 9 10
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3/41
List of figures
M41T94
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 16-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 28-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data and clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Input timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Alarm interrupt reset waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Back-up mode alarm waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 RSTIN1 and RSTIN2 timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Calibration waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 SO16 16-lead plastic small outline package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SOH28 28-lead plastic small outline, battery SNAPHAT, package outline . . . . . . . . . . . 35 SH 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline . . . . . . . . . . 36 SH 4-pin SNAPHAT housing for 120mAh battery & crystal, package outline . . . . . . . . . 37
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M41T94
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Clock register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Alarm repeat mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Reset AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 tREC definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DC and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Crystal electrical characteristics (externally supplied) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 SO16 16-lead Plastic small outline package mechanical data . . . . . . . . . . . . . . . . . . . . 34 SOH28 28-lead plastic small outline, battery SNAPHAT, package mechanical data . . . 35 SH 4-pin SNAPHAT housing for 48mAh battery & crystal, package mechanical data . . 36 SH 4-pin SNAPHAT housing for 120mAh battery & crystal, package mech. data. . . . . . 37 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 SNAPHAT battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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Description
M41T94
1
Description
The M41T94 is a serial real-time clock with 44 bytes of NVRAM and a RESET output. A built-in 32,768Hz oscillator (external crystal controlled) and 8 bytes of the SRAM (see Table 4 on page 19) are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. An additional 12 bytes of RAM provide status/control of Alarm, Watchdog and Square Wave functions. Addresses and data are transferred serially via a serial SPI interface. The built-in address register is incremented automatically after each WRITE or READ data byte. The M41T94 has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power failure occurs. The energy needed to sustain the SRAM and clock operations can be supplied by a small lithium button-cell supply when a power failure occurs. Functions available to the user include a non-volatile, time-of-day clock/calendar, Alarm interrupts, Watchdog timer and programmable Square Wave output. Other features include a Power-On reset as well as two additional debounced inputs (RSTIN1 and RSTIN2) which can also generate an output reset (RST). The eight clock address locations contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24 hour BCD format. Corrections for 28, 29 (leap year valid until year 2100), 30 and 31 day months are made automatically. The ninth clock address location controls user access to the clock information and also stores the clock software calibration setting. The M41T94 is supplied in either a 16-lead plastic SOIC (requiring user supplied crystal and battery) or a 28-lead SOIC SNAPHAT package (which integrates both crystal and battery in a single SNAPHAT top). The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the SNAPHAT battery/crystal package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is also keyed to prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is "M4TXX-BR12SH" (see Table 21 on page 38).
Caution:
Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery.
6/41
M41T94 Figure 1. Logic diagram
VCC VBAT
(1)
Description
XI XO
(1) (1)
SCL SDI E RSTIN1 RSTIN2 WDI THS M41T94
RST IRQ/FT/OUT SQW SDO
VSS
1. For SO16 package only.
AI03683
Figure 2.
16-pin SOIC connections
XI XO RST WDI RSTIN1 RSTIN2 VBAT VSS
1 2 3 4 5 6 7 8
M41T94
16 15 14 13 12 11 10 9
AI03684
VCC E IRQ/FT/OUT THS SDI SQW SCL SDO
7/41
Description Table 1.
E IRQ/FT/OUT RST RSTIN1 RSTIN2 SCL SDI SDO SQW THS WDI XI
(1)
M41T94 Signal names
Chip enable Interrupt/frequency test/out output (open drain) Reset output (open drain) Reset 1 input Reset 2 input Serial clock input Serial data input Serial data output Square wave output Threshold select pin Watchdog input Oscillator input Oscillator output Batter y supply voltage Supply voltage Ground
XO (1) VBAT VCC VSS
1. For SO16 package only.
(1)
Figure 3.
28-pin SOIC connections
SQW NC NC NC NC NC NC WDI RSTIN1 RSTIN2 NC NC NC VSS 1 2 3 4 5 6 7 M41T94 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
AI03685
VCC E IRQ/FT/OUT NC NC THS NC NC SCL NC RST SDI SDO NC
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M41T94 Figure 4. Block diagram
E SDO SDI SCL SPI INTERFACE REAL TIME CLOCK CALENDAR 44 BYTES USER RAM RTC w/ALARM & CALIBRATION WATCHDOG SQUARE WAVE AF WDF
Description
IRQ/FT/OUT(1)
Crystal
32KHz OSCILLATOR
SQW
WDI VCC
VBAT VBL= 2.5V COMPARE BL
VSO = 2.5V
COMPARE
VPFD = 4.4V RSTIN1 RSTIN2
COMPARE
(2.65V if THS = VSS)
POR RST(1)
AI04785
1. Open drain output
Figure 5.
Hardware hookup
SPI Interface with (CPOL, CPHA)(1) = ('0','0') or ('1','1')
D Q C
Master (ST6, ST7, ST9, ST10, Others) CS3 CS2 CS1
C
Q
D
C
Q XXXXX
D
C
Q XXXXX
D
M41T94 E E
E
AI03686
1. CPOL (clock polarity) and CPHA (clock phase) are bits that may be set in the SPI control register of the MCU.
9/41
Description Table 2. Function table
E H SCL Input disabled SDI Input disabled
M41T94
Mode Disable reset
SDO High Z
WRITE
L
AI04630
Data bit latch
High Z
READ
L
AI04631
X
Next data bit shift (1)
1. SDO remains at High Z until eight bits of data are ready to be shifted out during a READ.
Figure 6.
CPOL
Data and clock timing
CPHA
0
0
C
1
1
C
SDI
MSB
LSB
SDO
MSB
LSB
AI04632
10/41
M41T94
Signal description
2
2.1
Signal description
Serial data output (SDO)
The output pin is used to transfer data serially out of the Memory. Data is shifted out on the falling edge of the serial clock.
2.2
Serial data input (SDI)
The input pin is used to transfer data serially into the device. Instructions, addresses, and the data to be written, are each received this way. Input is latched on the rising edge of the serial clock.
2.3
Serial clock (SCL)
The serial clock provides the timing for the serial interface (as shown in Figure 7 on page 13 and Figure 8 on page 14). The W/R bit, addresses, or data are latched, from the input pin, on the rising edge of the clock input. The output data on the SDO pin changes state after the falling edge of the clock input. The M41T94 can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:
(CPOL, CPHA) = ('0', '0') or (CPOL, CPHA) = ('1', '1').
For these two modes, input data (SDI) is latched in by the low-to-high transition of clock SCL, and output data (SDO) is shifted out on the high-to-low transition of SCL (see Table 2 on page 10 and Figure 6 on page 10).
2.4
Chip enable (E)
When E is high, the memory device is deselected, and the SDO output pin is held in its high impedance state. After power-on, a high-to-low transition on E is required prior to the start of any operation.
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Operation
M41T94
3
Operation
The M41T94 clock operates as a slave device on the SPI serial bus. Each memory device is accessed by a simple serial interface that is SPI bus compatible. The bus signals are SCL, SDI and SDO (see Table 1 on page 8 and Figure 5 on page 9). The device is selected when the Chip Enable input (E) is held low. All instructions, addresses and data are shifted serially in and out of the chip. The most significant bit is presented first, with the data input (SDI) sampled on the first rising edge of the clock (SCL) after the Chip Enable (E) goes low. The 64 bytes contained in the device can then be accessed sequentially in the following order:
1st byte: tenths/hundredths of a second register 2nd byte: seconds register 3rd byte: minutes register 4th byte: century/hours register 5th byte: day register 6th byte: date register 7th byte: month register 8th byte: year register 9th byte: control register 10th byte: watchdog register 11th - 16th bytes: Alarm registers 17th - 19th bytes: reserved 20th byte: square wave register 21st - 64th bytes: user RAM
The M41T94 clock continually monitors VCC for an out-of tolerance condition. Should VCC fall below VPFD, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from a an out-of-tolerance system. When VCC falls below VSO, the device automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min) plus tREC (min). For more information on Battery Storage Life refer to Application Note AN1012.
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M41T94
Operation
3.1
SPI bus characteristics
The Serial Peripheral interface (SPI) bus is intended for synchronous communication between different ICs. It consists of four signal lines: Serial data input (SDI), Serial data output (SDO), Serial clock (SCL) and a Chip Enable (E). By definition a device that gives out a message is called "transmitter," the receiving device that gets the message is called "receiver." The device that controls the message is called "master." The devices that are controlled by the master are called "slaves." The E input is used to initiate and terminate a data transfer. The SCL input is used to synchronize data transfer between the master (micro) and the slave (M41T94) devices. The SCL input, which is generated by the microcontroller, is active only during address and data transfer to any device on the SPI bus (see Figure 5 on page 9). The M41T94 can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:
(CPOL, CPHA) = ('0', '0') or (CPOL, CPHA) = ('1', '1').
For these two modes, input data (SDI) is latched in by the low-to-high transition of clock SCL, and output data (SDO) is shifted out on the high-to-low transition of SCL (see Table 2 on page 10 and Figure 6 on page 10). There is one clock for each bit transferred. Address and data bits are transferred in groups of eight bits. Due to memory size the second most significant address bit is a Don't Care (address bit 6). Figure 7. Input timing requirements
tEHEL E tELCH SCL tDVCH tCHDX SDI MSB IN tDLDH tDHDL tCLCH LSB IN tCHCL tCHEH tEHCH
SDO
HIGH IMPEDANCE
AI04633
13/41
Operation Figure 8.
E tCH SCL tCLQV tCLQX SDO
MSB OUT
M41T94 Output timing requirements
tCL
tEHQZ
LSB OUT tQLQH tQHQL
SDI
ADDR. LSB IN AI04634
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M41T94 Table 3.
Symbol fSCL tCH
(2) (3)
Operation AC characteristics
Parameter(1) Serial clock input frequency Clock high Clock transition (fall time) Serial clock input high to input data transition Serial clock input high to chip enable high Clock low Clock transition (rise time) Serial clock input low to output valid Serial clock input low to output data transition Input data transition (fall time) Input data transition (rise time) Input data to serial clock input high Chip enable high to serial clock input high Chip enable high to chip enable low Chip enable high to output high-z Chip enable low to serial clock input high Output data transition (fall time) Output data transition (rise time) 200 100 100 40 200 200 250 0 1 1 50 200 200 1 150 Min DC 200 1 Max 2 Unit MHz ns s ns ns ns s ns ns s s ns ns ns ns ns ns ns
tCHCL
tCHDX tCHEH tCL
(2) (3)
tCLCH
tCLQV tCLQX tDHDL tDLDH
(3) (3)
tDVCH tEHCH tEHEL tEHQZ
(3)
tELCH tQHQL(3) tQLQH(3)
1. Valid for ambient operating temperature: TA = 40 to 85C; VCC = 2.7 to 5.5V (except where noted). 2. tCH + tCL 1/fSCL 3. Value guaranteed by design, not 100% tested in production.
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Operation
M41T94
3.2
Read and write cycles
Address and data are shifted MSB first into the Serial Data Input (SDI) and out of the Serial Data Output (SDO). Any data transfer considers the first bit to define whether a READ or WRITE will occur. This is followed by seven bits defining the address to be read or written. Data is transferred out of the SDO for a READ operation and into the SDI for a WRITE operation. The address is always the second through the eighth bit written after the Enable (E) pin goes low. If the first bit is a '1,' one or more WRITE cycles will occur. If the first bit is a '0,' one or more READ cycles will occur (see Figure Figure 9 on page 17 and Figure 10 on page 17). Data transfers can occur one byte at a time or in multiple byte burst mode, during which the address pointer will be automatically incremented. For a single byte transfer, one byte is read or written and then E is driven high. For a multiple byte transfer all that is required is that E continue to remain low. Under this condition, the address pointer will continue to increment as stated previously. Incrementing will continue until the device is deselected by taking E high. The address will wrap to 00h after incrementing to 3Fh. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). Although the clock continues to maintain the correct time, this will prevent updates of time and date during either a READ or WRITE of these address locations by the user. The update will resume either due to a deselect condition or when the pointer increments to an non-clock or RAM address (08h to 3Fh).
Note:
This is true both in READ and WRITE mode.
3.3
Data retention mode
With valid VCC applied, the M41T94 can be accessed as described above with READ or WRITE cycles. Should the supply voltage decay, the M41T94 will automatically deselect, write protecting itself when VCC falls between VPFD (max) and VPFD (min) (see Figure 17 on page 32). At this time, the reset pin (RST) is driven active and will remain active until VCC returns to nominal levels. When VCC falls below the switch-over voltage (VSO), power input is switched from the VCC pin to the SNAPHAT battery (or external battery for SO16) at this time, and the clock registers are maintained from the attached battery supply. All outputs become high impedance. On power up, when VCC returns to a nominal value, write protection continues for tREC by internally inhibiting E. The RST signal also remains active during this time (see Figure 17 on page 32). Before the next active cycle, Chip Enable should be taken high for at least tEHEL, then low. For a further more detailed review of battery lifetime calculations, please see Application Note AN1012.
16/41
M41T94 Figure 9.
E 0 SCL W/R BIT 7 BIT ADDRESS 1 2 3 4 5 6 7 8 9 12 13 14 15 16 17 22
Operation Read mode sequence
SDI
7 MSB
6
5
4
3
2
1
0 DATA OUT (BYTE 1) 7 MSB 6 5 4 3 2 1 0 7 MSB
AI04635
DATA OUT (BYTE 2) 6 5 4 3 2 1 0
SDO
HIGH IMPEDANCE
Figure 10. Write mode sequence
E 0 SCL 1 2 3 4 5 6 7 8 9 10 15
W/R BIT
7 BIT ADDR
DATA BYTE
SDI
7 MSB
6
5
4
3
2
1
0
7 MSB
6
5
4
3
2
1
0
7
SDO HIGH IMPEDANCE
AI04636
17/41
Clock operations
M41T94
4
Clock operations
The eight byte clock register (see Table 4 on page 19) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Tenths/Hundredths of Seconds, Seconds, Minutes, and Hours are contained within the first four registers. Bits D6 and D7 of clock register 03h (century/hours register) contain the CENTURY ENABLE bit (CEB) and the CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of register 04h contain the Day (day of week). Registers 05h, 06h, and 07h contain the Date (day of month), Month and Years. The ninth clock register is the Control register (this is described in the clock calibration section). Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts within one second. The eight clock registers may be read one byte at a time, or in a sequential block. The Control register (Address location 08h) may be accessed independently. Provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of data during the READ.
4.1
Power-down time-stamp
When a power failure occurs, the Halt Update bit (HT) will automatically be set to a '1.' This will prevent the clock from updating the clock registers, and will allow the user to read the exact time of the power-down event. Resetting the HT bit to a '0' will allow the clock to update the clock registers with the current time. For more information, see Application Note AN1572.
4.2
Clock registers
The M41T94 offers 20 internal registers which contain clock, Alarm, Watchdog, Flag, Square Wave and Control data (see Table 4 on page 19). These registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORTTM cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. The internal divider (or clock) chain will be reset upon the completion of a WRITE to any clock address. The system-to-user transfer of clock data will be halted whenever the clock addresses (00h to 07h) are being written. The update will resume either due to a deselect condition or when the pointer increments to a non-clock or RAM address. Clock and Alarm registers store data in BCD. Control, Watchdog and Square Wave registers store data in Binary format.
18/41
M41T94 Table 4.
Addr D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0 Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h OUT ST 0 CEB TR 0 0 CB 0 0 0 0 D6 D5 10 seconds 10 minutes 10 Hours 0 0 10 date 10M D4 D3 D2 D1 D0 0.1 seconds 0.01 seconds Seconds Minutes Hours (24 hour format) 0 Day of week Date: day of month Month Year Calibration BMB2 BMB1 BMB0 Al 10M RB1 RB0
Clock operations Clock register map(1)
Function/range BCD format Seconds Seconds Minutes 00-99 00-59 00-59
Century/hours 0-1/00-23 Day Date Month Year Control Watchdog Al month Al date Al hour Al min Al sec 01-12 01-31 00-23 00-59 00-59 01-7 01-31 01-12 00-99
10 Years FT S
WDS BMB4 BMB3 AFE SQWE ABE
Alarm month Alarm date Alarm hour Alarm minutes Alarm seconds 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RPT4 RPT5 RPT3 RPT2 RPT1 WDF 0 0 0 RS3 HT
AI 10 date AI 10 hour
Alarm 10 minutes Alarm 10 seconds AF 0 0 0 RS2 0 0 0 0 RS1 BL 0 0 0 RS0
Flags Reserved Reserved Reserved SQW
1. Keys: S = Sign bit FT = Frequency test bit ST = Stop bit 0 = Must be set to zero BL = Battery low flag (read only) BMB0-BMB4 = Watchdog multiplier bits CEB = Century enable bit CB = Century bit OUT = Output level AFE = Alarm flag enable flag RB0-RB1 = Watchdog resolution bits WDS = Watchdog steering bit ABE = Alarm in battery back-up mode enable bit RPT1-RPT5 = Alarm repeat mode bits WDF = Watchdog flag (read only) WDF = Watchdog flag (read only) AF = Alarm flag (read only) SQWE = Square wave enable RS0-RS3 = SQW frequency HT = Halt update bit TR = tREC bit
19/41
Clock operations
M41T94
4.3
Setting alarm clock registers
Address locations 0Ah-0Eh contain the Alarm settings. The Alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or second. It can also be programmed to go off while the M41T94 is in the battery back-up to serve as a system wake-up call. Bits RPT5-RPT1 put the Alarm in the Repeat mode of operation. Table 5 on page 20 shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect Alarm setting. When the clock information matches the Alarm clock settings based on the match criteria defined by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE (Alarm Flag Enable) is also set, the Alarm condition activates the IRQ/FT/OUT pin.
Note:
If the address pointer is allowed to increment to the Flag register address, an Alarm condition will not cause the Interrupt/Flag to occur until the address pointer is moved to a different address. It should also be noted that if the last address written is the "Alarm Seconds," the address pointer will increment to the Flag address, causing this situation to occur. To disable the Alarm, write '0' to the Alarm date register and to RPT15. The IRQ/FT/OUT output is cleared by a READ to the Flags register. This READ of the Flags register will also reset the Alarm Flag (D6; register 0Fh). See Figure 11 on page 21. The IRQ/FT/OUT pin can also be activated in the Battery Back-up mode. The IRQ/FT/OUT will go low if an Alarm occurs and both ABE (Alarm in Battery Back-up mode Enable) and AFE are set. The ABE and AFE bits are reset during power-up, therefore an Alarm generated during power-up will only set AF. The user can read the Flag register at system boot-up to determine if an Alarm was generated while the M41T94 was in the deselect mode during power-up. Figure 12 on page 21 illustrates the Back-up mode Alarm timing. Table 5.
RPT5 1 1 1 1 1 0
Alarm repeat mode
RPT4 1 1 1 1 0 0 RPT3 1 1 1 0 0 0 RPT2 1 1 0 0 0 0 RPT1 1 0 0 0 0 0 Alarm setting Once per second Once per minute Once per hour Once per day Once per month Once per year
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M41T94 Figure 11. Alarm interrupt reset waveforms
Clock operations
0Eh
0Fh
10h
ACTIVE FLAG
IRQ/FT/OUT
HIGH-Z
AI03664
Figure 12. Back-up mode alarm waveforms
VCC VPFD
VSO tREC ABE, AFE Bits in Interrupt Register
AF bit in Flags Register
IRQ/FT/OUT HIGH-Z HIGH-Z
AI03920
21/41
Clock operations
M41T94
4.4
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the Watchdog register, address 09h. bits BMB4-BMB0 store a binary multiplier and the two lower order bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (For example: writing 00001110 in the Watchdog register = 3*1 or 3 seconds).
Note:
Accuracy of timer is within the selected resolution. If the processor does not reset the timer within the specified period, the M41T94 sets the WDF (Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset. WDF is reset by reading the Flags register (0Fh). The most significant bit of the Watchdog register is the Watchdog Steering bit (WDS). When set to a '0,' the watchdog will activate the IRQ/FT/OUT pin when timed-out. When WDS is set to a '1,' the watchdog will output a negative pulse on the RST pin for tREC. The Watchdog register and the AFE, ABE, SQWE, and FT bits will reset to a '0' at the end of a Watchdog time-out when the WDS bit is set to a '1.' The watchdog timer can be reset by two methods: 1. 2. a transition (high-to-low or low-to-high) can be applied to the Watchdog Input pin (WDI), or the microprocessor can perform a WRITE of the Watchdog register.
The time-out period then starts over. The WDI pin should be tied to VSS if not used. In order to perform a software reset of the watchdog timer, the original time-out period can be written into the Watchdog register, effectively restarting the count-down cycle. Should the watchdog timer time-out, and the WDS bit is programmed to output an interrupt, a value of 00h needs to be written to the Watchdog register in order to clear the IRQ/FT/OUT pin. This will also disable the watchdog function until it is again programmed correctly. A READ of the Flags register will reset the Watchdog Flag (bit D7; register 0Fh). The watchdog function is automatically disabled upon power-up and the Watchdog register is cleared. If the watchdog function is set to output to the IRQ/FT/OUT pin and the Frequency Test (FT) function is activated, the watchdog function prevails and the Frequency Test function is denied.
4.5
Square wave output
The M41T94 offers the user a programmable Square Wave function which is output on the SQW pin. RS3-RS0 bits located in 13h establish the Square Wave output frequency. These frequencies are listed in Table Table 6 on page 23. Once the selection of the SQW frequency has been completed, the SQW pin can be turned on and off under software control with the Square Wave Enable bit (SQWE) located in register 0Ah.
22/41
M41T94 Table 6. Square wave output frequency
Square wave bits RS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Clock operations
Square wave Frequency None 32.768 8.192 4.096 2.048 1.024 512 256 128 64 32 16 8 4 2 1 Units kHz kHz kHz kHz kHz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz
4.6
Power-on reset
The M41T94 continuously monitors VCC. When VCC falls to the power fail detect trip point, the RST pulls low (open drain) and remains low on power-up for tREC after VCC passes VPFD (max). The RST pin is an open drain output and an appropriate pull-up resistor should be chosen to control rise time.
4.7
Reset inputs (RSTIN1 & RSTIN2)
The M41T94 provides two independent inputs which can generate an output reset. The duration and function of these resets is identical to a reset generated by a power cycle. Table 7 on page 24 and Figure 13 on page 24 illustrate the AC reset characteristics of this function. Pulses shorter than tRLRH1 and tRLRH2 will not generate a reset condition. RSTIN1 and RSTIN2 are each internally pulled up to VCC through a 100k resistor.
23/41
Clock operations Figure 13. RSTIN1 and RSTIN2 timing waveforms
RSTIN1 tRLRH1 RSTIN2 tRLRH2 RST
(1)
M41T94
tR1HRH
tR2HRH
AI03665
Table 7.
Symbol tRLRH1(2) tRLRH2(3) tR1HRH(4) tR2HRH(4)
Reset AC characteristics(1)
Parameter RSTIN1 low to RSTIN1 high RSTIN2 low to RSTIN2 high RSTIN1 high to RST high RSTIN2 high to RST high Min 200 100 40 40 200 200 Max Unit ns ms ms ms
1. Valid for ambient operating temperature: TA = 40 to 85C; VCC = 2.7 to 5.5V (except where noted). 2. Pulse width less than 50ns will result in no RESET (for noise immunity). 3. Pulse width less than 20ms will result in no RESET (for noise immunity). 4. Programmable (see Table on page 28).
4.8
Calibrating the clock
The M41T94 is driven by a quartz-controlled oscillator with a nominal frequency of 32,768Hz. Uncalibrated clock accuracy will not exceed 35 ppm (parts per million) oscillator frequency error at 25C, which equates to about 1.53 minutes per month. When the Calibration circuit is properly employed, accuracy improves to better than 2 ppm at 25C. The oscillation rate of crystals changes with temperature (see Figure 14 on page 26). Therefore, the M41T94 design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 15 on page 26. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five Calibration bits found in the Control register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration bits occupy the five lower order bits (D4-D0) in the Control register (8h). These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or 2.034 ppm of
24/41
M41T94
Clock operations adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768Hz, each of the 31 increments in the Calibration byte would represent +10.7 or 5.35 seconds per month which corresponds to a total range of +5.5 or 2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M41T94 may require. The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in Application Note AN934: TIMEKEEPER CALIBRATION. This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the Calibration Byte. The second approach is better suited to a manufacturing environment, and involves the use of the IRQ/FT/OUT pin. The pin will toggle at 512Hz, when the Stop bit (ST, D7 of 1h) is '0,' the Frequency Test bit (FT, D6 of 8h) is '1,' the Alarm Flag Enable bit (AFE, D7 of Ah) is '0,' and the Watchdog Steering bit (WDS, D7 of 9h) is '1' or the Watchdog register (9h = 0) is reset. Any deviation from 512Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124Hz would indicate a +20 ppm oscillator frequency error, requiring a 10 (XX001010) to be loaded into the Calibration Byte for correction.
Note:
Setting or changing the calibration byte does not affect the frequency test output frequency. The IRQ/FT/OUT pin is an open drain output which requires a pull-up resistor for proper operation. A 500 to 10k resistor is recommended in order to control the rise time. The FT bit is cleared on power-down.
25/41
Clock operations Figure 14. Crystal accuracy across temperature
Frequency (ppm) 20 0 20 40 60 80 100 120 140 160 40 30 20 10 0 10 20 30 40 50 60 70 80 F = K x (T T )2 O F K = 0.036 ppm/C2 0.006 ppm/C2 TO = 25C 5C
M41T94
Temperature C
AI00999b
Figure 15. Calibration waveform
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
4.9
Century bit
Bits D7 and D6 of clock register 03h contain the CENTURY ENABLE bit (CEB) and the CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle.
26/41
M41T94
Clock operations
4.10
Output driver pin
When the FT bit, AFE bit and Watchdog register are not set, the IRQ/FT/OUT pin becomes an output driver that reflects the contents of D7 of the Control register. In other words, when D7 (OUT bit) and D6 (FT bit) of address location 08h are a '0,' then the IRQ/FT/OUT pin will be driven low.
Note:
The IRQ/FT/OUT pin is an open drain which requires an external pull-up resistor.
4.11
Battery low warning
The M41T94 automatically performs battery voltage monitoring upon power-up and at factory-programmed time intervals of approximately 24 hours. The battery low (BL) bit, bit D4 of Flags register 0Fh, will be asserted if the battery voltage is found to be less than approximately 2.5V. The BL bit will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to maintain data integrity in the SRAM. Data should be considered suspect and verified as correct. A fresh battery should be installed. If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCC is supplied. In order to insure data integrity during subsequent periods of battery Back-up mode, the battery should be replaced. The SNAPHAT top may be replaced while VCC is applied to the device.
Note:
This will cause the clock to lose time during the interval the SNAPHAT battery/crystal top is disconnected. The M41T94 only monitors the battery when a nominal VCC is applied to the device. Thus applications which require extensive durations in the battery Back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique.
4.12
tREC bit
Bit D7 of clock register 04h contains the tREC bit (TR). tREC refers to the automatic continuation of the deselect time after VCC reaches VPFD. This allows for a voltage setting time before WRITEs may again be performed to the device after a power-down condition. The tREC bit will allow the user to set the length of this deselect time as defined by Table Table on page 28.
27/41
Clock operations
M41T94
4.13
Initial power-on defaults
Upon initial application of power to the device, the following register bits are set to a '0' state: Watchdog register, TR, FT, AFE, ABE, and SQWE. The following bits are set to a '1' state: ST, OUT, and HT (see Table 9: Default values). Table 8. tREC definitions
tREC time tREC bit (TR) 0 0 1
1. Default setting
STOP bit (ST) Min 0 1 X 96 40 50 Max 98 200
(1)
Units ms ms s
2000
Table 9.
Default values
TR ST HT Out FT AFE ABE SQWE WATCHDOG register(1) 0
Condition Initial power-up (battery attach for SNAPHAT)(2) Subsequent power-up (with battery back-up)(3)
1. BMB0-BMB4, RB0, RB1.
0
1
1
1
0
0
0
0
UC
UC
1
UC
0
0
0
0
0
2. State of other control bits undefined. 3. UC = Unchanged
28/41
M41T94
Maximum rating
5
Maximum rating
Stressing the device above the rating listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 10.
Symbol TSTG VCC TSLD(1) VIO IO PD
Absolute maximum ratings
Parameter SNAPHAT Storage temperature (VCC off, oscillator off) Supply voltage Lead solder temperature for 10 seconds Input or output Voltage Output current Power dissipation SOIC Value 40 to 85 55 to 125 0.3 to 7 260 0.3 to VCC+0.3 20 1 Unit C C V C V mA W
1. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds).
Caution: Caution:
Negative undershoots below 0.3V are not allowed on any pin while in the Battery Back-up mode. Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
29/41
DC and AC parameters
M41T94
6
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the Measurement Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 11. DC and AC measurement conditions(1)
Parameter VCC supply voltage Ambient operating temperature Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages
1. Output Hi-Z is defined as the point where data is no longer driven.
M41T94 2.7 to 5.5V 40 to 85C 100pF 50ns 0.2 to 0.8VCC 0.3 to 0.7VCC
Figure 16. AC testing input/output waveforms
0.8VCC
0.7VCC 0.3VCC
AI02568
0.2VCC
Table 12.
Symbol CIN COUT(3) tLP
Capacitance
Parameter(1)(2) Input capacitance Output capacitance Low-pass filter input time constant (SDA and SCL) Min Max 7 10 50 Unit pF pF ns
1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs are deselected.
30/41
M41T94 Table 13.
Symb. IBAT ICC1 ICC2 ILI(2) ILO(3) VIH VIL VBAT VOH VOL
DC and AC parameters DC characteristics
Parameter Batter y current OSC on Batter y current OSC off Supply current Supply current (standby) Input leakage current Output leakage current Input high voltage Input low voltage Batter y voltage Output high Output low voltage(5) IOH = 1.0mA IOL = 3.0mA IOL = 10mA RST, IRQ/FT/OUT 4.20 2.55 4.40 2.60 2.5 Test condition(1) TA = 25C, VCC = 0V, VBAT = 3V f = 2 MHz SCL, SDI = VCC 0.3V 0V VIN VCC 0V VOUT VCC 0.7VCC 0.3 2.5 2.4 0.4 V 0.4 5.5 4.50 V 2.70 V V Min Typ 400 50 2 1.4 1 1 VCC + 0.3 0.3VCC 3.5
(4)
Max 500
Unit nA nA mA mA A A V V V V
voltage(5)
Output low voltage (open drain)(6) Pull-up supply voltage (open drain)
VPFD VSO
Power fail deselect (THS = VCC) Power fail deselect (THS = VSS) Batter y back-up switchover
1. Valid for ambient operating temperature: TA = 40 to 85C; VCC = 2.7 to 5.5V (except where noted). 2. RSTIN1 and RSTIN2 internally pulled-up to VCC through 100K resistor. WDI internally pulled-down to VSS through 100K resistor. 3. Outputs deselected. 4. For rechargeable back-up, VBAT (max) may be considered VCC. 5. For SQW pin (CMOS). 6. For IRQ/FT/OUT, RST pins (open drain): if pulled-up to supply other than VCC, this supply must be equal to, or less than 3.0V when VCC = 0V (during battery back-up mode).
Table 14.
Symbol f0 RS CL
Crystal electrical characteristics (externally supplied)
Parameter(1)(2) Resonant frequency Series resistance Load capacitance 12.5 Typ 32.768 50 Mi n Max Unit kHz k pF
1. Load capacitors are integrated within the M41T94. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account. These characteristics are externally supplied. 2. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. For contact information on this crystal type, see Section 9: References on page 39.
31/41
DC and AC parameters Figure 17. Power down/up mode AC waveforms
VCC VPFD (max) VPFD (min) VSO tF tFB tDR INPUTS
RECOGNIZED
M41T94
tR tRB tREC
RECOGNIZED
DON'T CARE
RST HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI03687
Table 15.
Symbol tF(2) tFB(3) tR tRB tREC
(4)
Power down/up AC characteristics
Parameter(1) VPFD (max) to VPFD (min) VCC fall time VPFD (min) to VSS VCC fall time VPFD (min) to VPFD (max) VCC rise time VSS to VPFD (min) VCC rise time Power up deselect time Expected data retention time Min 300 10 10 1 40 10(5) 200 Typ Max Unit s s s s ms YEARS
tDR
1. Valid for ambient operating temperature: TA = 40 to 85C; VCC = 2.7 to 5.5V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. 4. Programmable (see Table 8 on page 28). 5. At 25C, VCC = 0V (when using SOH28 + M4T28-BR12SH SNAPHAT top).
32/41
M41T94
Package mechanical data
7
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
33/41
Package mechanical data Figure 18. SO16 16-lead plastic small outline package outline
M41T94
A2 B e D
A C CP
N
E
1
H A1 L
SO-b
1. Drawing is not to scale.
Table 16.
Symbol
SO16 16-lead Plastic small outline package mechanical data
millimeters Typ Min Max 1.75 0.10 0.25 1.60 0 0.35 0.19 8 0.46 0.25 0.10 9.80 1.27 3.80 0.40 16 10.00 4.00 1.27 16 0.050 0.386 0.150 0.016 0 0.014 0.007 0.004 Typ inches Min Max 0.069 0.010 0.063 8 0.018 0.010 0.004 0.394 0.157 0.050
A A1 A2 B C CP D e E L N
34/41
M41T94
Package mechanical data Figure 19. SOH28 28-lead plastic small outline, battery SNAPHAT, package outline
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH-A
1. Drawing is not to scale.
Table 17.
SOH28 28-lead plastic small outline, battery SNAPHAT, package mechanical data
millimeters inches Max 3.05 0.36 2.69 0.51 0.32 18.49 8.89 3.61 12.70 1.27 8 Typ 0.050 Min 0.002 0.092 0.014 0.006 0.697 0.324 0.126 0.453 0.016 0 28 0.10 0.004 Max 0.120 0.014 0.106 0.020 0.012 0.728 0.350 0.142 0.500 0.050 8
Symbol Typ A A1 A2 B C D E e eB H L N CP 1.27 Min 0.05 2.34 0.36 0.15 17.71 8.23 3.20 11.51 0.41 0 28
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Package mechanical data
M41T94
Figure 20. SH 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
1. Drawing is not to scale.
Table 18.
SH 4-pin SNAPHAT housing for 48mAh battery & crystal, package mechanical data
millimeters inches Max 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 Typ Min 0.265 0.255 0.018 0.835 0.556 0.612 0.126 0.080 Max 0.385 0.285 0.275 0.015 0.022 0.8560 0.590 0.628 0.142 0.090
Symbol Typ A A1 A2 A3 B D E eA eB L Min 6.73 6.48 0.46 21.21 14.22 15.55 3.20 2.03
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M41T94
Package mechanical data Figure 21. SH 4-pin SNAPHAT housing for 120mAh battery & crystal, package outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
1. Drawing is not to scale.
Table 19.
SH 4-pin SNAPHAT housing for 120mAh battery & crystal, package mech. data
millimeters inches Max 10.54 8.51 8.00 0.38 0.56 21.84 18.03 15.95 3.61 2.29 Typ Min 0.315 0.285 0.018 0.835 0.680 0.612 0.126 0.080 Max 0.415 0.335 0.315 0.015 0.022 0.860 0.710 0.628 0.142 0.090
Symbol Typ A A1 A2 A3 B D E eA eB L Min 8.00 7.24 0.46 21.21 17.27 15.55 3.20 2.03
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Part numbering
M41T94
8
Part numbering
Table 20.
Example: Device type M41T Supply voltage and write protect voltage 94 = VCC = 2.7 to 5.5V THS = VCC; 4.20V VPFD 4.50V THS = VSS; 2.55V VPFD 2.70V Package MQ = SO16 MH(1)= SOH28 Temperature range 6 = 40 to 85C Shipping method E = Lead-free package (ECOPACK), tubes F = Lead-free package (ECOPACK), tape & reel
1. The 28-pin SOIC package (SOH28) requires the SNAPHAT battery/crystal package which is ordered separately under the part number "M4TXX-BR12SHX" in plastic tube or "M4TXX-BR12SHXTR" in tape & reel form (see Table Table 21 on page 38).
Ordering information scheme
M41T 94 MH 6 E
Caution:
Do not place the SNAPHAT battery package "M4TXX-BR12SH" in conductive foam as it will drain the lithium button-cell battery. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. Table 21. SNAPHAT battery table
Description Lithium battery (48mAh) and crystal SNAPHAT Lithium battery (120mAh) and crystal SNAPHAT Package SH SH
Part number M4T28-BR12SH1 M4T32-BR12SHx
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References
9
References
The crystal supplier KDS as cited in Table 14: Crystal electrical characteristics (externally supplied) on page 31 can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp.
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Revision history
M41T94
10
Revision history
Table 22.
Date April 2002 25-Apr-02
Document revision history
Revision 1.0 1.1 First edition Adjust graphic (Figure 4 on page 9); fix table text (Table 10 on page 29, Table 20 on page 38); adjust characteristics (Table 13 on page 31, Table 14 on page 31) Modify DC, Crystal Electrical Characteristics footnotes, Default Value table (Table 13 on page 31, Table 14 on page 31, Table 9 on page 28) Correct dimensions (Table 19 on page 37) Update test condition (Table 15 on page 32) New Si changes (Figure 4 on page 9; Table 15 on page 32, Table 7 on page 24, Table 8 on page 28, Table 9 on page 28) Reformatted; added Lead-free information; update characteristics (Figure 14 on page 26; Table 10 on page 29, Table 13 on page 31, Table 20 on page 38) Changed document to new template; amalgamated diagrams in Features on page 1; updated Package mechanical data in Section 7: Package mechanical data; small text changes for entire document, ECOPACK compliant Added lead-free second level interconnect information to cover page and Section 7: Package mechanical data; minor formatting changes throughout document; updated Table 10, footnote 1 in Table 14, Table 20, 21; addition of Section 9: References. Changes
03-Jul-02 06-Nov-02 26-Mar-03 28-Apr-03
1.2 1.3 1.4 2.0
15-Jun-04
3.0
29-Aug-2006
4
09-Nov-2007
5
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