ST72F521, ST72521B
80/64-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE
Memories 32K to 60K dual voltage High Density Flash (HDFlash) or ROM with read-out protection capability. In-Application Programming and In-Circuit Programming for HDFlash devices 1K to 2K RAM HDFlash endurance: 100 cycles, data retention: 20 years at 55C Clock, Reset And Supply Management Enhanced low voltage supervisor (LVD) for main supply and auxiliary voltage detector (AVD) with interrupt capability Clock sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock PLL for 2x frequency multiplication Four power saving modes: Halt, Active-Halt, Wait and Slow Interrupt Management Nested interrupt controller 14 interrupt vectors plus TRAP and RESET Top Level Interrupt (TLI) pin 15 external interrupt lines (on 4 vectors) Up to 64 I/O Ports 48 multifunctional bidirectional I/O lines 34 alternate function lines 16 high sink outputs 5 Timers Main Clock Controller with: Real time base, Beep and Clock-out capabilities Configurable watchdog timer Two 16-bit timers with: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes 8-bit PWM Auto-Reload timer with: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
Features ST72F521(M/R/AR)9
Flash 60K 2048 (256)
TQFP64 14 x 14 TQFP80 14 x 14
TQFP64 10 x 10
4 Communications Interfaces SPI synchronous serial interface SCI asynchronous serial interface I2C multimaster interface (SMbus V1.1 compliant) CAN interface (2.0B Passive) Analog periperal (low current coupling) 10-bit ADC with 16 input robust input ports Instruction Set 8-bit Data Manipulation 63 Basic Instructions 17 main Addressing Modes 8 x 8 Unsigned Multiply Instruction Development Tools Full hardware/software development package In-Circuit Testing capability
Device Summary
ST72F521(R/AR)6
Flash 32K 1024 (256)
ST72521B(M/R/AR)9
ROM 60K 2048 (256)
ST72521B(R/AR)6
ROM 32K 1024 (256)
Program memory - bytes RAM (stack) - bytes Operating Voltage Temp. Range Package
TQFP80 14x14 (M), TQFP64 14x14 (R), TQFP64 10x10 (AR)
3.8V to 5.5V up to -40C to +125 C TQFP80 14x14 (M), TQFP64 14x14 (R), TQFP64 TQFP64 14x14 (R), 10x10 (AR) TQFP64 10x10 (AR)
TQFP64 14x14 (R), TQFP64 10x10 (AR)
Rev. 5
May 2005 1/215
1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3.1 Read-out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.7.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3 External Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.4 Internal Low Voltage Detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.5 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.1 Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.2 Auxiliary Voltage Detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.3 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 26 27 27 27 28 28 29 31 32 33 33
7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.6.1 I/O Port Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . . . 40 8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 . 42 ... 8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.4.1 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 45 47 47 47 47 47 50
9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.5.1 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.4 How to Program the Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.6 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.7 Using Halt Mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . . . . . . . . 10.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . . 10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 53 53 54 56 56 56 56 56 58 58 58 58 58 59 59 59 61 61 62 66 70 70 70 70 82 82 82 83 89
10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
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10.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.5.4 Clock Phase and Clock Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 10.5.5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 10.5.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 10.5.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 10.5.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 10.6 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.8 CONTROLLER AREA NETWORK (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.8.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.8.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.8.5 List of CAN Cell Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.9 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.9.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.9.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.9.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.9.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 100 100 102 109 109 110 116 116 116 116 118 122 122 123 129 129 130 130 136 146 155 155 155 156 156 156 157 159 159 160 160 160 160 160 161 161 162
12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 165 ... 12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
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12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.2 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . 12.3.3 Auxiliary Voltage Detector (AVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.4 External Voltage Detector (EVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4.1 CURRENT CONSUMPTION . . .. . .. . .. . .. . .. . .. . ... 12.4.2 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4.3 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.4 RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.5 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 165 165 165 165 166 166 166 167 167 167 168 168 168 169 169 171 172 173 173 173 174 176 177 178
12.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 12.6.2 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 12.7.1 Functional EMS (Electro Magnetic Susceptibility) . . . . . . . . . . . . . . . . . . . . . . . . 12.7.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7.3 Absolute Maximum Ratings (Electrical Sensitivity) . . . . . . . . . . . . . . . . . . . . . . . 12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 180 181 182
12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 12.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 12.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 12.9.2 ICCSEL/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 12.10TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 12.10.1 8-Bit PWM-ART Auto-Reload Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 12.10.2 16-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 12.11COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 189 12.11.1 SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.11.2 I2C - Inter IC Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.11.3 CAN - Controller Area Network Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1210-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 191 192 193
12.12.1 Analog Power Supply and Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 12.12.2 General PCB Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
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12.12.3 ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 13.3 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 14 ST72521 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . 201 14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . 203 14.2.1 Version-Specific Sales Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 14.3.1 Socket and Emulator Adapter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 15 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 15.1 ALL FLASH AND ROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 15.1.1 External RC option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.2 Safe Connection of OSC1/OSC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.3 Reset pin protection with LVD Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.4 Unexpected Reset Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.5 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . . . . . . . 15.1.6 SCI Wrong Break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.7 16-bit Timer PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.8 CAN Cell Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.9 I2C Multimaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2 ALL FLASH DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.1 Internal RC Oscillator with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.2 I/O behaviour during ICC mode entry sequence . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.3 Read-out protection with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 211 211 211 211 212 212 212 212 213 213 213 213 214
215
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1 INTRODUCTION
The ST72F521 and ST72521B devices are members of the ST7 microcontroller family designed for mid-range applications with a CAN bus interface (Controller Area Network). All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set and are available with FLASH or ROM program memory. Under software control, all devices can be placed in WAIT, SLOW, ACTIVE-HALT or HALT mode,
reducing power consumption when the application is in idle or stand-by state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. Related Documentation AN1131: Migrating applications from ST72511/ 311/314 to ST72521/321/324
Figure 1. Device Block Diagram
8-BIT CORE ALU RESET VPP TLI VSS VDD EVD OSC1 OSC2 CONTROL RAM (1024-2048 Bytes) LVD AVD WATCHDOG OSC I2C PORT A PORT B PB7:0 (8-bits) PWM ART PORT C TIMER B CAN SPI SCI PORT D PD7:0 (8-bits) 10-BIT ADC VAREF VSSA
1On
PROGRAM MEMORY (32K - 60K Bytes)
ADDRESS AND DATA BUS
MCC/RTC/BEEP
PA7:0 (8-bits)
PORT F PF7:0 (8-bits) TIMER A BEEP PORT E PE7:0 (8-bits)
PC7:0 (8-bits)
PORT G1 PORT H1
PG7:0 (8-bits) PH7:0 (8-bits)
some devices only, see Device Summary on page 1
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2 PIN DESCRIPTION
Figure 2. 80-Pin TQFP 14x14 Package Pinout
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 (HS) PE4 (HS) PE5 (HS) PE6 (HS) PE7 PWM3 / PB0 PWM2 / PB1 PWM1 / PB2 PWM0 / PB3 PG0 PG1 PG2 PG3 ARTCLK / (HS) PB4 ARTIC1 / PB5 ARTIC2 / PB6 PB7 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
TLI EVD RESET VPP / ICCSEL PA7 (HS) / SCLI PA6 (HS) / SDAI PA5 (HS) PA4 (HS)
PE3 / CANRX PE2 / CANTX PE1 / RDI PE0 / TDO VDD_2
OSC2 VSS_2
OSC1
PH7 PH6 PH5 PH4
ei0 ei2
VSS_1 VDD_1 PA3 (HS) PA2 PA1 PA0 PC7 / SS / AIN15 PC6 / SCK /ICCCLK PH3 PH2 PH1 PH0 PC5 / MOSI / AIN14 PC4 / MISO / ICCDATA PC3 (HS) /ICAP1_B PC2(HS) / ICAP2_B PC1 / OCMP1_B / AIN13 PC0 / OCMP2_B /AIN12 VSS_0 VDD_0
ei3
ei1 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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MCO /AIN8 / PF0 BEEP / (HS) PF1 (HS) PF2 OCMP2_A / AIN9 /PF3 OCMP1_A/AIN10 /PF4 ICAP2_A/ AIN11 /PF5 ICAP1_A / (HS) / PF6 EXTCLK_A / (HS) PF7 (HS) 20mA high sink capability eix associated external interrupt vector
PG6 PG7 AIN4/PD4 AIN5 / PD5 AIN6 / PD6 AIN7 / PD7 VAREF VSSA VDD3 VSS3 PG4 PG5
ST72F521, ST72521B
PIN DESCRIPTION (Cont'd) Figure 3. 64-Pin TQFP 14x14 and 10x10 Package Pinout
(HS) PE4 (HS) PE5 (HS) PE6 (HS) PE7 PWM3 / PB0 PWM2 / PB1 PWM1 / PB2 PWM0 / PB3 ARTCLK / (HS) PB4 ARTIC1 / PB5 ARTIC2 / PB6 PB7 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3
64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
PE3 / CANRX PE2 / CANTX PE1 / RDI PE0 / TDO VDD_2 OSC1 OSC2 VSS_2 TLI EVD RESET VPP / ICCSEL PA7 (HS) / SCLI PA6 (HS) / SDAI PA5 (HS) PA4 (HS) 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 ei0 44 43 ei2 42 41 40 39 ei3 38 37 36 35 ei1 34 33 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VSS_1 VDD_1 PA3 (HS) PA2 PA1 PA0 PC7 / SS / AIN15 PC6 / SCK / ICCCLK PC5 / MOSI / AIN14 PC4 / MISO / ICCDATA PC3 (HS) / ICAP1_B PC2 (HS) / ICAP2_B PC1 / OCMP1_B / AIN13 PC0 / OCMP2_B / AIN12 VSS_0 VDD_0
AIN4 / PD4 AIN5 / PD5 AIN6 / PD6 AIN7 / PD7 VAREF VSSA VDD_3 VSS_3 MCO / AIN8 / PF0 BEEP / (HS) PF1 (HS) PF2 OCMP2_A / AIN9 / PF3 OCMP1_A / AIN10 / PF4 ICAP2_A / AIN11 / PF5 ICAP1_A / (HS) PF6 EXTCLK_A / (HS) PF7 (HS) 20mA high sink capability eix associated external interrupt vector
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PIN DESCRIPTION (Cont'd) For external pin connection guidelines, refer to See "ELECTRICAL CHARACTERISTICS" on page 165. Legend / Abbreviations for Table 1: Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C = CMOS 0.3VDD/0.7VDD CT= CMOS 0.3VDD/0.7VDD with input trigger TT= TTL 0.8V / 2V with Schmitt trigger Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration: Input: float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog Output: OD = open drain 2), PP = push-pull Refer to "I/O PORTS" on page 47 for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state. Table 1. Device Pin Description
Pin n TQFP80 TQFP64 Type Pin Name Level Output Input Input float wpu ana int Port Main function Output (after reset) OD X X X X
ei2 ei2 ei2
Alternate function
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
1 2 3 4 5 6 7 8 9
PE4 (HS) PE5 (HS) PE6 (HS) PE7 (HS) PB0/PWM3 PB1/PWM2 PB2/PWM1 PB3/PWM0 P G0 P G1 P G2 P G3 PB4 (HS)/ARTCLK
I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT I/O TT I/O TT I/O TT I/O TT I/O CT I / O CT I / O CT I/O CT I/O CT I/O CT I/O CT I/O CT I/O TT I/O TT I / O CT
HS HS HS HS
X X X X X X X X X X X X
X X X X
PP X X X X X X X X X X X X X X X X X X X X X X X
Port E4 Port E5 Port E6 Port E7 Port B0 Port B1 Port B2 Port B3 Port G0 Port G1 Port G2 Port G3 Port B4 Port B5 Port B6 Port B7 Port D0 Port D1 Port D2 Port D3 Port G6 Port G7 Port D4 ADC Analog Input 4 ADC Analog Input 0 ADC Analog Input 1 ADC Analog Input 2 ADC Analog Input 3 PWM-ART External Clock PWM-ART Input Capture 1 PWM-ART Input Capture 2 PWM Output 3 PWM Output 2 PWM Output 1 PWM Output 0
X X X X X X X X X X X X X X X X X X X X X X X X
ei2 X X X X ei3 ei3 ei3 ei3 X X X X X X X
HS
X X X X X X X X X X X
10 P B5/ARTIC1 11 P B6/ARTIC2 1 2 P B7 13 PD0 /AIN0 14 P D1/AIN1 15 P D2/AIN2 16 P D3/AIN3 P G6 P G7
17 P D4/AIN4
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Pin n TQFP80 TQFP64 Type Pin Name
Level Output Input Input fl oat wpu
Port
ana
OD
24 25 26 27 28 29 30 31 32 33 34 35 36
18 P D5/AIN5 19 P D6/AIN6 20 P D7/AIN7 21 VAREF 22 VSSA 23 VDD_3 24 VSS_3 - P G4 P G5
I / O CT I/O CT I/O CT I S S S I/O TT I/O TT I / O CT I/O C T I/O C T I/O CT HS HS
X X X
X X X
X X X
X X X
PP
int
Main function Output (after reset) X X X Port D5 Port D6 Port D7
Alternate function
ADC Analog Input 5 ADC Analog Input 6 ADC Analog Input 7
Analog Reference Voltage for ADC Analog Ground Voltage Digital Main Supply Voltage Digital Ground Voltage X X X X X X X X X ei1 ei1 ei1 X X X X X X X X X X X X X X Port G4 Port G5 Port F0 Port F1 Port F2 Port F3 Timer A OutADC Analog put Compare Input 9 2 Timer A OutADC Analog put Compare Input 10 1 Timer A Input ADC Analog Capture 2 Input 11 Timer A Input Capture 1 Timer A External Clock Source Main clock out (fCPU) ADC Analog Input 8
25 PF0/MCO/AIN8 26 PF1 (HS)/BEEP 27 PF2 (HS) 28 PF3/OCMP2_A/AIN9
Beep signal output
37 38 39 40 41 42 43
29 PF4/OCMP1_A/AIN10 30 PF5/ICAP2_A/AIN11 31 PF6 (HS)/ICAP1_A 32 PF7 (HS)/EXTCLK_A 33 VDD_0 34 VSS_0 35 P C0/OC MP2_B/AIN12
I/O CT I/O C T I/O CT I/O CT S S I/O CT HS HS
X X X X
X X X X
X X
X X X X
X X X X
Port F4 Port F5 Port F6 Port F7
Digital Main Supply Voltage Digital Ground Voltage X X X X X Port C0 Timer B OutADC Analog put Compare Input 12 2 Timer B OutADC Analog put Compare Input 13 1 Timer B Input Capture 2 Timer B Input Capture 1 SPI Master In ICC Data In/ Slave Out put Data SPI Master ADC Analog Out / Slave In Input 14 Data
44 45 46 47
36 P C1/OC MP1_B/AIN13 37 PC2 (HS)/ICAP2_B 38 PC3 (HS)/ICAP1_B 39 P C4/MISO/ICC DATA
I/O CT I / O CT I / O CT I/O CT HS HS
X X X X
X X X X
X
X X X X
X X X X
Port C1 Port C2 Port C3 Port C4
48 49 50 51
40 P C 5/MO SI/AIN 14 P H0 P H1 P H2
I / O CT I/O TT I/O TT I/O TT
X X X X
X X X X
X
X X X X
X X X X
Port C5 Port H0 Port H1 Port H2
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Pin n TQFP80 TQFP64 Type Pin Name
Level Output Input Input fl oat wpu
Port
ana
OD
52
-
P H3
I/O TT
X
X
X
PP
int
Main function Output (after reset) X Port H3
Alternate function
SPI Serial Clock 53 41 PC6/SCK/ICCCLK I/O CT X X X X Port C6
ICC Clock Output
Caution: Negative current injection not allowed on this pin5) SPI Slave ADC Analog Select (active Input 15 low)
54 55 56 57 58 59 60 61 62 63 64
42 PC7/SS/AIN15 4 3 P A0 4 4 P A1 4 5 P A2 46 PA3 (HS) 47 VDD_1 48 VSS_1 49 PA4 (HS) 50 PA5 (HS) 51 PA6 (HS)/SDAI 52 PA7 (HS)/SCLI
I/O CT I/O CT I/O CT I/O CT I/O CT S S I/O CT I/O CT I/O CT I/O CT HS HS HS HS HS
X X X X X
X ei0 ei0 ei0 ei0
X
X X X X X
X X X X X
Port C7 Port A0 Port A1 Port A2 Port A3
Digital Main Supply Voltage Digital Ground Voltage X X X X X X X X T T X X Port A4 Port A5 Port A6 Port A7 I2C Data 1) I2C Clock 1)
65
53 VPP/ ICCSEL
I
Must be tied low. In flash programming mode, this pin acts as the programming voltage input VPP. See Section 12.9.2 for more details. High voltage must not be applied to ROM devices Top priority non maskable interrupt. External voltage detector X X X X X X X X X X X X X X X X X X Top level interrupt input pin Port H4 Port H5 Port H6 Port H7 Digital Ground Voltage Resonator oscillator inverter output External clock input or Resonator oscillator inverter input Digital Main Supply Voltage X X X X X X X X X X X X X Port E0 Port E1 Port E2 Port E3 SCI Transmit Data Out SCI Receive Data In CAN Transmit Data Output CAN Receive Data Input
66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
54 R ESET 5 5 E VD 56 TLI P H4 P H5 P H6 P H7
I/O CT I CT
I/O TT I/O TT I/O TT I/O TT S I/O I S I/O CT I / O CT I/O CT I/O CT
57 VSS_2 58 OSC23) 59 OSC13) 60 VDD_2 61 P E0/TDO 62 P E1/RDI 63 P E2/CAN T X 64 P E3/CAN RX
Notes: 1. In the interrupt input column, "eiX" defines the associated external interrupt vector. If the weak pull-up
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column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input. 2. In the open drain output column, "T" defines a true open drain I/O (P-Buffer and protection diode to VDD are not implemented). See See "I/O PORTS" on page 47. and Section 12.8 I/O PORT PIN CHARACTERISTICS for more details. 3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section 1 INTRODUCTION and Section 12.5 CLOCK AND TIMING CHARACTERISTICS for more details. 4. On the chip, each I/O port may have up to 8 pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption.
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3 REGISTER & MEMORY MAP
As shown in Figure 4, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, up to 2Kbytes of RAM and up to 60Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh. The highest address bytes contain the user reset and interrupt vectors. Figure 4. Memory Map
0000h 007Fh 0080h
IMPORTANT: Memory locations marked as "Reserved" must never be accessed. Accessing a reseved area can have unpredictable effects on the device. Related Documentation AN 985: Executing Code in ST7 RAM
HW Registers (see Table 2)
0080h
Short Addressing RAM (zero page)
00FFh 0100h
RA M (2048 or 1024 Bytes)
087Fh 0880h
256 By tes S tac k
01FFh 0200h or 047Fh or 067Fh or 087Fh 1000h
Reserved
0FFFh 1000h
16-bit Addressing RA M
8000h
60 KBytes
Program Memory (60K or 32K)
FFDFh FFE0h FFFFh
32 KBytes
Interrupt & Reset Vectors (see Table 7)
FFFFh
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Table 2. Hardware Register Map
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h SPIDR SPICR SPICSR Block Register Label PADR PADDR PAOR PBDR PBDDR PBOR PCDR PCDDR PCOR PDDR PDDDR PDOR PEDR PEDDR PEOR PFDR PFDDR PFOR PGDR PGDDR PGO R PHDR PHDDR PHOR I2CC R I2CS R1 I2CS R2 I2CC CR I2CO AR1 I2CO AR2 I2CD R Register Name Port A Data Register Port A Data Direction Register Port A Option Register Port B Data Register Port B Data Direction Register Port B Option Register Port C Data Register Port C Data Direction Register Port C Option Register Port D Data Register Port D Data Direction Register Port D Option Register Port E Data Register Port E Data Direction Register Port E Option Register Port F Data Register Port F Data Direction Register Port F Option Register Port G Data Register Port G Data Direction Register Port G Option Register Port H Data Register Port H Data Direction Register Port H Option Register I2C Control Register I2C Status Register 1 I2C Status Register 2 I2C Clock Control Register I2C Own Address Register 1 I2C Own Address Register2 I2C Data Register Reserved Area (2 Bytes) SPI Data I/O Register SPI Control Register SPI Control/Status Register xxh 0xh 00h R/W R/W R/W Reset Status 00h1 ) 00h 00h 00h1 ) 00h 00h 00h1 ) 00h 00h 00h1 ) 00h 00h 00h1 ) 00h 00h 00h1 ) 00h 00h 00h1 ) 00h 00h 00h1 ) 00h 00h 00h 00h 00h 00h 00h 00h 00h Remarks R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R / W2 ) R / W2 ) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Read Only Read Only R/W R/W R/W R/W
Port A
Port B
Port C
Port D
Port E
Port F
Port G
2)
Port H 2)
I2C
SPI
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Address 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh to 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh
Block
Register Label ISPR0 ISPR1 ISPR2 ISPR3 EIC R
Register Name Interrupt Software Priority Register 0 Interrupt Software Priority Register 1 Interrupt Software Priority Register 2 Interrupt Software Priority Register 3 External Interrupt Control Register Flash Control/Status Register Watchdog Control Register System Integrity Control/Status Register Main Clock Control / Status Register Main Clock Controller: Beep Control Register
Reset Status FFh FFh FFh FFh 00h 00h 7Fh
Remarks R/W R/W R/W R/W R/W R/W R/W
ITC
FLAS H W ATCHDOG
FCSR WD G C R SIC SR
000x 000x b R/W 00h 00h R/W R/W
MC C
MCCS R MCCB CR
Reserved Area (3 Bytes)
TIME R A
TACR2 TACR1 TACSR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR
Timer A Control Register 2 Timer A Control Register 1 Timer A Control/Status Register Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low Register Timer A Input Capture 2 High Register Timer A Input Capture 2 Low Register Timer A Output Compare 2 High Register Timer A Output Compare 2 Low Register Reserved Area (1 Byte)
00h 00h xxxx x0xx b xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h
R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W
TIME R B
TBCR2 TBCR1 TBCSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR
Timer B Control Register 2 Timer B Control Register 1 Timer B Control/Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register
00h 00h xxxx x0xx b xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h
R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W
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Address 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h to 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh
Block
Register Label SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR SCIETPR
Register Name SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 SCI Extended Receive Prescaler Register Reserved area SCI Extended Transmit Prescaler Register Reserved Area (2 Bytes)
Reset Status C0h xxh 00h x000 0000b 00h 00h --00h
Remarks Read Only R/W R/W R/W R/W R/W R/W
SCI
CA N
CANISR CANICR CANCSR CANBRP R CANBTR CANPSR
CAN Interrupt Status Register CAN Interrupt Control Register CAN Control / Status Register CAN Baud Rate Prescaler Register CAN Bit Timing Register CAN Page Selection Register First address to Last address of CAN page x Control/Status Register Data High Register Data Low Register PWM AR Timer Duty Cycle Register 3 PWM AR Timer Duty Cycle Register 2 PWM AR Timer Duty Cycle Register 1 PWM AR Timer Duty Cycle Register 0 PWM AR Timer Control Register Auto-Reload Timer Control/Status Register Auto-Reload Timer Counter Access Register Auto-Reload Timer Auto-Reload Register AR Timer Input Capture Control/Status Reg. AR Timer Input Capture Register 1 AR Timer Input Capture Register 1 Reserved Area (2 Bytes)
00h 00h 00h 00h 23h 00h --
R/W R/W R/W R/W R/W R/W See CAN Description
AD C
ADCCSR ADCDRH ADCDRL PWMDCR3 PWM DCR2 PWM DCR1 PWM DCR0 PWM C R ARTCSR ARTCAR ARTARR ARTICCSR ARTICR1 ARTICR2
00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
R/W Read Only Read Only R/W R/W R/W R/W R/W R/W R/W R/W R/W Read Only Read Only
PWM ART
Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value.
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4 FLASH PROGRAM MEMORY
4.1 Introduction The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external VPP supply. The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming). The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 Main Features
sectors (see Table 3). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required. The first two sectors have a fixed size of 4 Kbytes (see Figure 5). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000hFFFFh). Table 3. Sectors available in Flash devices
Flash Size (bytes) 4K 8K > 8K Available Sectors Sector 0 Sectors 0,1 Sectors 0,1, 2
Three Flash programming modes: Insertion in a programming tool. In this mode, all sectors including option bytes can be programmed or erased. ICP (In-Circuit Programming). In this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board. IAP (In-Application Programming) In this mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board and while the application is running. ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM Read-out protection Register Access Security System (RASS) to prevent accidental programming or erasing
4.3 Structure The Flash memory is organised in sectors and can be used for both code and data storage. Depending on the overall Flash memory size in the microcontroller device, there are up to three user Figure 5. Memory Map and Sector Address
4K
1000h 3FFFh 7FFFh 9FFFh BFFFh D7FFh DFFFh EFFFh FFFFh
4.3.1 Read-out Protection Read-out protection, when selected, provides a protection against Program Memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. In flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased and the device can be reprogrammed. Read-out protection selection depends on the device type: In Flash devices it is enabled and removed through the FMP_R bit in the option byte. In ROM devices it is enabled by mask option specified in the Option List. Note: In flash devices, the LVD is not supported if read-out protection is enabled.
8K
10K
16K
24K
32K
48K
60K
FLASH MEMORY SIZE
SECTOR 2 2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes 52 Kbytes 4 Kbytes 4 Kbytes SECTOR 1 SECTOR 0
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FLASH PROGRAM MEMORY (Cont'd) 4.4 ICC Interface ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see Figure 6). These pins are: RESET: device reset VSS: device power supply ground Figure 6. Typical ICC Interface
PROGRAMMING TOOL ICC CONNECTOR ICC Cable APPLICATION BOARD (See Note 3) OPTIONAL (See Note 4) ICC CONNECTOR HE10 CONNECTOR TYPE 9 10 7 8 5 6 3 4 1 2 APPLICATION RESET SOURCE See Note 2 10k APPLICATION POWER SUPPLY CL2 CL1 See Note 1 APPLICATION I/O
ICCCLK: ICC output serial clock pin ICCDATA: ICC input/output serial data pin ICCSEL/VPP: programming voltage OSC1(or OSCIN): main clock input for external source (optional) VDD: application board power supply (optional, see Figure 6, Note 3)
ST7
Notes: 1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values. 2. During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset man-
agement IC with open drain output and pull-up resistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session. 3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual. 4. Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case.
ICCSEL/VPP
ICCDATA
RESET
ICCCLK
OSC2
OSC1
VDD
VSS
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FLASH PROGRAM MEMORY (Cont'd) 4.5 ICP (In-Circuit Programming) To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool. Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 6). For more details on the pin locations, refer to the device pinout description. 4.6 IAP (In-Application Programming) This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool). This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). For example, it is possible to download code from the SPI, SCI, USB or CAN interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation. 4.7 Related Documentation For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual. 4.7.1 Register Description FLASH CONTROL/STATUS REGISTER (FCSR) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 0 0 0 0 0
This register is reserved for use by Programming Tool software. It controls the Flash programming and erasing operations.
Figure 7. Flash Control/Status Register Address and Reset Value
Address (Hex.) 0029h Register Label FC SR Reset Value 7 6 5 4 3 2 1 0
0
0
0
0
0
0
0
0
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5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES
5.3 CPU REGISTERS The 6 CPU registers shown in Figure 8 are not present in the memory mapping and are accessed by specific instructions. Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures. Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
Enable executing 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) Two 8-bit index registers 16-bit stack pointer Low power HALT and WAIT modes Priority maskable hardware interrupts Non-maskable software/hardware interrupts
Figure 8. CPU Registers
7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 0 CONDITION CODE REGISTER 1 1 I1 H I0 N Z C RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value 0 Y INDEX REGISTER 0 X INDEX REGISTER 0 ACCUMULATOR
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CENTRAL PROCESSING UNIT (Cont'd) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx
7
1 1 I1 H I0 N Z
Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test inst ructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions. Interrupt Management Bits Bit 5,3 = I1, I0 Interrupt The combination of the I1 and I0 bits gives the current interrupt software priority.
Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) I1 1 0 0 1 I0 0 1 0 1
0 C
The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Arithmetic Management Bits Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It's a copy of the result 7th bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions.
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See the interrupt management chapter for more details.
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CENTRAL PROCESSING UNIT (Cont'd) Stack Pointer (SP) Read/Write Reset Value: 01 FFh
15 0 7
SP7 SP6 SP5 SP4 SP3 SP2 SP1
8 0 0 0 0 0 0 1 0 SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 9). Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address. Figure 9. Stack Manipulation Example
CALL Subroutine @ 0100h Interrupt Event P USH Y
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 9. When an interrupt is received, the SP is decremented and the context is pushed on the stack. On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area.
PO P Y
IRET
RET or RSP
SP SP CC A X PC H SP PCH @ 01FFh PCL P CL PCH PCL Y CC A X PCH PCL PCH PC L SP CC A X PCH PCL PCH PCL SP PCH PCL SP
Stack Higher Address = 01FFh Stack Lower Address = 0100h
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6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 11. For more details, refer to dedicated parametric section. Main features Optional PLL for multiplying the frequency by 2 (not to be used with internal RC oscillator) Reset Sequence Manager (RSM) Multi-Oscillator Clock Management (MO) 5 Crystal/Ceramic resonator oscillators 1 Internal RC oscillator System Integrity Management (SI) Main supply Low voltage detection (LVD) Auxiliary Voltage detector (AVD) with interrupt capability for monitoring the main supply or the EVD pin
6.1 PHASE LOCKED LOOP If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to multiply the frequency by two to obtain an fOSC2 of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL is disabled, then fOSC2 = fOSC/2. Caution: The PLL is not recommended for applications where timing accuracy is required. See "PLL Characteristics" on page 177. Figure 10. PLL Block Diagram
PLL x 2
fOSC 0 fOSC2 1
/2
PLL OPTION BIT
Figure 11. Clock, Reset and Supply Block Diagram
OSC2 OSC1
MULTIOSCILLATOR (MO)
fOSC PLL (option)
fOSC2
MAIN CLOCK fCPU CONTROLLER WITH REALTIME CLOCK (MCC/RTC)
SYSTEM INTEGRITY MANAGEMENT RESET SEQUENCE RESET MANAGER (RSM) AVD Interrupt Request SICSR AVD AVD AVD LVD S IE F RF WDG RF WATCHDOG TIMER (WDG) 0 0 0
LOW VOLTAGE VSS VDD 0 EVD 1 DETECTOR (LVD)
AUXILIARY VOLTAGE DETECTOR (AVD)
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6.2 MULTI-OSCILLATOR (MO) The main clock of the ST7 can be generated by three different source types coming from the multioscillator block: an external source 4 crystal or ceramic resonator oscillators an internal high frequency RC oscillator Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in Table 4. Refer to the electrical characteristics section for more details. Caution: The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left unconnected, the ST7 main oscillator may start and, in this configuration, could generate an fOSC clock frequency in excess of the allowed maximum (>16MHz.), putting the ST7 in an unsafe/undefined state. The product behaviour must therefore be considered undefined when the OSC pins are left unconnected. External Clock Source In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground. Crystal/Ceramic Oscillators This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to section 14.1 on page 201 for more details on the frequency ranges). In this mode of the multi-oscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator. These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase. Internal RC Oscillator This oscillator allows a low cost solution for the main clock of the ST7 using only an internal resistor and capacitor. Internal RC oscillator mode has the drawback of a lower frequency accuracy and should not be used in applications that require accurate timing. In this mode, the two oscillator pins have to be tied to ground. Table 4. ST7 Clock Sources
Hardware Configuration
External Clock
ST7 OS C1 OSC 2
EX TERNAL SO URCE
Crystal/Ceramic Resonators
ST7 OSC 1 OSC2
CL1
LOA D CAPA CITO RS
CL 2
Internal R C Oscillator
ST7 OSC1 OSC2
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6.3 RESET SEQUENCE MANAGER (RSM) 6.3.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 13: External RESET source pulse Internal LVD RESET (Low Voltage Detection) Internal WATCHDOG RESET These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases as shown in Figure 12: Active Phase depending on the RESET source 256 or 4096 CPU clock cycle delay (selected by option byte) RESET vector fetch The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application (see section 14.1 on page 201). Figure 13. Reset Block Diagram The RESET vector fetch phase duration is 2 clock c ycles. Figure 12. RESET Sequence Phases
RESET
Active Phase INTERNAL RESET 256 or 4096 CLOCK CYCLES FETCH VECTOR
6.3.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See "CONTROL PIN CHARACTERISTICS" on page 185 for more details. A RESET signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized (see Figure 14). This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode.
VDD
RO N
RESET
Filter INTERNAL RESET
PULSE GENERATOR
WATCHDOG RESET LVD RESET
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RESET SEQUENCE MANAGER (Cont'd) The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. If the external RESET pulse is shorter than tw(RSTL)out (see short ext. Reset in Figure 14), the signal on the RESET pin may be stretched. Otherwise the delay will not be applied (see long ext. Reset in Figure 14). Starting from the external RESET pulse recognition, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out. 6.3.3 External Power-On RESET If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency. (see "OPERATING CONDITIONS" on page 167) A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin. 6.3.4 Internal Low Voltage Detector (LVD) R ESET Two different RESET sequences caused by the internal LVD circuitry can be distinguished: Power-On RESET Voltage Drop RESET The device RESET pin acts as an output that is pulled low when VDD
Figure 14. RESET Sequences VDD
VIT+(LVD) VIT-(LVD)
LVD RESET
SHORT EXT. RESET
LONG EXT. RESET
WATCHDOG RESET
RUN
ACTIVE PHASE
RUN
ACTIVE PHASE
RUN
ACTIVE PHASE
RUN
ACTIVE PHASE
RUN
tw(RSTL)out th(RSTL)in
EXTERNAL RESET SOURCE
tw(RSTL)out th(RSTL)in
DELAY
tw(RSTL)out
RESET PIN
WATCHDOG RESET WATCHDOG UNDERFLOW INTERNAL RESET (256 or 4096 TCPU) VECTOR FETCH
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6.4 SYSTEM INTEGRITY MANAGEMENT (SI) The System Integrity Management block contains the Low Voltage Detector (LVD) and Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register. 6.4.1 Low Voltage Detector (LVD) The Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT- reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD Reset circuitry generates a reset when VDD is below: VIT+ when VDD is rising VIT- when VDD is falling The LVD function is illustrated in Figure 15. The voltage threshold can be configured by option byte to be low, medium or high. Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-, the MCU can only be in two modes: Figure 15. Low Voltage Detector vs Reset
VDD
under full software control in static safe reset In these conditions, secure operation is always ensured for the application without the need for external reset hardware. During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Notes: The LVD allows the device to be used without any external RESET circuitry. If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range. Below 3.8V, device operation is not guaranteed. The LVD is an optional function which can be selected by option byte. It is recommended to make sure that the VDD supply voltage rises monotonously when the device is exiting from Reset, to ensure the application functions properly.
Vhys VIT+ VIT-
RESET
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SYSTEM INTEGRITY MANAGEMENT (Cont'd) 6.4.2 Auxiliary Voltage Detector (AVD) The Voltage Detector function (AVD) is based on an analog comparison between a VIT-(AVD) and VIT+(AVD) reference value and the VDD main supply or the external EVD pin voltage level (VEVD). The VIT- reference value for falling voltage is lower than the VIT+ reference value for rising voltage in order to avoid parasitic detection (hysteresis). The output of the AVD comparator is directly readable by the application software through a real time status bit (AVDF) in the SICSR register. This bit is read only. Caution: The AVD function is active only if the LVD is enabled through the option byte. 6.4.2.1 Monitoring the VDD Main Supply This mode is selected by clearing the AVDS bit in the SICSR register. The AVD voltage threshold value is relative to the selected LVD threshold configured by option byte (see section 14.1 on page 201). If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the VIT+(AVD) or VIT-(AVD) threshold (AVDF bit toggles). In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing software to shut down safely before the LVD resets the microcontroller. See Figure 16. The interrupt on the rising edge is used to inform the application that the VDD warning state is over. If the voltage rise time trv is less than 256 or 4096 CPU cycles (depending on the reset delay selected by option byte), no AVD interrupt will be generated when VIT+(AVD) is reached. If trv is greater than 256 or 4096 cycles then: If the AVD interrupt is enabled before the VIT+(AVD) threshold is reached, then 2 AVD interrupts will be received: the first when the AVDIE bit is set, and the second when the threshold is reached. If the AVD interrupt is enabled after the VIT+(AVD) threshold is reached then only one AVD interrupt will occur.
Figure 16. Using the AVD to Monitor VDD (AVDS bit=0) VDD Early Warning Interrupt (Power has dropped, MCU not not yet in reset)
Vh y s t
VIT+(AVD) VIT-(AVD) VIT+(LVD) VIT-(LVD)
trv VOLTAGE RISE TIME
AVDF bit AVD INTERRUPT REQUES T IF AVDIE bit = 1
0
1
RESET VALUE
1
0
INTERRUPT PROCESS
INTERRUPT PROCESS
LVD RESET
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SYSTEM INTEGRITY MANAGEMENT (Cont'd) 6.4.2.2 Monitoring a Voltage on the EVD pin This mode is selected by setting the AVDS bit in the SICSR register. The AVD circuitry can generate an interrupt when the AVDIE bit of the SICSR register is set. This interrupt is generated on the rising and falling edges of the comparator output. This means it is generated when either one of these two events occur: VEVD rises up to VIT+(EVD) VEVD falls down to VIT-(EVD) The EVD function is illustrated in Figure 17. For more details, refer to the Electrical Characteristics section.
Figure 17. Using the Voltage Detector to Monitor the EVD pin (AVDS bit=1) VEVD
VIT+(EVD) VIT-(EVD)
Vh y s t
AVDF AVD INTERRUPT REQUES T IF AVDIE = 1
0
1
0
INTERRUPT PROCESS
INTERRUPT PROCESS
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SYSTEM INTEGRITY MANAGEMENT (Cont'd) 6.4.3 Low Power Modes
Mode WAIT H ALT Description No effect on SI. AVD interrupts cause the device to exit from Wait mode. The CRSR register is frozen. Interrupt Event AVD event Enable Event Control Flag Bit AVDF A VDIE Exit from Wait Yes Exit from Halt No
set and the interrupt mask in the CC register is reset (RIM instruction).
6.4.3.1 Interrupts The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is
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SYSTEM INTEGRITY MANAGEMENT (Cont'd) 6.4.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read / Write ed by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See Reset Value: 000x 000x (00h) WDGRF flag description for more details. When the LVD is disabled by OPTION BYTE, the LVDRF 7 0 bit value is undefined.
A VD S AVD IE A VD F LVD RF 0 0 0 WDG RF
Bits 3:1 = Reserved, must be kept cleared. Bit 0 = WDGRF Watchdog reset flag This bit indicates that the last Reset was generated by the Watchdog peripheral. It is set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts). Combined with the LVDRF flag information, the flag description is given by the following table.
RESET Sources External RESET pin Watchdog LVD LV DRF 0 0 1 WDG RF 0 1 X
Bit 7 = AVDS Voltage Detection selection This bit is set and cleared by software. Voltage Detection is available only if the LVD is enabled by option byte. 0: Voltage detection on VDD supply 1: Voltage detection on EVD pin Bit 6 = AVDIE Voltage Detector interrupt enable This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag changes (toggles). The pending interrupt information is automatically cleared when software enters the AVD interrupt routine. 0: AVD interrupt disabled 1: AVD interrupt enabled Bit 5 = AVDF Voltage Detector flag This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt request is generated when the AVDF bit changes value. Refer to Figure 16 and to Section 6.4.2.1 for additional details . 0: VDD or VEVD over VIT+(AVD) threshold 1: VDD or VEVD under VIT-(AVD) threshold Bit 4 = LVDRF LVD reset flag This bit indicates that the last Reset was generat-
Application notes The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can be detected by software while an external reset can not. CAUTION: When the LVD is not activated with the associated option byte, the WDGRF flag can not be used in the application.
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7 INTERRUPTS
7.1 INTRODUCTION The ST7 enhanced interrupt management provides the following features: Hardware interrupts Software interrupt (TRAP) Nested or concurrent interrupt management with flexible interrupt priority and level management: Up to 4 software programmable nesting levels Up to 16 interrupt vectors fixed by hardware 2 non maskable events: RESET, TRAP 1 maskable Top Level event: TLI This interrupt management is based on: Bit 5 and bit 3 of the CPU CC register (I1:0), Interrupt software priority registers (ISPRx), Fixed interrupt vector addresses located at the high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order. This enhanced interrupt controller guarantees full upward compatibility with the standard (not nested) ST7 interrupt controller. 7.2 MASKING AND PROCESSING FLOW The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of Figure 18. Interrupt Processing Flowchart
RESET PENDING INTERRUPT N Y TRAP Interrupt has the same or a lower software priority than current one N I1:0 Interrupt has a higher software priority than current one Y
each interrupt vector (see Table 5). The processing flow is shown in Figure 18 When an interrupt request has to be serviced: Normal processing is suspended at the end of the current instruction execution. The PC, X, A and CC registers are saved onto the stack. I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx registers of the serviced interrupt vector. The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to "Interrupt Mapping" table for vector addresses). The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume. Table 5. Interrupt Software Priority Levels
Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) Level Low I1 1 0 0 1 I0 0 1 0 1
High
FETCH NEXT INSTRUCTION
THE INTERRUPT STAYS PENDING
Y
"IRET" N
RESTORE PC, X, A, CC FROM STACK
EXECUTE INSTRUCTION
STACK PC, X, A, CC LOAD I1:0 FROM INTERRUPT SW REG. LOAD PC FROM INTERRUPT VECTOR
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INTERRUPTS (Cont'd) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: the highest software priority interrupt is serviced, if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first. Figure 19 describes this decision process. Figure 19. Priority Decision Process
PENDING INTERRUPTS
TRAP (Non Maskable Software Interrupt) This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the flowchart in Figure 18. Caution: TRAP can be interrupted by a TLI. RESET The RESET source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See the RESET chapter for more details.
Same
SOFTWARE PRIORITY
Different
HIGHEST SOFTWARE PRIORITY SERVICED HIGHEST HARDWARE PRIORITY SERVICED
When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. Note 1: The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt. Note 2: TLI, RESET and TRAP can be considered as having the highest software priority in the decision process. Different Interrupt Vector Sources Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable type (RESET, TRAP) and the maskable type (external or from internal peripherals). Non-Maskable Sources These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see Figure 18). After stacking the PC, X, A and CC registers (except for RESET), the corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level 3). These sources allow the processor to exit HALT mode.
Maskable Sources Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending. TLI (Top Level Hardware Interrupt) This hardware interrupt occurs when a specific edge is detected on the dedicated TLI pin. It will be serviced according to the flowchart in Figure 18 as a trap. Caution: A TRAP instruction must not be used in a TLI service routine. External Interrupts External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitivity is software selectable through the External Interrupt Control register (EICR). External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ORed. Peripheral Interrupts Usually the peripheral interrupts cause the MCU to exit from HALT mode except those mentioned in the "Interrupt Mapping" table. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear sequence is executed.
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INTERRUPTS (Cont'd) 7.3 INTERRUPTS AND LOW POWER MODES All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT modes (see column "Exit from HALT" in "Interrupt Mapping" table). When several pending interrupts are present while exiting HALT mode, the first one serviced can only be an interrupt with exit from HALT mode capability and it is selected through the same decision process shown in Figure 19. Note: If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced. Figure 20. Concurrent Interrupt Management
TRAP SOFTW ARE PRIORITY LEVEL IT2 IT1 IT4 IT3 IT0 I1 I0
7.4 CONCURRENT & NESTED MANAGEMENT The following Figure 20 and Figure 21 show two different interrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in Figure 21. The interrupt hardware priority is given in this order from the lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0, TLI. The software priority is given for each interrupt. Warning: A stack overflow may occur without notifying the software of the failure.
HARDWARE PRIORITY
TRAP IT0 IT1 IT2 IT3 RIM IT4 MAIN MAIN IT1
3 3 3 3 3 3 3/0 10
11 11 11 11 11 11
11 / 10 Figure 21. Nested Interrupt Management
TRAP
SOFTW ARE PRIORITY LEVEL
IT0
IT2
IT1
IT4
IT3
I1
I0
HARDWARE PRIORITY
TRAP IT0 IT1 IT2 IT3 RIM IT4 MAIN IT4 MAIN IT1 IT2
3 3 2 1 3 3 3/0 10
11 11 00 01 11 11
11 / 10
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USED STACK = 10 BYTES
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INTERRUPTS (Cont'd) 7.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read / Write Reset Value: 111x 1010 (xAh)
7 1 1 I1 H I0 N Z 0 C ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I0_9 I1_4 I1_8 I0_4 I0_8
INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX) Read/Write (bit 7:4 of ISPR3 are read only) Reset Value: 1111 1111 (FFh)
7 ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 0 I0_0
Bit 5, 3 = I1, I0 Software Interrupt Priority These two bits indicate the current interrupt software priority.
Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable*) Level Low I1 1 0 0 1 I0 0 1 0 1
ISPR2 ISPR3
I1_11 I0_11 I1_10 I0_10 I1_9 1 1 1 1
I1_13 I0_13 I1_12 I0_12
High
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see "Interrupt Dedicated Instruction Set" table). *Note: TLI, TRAP and RESET events can interrupt a level 3 program.
These four registers contain the interrupt software priority of each interrupt vector. Each interrupt vector (except RESET and TRAP) has corresponding bits in these registers where its own software priority is stored. This correspondance is shown in the following table.
Vector address FFFBh-FFFAh FFF9h-FFF8h ... FFE1h-FFE0h ISPRx bits I1_0 and I0_0 bits* I1_1 and I0_1 bits ... I1_13 and I0_13 bits
Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits in the CC register. Level 0 can not be written (I1_x=1, I0_x=0). In this case, the previously stored value is kept. (example: previous=CFh, write=64h, result=44h) The TLI, RESET, and TRAP vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set. *Note: Bits in the ISPRx registers which correspond to the TLI can be read and written but they are not significant in the interrupt process management. Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behaviour has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x).
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INTERRUPTS (Cont'd)
Table 6. Dedicated Interrupt Instruction Set
Instruction HALT IR ET JRM JRNM POP CC RIM SIM TRAP WFI New Description Entering Halt mode Interrupt routine return Jump if I1:0=11 (level 3) Jump if I1:0<>11 Pop CC from the Stack Enable interrupt (level 0 set) Disable interrupt (level 3 set) Software trap Wait for interrupt Pop CC, A, X, PC I1:0=11 ? I1:0<>11 ? Mem => CC Load 10 in I1:0 of CC Load 11 in I1:0 of CC Software NMI I1 1 1 1 1 H I0 0 1 1 0 N Z C Function/Example I1 1 I1 H H I0 0 I0 N Z C N Z C
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions.
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INTERRUPTS (Cont'd) Table 7. Interrupt Mapping
Exit from Priority HALT/ Order ACTIVE HALT3) yes no yes Higher Priority yes yes yes yes yes CANIS R SPICS R T A SR T B SR SCISR SICSR (see periph) AR TCSR Lower Priority yes y es 1 no no no no no y e s2
N
Source Block
Description
Register Label
Address Vector
RES ET TRAP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 T LI MC C /RTC e i0 e i1 e i2 e i3 CAN S PI TIMER A TIMER B S CI AVD I2C PWM ART
Reset Software interrupt External top level interrupt Main clock controller time base interrupt External interrupt port A3..0 External interrupt port F2..0 External interrupt port B3..0 External interrupt port B7..4 CAN peripheral interrupts SPI peripheral interrupts TIMER A peripheral interrupts TIMER B peripheral interrupts SCI Peripheral interrupts Auxiliary Voltage detector interrupt I2C Peripheral interrupts PWM ART interrupt
N/A EICR MCCSR
FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h FFE2h-FFE3h FFE0h-FFE1h
N/A
Notes: 1. Exit from HALT possible when SPI is in slave mode. 2. Exit from HALT possible when PWM ART is in external clock mode. 3. In Flash devices only a RESET or MCC/RTC interrupt can be used to wake-up from Active Halt mode.
7.6 EXTERNAL INTERRUPTS 7.6.1 I/O Port Interrupt Sensitivity The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR register (Figure 22). This control allows to have up to 4 fully independent external interrupt source sensitivities. Each external interrupt source can be generated on four (or five) different events on the pin: Falling edge Rising edge Falling and rising edge
Falling edge and low level Rising edge and high level (only for ei0 and ei2) To guarantee correct functionality, the sensitivity bits in the EICR register can be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that interrupts must be disabled before changing sensitivity. The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits of the EICR.
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INTERRUPTS (Cont'd) Figure 22. External Interrupt Control bits
PORT A [3:0] INTERRUPTS PAOR.3 PADDR.3 PA3 CONTROL IPA BIT EICR IS20 IS21 PA3 PA2 PA1 PA0
SENSITIVITY
ei0 INTERRUPT SOURCE
PORT F [2:0] INTERRUPTS PFOR.2 PFDDR.2 PF2
EICR IS20 IS21 PF2 PF1 PF0
SENSITIVITY CONTROL
ei1 INTERRUPT SOURCE
PORT B [3:0] INTERRUPTS PBOR.3 PBDDR.3 PB3
EICR IS10 IS11 PB3 PB2 PB1 PB0
SENSITIVITY CONTROL
ei2 INTERRUPT SOURCE
IPB BIT
PORT B [7:4] INTERRUPTS PBOR.7 PBDDR.7 PB7
EICR IS10 IS11 PB7 PB6 PB5 PB4
SENSITIVITY CONTROL
ei3 INTERRUPT SOURCE
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7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) Read / Write Reset Value: 0000 0000 (00h)
7 IS11 IS10 IPB I S21 I S20 IPA TLIS 0 TLIE
- ei0 (port A3..0)
External Interrupt Sensitivity IS21 IS20 IPA bit =0 0 0 0 1 0 1 Falling edge & low level Rising edge only Falling edge only IPA bit =1 Rising edge & high level Falling edge only Rising edge only
Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external interrupts: - ei2 (port B3..0)
External Interrupt Sensitivity IS11 IS10 IPB bit =0 0 0 1 1 0 1 0 1 Falling edge & low level Rising edge only Falling edge only IPB bit =1 Rising edge & high level Falling edge only Rising edge only
1 1
Rising and falling edge
- ei1 (port F2..0)
I S 21 IS20 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
Rising and falling edge
- ei3 (port B7..4)
IS11 IS10 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bit 2 = IPA Interrupt polarity for port A This bit is used to invert the sensitivity of the port A [3:0] external interrupts. It can be set and cleared by software only when I1 and I0 of the CC register are both set to 1 (level 3). 0: No sensitivity inversion 1: Sensitivity inversion Bit 1 = TLIS TLI sensitivity This bit allows to toggle the TLI edge sensitivity. It can be set and cleared by software only when TLIE bit is cleared. 0: Falling edge 1: Rising edge Bit 0 = TLIE TLI enable This bit allows to enable or disable the TLI capability on the dedicated pin. It is set and cleared by software. 0: TLI disabled 1: TLI enabled Note: a parasitic interrupt can be generated when clearing the TLIE bit.
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bit 5 = IPB Interrupt polarity for port B This bit is used to invert the sensitivity of the port B [3:0] external interrupts. It can be set and cleared by software only when I1 and I0 of the CC register are both set to 1 (level 3). 0: No sensitivity inversion 1: Sensitivity inversion Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following external interrupts:
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INTERRUPTS (Cont'd) Table 8. Nested Interrupts Register Map and Reset Values
Address (Hex.) 0024h Register Label ISPR0 Reset Value ISPR1 Reset Value ISPR2 Reset Value ISPR3 Reset Value EICR Reset Value 7 ei1 I1_3 1 SP I 0025h I1_7 1 AVD 0026h I1_11 1 I0_11 1 I1_10 1 I0_7 1 I1_6 1 SCI I0_10 1 I0_3 1 I1_2 1 C AN I0_6 1 6 5 ei0 I0_2 1 I1_1 1 ei3 I1_5 I0_5 1 1 T IM ER B I1_9 I0_9 1 1 PWM A RT I1_13 I0_13 1 1 IS20 IPA 0 0 4 3 M CC I0_1 1 1 e i2 I1_4 I0_4 1 1 T IME R A I1_8 I0_8 1 1 I2C I1_12 I0_12 1 1 TLIS TLIE 0 0 2 1 TLI 1 0
0027h 0028h
1 IS11 0
1 IS10 0
1 IPB 0
1 IS21 0
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8 POWER SAVING MODES
8.1 INTRODUCTION To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 23): SLOW, WAIT (SLOW WAIT), ACTIVE HALT and HALT. After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided or multiplied by 2 (fOSC2). From RUN mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. Figure 23. Power Saving Mode Transitions
High
fOSC2/2 fOSC2/4 f OSC2
8.2 SLOW MODE This mode has two targets: To reduce power consumption by decreasing the internal clock in the device, To adapt the internal clock frequency (fCPU) to the available supply voltage. SLOW mode is controlled by three bits in the MCCSR register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (fCPU). In this mode, the master clock frequency (fOSC2) can be divided by 2, 4, 8 or 16. The CPU and peripherals are clocked at this lower frequency (fCPU). Note: SLOW-WAIT mode is activated when entering the WAIT mode while the device is already in SLOW mode. Figure 24. SLOW Mode Clock Transitions
RUN SLOW MCCS R WAIT SLOW WAIT ACTIVE HALT HALT Low PO WER CONS UMPTION
fCPU
fOSC2 CP1:0 SMS 00 01
NEW SLOW FREQUENCY REQUEST
NORMAL RUN MODE REQUEST
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POWER SAVING MODES (Cont'd) 8.3 WAIT MODE WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the `WFI' instruction. All peripherals remain active. During WAIT mode, the I[1:0] bits of the CC register are forced to `10', to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or RESET occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 25. Figure 25. WAIT Mode Flow-chart
OSCILLATOR PERIPHERALS CP U I[1:0] BITS ON ON OFF 10
WFI I N S T R U C T I O N
N RE SET N INTERRUP T Y OSCILLATOR PERIPHERALS CP U I[1:0] BITS ON OFF ON 10 Y
256 OR 4096 CPU CLOCK CYCLE DELAY
OSCILLATOR ON PERIPHERALS ON CP U ON I[1:0] BITS XX 1)
FETC H RES ET VEC TOR O R SE RVICE I NTERRUPT
Note: 1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.
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POWER SAVING MODES (Cont'd) 8.4 ACTIVE-HALT AND HALT MODES ACTIVE-HALT and HALT modes are the two lowest power consumption modes of the MCU. They are both entered by executing the `HALT' instruction. The decision to enter either in ACTIVE-HALT or HALT mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR register).
MCCSR O I E bi t 0 1 Power Saving Mode entered when HALT instruction is executed HALT mode ACTIVE-HALT mode HA LT IN STRUCTION [MCCS R.OIE=1]
lay depending on option byte). Otherwise, the ST7 enters HALT mode for the remaining tDELAY period. Figure 26. ACTIVE-HALT Timing Overview
RUN ACTIVE 256 OR 4096 CPU HA LT CYCLE DELAY 1) RESET OR INTER RUPT RUN
FE TCH VECTOR
8.4.1 ACTIVE-HALT MODE ACTIVE-HALT mode is the lowest power consumption mode of the MCU with a real time clock available. It is entered by executing the `HALT' instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is set (see section 10.2 on page 58 for more details on the MCCSR register). The MCU can exit ACTIVE-HALT mode on reception of an MCC/RTC interrupt or a RESET. In ROM devices, external interrupts can be used to wakeup the MCU. When exiting ACTIVE-HALT mode by means of an interrupt, no 256 or 4096 CPU cycle delay occurs. The CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 27). When entering ACTIVE-HALT mode, the I[1:0] bits in the CC register are forced to `10b' to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In ACTIVE-HALT mode, only the main oscillator and its associated counter (MCC/RTC) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). The safeguard against staying locked in ACTIVEHALT mode is provided by the oscillator interrupt. Note: As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set), entering ACTIVE-HALT mode while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode. CAUTION: When exiting ACTIVE-HALT mode following an MCC/RTC interrupt, OIE bit of MCCSR register must not be cleared before tDELAY after the interrupt occurs (tDELAY = 256 or 4096 tCPU de-
Figure 27. ACTIVE-HALT Mode Flow-chart
HALT INSTRUCTION (MCCSR.OIE=1) OSCILLATOR PERIPHERALS 2) CPU I[1:0] BITS N N ON OFF OFF 10
RESET Y
INTERRUPT 4) Y
OSCILLATOR PERIPHERALS CPU I[1:0] BITS
ON OFF ON XX 3)
256 OR 4096 CPU CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON ON ON XX 3)
FETCH RESET VECTOR OR SERVICE INTERRUPT
Notes: 1. This delay occurs only if the MCU exits ACTIVEHALT mode by means of a RESET. 2. Peripheral clocked with an external clock source can still be active. 3. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and restored when the CC register is popped. 4. In flash devices only the MCC/RTC interrupt can exit the MCU from ACTIVE-HALT mode.
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POWER SAVING MODES (Cont'd) 8.4.2 HALT MODE The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the `HALT' instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is cleared (see section 10.2 on page 58 for more details on the MCCSR register). The MCU can exit HALT mode on reception of either a specific interrupt (see Table 7, "Interrupt Mapping," on page 38) or a RESET. When exiting HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 29). When entering HALT mode, the I[1:0] bits in the CC register are forced to `10b'to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In HALT mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of Watchdog operation with HALT mode is configured by the "WDGHALT" option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see section 14.1 on page 201 for more details). Figure 28. HALT Timing Overview
RUN HA LT 256 OR 4096 CPU CYCLE DELAY RESET OR INTER RUPT FE TCH VECTOR FETC H RES ET VEC TOR O R SE RVICE I NTERRUPT RUN
Figure 29. HALT Mode Flow-chart
H AL T INSTRUCTION (MCCSR.OIE=0) ENABLE W D GH A L T 1 ) 1 W ATCHDO G RE SET OSCILLATOR OFF PERIPHERALS 2) OFF CP U OFF I[1:0] BITS 10 0 W ATCHDOG DISABLE
N RE SET N Y INTERRUPT 3) Y OSCILLATOR ON PERIPHERALS OFF CP U ON I[1:0] BITS XX 4) 256 OR 4096 CPU CLOCK C YCL E DE LAY OSCILLATOR ON PERIPHERALS ON CP U ON I[1:0] BITS XX 4)
HA LT IN STRUCTION [MCCS R.OIE=0]
Notes: 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 7, "Interrupt Mapping," on page 38 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.
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POWER SAVING MODES (Cont'd) 8.4.2.1 Halt Mode Recommendations Make sure that an external event is available to wake up the microcontroller from Halt mode. When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as "Input Pull-up with Interrupt" before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure. The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E. As the HALT instruction clears the interrupt mask in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). Related Documentation AN 980: ST7 Keypad Decoding Techniques, Implementing Wake-Up on Keystroke AN1014: How to Minimize the ST7 Power Consumption AN1605: Using an active RC to wakeup the ST7LITE0 from power saving mode
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9 I/O PORTS
9.1 INTRODUCTION The I/O ports offer different functional modes: transfer of data through digital inputs and outputs and for specific pins: external interrupt generation alternate signal input/output for the on-chip peripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 9.2 FUNCTIONAL DESCRIPTION Each port has 2 main registers: Data Register (DR) Data Direction Register (DDR) and one optional register: Option Register (OR) Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is shown in Figure 30 9.2.1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Notes: 1. Writing the DR register modifies the latch value but does not affect the pin status. 2. When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. 3. Do not use read/modify/write instructions (BSET or BRES) to modify the DR register External interrupt function When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the EICR register. Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt sources, these are first detected according to the sensitivity bits in the EICR register and then logically ORed. The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the EICR register must be modified. 9.2.2 Output Modes The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status:
DR 0 1 Push-pull VS S VDD Open-drain Vss Floating
9.2.3 Alternate Functions When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register. Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.
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I/O PORTS (Cont'd) Figure 30. I/O Port General Block Diagram
REGISTER ACCESS ALTERNATE OUTPUT 1 0 ALTERNATE ENABLE DR
VDD
P-BUFFER (see table below) PULL-UP (see table below) VDD
DDR P U LL-UP C ON D I T I O N If implemented OR SEL N-BUFFER DDR SEL C MOS SCHMITT TRIGGER AN ALOG INPUT DIODES (see table below) PAD
OR
E XTERNAL IN TERR UPT SOURCE (eix)
Table 9. I/O Port Mode Options
Configuration Mode Input Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) True Open Drain P ull-Up Off On Off NI P-Buffer Off On Off NI On On Diodes to VDD t o VS S
O u tput
Legend: NI - not implemented Off - implemented not activated On - implemented and activated
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DATA BUS
DR SEL
1 0
ALTERNATE INPUT
NI (see note)
Note: The diode to VDD is not implemented in the true open drain pads. A local protection between the pad and VSS is implemented to protect the device against positive stress.
ST72F521, ST72521B
I/O PORTS (Cont'd) Table 10. I/O Port Configurations
Hardware Configuration
NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS VDD RPU PAD PULL-UP CONDITION DR REGISTER ACCESS
DR REGISTER
W DATA BUS R
INPUT 1)
ALTERNATE INPUT EXTERNAL INTERRUPT SOURCE (eix) INTERRUPT CONDITION ANALOG INPUT NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS
OPEN-DRAIN O UTPUT 2 )
VDD RPU
DR REGISTER ACCESS
PAD
DR REGISTER
R/W
DATA BUS
ALTERNATE ENABLE
ALTERNATE OUTPUT
P U S H - P U L L OU T P U T 2 )
NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS
VDD RPU
DR REGISTER ACCESS
PAD
DR REGISTER
R/W
DATA BUS
ALTERNATE ENABLE
ALTERNATE OUTPUT
Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.
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I/O PORTS (Cont'd) CAUTION: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin. WARNING: The analog input voltage level must be within the limits stated in the absolute maximum ratings. 9.3 I/O PORT IMPLEMENTATION The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 31 Other transitions are potentially risky |
