STLC544 5
QUAD LINE FEED CONTROLLER
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BATTERY VOLTAGE UP TO 120V SUPPLIES POWER FOR UP TO FOUR DIGITAL TELEPHONE LINES PROGRAMMABLE CURRENT LIMITING LON GITUDINAL CURRENT CANCELLATION ETSI ETR80 COMPLIANT OUTPUT CURRENT UP TO 140 mA STATUS CONDITION DETECTION FOR EACH LINE AUTOMATIC THERMAL PROTECTION AUTO POWER ON SEQUENCE OUTPUT STAGE OPTIMIZED FOR MINIMAL OUTPUT OVERVOLTAGE PROTECTION TW O EXTERNAL RELAY DRIVERS PER LINE PAR ALLEL OR MPI CONTROL INTERFACE HI-QUAD PACKAGE 64 PIN
HiQUAD-64 ORDERING NUMBER: STLC5445
by a pin strap.
DESCRIPTION The QUAD LINE FEED CONTROLLER provides a power source for up to four U line interfaces. The power source to the device is a local battery or a centralized regulated power supply. Each powered line is individually controlled and monitored by the device interface. A MPI or a simple parallel interface can be selected
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Each line can be individually powered and monitored: therefore overload and faults can easily be detected and localized even in a large system. The status conditions detected by the device are: Current Overload, Thermal Overload, Open Loop. If activated (by means of a dedicated pin strap), a self generated power on sequence avoids the thermal over stress when a simultaneous power on has been requested for more than one channel. The current limiting value can globally be programmed for the four channels by means of an external resistor. The device has two integrated relay drivers per line to drive the test relays of the ISDN system.
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October 2002
1/23
STLC5445
BLOCK DIAGRAM
Channel 3 Channel 2
ILIM
Limiting current reference Reference & biasing generation Voltage and current biasing
Channel 1 Channel 0
WBP0 WB0
Ther ma l monitoring
110C
PSC PBIT CKILC RESETN INTN ALE ES0 (A0) ES1 (CSN) ES2 (RDN) ES3 (WRN) NACK0 (D0) NACK1 (D1) NACK2 (D2) NACK3 (D3)
On / Off & line current control
WA0
130C
160C
Logic int erface
COD OLD
V BAT
COD & OLD generation
V CC VCC BGND DGND RGND VBAT EREL3B EREL3A EREL2B EREL2A EREL1B EREL1A EREL0B EREL0A
Relay driver 3B Relay driver 3A Re lay driver 2B Re lay driver 2A Relay driver 1B
I / O connections on channels 1, 2 and 3 are similar to those reasons. shown for channel 0 but have been omitted for clarity
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VBAT
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Relay driver 1A Relay driver 0B
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Driving & output clamping
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CODC0
Relay driver 0A
REL3B REL3A REL2B REL2A REL1B REL1A REL0B REL0A
2/23
STLC5445
PIN CONNECTION (Top view)
RGND BGND WBP0 WBP3 VBAT VBAT WB3 WA0 WB0 WA3 N.C. ILIM
64 63 62 61 60 59 CODC0 CODC1 RGND CK_ILC NACK0(D0) NACK1(D1) REL0A *EREL0A *EREL0B REL0B REL1A *EREL1A *EREL1B REL1B ALE PBIT PSC INTN BGND N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
VBAT WBP1 WA1 WB1 N.C. VCC
58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 N.C. BGND *RESET NACK3(D3) NACK2(D2) REL3B *EREL3B *EREL3A REL3A REL2B *EREL2B *EREL2A REL2A *ES3(WR) *ES2(RD)
*INTERNAL PULL DOWN TO GROUND
PIN FUNCTION
N 1 2 4 5 Pin Name CODC0 CODC1
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CKILC REL0A
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Pin for connection of the external capacitor (100nF/6.3V) to GND for COD signal filtering on channel 0. Pin for connection of the external capacitor (100nF/6.3V) to GND for COD signal filtering on channel 1 External clock input pin for the internal power on sequencer
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VBAT WB2 WBP2 DGND
27 28 29 30 31 32
WA2 BGND
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*ES1(CS) *ES0(A0) RGND CODC3 CODC2
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D99TL437
Description
NACK0(D0) NACK1(D1)
Logic pin: with PSC = 0, Line 0 status information output with PSC = 1, Line 0 I/O tristate data bus Logic pin: with PSC = 0, Line 1 status information output with PSC = 1, Line 1 I/O tristate data bus Output of the 0A relay driver Logic input pin: relay 0A output driver's ON/OFF (high = ON) Logic input pin: relay 0B output driver's ON/OFF (high = ON) Output of the 0B relay driver Output of the 1A relay driver
*EREL0A *EREL0B REL0B REL1A
10 11
3/23
STLC5445
PIN FUNCTION (continued)
N 12 13 14 15 16 17 18 21 23 24 25 28 29 30 31 33 34 36 37 38 39 40 41 42 43 44 Pin Name *EREL1A *EREL1B REL1B ALE PBIT PSC INTN WA1 VCC WBP1 WB1 WB2 WBP2 DGND WA2 CODC2 CODC3 *ES0(A0) Description Logic input pin: relay 1A output driver's ON/OFF (high = ON) Logic input pin: relay 1B output driver's ON/OFF (high = ON) Output of the 1B relay driver Logic input pin: with PSC = 0, Don't care with PSC = 1, Address Latch Enable (active high) Power on sequencer enable: PBIT = 0: power on sequencer ON PBIT = 1: power on sequencer OFF Parallel or MPI mode input selection pin: 0 = parallel interface; 1 = MPI interface Logic output pin; open drain: with PSC = 0 high impedance with PSC = 1 interrupt (active low) Output feeder's switch side of line 1; negative respect to WB1 Positive supply voltage. It is referred to DGND Internal protection diodes for line 1 Output feeder's resistive side of line 1; positive respect to WA1 Output feeder's resistive side of line 2; positive respect to WA2 Internal protection diodes for line 2 Digital ground
Output feeder's switch side of line 2; negative respect to WB2 Pin for connection of the external capacitor (100nF/6.3V) to GND for COD signal filtering on channel 2 Pin for connection of the external capacitor (100nF/6.3V) to GND for COD signal filtering on channel 3
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REL2A *ERL2B REL2B REL3A
*ES1(CSN)
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Logic input pin: with PSC = 0, Line 0 ON/OFF request (high=ON) with PSC = 1, Address bit for R/W operations
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Logic input pin: with PSC = 0, Line 1 ON/OFF request (high=ON) with PSC = 1, chip select (active low) Logic input pin: with PSC = 0, Line 2 ON/OFF request (high=ON) with PSC = 1, Read command (active low)
*ES2(RDN)
*ES3(WRN)
Logic input pin: with PSC = 0, Line 3 ON/OFF request (high=ON) with PSC = 1, Write command (active low) Output of the 2A relay driver Logic input pin: relay 2A output driver's ON/OFF (high = ON) Logic input pin: relay 2B output driver's ON/OFF (high = ON) Output of the 2B relay driver Output of the 3A relay driver
*EREL2A
4/23
STLC5445
PIN FUNCTION (continued)
N 45 46 47 48 49 50 53 55 56 57 60 61 0 26 27 58 59 19 32 51 64 3 35 62 Pin Name *EREL3A *ERL3B REL3B Description Logic input pin: relay 3A output driver's ON/OFF (high = ON) Logic input pin: relay 3B output driver's ON/OFF (high = ON) Output of the 3B relay driver
NACK2 (D2) Logic pin: with PSC = 0, Line 2 status information output with PSC = 1, Line 2 I/O tristate data bus NACK3 (D3) Logic pin: with PSC = 0 line 3 status information output with PSC = 1 line 3 I/O tristate data bus *RESETN WA3 ILIM WBP3 WB3 WB0 WBP0 WA0 VBAT Logic input pin: reset (active low) Output feeder's switch side of line 3; negative respect toWB3 Current limit programming input Internal protection diodes for line 3 Output feeder's resistive side of line 3; positive respect to WA3 Output feeder's resistive side of line 0; positive respect to WA0 Internal protection diodes for line 0
Output feeder's switch side of line 0; negative respect to WB0 Negative battery supply voltage. It is referred to BGND
BGND
Battery ground
RGND
Relay ground
* Internal pull down to ground
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5/23
STLC5445
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VCD VBB VBD IWBn INEG Tstg Parameter Voltage from digital input to DGND Voltage from VCC to DGND Voltage from VBAT to BGND Voltage from BGND to DGND AC Current into the WBn outputs (WBPn not connected to GND Negative current injected in the WAn outputs (-40 to +85C) Storage temperature Value 0.5 to VCC + 0.5 0.4 to +7 143 to + 0.4 3 to +0.5 250 50 60 to 150 Unit V V V V mA peak mA C
RECOMMENDED OPERATING CONDITION
Symbol VCC VBAT VBGND ILIMT (1) IRelay Ta normal Parameter VCC supply voltage VBAT supply voltage BGND/DGND voltage Programmable range of the current limiting function Relay driver current Ambient temperature normal range Test Condition Min. 4.75
Ta extended Ambient temperature extended range Iloop RMIN Max operating loop current
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External, short circuit resistive load from WAn to WBn
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Typ. 5.25 38 0.5 140 70 70 85 140
Max.
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Unit V V V mA mA C C mA W
55
6/23
STLC5445
ELECTRICAL CHARACTERISTCS Unless otherwise specified the below listed parameters' values are referred to the following conditions: VBAT = 115V, VCC = 5V, Rlim = 53.6 kW, CODCn RC series = 100nF 10% and 510 1%, normal temperature range [0C to 70C]. The presence of an asterisk mark (*) indicates that the marked parameter must remain within the specified tolerance in the extended temperature range [-40C to 85C].
Symbol IVcc IVBAT ILIMT ILIMTL ILIM% Parameter VCC supply current VBAT supply current Current limiting value with transversal line current only Current limiting value with added longitudinal line current Current limiting accuracy in the range 20 to 140 mA(1) Leakage current of each WAn output to ground with output driver disabled Resistance from WAn to VBAT Resistance from WBn to BGND Absolute value of the difference between RWAn and its related RWBn 110C thermal monitoring threshold IWA = 30mA 3.15 Test Condition All the switches on o load All the switches on o load Ilong = 0 See Fig.1 42.5 1.5 50 Min. Typ. Max. 2.5 1.8 57.5 Unit mA mA mA
37.5 15
50
62.5
mA
Ilong = 0
%
I HZ
RWA
RWB ROUT
IWB = 30mA IWA = IWB = =30mA
Tj110 Tj130 Tj160 Thyst
130C thermal monitoring threshold 160C thermal monitoring threshold Thermal monitoring hysteresis
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5.5 7.85 5.5 7.5 0.7 1(*) 110
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A
C
130
C
160
C
10
C
Longitudinal output component of the fCKILC clock signal Relay drivers' output voltage
See Fig. 2
60
dBV
All the relay drivers activated at a load current of 33mA.(3) All the relay drivers activated at a load current of 70mA.(3) ERLn = Low
0.5
V
VRel70
Relay drivers output voltage
1.2
V
IRleak
Relay driver leakage current
100
A
7/23
STLC5445
ELECTRICAL CHARACTERISTICS (continued)
Symbol ISOC OLDH Parameter Open circuit detector threshold Open Loop detector Hysteresis Test Condition Min. 1.5 Typ. 3 0.6 Max. 4 1.6 Unit mA mA
Notes: 1. Our characterizations show that in the range 15mA - 20mA the accuracy is 20% over the 0C - 70C temperature range. 2. The longitudinal component of the signal detected by the spectrum analyzer must have an RMS voltage value, in any 4kHz equivalent bandwidth, averaged in any 1 second period, not greater of the specified value (60dBV) over the 100Hz - 150kHz range (for details see ETSI ETR80 and ANSI 601). 3. All the output lines activated at a line current of 35mA; no current limitation condition. Rth(j-a) 20C/W
Please note that, in order to assure the frequency stability of the output drivers, a 1F capacitor must always be connected between WAn and Wbn or, as shown in Fig. 6, immediately after the resistive protection elements used in the actual application. The RLIM value can be calculated starting from the value of the needed current limitation threshold ILIMT:
2664 R L I M = --------------IL I M I T SWITCHING TIMING
Symbol tE N P tDISP fCKILC Parameter Output driver's enable time Output driver's disable time Frequency of CKILC Test Condition Parallel interface mode Parallel interface mode Duty cycle 60% max Pulse width 500ns min Min.
Figure 1.
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STLC5445 output driver (one of four)
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WBn WAn
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20 500 8 200
Typ.
Max.
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Unit s s kHz
30 20 F 1% 0.01%
I LIMTL
1.3k 1% 8.5VRMS 16.6Hz
25 0.01%
30 20 F 1% 0.01%
8/23
STLC5445
Figure 2.
67.5 0.01% WBn 10 F 1%
STLC5445 output driver (one of four)
3.9k 1% 100 1%
Spectrum analyzer
WAn 67.5 0.01% 10F 1% 150nF10%
STATIC CHARACTERISTICS
Unless otherwise specified the below listed parameters values are referred to the following conditions: VCC = 5V, normal temperature range.
Symbol VIL VIH V OL VOH ILH ILL IOZ Parameter Input low voltage Input high voltage Output low voltage Output high voltage (Open drain with PSC = 0) Input high current Input low current Io = 1mA Test Condition
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Output current in High impedance state
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Io = 1 mA
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Min. 2 2.4 0 -10 -10
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Unit V V V V
Max.
10 0 10
A A A
9/23
STLC5445
SWITCHING CHARACTERISTICS MICROPROCESSOR WRITE / READ TIMING (refers to figures 3 and 4). Unless otherwise specified the below listed parameters' values are referred to the following conditions: VCC=5V, normal temperature range.
Symbol tRLRH tRHRL tRLDA t RHDZ tAHAL tADAL tADAZ tAZRL tAZWL tADDA tWLWH tWHWL tDAWH tWHDZ tRESN Parameter RDN, CSN pulse width RDN, recovery time Tamb = 40 to 0C and +70C to +85C RDN, CSN low to data available RDN or CSN high to data Z Tamb = 40 to 0C and +70C to +85C ALE pulse width Address setup time Address hold time Address Z to RDN low Address Z to WRN Low Address stable to data available WRN or CSN pulse width Write recovery time Data setup time Data hold time Reset Pulse with Tamb = 40 to 0C and +70C to +85C 100 60 50 0 0 Test Condition Min. 260 200 220 260 130 160 Typ. Max. Unit ns ns ns ns ns
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Tamb = 40 to 0C and +70C to +85C
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ns ns ns ns ns ns ns ns ns
ns
10/23
STLC5445
Figure 3. Microprocessor WRITE timing
tAHAL
ALE
tADAL tADAZ
AO
tCLRL (Note 1) tRHCH (Note 2)
CS
tAZRL tADDA
tRHRL tRLRH tRHDZ tRLDA
RD
DATA
Read Data
D94TL108A
Notes: 1. If tCLWL is negative tWLWH is measured from CS_ rather than fromWR_. 2. If tWHCH is negative, tWHWL, tWLWH, tDAWH and tWHDZ are measured from CS_ rather than fromWR_. The propagation delay from the writing of the T/I bit to the effect on the INT pin is approximately 1ms for both mask and enabl e operations.
Figure 4. Microprocessor READ timing
tAHAL
ALE
tADAL tADAZ
AO
CS
WR
DATA
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tWHCH (Note 2)
tWHWL
tAZWL
tDAWH Write Data
tWHDZ
(Note 3)
INT
D94TL109A
Notes: 1. If tCLRL is negative, tRHRL, tRLRH, tAZRL, and tRLDA are measured from CS_ rather than RD_. 2. If tRHCH is negative, tRHRL, tRLRH and tRHDZ are measured from CS_ rather than RD_. When a read from the LER immediately follows a write to the LER a minimum of 1ms is required between these operations
11/23
STLC5445
Figure 5. Typical Application Circuit
Z1 2 x SM6T68A C4 100nF BGND 59 51 58 32 27 19 26 8 9 12 13 41 42 45 46 7 10 11 14 40 64 DGND 30 ILIM 55 50 4 18 17 16 15 36 37 38 39 5 6 48 49 RESET CK_ILC INTN PSC PBIT ALE ES0/A0 ES1/CS ES2/RD ES3/WR NACK0(D0) NACK1(D1) NACK2(D2) NACK3(D3) DIGITAL CONTROL
VBAT C3 100nF BGND VBAT C2 100nF BGND VBAT C1 100nF BGND VBAT EREL0A EREL0B EREL1A EREL1B RELAYS COMAND EREL2A EREL2B EREL3A EREL3B REL0A REL0B REL1A REL1B RELAYS REL2A REL2B REL3A REL3B
VBAT
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61 24 29 56 60 25 28 57 63 21 31
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WBP_0 WBP_1 WBP_2 WBP_3 WB_0 WB_1 WB_2 WB_3 WA_0 WA_1 WA_2 WA_3
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OUTPUTS CLAMPING
DRIVER OUTPUTS
20,22,52,54 33 CODC1 C7 100nF CODC2 C8 100nF 34
53
RGND
VCC C5 100nF
CODC0 C6 100nF
CODC3 C9 100nF
D99TL440
External Component List
Coponents Description Value 100nF 100nF 53.6k 136V
C1, C2, C3, C4 & C5 Power Supply Filter Capacitance C6, C7, C8 & C9 RLIN Z1 Signal Filter Capacitance Programmable Limiting Current Resistor Transil Clamping Protection
12/23
STLC5445
Figure 6. Typical Protection Diagram (only channel 0 and 1 shown)
TIP SM5908 16PTC 1F 16PTC 22
BGND WBP1 WB1 WA1 22
CHANNEL's 1 OUTPUT DRIVER's STAGE
RING
2x SM6T68A WBAT
WBAT BGND WBP0 16PTC 16PTC SM5908 WB0 22 WA0 22
TIP
CHANNEL's 0 OUTPUT DRIVER's STAGE
1F
RING
Note: The 1F capacitors are required for output driver's stability
FUNCTIONAL DESCRIPTION WAn (n=0-3)
Drivers (output pins).
Each WAn output can sink up to 140mA. When the ESn input is High and the activation request is approved by the internal control circuitry, the respective WAn output is internally connected to VBAT through a DMOS switch and the low side sensing resistor. WBn (n=0-3)
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WBPn (n=0-3) Protection diodes connection (see the block diagram at page 3). Each channel of the STLC5445 has two internal, back to back connected diodes, whose clamping action can be used to protect the WBn outputs during lighting and power crossing events. The diodes' clamping action is normally disabled and can be activated by connecting the WBPn pin to BGND. In this case however, if the line current exceeds 57.5mA the forward drop across the high side sensing resistor (and then across the diodes) reaches the diodes' conduction threshold, strongly degrading the current limiting action and the longitudinal balance. For line currents higher than 57.5mA external clamping elements must then be connected in place of the internal diodes or in series to them in order to increase the clamping voltage value. Battery ground. Digital ground.
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Resistor to BGND. Each WBn output connects the wire B to ground through a 5W resistor used to perform the longitudinal balance and the high side current sensing function.
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BGND DGND
13/23
STLC5445
RGND CKILC Ground connection of the relay drivers. Logic input. External clock input for the Power On Sequencer embedded in the Logic interface (see the block diagram at page 3). The Power On Sequencer controls (if activated) the power on sequence of the lines. This will limit the chip's temperature increase that occurs, at channels switch on, due to the charging current of the capacitances used by the external ISDN circuitry. If used, the Power on sequencer is the only block of the circuit that needs an external clock signal. ESn (n=0-3) Logic inputs. These pins have double names (see the block diagram at page 3) because they perform a double function: one in Parallel mode ( PSC = 0 ), and another in MPI mode ( PSC = 1). In Parallel mode ESn acts as an activation or deactivation request for the respective line driver: ESn = 0: Line driver deactivation request. ESn = 1: Line driver activation request. In MPI mode the pins perform the following functions: A0: Selects the source and destination locations for read and write operations on the data bus. A0 must be valid on the falling edge of ALE or during RDN and WRN if ALE is tied High. Data transfer occurs over the D0-D3 lines. This pin acts as a chip select. It must be Low to enable the read or write operations of the device. Read command. The active Low read signal is conditioned by CSN and transfers internal information to the data bus. If A0 is a logical 0, the logic levels of the Indirect Address Register (IAR) and of the Thermal Shutdown Status bit will be transferred to D3-D0. If A0 is a logical 1, the data addressed by the IAR will be transferred to D3-D0.
CSN: RDN:
WRN: Write command. The active Low write signal is conditioned by CSN and transfers information from the data bus to one of the two internal registers selectable by A0: if A0 is a logical 1, D3-D0 is written into the Line Enable Register (LER); if A0 is a logical 0, D2-D0 are written into the Indirect Address Register (IAR) and D3 is written as bit 3 and manages the generation of the interrupt signal for the external microprocessor. LER and IAR are the only two writable registers in the device. RESETN Reset pin. It initializes the Power on sequencer, the TOR register and, in the MPI interface, the registers and the INTN (interrupt output pin). When applied it leaves all the line drivers switched off. It has no effect in Parallel interface mode if the power on sequencer is not used. When the supply voltages are applied to the circuit, an equivalent RESETN pulse (power on reset) is automatically, internally generated.
ALE
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Address Latch Enable. ALE is a logic input pin. It is used to strobe the address bit applied at the A0 pin, into the address latch. The address is latched on the High to Low transition of ALE. While ALE is High the address latch is transparent. For a non multiplexed microprocessor bus, ALE must be tied High. The current limiting programming input, ILIM, is used to program the current limit of the four drivers by means of an external resistor connected between this pin and DGND. The voltage at ILIM pin is a replica of the internal bandgap voltage (1.236V). When a line driver is in current limitation, its output current is 2155 times higher than the current flowing in the external current limiting programming resistor.
ILIM
INTN
The INTN (interrupt) open drain type output can only be used in MPI interface mode. INTN can be used to alerts an external microprocessor when a current overload condition occurs. It is not
14/23
STLC5445
latched and is active (Low level) when at least one of the CODn status detector bits is active (High level). When the four CODn status detector bits are Low, INTN goes inactive (High). INTN will also go inactive if (due to thermal overload) the QLFC automatically disables the output driver of the channel that caused the interrupt, or if the external microprocessor disables that line via the Line Enable Register (LER). The interrupt function can be disabled (INTN remains permanently High) via the Indirect Address Register (IAR) or a Low level on the RESETN pin. NACKn (n=0-3)Logic I/O. These pins have double names (see the block diagram at page 3) because they perform a double function: one in Parallel mode ( PSC = 0 ), and another in MPI mode ( PSC = 1). In Parallel mode each NACKn acts as an open drain output and gives the channel's status information. The NACKn bit goes in high impedance state (bit = 1 if a NACKn pull up is provided) when at least one of these conditions is verified: The current on the relative line reaches the current limit programmed by the user. The chip's temperature reach the thermal alarm threshold. The line driver is in the Power on phase. When the ESn input is set Low, the corresponding NACKn is set to zero.
In MPI mode the four pins become D3 - D0 and act as a bidirectional data bus with three state capability. The four bidirectional data bus lines are used to exchange information with an external microprocessor. D0 is the least significant bit and D3 is the most significant bit. An High Level on the data bus corresponds to a logical 1. When the chip select bit (CSN) is Low, these lines act as inputs when WRN is Low and as outputs when RDN is Low. When CSN is High the D3 - D0 pins are in a high impedance state. PSC Logic input. PSC = 0: Parallel mode. PSC = 1: MPI mode. ERLn (n=0A-3B) Logic inputs. ERLn = 0 : ERLn = 1 : This pin is used to select one of the two available logic interfaces.
Each ERLn pin controls directly the respective relay driver's DMOS: Switch off the relay driver. Switch on the relay driver.
RLn (n=0A-3B) Relay drivers' output.
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Each of the eight RLn pins is connected to the drain of an internal DMOS switch (see the block diagram at page 3) which acts as a driver for an external relay to be supplied from VCC. The relay drivers' current flows to ground through the RGND pins. Each output can sink up to 70 mA. An internal clamping circuit is provided, so no external kickback diodes are required.
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When a line over current condition exists, the output driver of the overloaded channel instantaneously limits the line current at the value programmed by means of the external RLIM resistor. In this condition the Current Overload Detector bit (COD) switches to a High logic level. When operating in MPI mode this bit can, for each of the four channels, be red by the external microprocessor in order to check which channel (if any) is overloaded. When in parallel mode each COD bit is internally OR combined with two other bits in order to generate the NACKn bit. Since in the ISDN application it can happens that the sum of the DC line current and the superimposed signal peaks, easily exceeds the needed DC current limit, the COD generation circuitry has been arranged in such a way that the COD bit will be pushed High only if the current overload persists for at least 20ms: this eliminates any spurious High level COD / NACK. The men15/23
STLC5445
tioned delaying function requires, for each of the four channels, one Capacitor of 100nF has to be connected between each CODCn and ground. OPERATIVE DESCRIPTION The device comprises three main blocks: the Analog section , the Logic section and the Relay driver section. The Analog section feeds the four lines and detects their status. The Logic section allows to exchange information and commands between the QLFC and the external digital system. The Relay driver section is completely independent: each relay command input is related to its own driver without any conditioning. Analog Section (see the Block diagram at page 3) The ANALOG section comprises the Channel 0-Channel 3 block, the Reference & biasing generation block and the Thermal monitoring block. As shown in the channel's card of the block diagram, the WBn and WAn pins to which the line is connected are respectively routed to the battery ground and to the VBAT line: WBn goes to BGND through the upper side sensing resistor; WAn goes to VBAT through a power DMOS and the lower side sensing resistor. The ON/OFF control for the power DMOS comes from the outside world through the Logic interface block. The implemented topology for the circuit used to cancel the longitudinal current effect is a DC coupled topology: it doesn't need external capacitors and its frequency band starts from DC. The QLFC has a double protection provided by its current limiting and thermal monitoring capabilities. The current limit threshold (ILIMT) of the four channels is hardware programmable by means of a single, external resistor (RLIM): 1.236 2155 I L I M I T = -------------------------------- . RL I M The protection implemented by the thermal monitoring is based on a three levels control system: A first temperature threshold controls the Power on sequencer (see the Logic Section for a detailed description of its behaviour). When activated (PBIT pin Low), the Power on sequencer manages the channels' activation requests received through the Parallel (PSC pin Low) or the MPI (PSC pin High) interface. The incoming channels' activation requests are stored in the Power on sequencer and then satisfied, one at a time, only when the previously activated channel leaves the current limiting condition that normally occurs at power on, due to the capacitive element that is part of the ISDN load. However when the chip's internal temperature reaches 110C, only the already stored activation requests will be satisfied; the new, eventually incoming ones, will be rejected and will be processed when the internal temperature decreases down to 100C. A second temperature threshold is set at 130C. When this value is reached the channels that are in current limiting condition are switched off and their reactivation will only be possible when the chip's internal temperature has decreased down to 120C or, if the Power on sequencer is activated, down to 100C. The third temperature threshold is set at 160C. When this temperature is reached the activated channels will all be switched off and their reactivation will only be possible when the chip's internal temperature has decreased down to 150C. The user must however take into account that if (like in ISDN application) the load seen by the channel has a high capacitive component, at channel's turn on a current limiting condition will always occur and the eventually reactivated channels will almost instantaneously be switched off by the 130C monitoring circuit, if the chip's internal temperature is still higher than 120C. More over (as explained at the previous point) if the Power on sequencer is activated it will not be possible to switch on any channel until the chip has cooled down to 100C.
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Each of the four channels generates two status detector bits (see the block diagram at page 3): the COD bit (Current Overload Detector) and the OLD bit (Open Loop Detector). The functions of the two bits are the following: The COD bit goes in a High logic state when its channel is in current limiting condition. Since in the ISDN application it can happens that the sum of the DC line current and the superimposed signal peaks, easily exceeds the needed DC current limit, the COD generation circuitry has been arranged in such a way that the COD bit will be pushed High only if the current overload persists for at least 20ms: this eliminates any spurious High level COD. The mentioned delaying function requires, for each of the four channels, one Capacitor of 100nF has to be connected between each CODCn and ground. The OLD bit goes in a High state logic when the current that the channel supplies to the line falls below a typical value of 3mA, indicating a probable open line condition. As explained in the following pages, when operating in MPI mode the COD and OLD bits can, for each of the four channels, be red by an external microprocessor in order to check which channel (if any) is over or under loaded. When in Parallel mode a single status bit (the NACKn bit) is provided for each channel and is directly available on a dedicated pin. The NACKn bit is internally generated by OR combining the COD bit with two other bits (see the Logic section for a more detailed explanation). Logic Section
The Logic section comprises the Parallel interface, the MPI interface and the Power on sequencer. In the block diagram shown at page 3 the three functions have been condensed in a single entity: the Logic interface block. For each of the four channels, both types of the two provided interfaces use the COD, OLD and TOR (Thermal Overload Register) status detector bits: The COD (Current Overload Detector) bit is in a High logic state when its channel is in current limiting condition since at least 20ms. The OLD (Open Loop Detector) bit is in a High logic state when the current that the channel supplies to the line falls below a typical value of 3mA (ISOC spec's parameter), indicating a possible open line condition. Each of the four output line drivers can be switched on, only if their corresponding TOR bit is High. The TOR bits are automatically set High by the internal power on reset when the chip is initially connected to its power supplies but can, however, also be globally set High by applying a reset pulse to the RESETN pin. Alternatively the TOR bits that are latched in a Low state can individually be set High by applying to the selected interface the switch off command relative to their channel.
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The TOR bits will go in a Low state (determining the shut off of their relative channel's driver) in two cases: The activated channel is in current limiting condition and the chip's temperature reaches 130C. In this case the TOR will be latched in Low state. The chip's temperature reaches 160C: in this case the TOR bits will all be set Low but only the TOR of the activated channels will be latched.
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Power on sequencer When activated (PBIT pin Low), the Power on sequencer manages the channels' activation requests received through the Parallel (PSC pin Low) or the MPI (PSC pin High) interface. The incoming channels' activation requests are stored in the Power on sequencer and then satisfied, one at a time, only when the previously activated channel exit the current limiting condition that normally occurs at power on, due to the capacitive element that is part of the ISDN load. It must be noted that once a channel exits from the channel's turn on current limiting phase, the fact that it can for example because of a new line overload fall again in a current limiting condition
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has no influence in the activation sequence of the next channels. The stored activation requests are satisfied starting from the lower index of the actually stored requests: if (for example) while channel 2 is in the activation phase, additional power on requests arrive for (in the order) channels 1, 3 and 0, when the channel's 2 activation phase will be concluded the stored activation requests will be satisfied in the order 0, 1 and 3. It must be noted that the channels' deactivation requests are not conditioned by the Power on sequencer. Figure 7. Power on sequence example
DAR0 COD0 POF0 DAR1 COD1 POF1 DAR2 COD2 POF2
Notes: DARn are the line Drivers' Activation Request bits sent to the Power on sequencer. They are internally generated starting from the activation requests coming from the outside world through the selected interface (Parallel or MPI). POFn are the Power On Flags. Each POFn goes High with its relative DARn bit and returns to a Low state when the current limiting condition ends: a POF High state indicates that the relative channel is in the power on phase.
The figure 6 shows, for three of the four available channels, a typical power on sequence example. The CODn pulse duration represents the time needed to charge the capacitive element that is part of the ISDN load, with part of the constant current that each line driver provides with the actually programmed current limiting value. It must be realized that if (for example) has been required the activation of the lines 0, 2 and 3 but line 2 is overloaded and cannot leave the current limiting condition, the activation sequence will remain blocked at the line 2 activation step. In this case the external software has to identify and shut off the overloaded line in order to allow the activation of the line 3. The previously mentioned RESETN pin will also influence the Power on sequencer: when RESETN is pushed Low the Power on sequencer is reset, switching off the actually activated drivers.
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The Power on sequencer is the only block of the circuit that needs an external clock signal to be applied at the CKILC pin. The clock frequency is not critical and has a nominal value of 8kHz. When PBIT=1 the power on sequencer is disabled and the incoming channels' activation requests will instantaneously be satisfied. In this case the user as to take into account the actual operative condition (VBAT, the programmed current limiting value, the load applied to the lines, the ambient temperature) and implement his own power on sequence in order to limit the chip's temperature increase induced by the channels' switch on transients.
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Parallel interface mode In Parallel interface mode (PSC pin Low), for each of the four output drivers a dedicated activation pin is provided (ES0-ES3): Each driver will unconditionally be switched off when its ESn is pushed Low. If the Power on sequencer is not used, each driver will be switched on (under the supervision of the previously described Thermal monitoring block) when its ESn is pushed High. If the Power on sequencer is activated the drivers' activation requests coming from the ESn inputs will (under the supervision of the previously described Thermal monitoring block) be processed by the Power on sequencer block (see the previous Power on sequencer's description). In Parallel interface mode a single status bit is provided for each of the four channels at the open drain NACK0 - NACK3 output pins. The NACKn bit is generated by OR combining the three previously described status detector bits: CODn, POFn and the complemented TOR. This means that each NACKn bit goes in high impedance state (bit=1 if a NACKn pull up is externally provided) when at least one of these conditions is verified: The current on the relative line reaches the current limit programmed by the user (the NACKn High state in this case will not be latched). The chip's temperature reaches 130C and the channel is in current limiting condition (the NACKn High state will in this case be latched). The chip's temperature reaches 160C (in this case all the NACKn will go in High state, but only the NACKn of the activated channels will be latched). The line driver is in the power on phase (in this case the NACKn will remain in High state only for the time during which its channel is in current limiting condition). When the ESn input is set Low, the corresponding NACKn is always set to zero. In Parallel interface mode the output pin INTN and the input pin ALE are not used (ALE must in this case be tied High or Low). MPI interface mode
In MPI mode (PSC pin High), the ALE and INTN pins become active and the pins NACK0-NACK3 and ES0-ES3 have a function that is completely different from that performed in Parallel mode: The four NACK0-NACK3 pins become D0 -D3 and act as a bidirectional data bus with three state capability. The four ES0-ES3 pins become respectively A0, CSN, RDN and WRN. In MPI mode the above mentioned four bits data bus and three internal four bits registers, LER (Line Enable Register), LEC (Line Enable Control) and IAR (Indirect Address Register) are used to perform the following operations:
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Channels' output drivers switch on and switch off. Enabling/disabling of the INTN (interrupt) signal generation. Status detector bits reading. T bit reading (this bit is High only when the internal chip's temperature exceeds 160C).
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The read/write operations on the data bus can only be performed when the CSN (Chip Select) pin is Low since when CSN is High the data bus is inactive (high impedance state). The active Low RDN and WRN signals are used to perform the read and write operations on the registers selected by the logic level applied at the A0 pin: A0=0 selects: The IAR register if a write operation is performed (status detector bits type selection and enabling/disabling of the INTN signal generation via the I bit). The reading of the bits actually written in the IAR register if a read operation is performed. A0=1 selects: The LER register if a write operation is performed (switch on and switch off requests programming for the output drivers).
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The status detector bits reading if a read operation is performed. A0 must be valid on the falling edge of the signal applied at the ALE (Address Latch Enable) pin or during the read and write operations if ALE is tied High. NOTE: A delay of at least 1ms is required between a LER writing and the next LER reading. Subsequent LER reading operations do not have this constraint. The line output drivers' switch on or switch off requests are implemented by first selecting the LER register and then by writing in its D0-D3 bits a 1 (turn on request) or a 0 (turn off request). D0 controls channel 0, D1 channel 1 and so on. If the requests are accepted by the Thermal monitoring block and (if activated) by the Power on sequencer, the bits stored in the LER register are copied in the LEC register whose status (1 = turn on; 0 = turn off) directly controls the output drivers' ON/OFF condition. For each of the four channels, in MPI mode the following six status detector bits are available: The COD, OLD and TOR bits whose function has already been described at the beginning of the Logic Section paragraph. The LER and the LEC bits. The POF (Power On Sequencer) bit already described at the Power on sequencer paragraph. The status detector bits reading is performed by first writing in the 2 - 0 bits of the IAR register (via the D2-D0 bus lines) a three bits code used to select which of the six available status detector bits type has to be red. A0 must then to be set at 1 and the reading cycle has to be performed. The status detector bits' selection codes are listed in the following table. If (for example) a 010 code has been written in the IAR, the output on the D0 - D3 lines at the end of the reading cycle will be the COD0 - COD3 bits. Please, note that since the red data are not latched (apart from the TOR status detector bits of the channels whose output drivers are switched on), the user should filter them (multiple samples) to ensure theirs integrity.
IAR2 0 0 0 0 1 1 1 IAR1 0 0 1 1 0 IAR0 0 1 0 Selected status detector bits type POF OLD COD LEC RESERVED RESERVED LER TOR
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As already explained the IAR is a four bits register but only three bits (D2 - D0) are required to select one of the six available status detector bits types. The fourth IAR bit (D3) is the I bit and is used to enable (1) or disable (0) the generation of the interrupt signal INTN that, via the INTN pin, can alerts an external microprocessor when a current overload condition occurs. INTN is active (Low level) when at least one of the CODn status detector bits is active (High level). When the four CODn status detector bits are Low, INTN goes inactive (High): this clearly means that INTN will also go inactive if (due to thermal overload) the QLFC automatically disables the output driver of the channel that caused the interrupt or if the external microprocessor disables that line via the LER register. The interrupt function can also be disabled (INTN remains permanently High) by applying a Low level on the RESETN pin.
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As previously explained, when a reading operation is performed while A0 = 0 the four bits actually written in the IAR register can be read on the D3 - D0 bus lines. We already know that the D2 - D0 bits represent the status detector bits selection code. The D3 bit is the T bit: it is High only when the internal chip's temperature exceeds 160C.
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The IAR bits' function has been summarized in the following table:
Bit 0 1 2 3 Symbol IAR0 IAR1 IAR2 IAR3: T (read) I (write) Bit function Bit 0 of the status detector bits selection code Bit 1 of the status detector bits selection code Bit 2 of the status detector bits selection code T bit (read only): Logical 0 when chip's temperature is below 160C Logical 1 when chip's temperature exceeds 160C I bit (write only): Logical 0 to disable the interrupt generation Logical 1 to enable the interrupt generation
The logic behaviour of the MPI's chip select and read/write operations has been summarized in the following table:
CSN 0 0 0 0 1 RDN 1 0 1 0 X WRN 0 1 0 1 X A0 0 0 1 1 X Write IAR Read IAR Write LER Performed operation
Read the status detector bits types selected via the IAR No access
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mm MIN. A A1 A2 A3 b c D D1 (1) D2 E E1 (1) e E2 E3 E4 F G L N S 0.80 2.35 9.30 13.30 9.50 13.50 0.10 0.12 1.10 0.031 10(max.) 0(min.), 7(max.) 0 2.50 0 0.22 0.23 17.00 13.90 2.65 17.00 13.90 14.00 0.65 2.65 9.70 13.70 0.092 0.366 0.523 0.374 0.531 0.004 0.005 0.043 14.00 2.80 TYP. MAX. 3.15 0.25 2.90 0.10 0.38 0.32 17.40 14.10 2.95 17.40 14.10 0 0.10 0 0.008 0.009 0.669 0.547 0.104 0.669 0.547 0.551 0.025 0.104 0.382 0.539 0.551 0.110 MIN. inch TYP. MAX. 0.124 0.010 0.114 0.004 0.015 0.012 0.685 0.555 0.116 0.685 0.555
DIM.
OUTLINE AND MECHANICAL DATA
(1): "D1" and "E1" do not include mold flash or protusions - Mold flash or protusions shall not exceed 0.15mm(0.006inch) per side
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ESD - The STMicroelectronics Internal Quality Standards set a target of 2KV that each pin of the device should withstand in a series of tests based on the Human Body Model (MIL-STD 883 Method 3015): with C = 100pF; R = 1500 and performing 3 pulses for each pin versus V CC and GND. Device characterization showed that, in front of the STMicroelectronics Internaly Quality Standards, all pins of STLC5445 withstand at least 1500V. The above points are not expected to represent a pratical limit for the correct device utilization nor for its reliability in the field. Nonetheless they must be mentionned in connection with the applicability of the different SURE 8 requirements to STLC5445.
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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