PSD835G2
Flash PSD, 5 V supply, for 8-bit MCUs 4 Mbit + 256 Kbit Dual Flash memories and 64 Kbit SRAM
Features
Flash in-system programmable (ISP) peripheral for 8-bit MCUs dual bank flash memories 4 Mbits of Primary Flash memory (8 uniform sectors, 64 Kbyte) 256 Kbits of Secondary Flash memory with 4 sectors Concurrent operation: READ from one memory while erasing and writing the other 64 Kbit of battery-backed SRAM 52 reconfigurable I/O ports Enhanced JTAG serial port PLD with macrocells Over 3000 gates of PLD: CPLD and DPLD CPLD with 16 Output macrocells (OMCs) and 24 Input macrocells (IMCs) DPLD - user defined internal chip select decoding 52 individually configurable I/O port pins They can be used for the following functions: MCU I/Os PLD I/Os Latched MCU address output Special function I/Os. I/O ports may be configured as open-drain outputs. In-system programming (ISP) with JTAG Built-in JTAG compliant serial port allows full-chip in-system programmability Efficient manufacturing allow easy product testing and programming Use low cost FlashLINK cable with PC Page Register Internal page register that can be used to expand the microcontroller address space by a factor of 256
TQFP80 (U)
Programmable power management High endurance: 100 000 Erase/WRITE cycles of Flash memory 1 000 Erase/WRITE cycles of PLD 15 year data retention 5 V10% single supply voltage Standby current as low as 50 A Memory speed 70 ns Flash memory and SRAM access time for VCC = 4.5 V to 5.5 V 90 ns Flash memory and SRAM access time for VCC = 4.5 V to 5.5 V ECOPACK packages
April 2007
Rev 4
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www.st.com 1
Contents
PSD835G2
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1 In-system programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1.1 1.1.2 1.1.3 First time programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Inventory build-up of pre-programmed devices . . . . . . . . . . . . . . . . . . . 11 Expensive sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2
In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2.1 1.2.2 1.2.3 Simultaneous READ and WRITE to Flash memory . . . . . . . . . . . . . . . . 12 Complex memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Separate Program and Data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3
PSDsoft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2
PSD architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 JTAG port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 In-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 In-application re-programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power management unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3 4 5 6
Development system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PSD register description and address offset . . . . . . . . . . . . . . . . . . . . 23 Register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Detailed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1 6.2 6.3 6.4 Memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Primar y Flash memory and Secondary Flash memory description . . . . . 30 Memory Block Select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Upper and lower block IN MAIN FLASH SECTOR . . . . . . . . . . . . . . . . . . 30
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6.5 6.6
Ready/Busy (PE4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Memory operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 Power-up mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Read Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Read Primary Flash Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Read Memory Sector Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Read the Erase/Program Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Data polling flag (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Toggle flag (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Error flag (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Erase time-out flag (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8
Programming Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.1 8.2 8.3 Data polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Data toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Unlock Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9
Erasing Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.1 9.2 9.3 9.4 Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Flash Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10
Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.1 10.2 10.3 Flash memory Sector Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Reset Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Reset (RESET) signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
11 12
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Sector Select and SRAM Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12.1 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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12.2 12.3
Memory Select configuration for MCUs with separate program and data spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Configuration modes for MCUs with separate program and data spaces 46
12.3.1 12.3.2 Separate space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Combined space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
13 14 15
Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Memory ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 15.9 The Turbo bit in PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Output macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Product term allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Loading and reading the output macrocells (OMC) . . . . . . . . . . . . . . . . . 56 The OMC Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
15.10 External chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
16
MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
16.1 16.2 16.3 16.4 16.5 16.6 16.7 PSD interface to a multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . . . . . 62 PSD Interface to a non-multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . 63 MCU bus interface examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 80C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
17
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
17.1 17.2 17.3 General port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Por t operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 MCU I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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17.4 17.5 17.6 17.7 17.8 17.9
PLD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Address Out mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Address In mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Data Port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 JTAG in-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
17.10 Por t Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 17.11 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 17.12 Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 17.13 Drive Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 17.14 Por t Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 17.15 Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 17.16 Data Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 17.17 Output macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 17.18 OMC Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 17.19 Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 17.20 Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 17.21 Por ts A, B and C functionality and structure . . . . . . . . . . . . . . . . . . . . . 80 17.22 Por t D functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 17.23 Por t E functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 17.24 Por t F functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 17.25 Por t G functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
18
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
18.1 18.2 18.3 18.4 18.5 18.6 Automatic Power-down (APD) unit and Power-down mode . . . . . . . . . . . 85
18.1.1 Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Other power saving options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 PLD power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
18.3.1 SRAM Standby mode (battery backup) . . . . . . . . . . . . . . . . . . . . . . . . . 87
PSD Chip Select input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Input control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
19
Reset timing and device status at reset . . . . . . . . . . . . . . . . . . . . . . . . 89
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19.1 19.2 19.3 19.4
Power-Up reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Warm reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 I/O Pin, Register and PLD status at reset . . . . . . . . . . . . . . . . . . . . . . . . 89 Reset of Flash memory Erase and Program cycles . . . . . . . . . . . . . . . . . 89
20
Programming in-circuit using the JTAG/ISP interface . . . . . . . . . . . . . 91
20.1 20.2 20.3 Standard JTAG signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 JTAG extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Security and Flash memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
21 22 23 24 25
AC/DC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Appendix A Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
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List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PLD I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 JTAG signals on port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Methods of programming different functional blocks of the PSD . . . . . . . . . . . . . . . . . . . . 21 Register address offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Data-In Registers Ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Data-Out Registers Ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Direction Registers Ports A, B, C, D, E, F, G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Control Registers Ports E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Drive Registers Ports A, B, D, E, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Drive Registers Ports C, F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Enable-Out Registers Ports A, B, C, F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Input Macrocells Ports A, B, C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Output Macrocells A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Output Macrocells B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Mask Macrocells A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Mask Macrocells B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Flash Memory Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Flash Boot Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 JTAG Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PMMR0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PMMR2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 VM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Memory_ID0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Memory_ID1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Memory block size and organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DPLD and CPLD inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Output macrocell port and data bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 MCUs and their control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 80C251 configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Interfacing the PSD with the 80C251, with One READ Input . . . . . . . . . . . . . . . . . . . . . . . 67 Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Port operating mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 I/O port latched address output assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Port pin direction control, Output Enable P.T. not defined . . . . . . . . . . . . . . . . . . . . . . . . . 77 Port pin direction control, Output Enable P.T. defined . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Port direction assignment example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Drive Register pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Power-down mode's effect on ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 PSD timing and Standby current during Power-down mode. . . . . . . . . . . . . . . . . . . . . . . . 86 APD counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Status during Power-Up reset, warm reset and Power-down mode . . . . . . . . . . . . . . . . . . 90 JTAG port signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
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List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74.
PSD835G2
Example of PSD typical power calculation at VCC = 5.0 V (with Turbo mode On) . . . . . . . 94 Example of PSD typical power calculation at VCC = 5.0 V (with Turbo mode off) . . . . . . . 95 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 AC signal letters for PLD timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 AC signal behavior symbols for PLD timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 CPLD combinatorial timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 CPLD macrocell synchronous clock mode timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 CPLD macrocell asynchronous clock mode timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Input macrocell timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 READ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 WRITE timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Port F peripheral data mode read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Port F peripheral data mode Write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Program, Write and Erase times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Power-down timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Reset (RESET) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 VSTBYON timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 ISC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 TQFP80 - 80 lead Thin, Quad, Flat package mechanical data. . . . . . . . . . . . . . . . . . . . . 114 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 PSD835G2 TQFP80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
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PSD835G2
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. TQFP80 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PSD block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PSDsoft development tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Example for Flash Sector Chip Select FS0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Selecting the upper or lower block in a Primary Flash memory sector . . . . . . . . . . . . . . . . 31 Data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Data toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Priority level of memory and I/O components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8031 memory modules separate space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8031 memory modules combined space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 PLD diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 DPLD logic array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Macrocell and I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 CPLD output macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Input macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Handshaking communication using input macrocells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 An example of a typical 8-bit multiplexed bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 An example of a typical 8-bit non-multiplexed bus interface. . . . . . . . . . . . . . . . . . . . . . . . 64 Interfacing the PSD with an 80C31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Interfacing the PSD with the 80C251, with RD and PSEN inputs. . . . . . . . . . . . . . . . . . . . 68 Interfacing the PSD with the 80C51X, 8-bit data bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Interfacing the PSD with a 68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 General I/O port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Port A, B and C structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Port D structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Port E, F, G structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 APD unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Enable Power-down flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Power-Up and warm reset (RESET) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 PLD ICC /frequency consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Switching waveforms key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Input to Output Disable / Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Combinatorial timing PLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Synchronous clock mode timing PLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Asynchronous Reset / Preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Asynchronous Clock mode timing (product term clock) . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Input macrocell timing (product term clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 READ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 WRITE timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Peripheral I/O Read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Peripheral I/O Write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Reset (RESET) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 ISC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
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List of figures Figure 49.
PSD835G2
TQFP80 - 80 lead Thin, Quad, Flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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PSD835G2
Description
1
Description
The PSD family of memory systems for microcontrollers (MCUs) brings In-SystemProgrammability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications. The CPLD in the PSD devices features an optimized macrocell logic architecture. The PSD macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices. The PSD family offers two methods to program the PSD Flash memory while the PSD is soldered to the circuit board: In-System Programming (ISP) via JTAG, and In-Application Programming (IAP).
1.1
In-system programming (ISP) via JTAG
An IEEE 1149.1 compliant JTAG In-System Programming (ISP) interface is included on the PSD enabling the entire device (Flash memories, PLD, configuration) to be rapidly programmed while soldered to the circuit board. This requires no MCU participation, which means the PSD can be programmed anytime, even when completely blank. The innovative JTAG interface to Flash memories is an industry first, solving key problems faced by designers and manufacturing houses, such as:
1.1.1
First time programming
How do I get firmware into the Flash memory the very first time? JTAG is the answer. Program the blank PSD with no MCU involvement.
1.1.2
Inventory build-up of pre-programmed devices
How do I maintain an accurate count of pre-programmed Flash memory and PLD devices based on customer demand? How many and what version? JTAG is the answer. Build your hardware with blank PSDs soldered directly to the board and then custom program just before they are shipped to the customer. No more labels on chips, and no more wasted inventory.
1.1.3
Expensive sockets
How do I eliminate the need for expensive and unreliable sockets? JTAG is the answer. Solder the PSD directly to the circuit board. Program first time and subsequent times with JTAG. No need to handle devices and bend the fragile leads.
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Description
PSD835G2
1.2
In-application programming (IAP)
Two independent Flash memory arrays are included so that the MCU can execute code from one while erasing and programming the other. Robust product firmware updates in the field are possible over any communications channel (CAN, Ethernet, UART, J1850, etc.) using this unique architecture. Designers are relieved of these problems:
1.2.1
Simultaneous READ and WRITE to Flash memory
How can the MCU program the same memory from which it is executing code? It cannot. The PSD allows the MCU to operate the two Flash memory blocks concurrently, reading code from one while erasing and programming the other during IAP.
1.2.2
Complex memory mapping
How can I map these two memories efficiently? A programmable Decode PLD (DPLD) is embedded in the PSD. The concurrent PSD memories can be mapped anywhere in MCU address space, segment by segment with extremely high address resolution. As an option, the secondary Flash memory can be swapped out of the system memory map when IAP is complete. A built-in page register breaks the MCU address limit.
1.2.3
Separate Program and Data space
How can I write to Flash memory while it resides in Program space during field firmware updates? My 80C51 will not allow it. The PSD provides means to reclassify Flash memory as Data space during IAP, then back to Program space when complete.
1.3
PSDsoft
PSDsoft, a software development tool from ST, guides you through the design process stepby-step making it possible to complete an embedded MCU design capable of ISP/IAP in just hours. Select your MCU and PSDsoft takes you through the remainder of the design with point and click entry, covering PSD selection, pin definitions, programmable logic inputs and outputs, MCU memory map definition, ANSI-C code generation for your MCU, and merging your MCU firmware with the PSD design. When complete, two different device programmers are supported directly from PSDsoft: FlashLINK (JTAG) and PSDpro.
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PSD835G2 Figure 1. TQFP80 connections
Description
70 GND
69 VCC
80 PD1
79 PD0
68 PB7
67 PB6
66 PB5
65 PB4
64 PB3
63 PB2
62 PB1
PD2 1 PD3 2 AD0 3 AD1 4 AD2 5 AD3 6 AD4 7 GND 8 VCC 9 AD5 10 AD6 11 AD7 12 AD8 13 AD9 14 AD10 15 AD11 16 AD12 17 AD13 18 AD14 19 AD15 20
61 PB0
78 PE7
77 PE6
76 PE5
75 PE4
74 PE3
73 PE2
72 PE1
71 PE0
60 CNTL1 59 CNTL0 58 PA7 57 PA6 56 PA5 55 PA4 54 PA3 53 PA2 52 PA1 51 PA0 50 GND 49 GND 48 PC7 47 PC6 46 PC5 45 PC4 44 PC3 43 PC2 42 PC1 41 PC0
PG0 21
PG1 22
PG2 23
PG3 24
PG4 25
PG5 26
PG6 27
PG7 28
VCC 29
GND 30
PF0 31
PF1 32
PF2 33
PF3 34
PF4 35
PF5 36
PF6 37
PF7 38
RESET 39
CNTL2 40
AI04943
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Description Table 1.
Pin name
PSD835G2 Pin description
Pin Type Description This is the lower Address/Data port. Connect your MCU address or address/data bus according to the following rules: If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect AD0-AD7 to this port. If your MCU does not have a multiplexed address/data bus, connect A0-A7 to this port. If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this port. ALE or AS latches the address. The PSD drives data out only if the READ signal is active and one of the PSD functional blocks was selected. The addresses on this port are passed to the PLDs. This is the upper Address/Data port. Connect your MCU address or address/data bus according to the following rules: If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect A8-A15 to this port. If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this port. If you are using an 80C251 in page mode, connect AD8-AD15 to this port. If you are using an 80C51XA in burst mode, connect A12-A19 to this port. ALE or AS latches the address. The PSD drives data out only if the READ signal is active and one of the PSD functional blocks was selected. The addresses on this port are passed to the PLDs. The following control signals can be connected to this port, based on your MCU: WR active Low Write Strobe input. R_W active High READ/active Low WRITE input. This port is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. The following control signals can be connected to this port, based on your MCU: RD active Low Read Strobe input. E E clock input. DS active Low Data Strobe input. PSEN connect PSEN to this port when it is being used as an active Low READ signal. For example, when the 80C251 outputs more than 16 address bits, PSEN is actually the READ signal. This port is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. This port can be used to input the PSEN (Program Select Enable) signal from any MCU that uses this signal for code exclusively. If your MCU does not output a Program Select Enable signal, this port can be used as a generic input. This port is connected to the PLDs as input. Active Low input. Resets I/O Ports, PLD macrocells and some of the Configuration Registers and JTAG registers. Must be Low at Power-up. Reset also aborts the Flash programming/erase cycle that is in progress.
ADIO0-7
3-7-1012
I/O
ADIO8-15
13-20
I/O
CNTL0
59
I
CNTL1
60
I
CNTL2
40
I
Reset
39
I
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PSD835G2 Table 1.
Pin name PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
Description Pin description (continued)
Pin 58 57 56 55 54 53 52 51 68 67 66 65 64 63 62 61 48 47 46 45 44 43 42 41 Type Description
These pins make up Port A. These port pins are configurable and can have the following functions: I/O CMOS MCU I/O write to or read from a standard output or input port. or Open CPLD macrocell (McellA0-7) outputs. Drain Inputs to the PLDs. Latched, transparent or registered PLD input.
These pins make up Port B. These port pins are configurable and can have the following functions: I/O CMOS MCU I/O write to or read from a standard output or input port. or Open CPLD macrocell (McellB0-7) output. Drain Inputs to the PLDs. Latched, transparent or registered PLD input.
These pins make up Port C. These port pins are configurable and can have the I/O following functions: CMOS MCU I/O write to or read from a standard output or input port. or Open Drain External Chip Select (ECS0-7) output. Latched, transparent or registered PLD input.
PD0
79
PD0 pin of Port D. This port pin can be configured to have the following functions: I/O ALE/AS input latches addresses on ADIO0-ADIO15 pins. CMOS AS input latches addresses on ADIO0-ADIO15 pins on the rising edge. or Open Drain Input to the PLDs. Transparent PLD input. PD1 pin of Port D. This port pin can be configured to have the following functions: I/O MCU I/O write to or read from a standard output or input port. CMOS or Open Input to the PLDs. Drain CLKIN clock input to the CPLD macrocells, the APD Unit's Power-down counter, and the CPLD AND Array. PD2 pin of Port D. This port pin can be configured to have the following functions: MCU I/O write to or read from a standard output or input port. I/O CMOS Input to the PLDs. or Open PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory Drain and I/O. When High, the PSD memory blocks are disabled to conserve power. The trailing edge of CSI can be used to get the PSD out of power-down mode. I/O PD3 pin of Port D. This port pin can be configured to have the following functions: CMOS MCU I/O write to or read from a standard output or input port. or Open Drain Input to the PLDs.
PD1
80
PD2
1
PD3
2
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Description Table 1.
Pin name
PSD835G2 Pin description (continued)
Pin Type I/O CMOS or Open Drain I/O CMOS or Open Drain I/O CMOS or Open Drain I/O CMOS or Open Drain Description PE0 pin of Port E. This port pin can be configured to have the following functions: MCU I/O write to or read from a standard output or input port. Latched address output. TMS input for JTAG/ISP interface. PE1 pin of Port E. This port pin can be configured to have the following functions: MCU I/O write to or read from a standard output or input port. Latched address output. TCK input for JTAG/ISP interface (Schmidt Trigger). PE2 pin of Port E. This port pin can be configured to have the following functions: MCU I/O write to or read from a standard output or input port. Latched address output. TDI input for JTAG/ISP interface. PE3 pin of Port E. This port pin can be configured to have the following functions: MCU I/O write to or read from a standard output or input port. Latched address output. TDO input for JTAG/ISP interface.
PE0
71
PE1
72
PE2
73
PE3
74
PE4
75
PE4 pin of Port E. This port pin can be configured to have the following functions: I/O MCU I/O write to or read from a standard output or input port. CMOS Latched address output. or Open Drain TSTAT input for the ISP interface. Ready/Busy for in-circuit Parallel Programming. I/O CMOS or Open Drain I/O CMOS or Open Drain PE5 pin of Port E. This port pin can be configured to have the following functions: MCU I/O write to or read from a standard output or input port. Latched address output. TERR active Low input for ISP interface. PE6 pin of Port E. This port pin can be configured to have the following functions: MCU I/O write to or read from a standard output or input port. Latched address output. VSTBY SRAM standby voltage input for battery backup SRAM.
PE5
76
PE6
77
PE7
78
PE7 pin of Port E. This port pin can be configured to have the following functions: I/O MCU I/O write to or read from a standard output or input port. CMOS or Open Latched address output. Drain VBATON battery backup indicator output. Goes High when power is drawn from an external battery. PF0 through PF7 pins of Port F. This port pins can be configured to have the following functions: I/O MCU I/O write to or read from a standard output or input port. CMOS Input to the PLDs. or Open Drain Latched address outputs. As address A0-A3 inputs in 80C51XA mode. As data bus port (D07) in non-multiplexed bus configuration.
PF0-PF7
31-38
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PSD835G2 Table 1.
Pin name
Description Pin description (continued)
Pin Type I/O CMOS or Open Drain Description PG0 through PG7 pins of Port G. This port pins can be configured to have the following functions: MCU I/O write to or read from a standard output or input port. Latched address outputs. Supply Voltage Ground pins
PG0-PG7
8, 30, 49, 50, 70 9, 29, 69 8, 30, 49, 50, 70
VCC GND
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Description
Figure 2.
ADDRESS/ DATA/CONTROL BUS
PLD INPUT BUS PAGE REGISTER EMBEDDED ALGORITHM 8 SECTORS 4 MBIT PRIMARY FLASH MEMORY
CNTL0, CNTL1, CNTL2 SECTOR SELECTS FLASH DECODE PLD (DPLD) 82 SECTOR SELECTS SRAM SELECT PERIP I/O MODE SELECTS ADIO PORT CSIOP RUNTIME CONTROL AND I/O REGISTERS 8 EXT CS TO PORT C OR F 16 OUTPUT MACROCELLS PROG. PORT PORT F CLKIN PORT A & B 24 INPUT MACROCELLS PORT A ,B & C 64 KBIT BATTERY BACKUP SRAM PROG. MCU BUS INTRF. 256 KBIT SECONDARY FLASH MEMORY (BOOT OR DATA) 4 SECTORS
PSD block diagram
POWER MANGMT UNIT
VSTDBY (PE6 )
PROG. PORT
PA0 PA7
AD0 AD15
PORT A
PROG. PORT PORT B
PB0 PB7
82
FLASH ISP CPLD (CPLD)
PF0 PF7
PROG. PORT PORT C
PC0 PC7
MACROCELL FEEDBACK OR PORT INPUT CLKIN
PORT F
PROG. PORT PORT D
PD0 PD2
PG0 PG7 PORT G
PROG. PORT
PROG. PORT GLOBAL CONFIG. & SECURITY PLD, CONFIGURATION & FLASH MEMORY LOADER JTAG SERIAL CHANNEL PORT E
PE0 PE7
CLKIN (PD1)
PSD835G2
AI05793b
PSD835G2
PSD architectural overview
2
PSD architectural overview
PSD devices contain several major functional blocks. Figure 2. on page 18 shows the architecture of the PSD device family. The functions of each block are described briefly in the following sections. Many of the blocks perform multiple functions and are user configurable.
2.1
Memory
Each of the memory blocks is briefly discussed in the following paragraphs. A more detailed discussion can be found in the section entitled Memory blocks on page 29. The 4 Mbit (512K x 8) Flash memory is the primary memory of the PSD. It is divided into 8 equallysized sectors that are individually selectable. The 256 Kbit (32K x 8) secondary Flash memory is divided into 4 equally-sized sectors. Each sector is individually selectable. The 64 Kbit SRAM is intended for use as a scratch-pad memory or as an extension to the MCU SRAM. If an external battery is connected to Voltage Standby (VSTBY, PC2), data is retained in the event of power failure. Each sector of memory can be located in a different address space as defined by the user. The access times for all memory types includes the address latching and DPLD decoding time.
2.2
Page Register
The 8-bit Page Register expands the address range of the MCU by up to 256 times. The paged address can be used as part of the address space to access external memory and peripherals, or internal memory and I/O. The Page Register can also be used to change the address mapping of sectors of the Flash memories into different memory spaces for IAP.
2.3
PLDs
The device contains two PLDs, the Decode PLD (DPLD) and the Complex PLD (CPLD), as shown in Table 2, each optimized for a different function. The functional partitioning of the PLDs reduces power consumption, optimizes cost/performance, and eases design entry. The DPLD is used to decode addresses and to generate Sector Select signals for the PSD internal memory and registers. The CPLD can implement user-defined logic functions. The DPLD has combinatorial outputs. The CPLD has 16 Output Macrocells (OMC) and 8 combinatorial outputs. The PSD also has 24 Input Macrocells (IMC) that can be configured as inputs to the PLDs. The PLDs receive their inputs from the PLD Input Bus and are differentiated by their output destinations, number of product terms, and macrocells. The PLDs consume minimal power by using Power-Management design techniques. The speed and power consumption of the PLD is controlled by the Turbo Bit in PMMR0 and other bits in the PMMR2. These registers are set by the MCU at run-time. There is a slight penalty to PLD propagation time when invoking the power management features.
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PSD architectural overview
PSD835G2
2.4
I/O ports
The PSD has 52 I/O pins distributed over the seven ports (Port A, B, C, D, E, F and G). Each I/O pin can be individually configured for different functions. Ports can be configured as standard MCU I/O ports, PLD I/O, or latched address outputs for MCUs using multiplexed address/data buses. The JTAG pins can be enabled on Port E for In-System Programming (ISP). Ports F and G can also be configured as data ports for a non-multiplexed bus. Por ts A and B can also be configured as a data port for a non-multiplexed bus.
2.5
MCU bus interface
PSD interfaces easily with most 8-bit MCUs that have either multiplexed or non-multiplexed address/data buses. The device is configured to respond to the MCU's control signals, which are also used as inputs to the PLDs. For examples, please see MCU bus interface examples on page 63. Table 2. PLD I/O
Name Decode PLD (DPLD) Complex PLD (CPLD) Inputs 82 82 Outputs 17 24 Product Terms 43 150
Table 3.
JTAG signals on port E
Port E pins PE0 PE1 PE2 PE3 PE4 PE5 TMS TCK TDI TDO TSTAT TERR JTAG signal
2.6
JTAG port
In-System Programming (ISP) can be performed through the JTAG signals on Port E. This serial interface allows complete programming of the entire PSD device. A blank device can be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can be multiplexed with other functions on Port E. Table 3. on page 20 indicates the JTAG pin assignments.
2.7
In-system programming (ISP)
Using the JTAG signals on Port E, the entire PSD device (memory, logic, configuration) can be programmed or erased without the use of the MCU.
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PSD835G2
PSD architectural overview
2.8
In-application re-programming (IAP)
The primary Flash memory can also be programmed in-system by the MCU executing the programming algorithms out of the secondary memory, or SRAM. Since this is a sizable separate block, the application can also continue to operate. The secondary memory can be programmed the same way by executing out of the primary Flash memory. The PLD or other PSD Configuration blocks can be programmed through the JTAG port or a device programmer. Table 4 indicates which programming methods can program different functional blocks of the PSD.
2.9
Power management unit (PMU)
The Power Management Unit (PMU) gives the user control of the power consumption on selected functional blocks based on system requirements. The PMU includes an Automatic Power-down (APD) Unit that turns off device functions during MCU inactivity. The APD Unit has a Power-down mode that helps reduce power consumption. The PSD also has some bits that are configured at run-time by the MCU to reduce power consumption of the CPLD. The Turbo Bit in PMMR0 can be reset to '0' and the CPLD latches its outputs and goes to sleep until the next transition on its inputs. Additionally, bits in PMMR2 can be set by the MCU to block signals from entering the CPLD to reduce power consumption. Please see Power management on page 84 for more details. Table 4. Methods of programming different functional blocks of the PSD
Functional Block Primar y Flash memory Secondary Flash memory PLD Array (DPLD and CPLD) PSD configuration Yes Yes Yes Yes JTAG/ISP Device programmer Yes Yes Yes Yes Yes Yes No No IAP
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Development system
PSD835G2
3
Development system
The PSD family is supported by PSDsoft, a Windows-based (95, 98, NT) software development tool. A PSD design is quickly and easily produced in a point-and-click environment. The designer does not need to enter Hardware Description Language (HDL) equations, unless desired, to define PSD pin functions and memory map information. The general design flow is shown in Figure 3. PSDsoft is available from our web site (the address is given on the back page of this data sheet) or other distribution channels. PSDsoft directly supports two low cost device programmers form ST: PSDpro and FlashLINK (JTAG). Both of these programmers may be purchased through your local distributor/representative, or directly from our web site using a credit card. The PSD is also supported by third party device programmers. See our web site for the current list. Figure 3. PSDsoft development tool
Choose MCU and PSD
Automatically Configures MCU bus interface and other PSD attributes.
Define PSD Pin and Node Functions
Point-and-click definition of PSD pin functions, internal nodes and MCU system memory map
Define General Purpose Logic in CPLD
Point-and-click definition of combinatorial and registered logic in CPLD. Access to HDL is available if needed.
C Code Generation
GENERATE C CODE SPECIFIC TO PSD FUNCTIONS
Merge MCU Firmware with PSD Configuration
A composite object file is created containing MCU firmware and PSD configuration
MCU FIRMWARE HEX OR S-RECORD FORMAT
USER'S CHOICE OF MICROCONTROLLER COMPILER/LINKER
*.OBJ FILE
ST PSD Programmer
PSDPro, or FlashLINK (JTAG)
*.OBJ FILE AVAILABLE FOR 3rd PARTY PROGRAMMERS (CONVENTIONAL or JTAG/ISP)
AI04918b
22/118
PSD835G2
PSD register description and address offset
4
PSD register description and address offset
Table 5 shows the offset addresses to the PSD registers relative to the CSIOP base address. The CSIOP space is the 256 Bytes of address that is allocated by the user to the internal PSD registers. Table 5 provides brief descriptions of the registers in CSIOP space. The following section gives a more detailed description. Table 5.
Register name Data In Control Data Out Direction 04 06 05 07 14 14 15 15
Register address offset
Port Port Port Port Port Port Port Other(1) A B C D E F G 00 01 10 11 30 32 34 36 40 42 44 46 41 43 45 47 Description Reads Port pin as input, MCU I/O input mode Selects mode between MCU I/O or Address Out Stores data for output to Port pins, MCU I/O output mode Configures Port pin as input or output Configures Port pins as either CMOS or Open Drain on some pins, while selecting high slew rate on other pins. Reads Input Macrocells 4C Reads the status of the output enable to the I/O Port driver READ reads output of macrocells A WRITE loads macrocell flipflops READ reads output of macrocells B WRITE loads macrocell flipflops Blocks writing to the Output Macrocells A 23 Blocks writing to the Output Macrocells B C0 Read only Primary Flash Sector Protection Read only PSD Security and Secondary Flash memory Sector Protection Enables JTAG Port
Drive Select
08
09
18
19
38
48
49
Input macrocell Enable Out
0A 0C
0B 0D 1C
1A 1B
Output macrocells A
20
Output macrocells B Mask macrocells A Mask macrocells B Primar y Flash Protection Secondar y Flash memory Protection JTAG Enable
21
22
C2
C7
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PSD register description and address offset Table 5.
Register name PMMR0 PMMR2 Page VM
PSD835G2
Register address offset (continued)
Port Port Port Port Port Port Port Other(1) A B C D E F G B0 B4 E0 E2 Description Power Management Register 0 Power Management Register 2 Page Register Places PSD memory areas in Program and/or Data space on an individual basis. Read only Primary Flash memory and SRAM size Read only Secondary Flash memory type and size
Memory_ID0 Memory_ID1
1. Other registers that are not part of the I/O ports.
F0 F1
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PSD835G2
Register bit definition
5
Register bit definition
All the registers of the PSD are included here, for reference. Detailed descriptions of these registers can be found in the following sections. Table 6.
Bit 7 Por t pin 7
Data-In Registers Ports A, B, C, D, E, F, G(1)
Bit 6 Por t pin 6 Bit 5 Por t pin 5 Bit 4 Por t pin 4 Bit 3 Por t pin 3 Bit 2 Por t pin 2 Bit 1 Por t pin 1 Bit 0 Por t pin 0
1. Bit Definitions (Read only registers): Read Port pin status when Port is in MCU I/O input mode.
Table 7.
Bit 7 Por t pin 7
Data-Out Registers Ports A, B, C, D, E, F, G(1)
Bit 6 Por t pin 6 Bit 5 Por t pin 5 Bit 4 Por t pin 4 Bit 3 Por t pin 3 Bit 2 Por t pin 2 Bit 1 Por t pin 1 Bit 0 Por t pin 0
1. Bit Definitions: Latched data for output to Port pin when pin is configured in MCU I/O output mode.
Table 8.
Bit 7 Por t pin 7
Direction Registers Ports A, B, C, D, E, F, G(1)
Bit 6 Por t pin 6 Bit 5 Por t pin 5 Bit 4 Por t pin 4 Bit 3 Por t pin 3 Bit 2 Por t pin 2 Bit 1 Por t pin 1 Bit 0 Por t pin 0
1. Bit Definitions: Port pin 0 = Port pin is configured in Input mode (default). Port pin 1 = Port pin is configured in Output mode.
Table 9.
Bit 7 Por t pin 7
Control Registers Ports E, F, G(1)
Bit 6 Por t pin 6 Bit 5 Por t pin 5 Bit 4 Por t pin 4 Bit 3 Por t pin 3 Bit 2 Por t pin 2 Bit 1 Por t pin 1 Bit 0 Por t pin 0
1. Bit Definitions: Port pin 0 = Port pin is configured in MCU I/O mode (default). Port pin 1 = Port pin is configured in Latched Address Out mode.
Table 10.
Bit 7 Por t pin 7
Drive Registers Ports A, B, D, E, G(1)
Bit 6 Por t pin 6 Bit 5 Por t pin 5 Bit 4 Por t pin 4 Bit 3 Por t pin 3 Bit 2 Por t pin 2 Bit 1 Por t pin 1 Bit 0 Por t pin 0
1. Bit Definitions: Port pin 0 = Port pin is configured for CMOS Output driver (default). Port pin 1 = Port pin is configured for Open Drain output driver.
Table 11.
Bit 7 Por t pin 7
Drive Registers Ports C, F(1)
Bit 6 Por t pin 6 Bit 5 Por t pin 5 Bit 4 Por t pin 4 Bit 3 Por t pin 3 Bit 2 Por t pin 2 Bit 1 Por t pin 1 Bit 0 Por t pin 0
1. Bit Definitions: Port pin 0 = Port pin is configured for CMOS Output driver (default). Port pin 1 = Port pin is configured in Slew Rate mode.
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Register bit definition Table 12.
Bit 7 Por t pin 7
PSD835G2 Enable-Out Registers Ports A, B, C, F(1)
Bit 6 Por t pin 6 Bit 5 Por t pin 5 Bit 4 Por t pin 4 Bit 3 Por t pin 3 Bit 2 Por t pin 2 Bit 1 Por t pin 1 Bit 0 Por t pin 0
1. Bit Definitions (Read only registers): Port pin 0 = Port pin is in tri-state driver (default). Port pin 1 = Port pin is enabled.
Table 13.
Bit 7 IMcell 7
Input Macrocells Ports A, B, C(1)
Bit 6 IMcell 6 Bit 5 IMcell 5 Bit 4 IMcell 4 Bit 3 IMcell 3 Bit 2 IMcell 2 Bit 1 IMcell 1 Bit 0 IMcell 0
1. Bit Definitions (Read only registers): Read Input Macrocell (IMC7-IMC0) status on Ports A, B and C.
Table 14.
Bit 7 Mcella 7
Output Macrocells A Register(1)
Bit 6 Mcella 6 Bit 5 Mcella 5 Bit 4 Mcella 4 Bit 3 Mcella 3 Bit 2 Mcella 2 Bit 1 Mcella 1 Bit 0 Mcella 0
1. Bit Definitions: Write Register: Load MCellA7-MCellA0 with '0' or '1.' Read Register: Read MCellA7-MCellA0 output status.
Table 15.
Bit 7 Mcellb 7
Output Macrocells B Register(1)
Bit 6 Mcellb 6 Bit 5 Mcellb 5 Bit 4 Mcellb 4 Bit 3 Mcellb 3 Bit 2 Mcellb 2 Bit 1 Mcellb 1 Bit 0 Mcellb 0
1. Bit Definitions: Write Register: Load MCellB7-MCellB0 with '0' or '1.' Read Register: Read MCellB7-MCellB0 output status.
Table 16.
Bit 7 Mcella 7
Mask Macrocells A Register(1)
Bit 6 Mcella 6 Bit 5 Mcella 5 Bit 4 Mcella 4 Bit 3 Mcella 3 Bit 2 Mcella 2 Bit 1 Mcella 1 Bit 0 Mcella 0
1. Bit Definitions: McellA_Prot 0 = Allow MCellA flip-flop to be loaded by MCU (default). McellA_Prot 1 = Prevent MCellA flip-flop from being loaded by MCU.
Table 17.
Bit 7 Mcellb 7
Mask Macrocells B Register(1)
Bit 6 Mcellb 6 Bit 5 Mcellb 5 Bit 4 Mcellb 4 Bit 3 Mcellb 3 Bit 2 Mcellb 2 Bit 1 Mcellb 1 Bit 0 Mcellb 0
1. Bit Definitions: McellB_Prot 0 = Allow MCellB flip-flop to be loaded by MCU (default). McellB_Prot 1 = Prevent MCellB flip-flop from being loaded by MCU.
Table 18.
Bit 7
Flash Memory Protection Register(1)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
1. Bit Definitions (Read only register): Sec_Prot 1 = Primary Flash memory Sector is write protected. Sec_Prot 0 = Primary Flash memory Sector is not write protected.
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PSD835G2 Table 19.
Bit 7
Register bit definition Flash Boot Protection Register(1)
Bit 6 Bit 5 not used Bit 4 not used Bit 3 Bit 2 Bit 1 Bit 0 Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
Security_Bit not used
1. Bit Definitions: Sec_Prot 1 = Secondary Flash memory Sector is write protected. Sec_Prot 0 = Secondary Flash memory Sector is not write protected. Security_Bit 0 = Security Bit in device has not been set. Security_Bit 1 = Security Bit in device has been set.
Table 20.
Bit 7 not used
JTAG Enable Register(1)
Bit 6 not used Bit 5 not used Bit 4 not used Bit 3 not used Bit 2 not used Bit 1 not used Bit 0 JTAGEnable
1. Bit Definitions: JTAG_Enable 1 = JTAG Port is enabled. JTAG_Enable 0 = JTAG Port is disabled.
Table 21.
Bit 7 PGR 7
Page Register(1)
Bit 6 PGR 6 Bit 5 PGR 5 Bit 4 PGR 4 Bit 3 PGR 3 Bit 2 PGR 2 Bit 1 PGR 1 Bit 0 PGR 0
1. Bit Definitions: Configure Page input to PLD. Default is PGR7-PGR0=00.
Table 22.
Bit 7
PMMR0 Register(1) (2)
Bit 6 Bit 5 Bit 4 PLD Array CLK Bit 3 PLD Turbo Bit 2 Bit 1 Bit 0 not used (set to '0')
PLD not used not used MCells (set to '0') (set to '0') CLK
not used APD (set to '0') Enable
1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the registers. 2. Bit Definitions: APD Enable0 = Automatic Power-down (APD) is disabled. 1 = Automatic Power-down (APD) is enabled. PLD Turbo0 = PLD Turbo is on. 1 = PLD Turbo is off, saving power. PLD Array CLK0 = CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo Bit is off. 1 = CLKIN to the PLD AND array is disconnected, saving power. PLD MCells CLK0 = CLKIN to the PLD Macrocells is connected. 1 = CLKIN to the PLD Macrocells is disconnected, saving power.
Table 23.
Bit 7 not used (set to '0')
PMMR2 Register(1)
Bit 6 PLD Array WRH Bit 5 PLD Array ALE Bit 4 PLD Array CNTL2 Bit 3 PLD Array CNTL1 Bit 2 PLD Array CNTL0 Bit 1 not used (set to '0') Bit 0 PLD Array Addr
1. Bit Definitions: PLD Array Addr0 = Address A7-A0 are connected to the PLD array. 1 = Address A7-A0 are blocked from the PLD array, saving power. (Note: in XA mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7-ADIO4) PLD Array CNTL20 = CNTL2 input to the PLD AND array is connected. 1 = CNTL2 input to the PLD AND array is disconnected, saving power. PLD Array CNTL10 = CNTL1 input to the PLD AND array is connected. 1 = CNTL1 input to the PLD AND array is disconnected, saving power. PLD Array CNTL00 = CNTL0 input to the PLD AND array is connected. 1 = CNTL0 input to the PLD AND array is disconnected, saving power. PLD Array ALE0 = ALE input to the PLD AND array is connected. 1 = ALE input to the PLD AND array is disconnected, saving power. PLD Array WRH0 = WRH/DBE input to the PLD AND array is connected. 1 = WRH/DBE input to the PLD AND array is disconnected, saving power.
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Register bit definition Table 24.
Bit 7
PSD835G2 VM Register(1) (2)
Bit 6 Bit 5 not used (set to '0') Bit 4 FL_data Bit 3 Bit 2 Bit 1 Boot_code Bit 0 SR_code
Peripheral not used mode (set to '0')
Boot_data FL_code
1. On reset, Bit1-Bit4 are loaded to configurations that are selected by the user in PSDsoft. Bit0 and Bit7 are always cleared on reset. Bit0-Bit4 are active only when the device is configured for the 8031 and compatible MCU families. 2. Bit Definitions: SR_code0 = PSEN cannot access SRAM. 1 = PSEN can access SRAM. Boot_code0 = PSEN cannot access Secondary NVM. 1 = PSEN can access Secondary NVM. FL_code0 = PSEN cannot access Primary Flash memory. 1 = PSEN can access Primary Flash memory. Boot_data0 = RD cannot access Secondary NVM. 1 = RD can access Secondary NVM. FL_data0 = RD cannot access Primary Flash memory. 1 = RD can access Primary Flash memory. Peripheral mode0 = Peripheral mode of Port F is disabled. 1 = Peripheral mode of Port F is enabled.
Table 25.
Bit 7 S_size 3
Memory_ID0 Register(1)
Bit 6 S_size 2 Bit 5 S_size 1 Bit 4 S_size 0 Bit 3 F_size 3 Bit 2 F_size 2 Bit 1 F_size 1 Bit 0 F_size 0
1. Bit Definitions: F_size[3:0]4h = Primary Flash memory size is 4 Mbit 5h = Primary Flash memory size is 8Mbit S_size[3:0]0h = There is no SRAM 1h = SRAM size is 16 Kbit 3h = SRAM size is 64 Kbit
Table 26.
Bit 7 not used (set to '0')
Memory_ID1 Register(1)
Bit 6 not used (set to '0') Bit 5 B_type 1 Bit 4 B_type 0 Bit 3 B_size 3 Bit 2 B_size 2 Bit 1 B_size 1 Bit 0 B_size 0
1. Bit Definitions: B_size[3:0]0h = There is no Secondary NVM 2h = Secondary NVM size is 256 Kbit B_type[1:0]0h = Secondary NVM is Flash memory 1h = Secondary NVM is EEPROM
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PSD835G2
Detailed operation
6
Detailed operation
As shown in Figure 2. on page 18, the PSD consists of six major types of functional blocks:
Memory Blocks PLD Blocks MCU Bus Interface I/O Ports Power Management Unit (PMU) JTAG/ISP Interface
The functions of each block are described in the following sections. Many of the blocks perform multiple functions, and are user configurable.
6.1
Memory blocks
The PSD has the following memory blocks:
Primary Flash memory Secondary Flash memory SRA M
The Memory Select signals for these blocks originate from the Decode PLD (DPLD) and are user-defined in PSDsoft. Table 27. Memory block size and organization
Primary Flash memory Sector number 0 1 2 3 4 5 6 7 Total Secondary Flash memory SRAM
Sector size Sector Sector size Sector SRAM size SRAM Select (bytes) Select signal (bytes) Select signal (bytes) signal 64K 64K 64K 64K 64K 64K 64K 64K 512K FS0 FS1 FS2 FS3 FS4 FS5 FS6 FS7 8 Sectors 32K 4 Sectors 16K 8K 8K 8K 8K CSBOOT0 CSBOOT1 CSBOOT2 CSBOOT3 16K RS0
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Detailed operation
PSD835G2
6.2
Primary Flash memory and Secondary Flash memory description
The primary Flash memory is divided evenly into eight equal sectors. The secondary Flash memory is divided into four equal sectors of eight KBytes each. Each sector of either memory block can be separately protected from Program and Erase cycles. Flash memory may be erased on a sector-by-sector basis and programmed Word-by-Word. Flash sector erasure may be suspended while data is read from other sectors of the block and then resumed after reading. During a Program or Erase cycle in Flash memory, the status can be output on Ready/Busy (PE4). This pin is set up using PSDsoft.
6.3
Memory Block Select signals
The DPLD generates the Select signals for all the internal memory blocks (see PLDs on page 49). Each of the eight sectors of the primary Flash memory has a Select signal (FS0FS7) which can contain up to three product terms. Each of the four sectors of the secondary Flash memory has a Select signal (CSBOOT0-CSBOOT3) which can contain up to three product terms. Having three product terms for each Select signal allows a given sector to be mapped in different areas of system memory. When using an MCU with separate Program and Data space, these flexible Select signals allow dynamic re-mapping of sectors from one memory space to the other before and after IAP.
6.4
Upper and lower block IN MAIN FLASH SECTOR
The PSD835G2's main Flash memory has eight 64-KByte sectors. The 64-KByte sector size may cause some difficulty in code mapping for an 8-bit MCU with only 64-KByte address space. To resolve this mapping issue, the PSD835G2 provides additional logic (see Figure 5. on page 31) for the user to split the 8 sectors such that each sector has a lower and upper 32-KByte block, and the two blocks can reside in different pages but in the same address range. If your design works with 64KB sectors, you don't need to configure this logic. If the design requires 32KB blocks in each sector, you need to define a "FA15" PLD equation in PSDsoft as the A15 address input to the main Flash module. FA15 consists of 3 product terms and will control whether the MCU is accessing the lower or upper 32KB in the selected sector. Figure 4 shows an example for Flash sector chip select FS0. A typical equation is FA15 = pgr4 of the Page Register. When pgr4 is 0 (page 00), the lower 32KB is selected. When pgr4 is switched to '1' by the user, the upper 32KB is selected. PSDsoft will automatically generate the PLD equations shown, based on your point and click selections. If no FA15 equation is defined in PSDsoft, the A15 that comes from the MCU address bus will be routed as input to the primary Flash memory instead of FA15. The FA15 equation has no impact on the Sector Erase operation.
Note:
FA15 affects all eight sectors of the primary Flash memory simultaneously. You cannot direct FA15 to a particular Flash sector only.
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PSD835G2 Figure 4. Example for Flash Sector Chip Select FS0
Detailed operation
page = [pgr7... pgr0]; "Page Register output "Sector Chip Select Equation FS0 = ((0000h <= address <= 7FFFh) & page = 00h) # "select first 32KB block ((0000h <= address <= 7FFFh) & page = 10h); "select second 32KB block FA15 = pgr4; "as address A15 input to the primary Flash memory
ai07652
Figure 5.
Selecting the upper or lower block in a Primary Flash memory sector
FLASH MEMORY CHIP SELECT PINS FS0-FS7
DPLD ARRAY FA15 MUX A15 ADDR A15
PRIMARY FLASH MEMORY SECTOR
NVM CONTROL BIT(1)
A14-A0 ai07653
6.5
Ready/Busy (PE4)
This signal can be used to output the Ready/Busy status of the PSD. The output on Ready/Busy (PE4) is a '0' (Busy) when Flash memory blocks are being written to, or when the Flash memory block is being erased. The output is a '1' (Ready) when no WRITE or Erase cycle is in progress.
6.6
Memory operation
The primary Flash memory and secondary Flash memory are addressed through the MCU Bus Interface. The MCU can access these memories in one of two ways:
The MCU can execute a typical bus WRITE or READ operation just as it would if accessing a RAM or ROM device using standard bus cycles. The MCU can execute a specific instruction that consists of several WRITE and READ operations. This involves writing specific data patterns to special addresses within the Flash memory to invoke an embedded algorithm. These instructions are summarized in Table Table 28. on page 32.
Typically, the MCU can read Flash memory using READ operations, just as it would read a ROM device. However, Flash memory can only be altered using specific Erase and Program instructions. For example, the MCU cannot write a single byte directly to Flash memory as it would write a byte to RAM. To program a byte into Flash memory, the MCU must execute a Program instruction, then test the status of the Program cycle. This status test is achieved by a READ operation or polling Ready/Busy (PE4). Flash memory can also be read by using special instructions to retrieve particular Flash device information (sector protect status and ID).
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Detailed operation Table 28. Instructions(1) (2) (3)
FS0-FS7 or CSBOOT0CSBOOT3(4) 1 1 1 1 1 1 1 1 1 1 1 1 Cycle 1 "Read" RA @ RD AAh@ 555h 55h@ AAAh 90h@ 555h Read identifier @X01h Cycle 2 Cycle 3 Cycle 4
PSD835G2
Instruction Read(5) Read Primary Flash ID(6)(7) Read Sector Protection(6)(8)(7) Program a Flash Byte(13) Flash Sector Erase(9) Flash Bulk Erase Suspend Sector Erase(10) Resume Sector Erase(11) Reset(6) Unlock Bypass Unlock Bypass Program(12) Unlock Bypass Reset(13)
Cycle 5 Cycle 6
Cycle 7
Read identifier AAh@ 555h 55h@ AAAh 90h@ 555h 00h or 01h @X02h AAh@ 555h 55h@ AAAh A0h@ 555h PD@ PA 55h@ AAAh 55h@ AAAh 30h@ SA 10h@ 555h 30h(9)@ next SA
AAh@ 555h 55h@ AAAh 80h@ 555h AAh@ 555h AAh@ 555h 55h@ AAAh 80h@ 555h AAh@ 555h B0h@ XXXh 30h@ XXXh F0h@ any address AAh@ 555h 55h@ AAAh 20h@ 555h A0h@ XXXh 90h@ XXXh PD@ PA 00h@ XXXh
1. All bus cycles are WRITE bus cycles, except the ones with the "Read" label 2. All values are in hexadecimal: X = Don't Care. RA = Address of the memory location to be read RD = Data read from location RA during the READ cycle PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR, CNTL0). PA is an even address for PSD in word programming mode. PD = Data to be programmed at location PA. Data is latched on the rising edge of Write Strobe (WR, CNTL0) SA = Address of the sector to be erased or verified. The Sector Select pins (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector or whole memory to be erased, or verified, must be Active (High). 3. Only address Bits A11-A0 are used in instruction decoding. A15-A12 (or A16-A12) are don't care. 4. Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) signals are active High, and are defined in PSDsoft. 5. No Unlock or instruction cycles are required when the device is in the READ mode 6. The Reset instruction is required to return to the READ mode after reading the Flash ID, or after reading the Sector Protection Status, or if the Error Flag Bit (DQ5/DQ13) goes High. 7. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the Sector Protection Status of the primary Flash memory. 8. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and (A1,A0)=(1,0) 9. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80 s. 10. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle. 11. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode. 12. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction. 13. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass mode.
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PSD835G2
Instructions
7
Instructions
An instruction consists of a sequence of specific operations. Each received Byte is sequentially decoded by the PSD and not executed as a standard WRITE operation. The instruction is executed when the correct number of Bytes is properly received and the time between two consecutive Bytes is shorter than the time-out period. Some instructions are structured to include READ operations after the initial WRITE operations. The instruction must be followed exactly. Any invalid combination of instruction Bytes or time-out between two consecutive bytes while addressing Flash memory resets the device logic into READ mode (Flash memory is read like a ROM device). The PSD supports the instructions summarized in Table 28. on page 32: Flash memory:
Erase memory by chip or sector Suspend or resume sector erase Program a Byte Reset to READ mode Read primary Flash Identifier value Read Sector Protection Status Bypass
These instructions are detailed in Table 28. For efficient decoding of the instructions, the first two Bytes of an instruction are the coded cycles and are followed by an instruction Byte or a confirmation Byte. The coded cycles consist in writing the data AAh to address X555h during the first cycle and data 55h to address XAAAh during the second cycle unless the Bypass Instruction feature is used). Address signals A15-A12 are Don't Care during the instruction WRITE cycles. However, the appropriate Sector Select (FS0-FS7 or CSBOOT0CSBOOT3) must be selected. The primary and secondary Flash memories have the same instruction set (except for Read Primary Flash Identifier). The Sector Select signals determine which Flash memory is to receive and execute the instruction. The primary Flash memory is selected if any one of Sector Select (FS0-FS7) is High, and the secondary Flash memory is selected if any one of Sector Select (CSBOOT0-CSBOOT3) is High.
7.1
Power-up mode
The PSD internal logic is reset upon Power-up to the READ mode. Sector Select (FS0-FS7 and CSBOOT0-CSBOOT3) must be held Low, and Write Strobe (WR, CNTL0) High, during Power-up for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of Write Strobe (WR, CNTL0). Any WRITE cycle initiation is locked when VCC is below VLKO.
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Instructions
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7.2
READ
Under typical conditions, the MCU may read the primary Flash memory or the secondary Flash memory using READ operations just as it would a ROM or RAM device. Alternately, the MCU may use READ operations to obtain status information about a Program or Erase cycle that is currently in progress. Lastly, the MCU may use instructions to read special data from these memory blocks. The following sections describe these READ functions.
7.3
Read Memory Contents
Primar y Flash memory and secondary Flash memory are placed in the READ mode after Power-up, chip reset, or a Reset Flash instruction (see Table 28). The MCU can read the memory contents of the primary Flash memory or the secondary Flash memory by using READ operations any time the READ operation is not part of an instruction.
7.4
Read Primary Flash Identifier
The primary Flash memory identifier is read with an instruction composed of 4 operations: 3 specific WRITE operations and a READ operation (see Table 28. on page 32). The identifier for the device is E8h.
7.5
Read Memory Sector Protection Status
The primary Flash memory Sector Protection Status is read with an instruction composed of 4 operations: 3 specific WRITE operations and a READ operation (see Table 28). The READ operation produces 01h if the Flash memory sector is protected, or 00h if the sector is not protected. The sector protection status for all NVM blocks (primary Flash memory or secondary Flash memory) can also be read by the MCU accessing the Flash Protection and Flash Boot Protection registers in PSD I/O space. See Flash memory Sector Protect on page 43 for register definitions.
7.6
Read the Erase/Program Status Bits
The PSD provides several status bits to be used by the MCU to confirm the completion of an Erase or Program cycle of Flash memory. These status bits minimize the time that the MCU spends performing these tasks and are defined in Table 29. The status bits can be read as many times as needed. For Flash memory, the MCU can perform a READ operation to obtain these status bits while an Erase or Program instruction is being executed by the embedded algorithm. See Programming Flash memory on page 37 for details.
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PSD835G2 Table 29.
Functional Block Flash memory
Instructions Status bit(1) (2)
FS0-FS7/CSBOOT0CSBOOT3(3) VIH DQ7 DQ6 DQ5 DQ4 X DQ3 Erase Time-out DQ2 DQ1 DQ0 X X X
Data Toggle Error Polling Flag Flag
1. X = Not guaranteed value, can be read either '1' or '0.' 2. DQ7-DQ0 represent the Data Bus Bits, D7-D0. 3. FS0-FS7 and CSBOOT0-CSBOOT3 are active High.
7.7
Data polling flag (DQ7)
When erasing or programming in Flash memory, the Data Polling Flag Bit (DQ7) outputs the complement of the bit being entered for programming/writing on the DQ7 Bit. Once the Program instruction or the WRITE operation is completed, the true logic value is read on the Data Polling Flag Bit (DQ7, in a READ operation).
Data Polling is effective after the fourth WRITE pulse (for a Program instruction) or after the sixth WRITE pulse (for an Erase instruction). It must be performed at the address being programmed or at an address within the Flash memory sector being erased. During an Erase cycle, the Data Polling Flag Bit (DQ7) outputs a '0.' After completion of the cycle, the Data Polling Flag Bit (DQ7) outputs the last bit programmed (it is a '1' after erasing). If the Byte to be programmed is in a protected Flash memory sector, the instruction is ignored. If all the Flash memory sectors to be erased are protected, the Data Polling Flag Bit (DQ7) is reset to '0' for about 100 s, and then returns to the previous addressed byte. No erasure is performed.
7.8
Toggle flag (DQ6)
The PSD offers another way for determining when the Flash memory Program cycle is completed. During the internal WRITE operation and when either the FS0-FS7 or CSBOOT0-CSBOOT3 is true, the Toggle Flag Bit (DQ6) toggles from '0' to '1' and '1' to '0' on subsequent attempts to read any Byte of the memory. When the internal cycle is complete, the toggling stops and the data read on the Data Bus D0-D7 is the addressed memory Byte. The device is now accessible for a new READ or WRITE operation. The cycle is finished when two successive READs yield the same output data.
The Toggle Flag Bit (DQ6) is effective after the fourth WRITE pulse (for a Program instruction) or after the sixth WRITE pulse (for an Erase instruction). If the Byte to be programmed belongs to a protected Flash memory sector, the instruction is ignored. If all the Flash memory sectors selected for erasure are protected, the Toggle Flag Bit (DQ6) toggles to '0' for about 100 s and then returns to the previous addressed Byte.
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7.9
Error flag (DQ5)
During a normal Program or Erase cycle, the Error Flag Bit (DQ5) is set to '0.' This bit is set to '1' when there is a failure during Flash memory Byte Program, Sector Erase, or Bulk Erase cycle. In the case of Flash memory programming, the Error Flag Bit (DQ5) indicates the attempt to program a Flash memory bit from the programmed state, 0, to the erased state, 1, which is not valid. The Error Flag Bit (DQ5) may also indicate a Time-out condition while attempting to program a Byte. In case of an error in a Flash memory Sector Erase or Byte Program cycle, the Flash memory sector in which the error occurred or to which the programmed Byte belongs must no longer be used. Other Flash memory sectors may still be used. The Error Flag Bit (DQ5) is reset after a Reset Flash instruction.
7.10
Erase time-out flag (DQ3)
The Erase Time-out Flag Bit (DQ3) reflects the time-out period allowed between two consecutive Sector Erase instructions. The Erase Time-out Flag Bit (DQ3) is reset to '0' after a Sector Erase cycle for a time period of 100 s + 20% unless an additional Sector Erase instruction is decoded. After this time period, or when the additional Sector Erase instruction is decoded, the Erase Time-out Flag Bit (DQ3) is set to '1.'
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PSD835G2
Programming Flash memory
8
Programming Flash memory
Flash memory must be erased prior to being programmed. The MCU may erase Flash memory all at once or by-sector. A Flash memory sector is erased to all 1s (FFh), and is programmed by setting selected bits to '0.' Although Flash memory is erased by-sector, it is programmed Word-by-Word. The primary and secondary Flash memories require the MCU to send an instruction to program a Word or to erase sectors (see Table 28. on page 32). Once the MCU issues a Flash memory Program or Erase instruction, it must check the status bits for completion. The embedded algorithms that are invoked inside the PSD support several means to provide status to the MCU. Status may be checked using any of three methods: Data Polling, Data Toggle, or the Ready/Busy (PE4) output pin.
8.1
Data polling
Polling on the Data Polling Flag Bit (DQ7) is a method of checking whether a Program or Erase cycle is in progress or has completed. Figure 6 shows the Data Polling algorithm. When the MCU issues a Program instruction, the embedded algorithm within the PSD begins. The MCU then reads the location of the Word to be programmed in Flash memory to check status. The Data Polling Flag Bit (DQ7) of this location becomes the complement of b7 of the original data byte to be programmed. The MCU continues to poll this location, comparing the Data Polling Flag Bit (DQ7) and monitoring the Error Flag Bit (DQ5). When the Data Polling Flag Bit (DQ7) matches b7 of the original data, and the Error Flag Bit (DQ5) remains '0,' the embedded algorithm is complete. If the Error Flag Bit (DQ5) is '1,' the MCU should test the Data Polling Flag Bit (DQ7) again since the Data Polling Flag Bit (DQ7) may have changed simultaneously with the Error Flag Bit (DQ5, see Figure 6). The Error Flag Bit (DQ5) is set if either an internal time-out occurred while the embedded algorithm attempted to program the Byte or if the MCU attempted to program a '1' to a bit that was not erased (not erased is logic 0). It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed, to compare the Byte that was written to the Flash memory with the Byte that was intended to be written. When using the Data Polling method after an Erase cycle, Figure 6 still applies. However, the Data Polling Flag Bit (DQ7) is '0' until the Erase cycle is complete. A '1' on the Error Flag Bit (DQ5) indicates a time-out condition on the Erase cycle; a '0' indicates no error. The MCU can read any location within the sector being erased to get the Data Polling Flag Bit (DQ7) and the Error Flag Bit (DQ5). PSDsoft generates ANSI C code functions which implement these Data Polling algorithms.
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Programming Flash memory Figure 6. Data polling flowchart
START
PSD835G2
READ DQ5 & DQ7 at VALID ADDRESS
DQ7 = DATA NO NO
YES
DQ5 =1 YES READ DQ7
DQ7 = DATA NO FAIL
YES
PASS
AI01369B
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PSD835G2
Programming Flash memory
8.2
Data toggle
Checking the Toggle Flag Bit (DQ6) is a method of determining whether a Program or Erase cycle is in progress or has completed. Figure 7 shows the Data Toggle algorithm. When the MCU issues a Program instruction, the embedded algorithm within the PSD begins. The MCU then reads the location of the byte to be programmed in Flash memory to check status. The Toggle Flag Bit (DQ6) of this location toggles each time the MCU reads this location until the embedded algorithm is complete. The MCU continues to read this location, checking the Toggle Flag Bit (DQ6) and monitoring the Error Flag Bit (DQ5). When the Toggle Flag Bit (DQ6) stops toggling (two consecutive READs yield the same value), and the Error Flag Bit (DQ5) remains '0,' the embedded algorithm is complete. If the Error Flag Bit (DQ5) is 1,' the MCU should test the Toggle Flag Bit (DQ6) again, since the Toggle Flag Bit (DQ6) may have changed simultaneously with the Error Flag Bit (DQ5, see Figure 7). The Error Flag Bit (DQ5) is set if either an internal time-out occurred while the embedded algorithm attempted to program the byte, or if the MCU attempted to program a '1' to a bit that was not erased (not erased is logic 0). It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed, to compare the Byte that was written to Flash memory with the Byte that was intended to be written. When using the Data Toggle method after an Erase cycle, Figure 7 still applies. the Toggle Flag Bit (DQ6) toggles until the Erase cycle is complete. A 1 on the Error Flag Bit (DQ5) indicates a time-out condition on the Erase cycle; a '0' indicates no error. The MCU can read any location within the sector being erased to get the Toggle Flag Bit (DQ6) and the Error Flag Bit (DQ5). PSDsoft generates ANSI C code functions which implement these Data Toggling algorithms. Figure 7. Data toggle flowchart
START
READ DQ5 & DQ6
DQ6 = TOGGLE YES NO
NO
DQ5 =1 YES READ DQ6
DQ6 = TOGGLE YES FAIL
NO
PASS
AI01370B
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Programming Flash memory
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8.3
Unlock Bypass
The Unlock Bypass instructions allow the system to program bytes to the Flash memories faster than using the standard Program instruction. The Unlock Bypass mode is entered by first initiating two Unlock cycles. This is followed by a third WRITE cycle containing the Unlock Bypass code, 20h (as shown in Table 28. on page 32). The Flash memory then enters the Unlock Bypass mode. A two-cycle Unlock Bypass Program instruction is all that is required to program in this mode. The first cycle in this instruction contains the Unlock Bypass Program code, A0h. The second cycle contains the program address and data. Additional data is programmed in the same manner. These instructions dispense with the initial two Unlock cycles required in the standard Program instruction, resulting in faster total Flash memory programming. During the Unlock Bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset Flash instructions are valid. To exit the Unlock Bypass mode, the system must issue the two-cycle Unlock Bypass Reset Flash instruction. The first cycle must contain the data 90h; the second cycle, the data 00h. Addresses are Don't Care for both cycles. The Flash memory then returns to READ mode.
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PSD835G2
Erasing Flash memory
9
9.1
Erasing Flash memory
Flash Bulk Erase
The Flash Bulk Erase instruction uses six WRITE operations followed by a READ operation of the status register, as described in Table 28. on page 32. If any byte of the Bulk Erase instruction is wrong, the Bulk Erase instruction aborts and the device is reset to the Read Flash memory status. During a Bulk Erase, the memory status may be checked by reading the Error Flag Bit (DQ5), the Toggle Flag Bit (DQ6), and the Data Polling Flag Bit (DQ7), as detailed in "Programming Flash memory on page 37. The Error Flag Bit (DQ5) returns a '1' if there has been an Erase Failure (maximum number of Erase cycles has been executed). It is not necessary to program the memory with 00h because the PSD automatically does this before erasing to 0FFh. During execution of the Bulk Erase instruction, the Flash memory does not accept any instructions.
9.2
Flash Sector Erase
The Sector Erase instruction uses six WRITE operations, as described in Table 28. on page 32. Additional Flash Sector Erase codes and Flash memory sector addresses can be written subsequently to erase other Flash memory sectors in parallel, without further coded cycles, if the additional bytes are transmitted in a shorter time than the time-out period of about 100 s. The input of a new Sector Erase code restarts the time-out period. The status of the internal timer can be monitored through the level of the Erase Time-out Flag Bit (DQ3). If the Erase Time-out Flag Bit (DQ3) is '0,' the Sector Erase instruction has been received and the time-out period is counting. If the Erase Time-out Flag Bit (DQ3) is '1,' the time-out period has expired and the PSD is busy erasing the Flash memory sector(s). Before and during Erase time-out, any instruction other than Suspend Sector Erase and Resume Sector Erase instructions abort the cycle that is currently in progress, and reset the device to READ mode. It is not necessary to program the Flash memory sector with 00h as the PSD does this automatically before erasing (Byte=FFh). During a Sector Erase, the memory status may be checked by reading the Error Flag Bit (DQ5), the Toggle Flag Bit (DQ6), and the Data Polling Flag Bit (DQ7), as detailed in Programming Flash memory on page 37. During execution of the Erase cycle, the Flash memory accepts only Reset and Suspend Sector Erase instructions. Erasure of one Flash memory sector may be suspended, in order to read data from another Flash memory sector, and then resumed.
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Erasing Flash memory
PSD835G2
9.3
Suspend Sector Erase
When a Sector Erase cycle is in progress, the Suspend Sector Erase instruction can be used to suspend the cycle by writing 0B0h to any even address when an appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) is High. (See Table 28. on page 32). This allows reading of data from another Flash memory sector after the Erase cycle has been suspended. Suspend Sector Erase is accepted only during an Erase cycle and defaults to READ mode. A Suspend Sector Erase instruction executed during an Erase time-out period, in addition to suspending the Erase cycle, terminates the time out period. The Toggle Flag Bit (DQ6) stops toggling when the PSD internal logic is suspended. The status of this bit must be monitored at an address within the Flash memory sector being erased. The Toggle Flag Bit (DQ6) stops toggling between 0.1 s and 15 s after the Suspend Sector Erase instruction has been executed. The PSD is then automatically set to READ mode. If a Suspend Sector Erase instruction was executed, the following rules apply:
Attempting to read from a Flash memory sector that was being erased outputs invalid data. Reading from a Flash sector that was not being erased is valid. The Flash memory cannot be programmed, and only responds to Resume Sector Erase and Reset Flash instructions (READ is an operation and is allowed). If a Reset Flash instruction is received, data in the Flash memory sector that was being erased is invalid.
9.4
Resume Sector Erase
If a Suspend Sector Erase instruction was previously executed, the erase cycle may be resumed with this instruction. The Resume Sector Erase instruction consists in writing 030h to any even address while an appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) is High. (See Table 28. on page 32.)
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PSD835G2
Specific features
10
10.1
Specific features
Flash memory Sector Protect
Each primary and secondary Flash memory sector can be separately protected against Program and Erase cycles. Sector Protection provides additional data security because it disables all Program or Erase cycles. This mode can be activated through the JTAG/ISP Port or a Device Programmer. Sector protection can be selected for each sector using the PSDsoft program. This automatically protects selected sectors when the device is programmed through the JTAG Port or a Device Programmer. Flash memory sectors can be unprotected to allow updating of their contents using the JTAG Port or a Device Programmer. The MCU can read (but cannot change) the sector protection bits. Any attempt to program or erase a protected Flash memory sector is ignored by the device. The Verify operation results in a READ of the protected data. The retention of the Protection status is thus ensured. The sector protection status can be read by the MCU through the primary and secondary Flash memory protection registers (in the CSIOP block). See Table 18. on page 26 and Table 19. on page 27.
10.2
Reset Flash
The Reset Flash instruction consists of one WRITE cycle (see Table 28. on page 32). It can also be optionally preceded by the standard two WRITE decoding cycles (writing AAh to AAAh and 55h to 554h). It must be executed after:
Reading the Flash Protection Status or Flash ID using the Flash instruction. An Error condition has occurred (and the device has set the Error Flag Bit (DQ5) to '1') during a Flash memory Program or Erase cycle.
The Reset Flash instruction puts the Flash memory back into normal READ mode immediately. If an Error condition has occurred (and the device has set the Error Flag Bit (DQ5) to '1') the Flash memory is put back into normal READ mode within 25 s of the Reset Flash instruction having been issued. The Reset Flash instruction is ignored when it is issued during a Program or Bulk Erase cycle of the Flash memory. The Reset Flash instruction aborts any on-going Sector Erase cycle, and returns the Flash memory to the normal READ mode within 25s.
10.3
Reset (RESET) signal
A pulse on Reset (RESET) aborts any cycle that is in progress, and resets the Flash memory to the READ mode. When the reset occurs during a Program or Erase cycle, the Flash memory takes up to 25 s to return to the READ mode. It is recommended that the Reset (RESET) pulse (except for the one described in Power-Up reset on page 89) be at least 25 s so that the Flash memory is always ready for the MCU to fetch the bootstrap instructions after the Reset cycle is complete.
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SRAM
PSD835G2
11
SRAM
The SRAM is enabled when SRAM Select (RS0) from the DPLD is High. SRAM Select (RS0) can contain up to three product terms, allowing flexible memory mapping. The SRAM can be backed up using an external battery. The external battery should be connected to Voltage Stand-by (VSTBY, PE6). If you have an external battery connected to the PSD, the contents of the SRAM are retained in the event of a power loss. The contents of the SRAM are retained so long as the battery voltage remains at 2 V or greater. If the supply voltage falls below the battery voltage, an internal power switch-over to the battery occurs. PE7 can be configured as an output that indicates when power is being drawn from the external battery. Battery-on Indicator (VBATON, PE7) is High when the supply voltage falls below the battery voltage and the battery on Voltage Stand-by (VSTBY, PE6) is supplying power to the internal SRAM. SRAM Select (RS0), Voltage Stand-by (VSTBY, PC2) and Battery-on Indicator (VBATON, PC4) are all configured using PSDsoft Express Configuration. The SRAM Select (RS0), VBATON and VSTBY are all configured using PSDsoft.
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PSD835G2
Sector Select and SRAM Select
12
Sector Select and SRAM Select
Sector Select (FS0-FS7 for primary Flash memory, CSBOOT0-CSBOOT3 for secondary Flash memory) and SRAM Select (RS0) are all outputs of the DPLD. They are setup using PSDsoft. The following rules apply to the equations for these signals: 1. 2. 3. 4. 5. 6. Primary Flash memory and secondary Flash memory Sector Select signals must not be larger than the physical sector size. Any primary Flash memory sector must not be mapped in the same memory space as another primary Flash memory sector. A secondary Flash memory sector must not be mapped in the same memory space as another secondary Flash memory sector. SRAM and I/O spaces must not overlap. A secondary Flash memory sector may overlap a primary Flash memory sector. In case of overlap, priority is given to the secondary Flash memory sector. SRAM and I/O spaces may overlap any other memory sector. Priority is given to the SRAM and I/O.
12.1
Example
FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from 8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0 always accesses the SRAM. Any address in the range of CSBOOT0 greater than 87FFh (and less than 9FFFh) automatically addresses secondary Flash memory segment 0. Any address greater than 9FFFh accesses the primary Flash memory segment 0. You can see that half of the primary Flash memory segment 0 and one-fourth of secondary Flash memory segment 0 cannot be accessed in this example. Also note that an equation that defined FS1 to anywhere in the range of 8000h to BFFFh would not be valid. Figure 8 shows the priority levels for all memory components. Any component on a higher level can overlap and has priority over any component on a lower level. Components on the same level must not overlap. Level one has the highest priority and level 3 has the lowest.
12.2
Memory Select configuration for MCUs with separate program and data spaces
The 80C51 and compatible family of MCUs have separate address spaces for Program memory (selected using Program Select Enable (PSEN, CNTL2)) and Data memory (selected using Read Strobe (RD, CNTL1)). Any of the memories within the PSD can reside in either space or both spaces. This is controlled through manipulation of the VM register that resides in the CSIOP space. The VM register is set using PSDsoft to have an initial value. It can subsequently be changed by the MCU so that memory mapping can be changed on-the-fly. For example, you may wish to have SRAM and primary Flash memory in the Data space at Boot-up, and secondary Flash memory in the Program space at Boot-up, and later swap the primary and secondary Flash memories. This is easily done with the VM register by using PSDsoft to configure it for Boot-up and having the MCU change it when desired. Table 24. on page 28 describes the VM Register.
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Sector Select and SRAM Select Figure 8. Priority level of memory and I/O components
Highest Priority
PSD835G2
Level 1 SRAM, I /O, or Peripheral I /O Level 2 Secondar y Non-Volatile Memory Level 3 Primar y Flash Memory Lowest Priority
AI02867D
12.3
12.3.1
Configuration modes for MCUs with separate program and data spaces
Separate space modes
Program space is separated from Data space. For example, Program Select Enable (PSEN, CNTL2) is used to access the program code from the primary Flash memory, while Read Strobe (RD, CNTL1) is used to access data from the secondary Flash memory, SRAM and I/O Port blocks. This configuration requires the VM register to be set to 0Ch (see Figure 9).
12.3.2
Combined space modes
The Program and Data spaces are combined into one memory space that allows the primary Flash memory, secondary Flash memory, and SRAM to be accessed by either Program Select Enable (PSEN, CNTL2) or Read Strobe (RD, CNTL1). For example, to configure the primary Flash memory in Combined space, Bits b2 and b4 of the VM register are set to '1' (see Figure 10). Figure 9. 8031 memory modules separate space
DPLD
RS0 CSBOOT0-3 FS0-FS7
Primary Flash Memory
Secondary Flash Memory
SRAM
CS OE
CS OE
CS OE
PSEN RD
AI02869C
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PSD835G2 Figure 10. 8031 memory modules combined space
Sector Select and SRAM Select
DPLD
RS0 CSBOOT0-3 FS0-FS7
Primary Flash Memory
Secondary Flash Memory
SRAM
RD
CS OE
CS OE
CS OE
VM REG BIT 3
VM REG BIT 4
PSEN
VM REG BIT 1
VM REG BIT 2
RD
VM REG BIT 0
AI02870C
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Page Register
PSD835G2
13
Page Register
The 8-bit Page Register increases the addressing capability of the MCU by a factor of up to 256. The contents of the register can also be read by the MCU. The outputs of the Page Register (PGR0-PGR7) are inputs to the DPLD decoder and can be included in the Sector Select (FS0-FS7, CSBOOT0-CSBOOT3), and SRAM Select (RS0) equations. If memory paging is not needed, or if not all 8 page register bits are needed for memory paging, then these bits may be used in the CPLD for general logic. See Application Note AN1154. Figure 11 shows the Page Register. The eight flip-flops in the register are connected to the internal data bus D0-D7. The MCU can write to or read from the Page Register. The Page Register can be accessed at address location CSIOP + E0h. Figure 11. Page Register
RESET
D0 D1 D0 - D7 D2 D3 D4 D5 D6 R/W D7
Q0 Q1 Q2 Q3 Q4 Q5
PGR0 PGR1 PGR2 PGR3 PGR4 PGR5 PGR6 DPLD AND CPLD
INTERNAL SELECTS AND LOGIC
Q6 PGR7 Q7
PAGE REGISTER
PLD
AI02871B
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PSD835G2
Memory ID Registers
14
Memory ID Registers
The 8-bit Read-only Memory Status Registers are included in the CSIOP space. The user can determine the memory configuration of the PSD device by reading the Memory ID0 and ID1 Registers. The contents of the registers are defined in Table 25. on page 28 and Table 26. on page 28.
15
PLDs
The PLDs bring programmable logic functionality to the PSD. After specifying the logic for the PLDs in PSDsoft, the logic is programmed into the device and available upon Power-up. The PSD contains two PLDs: the Decode PLD (DPLD), and the Complex PLD (CPLD). The PLDs are briefly discussed in the next few paragraphs, and in more detail in Decode PLD (DPLD) on page 52 and Complex PLD (CPLD) on page 53. Figure 12 shows the configuration of the PLDs. The DPLD performs address decoding for Select signals for internal components, such as memory, registers, and I/O ports. The CPLD can be used for logic functions, such as loadable counters and shift registers, state machines, and encoding and decoding logic. These logic functions can be constructed using the 16 Output Macrocells (OMC), 24 Input Macrocells (IMC), and the AND Array. The CPLD can also be used to generate External Chip Select (ECS0-ECS2) signals. The AND Array is used to form product terms. These product terms are specified using PSDsoft. An Input Bus consisting of 82 signals is connected to the PLDs. The signals are shown in Table 30.
15.1
The Turbo bit in PSD
The PLDs in the PSD can minimize power consumption by switching to standby when inputs remain unchanged for an extended time of about 70ns. Resetting the Turbo Bit to '0' (Bit 3 of PMMR0) automatically places the PLDs into standby if no inputs are changing. Turning the Turbo mode off increases propagation delays while reducing power consumption. See Power management on page 84, on how to set the Turbo Bit. Additionally, five bits are available in PMMR2 to block MCU control signals from entering the PLDs. This reduces power consumption and can be used only when these MCU control signals are not used in PLD logic equations. Each of the two PLDs has unique characteristics suited for its applications. They are described in the following sections.
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PLDs Table 30. DPLD and CPLD inputs
Input source MCU Address Bus(1) MCU Control Signals Reset Power-down Por t A Input Macrocells Por t B Input Macrocells Por t C Input Macrocells Por t D Inputs Por t F Inputs Page Register Macrocell A Feedback Macrocell B Feedback Secondary Flash memory Program Status Bit
1. The address inputs are A19-A4 in 80C51XA mode.
PSD835G2
Input name A15-A0 CNTL2-CNTL0 RST PDN PA7-PA0 PB7-PB0 PC7-PC0 PD3-PD0 PF7-PF0 PGR7-PGR0 MCELLA.FB7-FB0 MCELLB.FB7-FB0 Ready/Busy
Number of signals 16 3 1 1 8 8 8 4 8 8 8 8 1
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PSD835G2
8 DATA BUS
PAGE REGISTER
DECODE PLD
PRIMARY FLASH MEMORY SELECTS 73 4 1 SRAM SELECT CSIOP SELECT PERIPHERAL SELECTS JTAG SELECT 1 2 1
8
Figure 12. PLD diagram
SECONDARY NON-VOLATILE MEMORY SELECTS
PLD INPUT BUS
16
OUTPUT MACROCELL FEEDBACK
DIRECT MACROCELL ACCESS FROM MCU DATA BUS
CPLD
82 PT ALLOC.
16 OUTPUT MACROCELL
MCELLA TO PORT A MCELLB TO PORT B I/O PORTS
8
24 INPUT MACROCELL (PORT A,B,C)
8 3 EXTERNAL CHIP SELECTS TO PORT C OR F
DIRECT MACROCELL INPUT TO MCU DATA BUS 24 INPUT MACROCELL & INPUT PORTS
12
PORT D AND F INPUTS
PLDs
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AI02872D
PLDs
PSD835G2
15.2
Decode PLD (DPLD)
The DPLD, shown in Figure 13, is used for decoding the address for internal and external components. The DPLD can be used to generate the following decode signals:
8 Sector Select (FS0-FS7) signals for the primary Flash memory (three product terms each) 4 Sector Select (CSBOOT0-CSBOOT3) signals for the secondary Flash memory (three product terms each) 1 internal SRAM Select (RS0) signal (three product terms) 1 internal CSIOP Select (PSD Configuration Register) signal 1 JTAG Select signal (enables JTAG/ISP on Port E) 2 internal Peripheral Select signals (Peripheral I/O mode).
Figure 13. DPLD logic array
3 3 3 3 (INPUTS) I /O PORTS (PORT A,B,C,F) MCELLA.FB7-FB0 (FEEDBACKS) MCELLB.FB7-FB0 (FEEDBACKS) PGR0 - PGR7 A15-A0(1,2) PD3-PD0 (ALE,CLKIN,CSI) PDN (APD OUTPUT) (32) 3 (8) 3 (8) 3 (8) 3 (16) 3 (4) 3 (1) 3 CNTRL2-CNTRL0 (READ/WRITE CONTROL SIGNALS) (3) RESET RD_BSY (1) 3 (1) CSIOP PSEL0 PSEL1 JTAGSEL
AI02873E
CSBOOT 0 CSBOOT 1 CSBOOT 2 CSBOOT 3
3
FS0 FS1 FS2 FS3 FS4 FS5 FS6 FS7 8 PRIMARY FLASH MEMORY SECTOR SELECTS
RS0
SRAM SELECT I/O DECODER SELECT PERIPHERAL I/O MODE SELECT
1. The address inputs are A19-A4 in 80C51XA mode. 2. Additional address lines can be brought into PSD via Port A, B, C, D or F.
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PSD835G2
PLDs
15.3
Complex PLD (CPLD)
The CPLD can be used to implement system logic functions, such as loadable counters and shift registers, system mailboxes, handshaking protocols, state machines, and random logic. The CPLD can also be used to generate three External Chip Select (ECS0-ECS2), routed to Port D. Although External Chip Select (ECS0-ECS2) can be produced by any Output Macrocell (OMC), these three External Chip Select (ECS0-ECS2) on Port D do not consume any Output Macrocells (OMC). As shown in Figure 12. on page 51, the CPLD has the following blocks:
24 Input Macrocells (IMC) 16 Output Macrocells (OMC) Macrocell Allocator Product Term Allocator AND Array capable of generating up to 137 product terms Four I/O Ports.
Each of the blocks are described in the sections that follow. The Input Macrocells (IMC) and Output Macrocells (OMC) are connected to the PSD internal data bus and can be directly accessed by the MCU. This enables the MCU software to load data into the Output Macrocells (OMC) or read data from both the Input and Output Macrocells (IMC and OMC). This feature allows efficient implementation of system logic and eliminates the need to connect the data bus to the AND Array as required in most standard PLD macrocell architectures.
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PLDs
PLD INPUT BUS
AND ARRAY
PR DI LD D/T Q COMB. /REG SELECT PDR INPUT MUX D/T/JK FF SELECT CK CL WR PT CLEAR D Q DIR REG. PT CLOCK GLOBAL CLOCK CLOCK SELECT SELECT
PLD INPUT BUS
PT OUTPUT ENABLE (OE) MACROCELL FEEDBACK I/O PORT INPUT
MUX
PT INPUT LATCH GATE/CLOCK MUX ALE/AS
MUX
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PRODUCT TERMS FROM OTHER MACROCELLS MCU ADDRESS / DATA BUS
CPLD MACROCELLS I/O PORTS
MCU DATA IN MCU LOAD D WR UP TO 10 PRODUCT TERMS MACROCELL OUT TO MCU CPLD OUTPUT DATA Q MUX DATA LOAD CONTROL LATCHED ADDRESS OUT PT PRESET PRODUCT TERM ALLOCATOR
Figure 14. Macrocell and I/O port
I/O PIN
POLARITY SELECT
INPUT MACROCELLS
QD
QD G
AI02874b
PSD835G2
PSD835G2
PLDs
15.4
Output macrocell (OMC)
Eight of the Output Macrocells (OMC) are connected to Port A pins and are named as McellA0-McellA7. The other eight macrocells are connected to Port B pins and are named as McellB0-McellB7. The Output Macrocell (OMC) architecture is shown in Figure 15. on page 57. As shown in the figure, there are native product terms available from the AND Array, and borrowed product terms available (if unused) from other Output Macrocells (OMC). The polarity of the product term is controlled by the XOR gate. The Output Macrocell (OMC) can implement either sequential logic, using the flip-flop element, or combinatorial logic. The multiplexer selects between the sequential or combinatorial logic outputs. The multiplexer output can drive a port pin and has a feedback path to the AND Array inputs. The flip-flop in the Output Macrocell (OMC) block can be configured as a D, T, JK, or SR type in the PSDsoft program. The flip-flop's clock, preset, and clear inputs may be driven from a product term of the AND Array. Alternatively, CLKIN (PD1) can be used for the clock input to the flip-flop. The flip-flop is clocked to the rising edge of CLKIN (PD1). The preset and clear are active High inputs. Each clear input can use up to two product terms. Table 31.
Output macrocell McellA0 McellA1 McellA2 McellA3 McellA4 McellA5 McellA6 McellA7 McellB0 McellB1 McellB2 McellB3 McellB4 McellB5 McellB6 McellB7
Output macrocell port and data bit assignments
Port assignment Por t A0 Por t A1 Por t A2 Por t A3 Por t A4 Por t A5 Por t A6 Por t A7 Por t B0 Por t B1 Por t B2 Por t B3 Por t B4 Por t B5 Por t B6 Por t B7 Native product terms 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 Maximum borrowed product terms 6 6 6 6 6 6 6 6 5 5 5 5 6 6 6 6 Data bit for loading or reading D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
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PLDs
PSD835G2
15.5
Product term allocator
The CPLD has a Product Term Allocator. The PSD uses the Product Term Allocator to borrow and place product terms from one macrocell to another. The following list summarizes how product terms are allocated:
McellA0-McellA7 all have three native product terms and may borrow up to six more McellB0-McellB3 all have four native product terms and may borrow up to five more McellB4-McellB7 all have four native product terms and may borrow up to six more.
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