PSD4235G2
Flash In-System Programmable (ISP) for 16-bit MCUs (5V Supply)
FEATUR ES SUMMARY D UAL BANK FLASH MEMORIES 4 Mbit of Primary Flash Memory (8 uniform sectors, 32K x 16) 256 Kbit Secondary Flash Memory with 4 sectors Concurrent operation: read from one memory while erasing and writing the other 64 Kbit SRAM (BATTERY BACKED) PLD WITH MACROCELLS Over 3000 Gates of PLD: CPLD and DPLD CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs) DPLD - user defined internal chip select decoding SEVEN L/O PORTS WITH 52 I/O PINS 52 individually configurable I/O port pins that can be used for the following functions: MCU I/Os PLD I/Os Latched MCU address output Special function l/Os l/O ports may be configured as open-drain outputs IN-SYSTEM PROGRAMMING (ISP) WITH JTAG Built-in JTAG compliant serial port allows full-chip In-System Programmability Efficient manufacturing allow easy product testing and programming Use low cost FlashLINK cable with PC PAGE REGISTER Internal page register that can be used to expand the microcontroller address space by a factor of 256 PROGRAMMABLE POWER MANAGEMENT
Figure 1. Package
TQFP80 (U) 80-lead, Thin, Quad, Flat
H IGH ENDURANCE: 100,000 Erase/WRITE Cycles of Flash Memory 1,000 Erase/WRITE Cycles of PLD 15 Year Data Retention SINGLE SUPPLY VOLTAGE 5V 10% MEMORY SPEED 70ns Flash memory and SRAM access time
March 2004
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TABLE OF CONTENTS Features Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Summary Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 In-System Programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 First time programming.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Inventory build-up of pre-programmed devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Expensive sockets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 In-Application Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Simultaneous READ and WRITE to Flash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 C omplex memory mapping.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Separate Program and Data space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PSDsoft Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 1. Pin Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 3. TQFP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 2. Pin Description (for the TQFP package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 4. PSD Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PSD Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 M e m o ry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 P L D s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 MCU Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ISP via JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3. PLD I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4. JTAG SIgnals on Port E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 In-Application Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5. Methods of Programming Different Functional Blocks of the PSD . . . . . . . . . . . . . . . . . 17 Development System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 5. PSDsoft Express Development Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PSD Register Description and Address Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 6. Register Address Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 7. Data-In Registers - Ports A, B, C, D, E, F, G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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Table 8. Data-Out Registers - Ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 9. Direction Registers - Ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 10. Control Registers - Ports E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 11. Drive Registers - Ports A, B, D, E, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 12. Drive Registers - Ports C, F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 13. Enable-Out Registers - Ports A, B, C, F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 14. Input Macrocells - Ports A, B, C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 15. Output Macrocells A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 16. Output Macrocells B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 17. Mask Macrocells A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 18. Mask Macrocells B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 19. Flash Memory Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 20. Flash Boot Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 21. JTAG Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 22. Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 23. PMMR0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 24. PMMR2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 25. VM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 26. Memory_ID0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 27. Memory_ID1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Detailed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 28. Memory Block Size and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Primary Flash Memory and Secondary Flash memory Description . . . . . . . . . . . . . . . . . . . . . 26 Memory Block Select Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 R eady/Busy (PE4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Memory Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 29. Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Power-up Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 R eading Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 R ead Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 R ead Primary Flash Identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 R ead Memory Sector Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 R eading the Erase/Program Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 30. Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 31. Status Bits for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 D ata Polling (DQ7) - DQ15 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Toggle Flag (DQ6) - DQ14 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Error Flag (DQ5) - DQ13 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Erase Time-out Flag (DQ3) - DQ11 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PROGRAMMING FLASH MEMORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 D ata Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Figure 6. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . D ata Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U nlock Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 7. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . ... . . ... . . ... . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . . . 31 . . . . 32 . . . . 32 . . . . 32
ERA SING FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . R esume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 . . . . 33 . . . . 33 . . . . 33
SPECIFIC FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Flash Memory Sector Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 R ESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 R eset (RESET) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SRA M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 MEMORY SELECT SIGNALS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Memory Select Configuration for MCUs with Separate Program and Data Spaces . . . . . . . . 35 Figure 8. Priority Level of Memory and I/O Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Separate Space Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 C ombined Space Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 80C51XA Memory Map Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 9. 8031 Memory Modules - Separate Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 10.8031 Memory Modules - Combined Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PAGE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 11.Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 MEMORY ID REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 PLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 The Turbo Bit in PSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 32. DPLD and CPLD Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 12.PLD Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Decode PLD (DPLD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 13.DPLD Logic Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 14.Macrocell and I/O Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Output Macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 33. Output Macrocell Port and Data Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Product Term Allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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Loading and Reading the Output Macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 The OMC Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 15.CPLD Output Macrocell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 16.Input Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 17.External Chip Select Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 18.Handshaking Communication Using Input Macrocells . . . . . . . . . . . . . . . . . . . . . . . . . . 46 MCU Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 34. MCUs and their Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PSD Interface to a Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 19.An Example of a Typical 16-bit Multiplexed Bus Interface . . . . . . . . . . . . . . . . . . . PSD Interface to a Non-Multiplexed 8-bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 20.An Example of a Typical 16-bit Non-Multiplexed Bus Interface . . . . . . . . . . . . . . . D ata Byte Enable Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 35. 16-bit Data Bus with BHE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Bus Interface Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 36. 16-bit Data Bus with WRH and WRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 37. 16-bit Data Bus with SIZ0, A0 (Motorola MCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 38. 16-bit Data Bus with LDS, UDS (Motorola MCU) . . . . . . . . . . . . . . . . . . . . . . . . . . 80C196 and 80C186 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 21.Interfacing the PSD with an 80C196 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC683xx and MC68HC16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 22.Interfacing the PSD with an MC68331 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 0C 51X A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 23.Interfacing the PSD with an 80C51XA-G3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H 8/300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 24.Interfacing the PSD with an H83/2350 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M M C 2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 16x Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 25.Interfacing the PSD with an MMC2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 26.Interfacing the PSD with a C167CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 . . . . 48 . . . . 48 . . . . 49 . . . . 49 . . . . 50 . . . . 50 . . . . 50 . . . . 50 . . . . 50 . . . . 50 . . . . 51 . . . . 51 . . . . 52 . . . . 52 . . . . 53 . . . . 53 . . . . 54 . . . . 54 . . . . 55 . . . . 55 . . . . 56 . . . . 57
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 General Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 27.General I/O Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A ddress Out Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 39. Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 40. Port Operating Mode Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 41. I/O Port Latched Address Output Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . A ddress In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 . . . . 58 . . . . 59 . . . . 60 . . . . 60 . . . . 60 . . . . 60 . . . . 61 . . . . 61 . . . . 62
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D ata Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Peripheral I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 28.Peripheral I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 JTAG In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 MCU Reset Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 C ontrol Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 42. Port Configuration Registers (PCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 D irection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 D rive Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 43. Port Pin Direction Control, Output Enable P.T. Not Defined . . . . . . . . . . . . . . . . . . . . . . 64 Table 44. Port Pin Direction Control, Output Enable P.T. Defined . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 45. Port Direction Assignment Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 46. Drive Register Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 D ata In. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 D ata Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Output Macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Mask Macrocell Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 47. Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Ports A, B and C - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 29.Port A, B and C Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Port D - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 30.Port D Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Port E - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Port F - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Port G - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 31.Port E, F and G Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 A utomatic Power-down (APD) Unit and Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 48. Effect of Power-down Mode on Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 32.APD Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 49. PSD Timing and Stand-by Current during Power-down Mode . . . . . . . . . . . . . . . . . . . . 71 Other Power Saving Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 PLD Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 SRAM Stand-by Mode (Battery Backup) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 33.Enable Power-down Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 50. APD Counter Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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POWER-ON RESET, WARM RESET AND POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Power-On RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 W arm RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 I/O Pin, Register and PLD Status at RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 R eset of Flash Memory Erase and Program Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 51. Status During Power-On Reset, Warm Reset and Power-down Mode . . . . . . . . . . . . . . 74 Figure 34.Reset (RESET) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . 75 Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 JTAG Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Security and Flash memory Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 52. JTAG Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 AC/DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 35.PLD ICC /Frequency Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 53. Example of PSD Typical Power Calculation at VCC = 5.0V (with Turbo Mode On) . . . . . 78 Table 54. Example of PSD Typical Power Calculation at VCC = 5.0V (with Turbo Mode Off) . . . . . 79 Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 55. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 DC and AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 56. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 57. AC Signal Letters for PLD Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 58. AC Signal Behavior Symbols for PLD Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 59. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 60. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 36.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 37.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 38.Switching Waveforms - Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 61. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 39.Input to Output Disable / Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 62. CPLD Combinatorial Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 63. CPLD Macrocell Synchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 64. CPLD Macrocell Asynchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 40.Synchronous Clock Mode Timing - PLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 41.Asynchronous RESET / Preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 42.Asynchronous Clock Mode Timing (product term clock) . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 43.Input Macrocell Timing (product term clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 65. Input Macrocell Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 66. Program, WRITE and Erase Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 44.Peripheral I/O Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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Figure 45.READ Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 67. READ Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 46.WRITE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 68. WRITE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 47.Peripheral I/O Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 69. Port F Peripheral Data Mode Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 70. Port F Peripheral Data Mode Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure 48.Reset (RESET) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 71. Reset (RESET)Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 72. Power-down Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 73. VSTBYON Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Figure 49.ISC Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 74. ISC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Package Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 50.TQFP80 - 80-lead Plastic Thin, Quad, Flat Package Outline . . . . . . . . . . . . . . . . . . . . . 95 Table 75. TQFP80 - 80-lead Plastic Thin, Quad, Flat Package Mechanical Data. . . . . . . . . . . . . . 96 PAR T NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 76. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 APPENDIX A.PIN ASSIGNMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 77. PSD4235G2 TQFP80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 78. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
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SUMMARY DESCRIPTION The PSD family of memory systems for microcontrollers (MCUs) brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications. PSD devices integrate an optimized Macrocell logic architecture. The Macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices. The PSD family offers two methods to program the PSD Flash memory while the PSD is soldered to the circuit board: In-System Programming (ISP) via JTAG An IEEE 1149.1 compliant JTAG In-System Programming (ISP) interface is included on the PSD enabling the entire device (Flash memories, PLD, configuration) to be rapidly programmed while soldered to the circuit board. This requires no MCU participation, which means the PSD can be programmed anytime, even when completely blank. The innovative JTAG interface to Flash memories is an industry first, solving key problems faced by designers and manufacturing houses, such as: First time programming. H ow do I get firmware into the Flash memory the very first time? JTAG is the answer. Program the blank PSD with no MCU involvement. Inventory build-up of pre-programmed devices. How do I maintain an accurate count of preprogrammed Flash memory and PLD devices based on customer demand? How many and what version? JTAG is the answer. Build your hardware with blank PSDs soldered directly to the board and then custom program just before they are shipped to the customer. No more labels on chips, and no more wasted inventory. Expensive sockets. How do I eliminate the need for expensive and unreliable sockets? JTAG is the answer. Solder the PSD directly to the circuit board. Program first time and subsequent times with JTAG. No need to handle devices and bend the fragile leads.
In-Application Programming (IAP) Two independent Flash memory arrays are included so that the MCU can execute code from one while erasing and programming the other. Robust product firmware updates in the filed are possible over any communication channel (CAN, Ethernet, UAR T, J1850, etc) using this unique architecture. Designers are relieved of these problems: Simultaneous READ and WRITE to Flash memory. How can the MCU program the same memory from which it executing code? It cannot. The PSD allows the MCU to operate the two Flash memory blocks concurrently, reading code from one while erasing and programming the other during IAP. Complex memory mapping. How can I map these two memories efficiently? A programmable Decode PLD (DPLD) is embedded in the PSD. The concurrent PSD memories can be mapped anywhere in MCU address space, segment by segment with extermely high address resolution. As an option, the secondary Flash memory can be sw apped out of the system memory map when IAP is complete. A built-in page register breaks the MCU address limit. Separate Program and Data space. How can I write to Flash memory while it resides in Program space during field firmware updates? My 80C51XA will not allow it. The PSD provides means to reclassify Flash memory as Data space during IAP, then back to Program space when complete. PSDsoft Express PSDsoft Express, a software development tool from ST, guides you through the design process step-by-step making it possible to complete an embedded MCU design capable of ISP/IAP in just hours. Select your MCU and PSDsoft Express takes you through the remainder of the design with point and click entry, covering PSD selection, pin definitions, programmable logic inputs and outpus, MCU memory map definition, ANSI-C code generation for your MCU, and merging your MCU firmware with the PSD design. When complete, two different device programmers are supported directly from PSDsoft Express: FlashLINK (JTAG) and PSDpro.
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Figure 2. Logic Diagram
VCC
Table 1. Pin Names
PA0-PA7 PB0-PB7 Port-A Port-B Port-C Port-D Port-E Port-F Port-G Address/Data Control Reset Supply Voltage Ground
8 PA0-PA7 8 PB0-PB7 3 CNTL0CNTL2 4 PSD4xxxGx 16 AD0-AD15 8 RESET 8 PG0-PG7 PF0-PF7 8 PE0-PE7 PD0-PD3 8 PC0-PC7
PC0-PC7 PD0-PD3 PE0-PE7 PF0-PF7 PG0-PG7 AD0-AD15 CNTL0-CNTL2 RESET V CC VSS
VSS
AI04916
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PS D 4235G2
Figure 3. TQFP Connections
70 GND
69 VCC 68 PB7
80 PD1
79 PD0
67 PB6
66 PB5
65 PB4
64 PB3
63 PB2
62 PB1
PD2 1 PD3 2 AD0 3 AD1 4 AD2 5 AD3 6 AD4 7 GND 8 VCC 9 AD5 10 AD6 11 AD7 12 AD8 13 AD9 14 AD10 15 AD11 16 AD12 17 AD13 18 AD14 19 AD15 20
61 PB0
78 PE7
77 PE6
76 PE5
75 PE4
74 PE3
73 PE2
72 PE1
71 PE0
60 CNTL1 59 CNTL0 58 PA7 57 PA6 56 PA5 55 PA4 54 PA3 53 PA2 52 PA1 51 PA0 50 GND 49 GND 48 PC7 47 PC6 46 PC5 45 PC4 44 PC3 43 PC2 42 PC1 41 PC0
PG0 21
PG1 22
PG2 23
PG3 24
PG4 25
PG5 26
PG6 27
PG7 28
VCC 29 GND 30
PF0 31
PF1 32
PF2 33
PF3 34
PF4 35
PF5 36
PF6 37
PF7 38
RESET 39
CNTL2 40
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PIN DESCRIPTION Table 2. Pin Description (for the TQFP package)
Pin Name Pin Type Description This is the lower Address/Data port. Connect your MCU address or address/data bus according to the following rules: 1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect AD0-AD7 to this port. 2. If your MCU does not have a multiplexed address/data bus, connect A0-A7 to this port. 3. If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this port. ALE or AS latches the address. The PSD drives data out only if the READ signal is active and one of the PSD functional blocks has been selected. The addresses on this port are passed to the PLDs. This is the upper Address/Data port. Connect your MCU address or address/data bus according to the following rules: 1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the upper address bits, connect A8-A15 to this port. 2. If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this port. 3. If you are using an 80C51XA in burst mode, connect A12/D8 through A19/D15 to this port. ALE or AS latches the address. The PSD drives data out only if the READ signal is active and one of the PSD functional blocks has been selected. The addresses on this port are passed to the PLDs. The following control signals can be connected to this pin, based on your MCU: 1. WR - active Low, Write Strobe input. 2. R_W - active High, READ/active Low WRITE input. 3. WRL - active Low, WRITE to Low-byte. This pin is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. The following control signals can be connected to this pin, based on your MCU: 1. RD - active Low, Read Strobe input. 2. E - E clock input. 3. DS - active Low, Data Strobe input. 4. LDS - active Low, Strobe for low data byte. This pin is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. READ or other Control input pin, with multiple configurations. Depending on the MCU interface selected, this pin can be: 1. PSEN - Program Select Enable, active Low in code fetch bus cycle (80C51XA mode). 2. BHE - High-byte enable, 16-bit data bus. 3. UDS - active Low, Strobe for high data byte, 16-bit data bus mode. 4. SIZ0 - Byte enable input. 5. LSTRB - Low Strobe input. This pin is also connected to the PLDs. Active Low input. Resets I/O Ports, PLD Macrocells and some of the Configuration Registers and JTAG registers. Must be Low at Power-up. Reset also aborts any Flash memory Program or Erase cycle that is currently in progress. These pins make up Port A. These port pins are configurable and can have the following functions: 1. MCU I/O - standard output or input port. 2. CPLD Macrocell (McellA0-McellA7) outputs. 3. Latched, transparent or registered PLD inputs (can also be PLD input for address A16 and above).
ADIO0ADIO7
3-7 10-12
I/O
ADIO8ADIO15
13-20
I/O
CNTL0
59
I
CNTL1
60
I
CNTL2
40
I
Reset
39
I
PA0-PA7
51-58
I/O CMO S or Open Drain
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Pin Name Pin Type I/O CMO S or Open Drain I/O CMO S or Slew Rate I/O CMO S or Open Drain I/O CMO S or Open Drain I/O CMO S or Open Drain I/O CMO S or Open Drain I/O CMO S or Open Drain I/O CMO S or Open Drain I/O CMO S or Open Drain I/O CMO S or Open Drain Description These pins make up Port B. These port pins are configurable and can have the following functions: 1. MCU I/O - standard output or input port. 2. CPLD Macrocell (McellB0-McellB7) outputs. 3. Latched, transparent or registered PLD inputs (can also be PLD input for address A16 and above). These pins make up Port C. These port pins are configurable and can have the following functions: 1. MCU I/O - standard output or input port. 2. External Chip Select (ECS0-ECS7) outputs. 3. Latched, transparent or registered PLD inputs (can also be PLD input for address A16 and above). PD0 pin of Port D. This port pin can be configured to have the following functions: 1. ALE/AS input - latches address on ADIO0-ADIO15. 2. AS input - latches address on ADIO0-ADIO15 on the rising edge. 3. MCU I/O - standard output or input port. 4. Transparent PLD input (can also be PLD input for address A16 and above). PD1 pin of Port D. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Transparent PLD input (can also be PLD input for address A16 and above). 3. CLKIN - clock input to the CPLD Macrocells, the APD Unit's Power-down counter, and the CPLD AND Array. PD2 pin of Port D. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Transparent PLD input (can also be PLD input for address A16 and above). 3. PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory and I/O. When High, the PSD memory blocks are disabled to conserve power. The falling edge of this signal can be used to get the device out of Power-down mode. PD3 pin of Port D. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Transparent PLD input (can also be PLD input for address A16 and above). 3. WRH - for 16-bit data bus, WRITE to high byte, active low. PE0 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address output. 3. TMS Input for the JTAG Serial Interface. PE1 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address output. 3. TCK Input for the JTAG Serial Interface. PE2 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address output. 3. TDI input for the JTAG Serial Interface. PE3 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address output. 3. TDO output for the JTAG Serial Interface.
PB0-PB7
61-68
PC0-PC7
41-48
P D0
79
P D1
80
P D2
1
P D3
2
PE0
71
PE1
72
PE2
73
PE3
74
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Pin Name Pin Type I/O CMO S or Open Drain I/O CMO S or Open Drain I/O CMO S or Open Drain I/O CMO S or Open Drain Description PE4 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address output. 3. TSTAT output for the JTAG Serial Interface. 4. Ready/Busy output for parallel In-System Programming (ISP). PE5 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address output. 3. TERR active Low output for the JTAG Serial Interface. PE6 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address output. 3. VSTBY - SRAM stand-by voltage input for SRAM battery backup. PE7 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address output. 3. Battery-on Indicator (VBATON). Goes High when power is being drawn from the external battery. These pins make up Port F. These port pins are configurable and can have the following functions: 1. MCU I/O - standard output or input port. 2. External Chip Select (ECS0-ECS7) outputs, or inputs to CPLD. 3. Latched address outputs. 4. Address A1-A3 inputs in 80C51XA mode (PF0 is grounded) 5. Data bus port (D0-D7) in a non-multiplexed bus configuration. 6. Peripheral I/O mode. 7. MCU reset mode. These pins make up Port G. These port pins are configurable and can have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address outputs. 3. Data bus port (D8-D15) in a non-multiplexed bus configuration. 4. MCU reset mode. Supply Voltage
PE4
75
PE5
76
PE6
77
PE7
78
PF0-PF7
31-38
I/O CMO S or Open Drain
PG0-PG7
21-28
I/O CMO S or Open Drain
V CC
9, 29, 69 8, 30, 49, 50, 70
G ND
Ground pins
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ADDRESS/ DATA/CONTROL BUS
PLD INPUT BUS PAGE REGISTER EMBEDDED ALGORITHM 16 SECTORS 4 MBIT PRIMARY FLASH MEMORY
POWER MANGMT UNIT
VSTDBY (PE6 )
Figure 4. PSD Block Diagram
8
CNTL0, CNTL1, CNTL2 SECTOR SELECTS FLASH DECODE PLD (DPLD) 82 SECTOR SELECTS SRAM SELECT ADIO PORT CSIOP RUNTIME CONTROL AND I/O REGISTERS 8 EXT CS TO PORT C or F 16 OUTPUT MACROCELLS PORT A & B 24 INPUT MACROCELLS CLKIN PROG. PORT PORT G CLKIN MACROCELL FEEDBACK OR PORT INPUT PORT F PORT A ,B & C PERIP I/O MODE SELECTS 64 KBIT BATTERY BACKUP SRAM PROG. MCU BUS INTRF. 256 KBIT SECONDARY FLASH MEMORY (BOOT OR DATA) 4 SECTORS
AD0 AD15
PROG. PORT PORT A
PA0 PA7
PF0 PF7 PORT F
Note: Additional address lines can be brought in to the device via Port A, B, C, D or F.
PROG. PORT 82 FLASH ISP CPLD (CPLD) PROG. PORT PORT B PB0 PB7 PROG. PORT PORT C PC0 PC7 PROG. PORT PORT D PD0 PD3 CLKIN GLOBAL CONFIG. & SECURITY PLD, CONFIGURATION & FLASH MEMORY LOADER JTAG SERIAL CHANNEL PROG. PORT PORT E PE0 PE7
PG0 PG7
PS D 4235G2
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PSD ARCHITECTURAL OVERVIEW PSD devices contain several major functional blocks. Figure 4 shows the architecture of the PSD device family. The functions of each block are described briefly in the following sections. Many of the blocks perform multiple functions and are user configurable. Mem ory Each of the memory blocks is briefly discussed in the following paragraphs. A more detailed discussion can be found in the section entitled "Memory Blocks" on page 25. The 4 Mbit primary Flash memory is the main memory of the PSD. It is divided into 8 equallysized sectors that are individually selectable. The 256 Kbit secondary Flash memory is divided into 4 equally-sized sectors. Each sector is individually selectable. The 64 Kbit SRAM is intended for use as a scratch-pad memory or as an extension to the MCU SRAM. If an external battery is connected to the PSD's Voltage Stand-by (VSTBY, PE6) signal, data is retained in the event of power failure. Each memory block can be located in a different address space as defined by the user. The access times for all memory types includes the address latching and DPLD decoding time. PLDs The device contains two PLD blocks, the Decode PLD (DPLD) and the Complex PLD (CPLD), as shown in Table 3, each optimized for a different function. The functional partitioning of the PLDs reduces power consumption, optimizes cost/performance, and eases design entry. The DPLD is used to decode addresses and to generate Sector Select signals for the PSD internal memory and registers. The DPLD has combinatorial outputs, while the CPLD can implement more general user-defined logic functions. The CPLD has 16 Output Macrocells (OMC) and 8 combinatorial outputs. The PSD also has 24 Input Macrocells (IMC) that can be configured as inputs to the PLDs. The PLDs receive their inputs from the PLD Input Bus and are differentiated by their output destinations, number of product terms, and Macrocells. The PLDs consume minimal power. The speed and power consumption of the PLD is controlled by the Turbo Bit in PMMR0 and other bits in PMMR2. These registers are set by the MCU at
run-time. There is a slight penalty to PLD propagation time when not in the Turbo mode. I/O Ports The PSD has 52 I/O pins divided among seven ports (Port A, B, C, D, E, F and G). Each I/O pin can be individually configured for different functions. Ports can be configured as standard MCU I/ O ports, PLD I/O, or latched address outputs for MCUs using multiplexed address/data buses The JTAG pins can be enabled on Port E for InSystem Programming (ISP). MCU Bus Interface The PSD easily interfaces easily with most 16-bit MCUs, either with multiplexed or non-multiplexed address/data buses. The device is configured to respond to the MCU's control pins, which are also used as inputs to the PLDs. ISP via JTAG Port In-System Programming (ISP) can be performed through the JTAG signals on Port E. This serial interface allows complete programming of the entire PSD device. A blank device can be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can be multiplexed with other functions on Port E. Table 4 indicates the JTAG pin assignments. Table 3. PLD I/O
Name Decode PLD (DPLD) Complex PLD (CPLD) Inputs 82 82 Outputs 17 24 Product Terms 43 150
Table 4. JTAG SIgnals on Port E
Port E Pins PE0 PE1 PE2 PE3 PE4 PE5 TM S TC K TD I TD O TSTAT TERR JTAG Signal
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In-System Programming (ISP) Using the JTAG signals on Port E, the entire PSD device (memory, logic, configuration) can be programmed or erased without the use of the MCU. In-Application Programming (IAP) The primary Flash memory can also be programmed, or re-programmed, in-system by the MCU executing the programming algorithms out of the secondary Flash memory, or SRAM. The secondary Flash memory can be programmed the same way by executing out of the primary Flash memory. Table 5 indicates which programming methods can program different functional blocks of the PSD. Page Register The 8-bit Page Register expands the address range of the MCU by up to 256 times. The paged address can be used as part of the address space to access external memory and peripherals, or internal memory and I/O. The Page Register can also be used to change the address mapping of the Flash memory blocks into different memory spaces for IAP. Power Management Unit (PMU) The Power Management Unit (PMU) gives the user control of the power consumption on selected functional blocks based on system requirements. The PMU includes an Automatic Power-down (APD) Unit that turns off device functions during MCU inactivity. The APD Unit has a Power-down mode that helps reduce power consumption. The PSD also has some bits that are configured at run-time by the MCU to reduce power consumption of the CPLD. The Turbo Bit in PMMR0 can be reset to '0' and the CPLD latches its outputs and goes to Stand-by mode until the next transition on its inputs. Additionally, bits in PMMR2 can be set by the MCU to block signals from entering the CPLD to reduce power consumption. See the section entitled "Power Management" on page 70 for more details.
Table 5. Methods of Programming Different Functional Blocks of the PSD
Functional Block Primary Flash Memory Secondary Flash memory PLD Array (DPLD and CPLD) PSD Configuration JTAG-ISP Yes Yes Yes Yes Device Programmer Yes Yes Yes Yes IAP Yes Yes No No
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DEVELOPMENT SYSTEM The PSD family is supported by PSDsoft Express, a Windows-based software development tool (Windows-95, Windows-98, Windows-2000, Windows-NT). A PSD design is quickly and easily produced in a point and click environment. The designer does not need to enter Hardware Description Language (HDL) equations, unless desired, to define PSD pin functions and memory map information. The general design flow is shown in Figure 5. PSDsoft Express is available from our web site (the address is given on the back page of this data sheet) or other distribution channels. Figure 5. PSDsoft Express Development Tool
Choose MCU and PSD
Automatically configures MCU bus interface and other PSD attributes
PSDsoft Express directly supports two low cost device programmers form ST: PSDpro and FlashLINK (JTAG). Both of these programmers may be purchased through your local distributor/ representative, or directly from our web site using a credit card. The PSD is also supported by thid party device programmers. See our web site for the current list.
Define PSD Pin and Node Functions
Point and click definition of PSD pin functions, internal nodes, and MCU system memory map
Define General Purpose Logic in CPLD
Point and click definition of combinatorial and registered logic in CPLD. Access HDL is available if needed
C Code Generation
GENERATE C CODE SPECIFIC TO PSD FUNCTIONS
Merge MCU Firmware with PSD Configuration
A composite object file is created containing MCU firmware and PSD configuration
MCU FIRMWARE HEX OR S-RECORD FORMAT
USER'S CHOICE OF MICROCONTROLLER COMPILER/LINKER
*.OBJ FILE
PSD Programmer
PSDPro, or FlashLINK (JTAG)
*.OBJ FILE AVAILABLE FOR 3rd PARTY PROGRAMMERS (CONVENTIONAL or JTAG-ISC)
AI04919
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PSD REGISTER DESCRIPTION AND ADDRESS OFFSETS Table 6 shows the offset addresses to the PSD Table 6 provides brief descriptions of the registers registers relative to the CSIOP base address. The in CSIOP space. The following sections give a CSIOP space is the 256 bytes of address that is almore detailed description. located by the user to the internal PSD registers. Table 6. Register Address Offset
Register Name Data In Control Data Out Direction Drive Select Input Macrocell Enable Out Output Macrocells A Output Macrocells B Mask Macrocells A Mask Macrocells B Flash Memory Protection Flash Boot Protection JTAG Enable PMMR0 PMMR2 Page VM 22 23 C0 04 06 08 0A 0C 20 21 05 07 09 0B 0D 1C 14 16 18 15 17 19 1A 4C Port A 00 Port B 01 Port C 10 Port D 11 Port E 30 32 34 36 38 Port F 40 42 44 46 48 Port G 41 43 45 47 49 Other(1) Description Reads Port pin as input, MCU I/O input mode Selects mode between MCU I/O or Address Out Stores data for output to Port pins, MCU I/O output mode Configures Port pin as input or output Configures Port pins as either CMOS or Open Drain on some pins, while selecting high slew rate on other pins. Reads Input Macrocells Reads the status of the output enable to the I/O Port driver READ - reads output of Macrocells A WRITE - loads Macrocell Flip-flops READ - reads output of Macrocells B WRITE - loads Macrocell Flip-flops Blocks writing to the Output Macrocells A Blocks writing to the Output Macrocells B Read only - Primary Flash Sector Protection Read only - PSD Security and Secondary Flash memory Sector Protection Enables JTAG Port Power Management Register 0 Power Management Register 2 Page Register Places PSD memory areas in Program and/or Data space on an individual basis. Read only - SRAM and Primary memory size Read only - Secondary memory type and size
C2 C7 B0 B4 E0 E2
Memory_ID0 Memory_ID1
Note: 1. Other registers that are not part of the I/O ports.
F0 F1
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REGISTER BIT DEFINITION All the registers of the PSD are included here, for reference. Detailed descriptions of these registers can be found in the following sections. Table 7. Data-In Registers - Ports A, B, C, D, E, F, G
B it 7 Port pin 7 Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0
Note: Bit Definitions (Read-only registers): Read Port pin status when Port is in MCU I/O input mode.
Table 8. Data-Out Registers - Ports A, B, C, D, E, F, G
B it 7 Port pin 7 Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0
Note: Bit Definitions: Latched data for output to Port pin when pin is configured in MCU I/O output mode.
Table 9. Direction Registers - Ports A, B, C, D, E, F, G
B it 7 Port pin 7 Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0
Note: Bit Definitions: Port pin 0 = Port pin is configured in Input mode (default). Port pin 1 = Port pin is configured in Output mode.
Table 10. Control Registers - Ports E, F, G
B it 7 Port pin 7 Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0
Note: Bit Definitions: Port pin 0 = Port pin is configured in MCU I/O mode (default). Port pin 1 = Port pin is configured in Latched Address Out mode.
Table 11. Drive Registers - Ports A, B, D, E, G
B it 7 Port pin 7 Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0
Note: Bit Definitions: Port pin 0 = Port pin is configured for CMOS Output driver (default). Port pin 1 = Port pin is configured for Open Drain output driver.
Table 12. Drive Registers - Ports C, F
B it 7 Port pin 7 Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0
Note: Bit Definitions: Port pin 0 = Port pin is configured for CMOS Output driver (default). Port pin 1 = Port pin is configured in Slew Rate mode.
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Table 13. Enable-Out Registers - Ports A, B, C, F
B it 7 Port pin 7 Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0
Note: Bit Definitions (Read-only registers): Port pin 0 = Port pin is in tri-state driver (default). Port pin 1 = Port pin is enabled.
Table 14. Input Macrocells - Ports A, B, C
B it 7 IM cell 7 Bit 6 IMcell 6 Bit 5 IMcell 5 Bit 4 IMcell 4 Bit 3 IMcell 3 Bit 2 IMcell 2 Bit 1 IMcell 1 Bit 0 IMcell 0
Note: Bit Definitions (Read-only registers): Read Input Macrocell (IMC7-IMC0) status on Ports A, B and C.
Table 15. Output Macrocells A Register
B it 7 Mcella 7 Bit 6 Mcella 6 Bit 5 Mcella 5 Bit 4 Mcella 4 Bit 3 Mcella 3 Bit 2 Mcella 2 Bit 1 Mcella 1 Bit 0 Mcella 0
Note: Bit Definitions: Write Register: Load MCellA7-MCellA0 with 0 or 1. Read Register: Read MCellA7-MCellA0 output status.
Table 16. Output Macrocells B Register
B it 7 Mcellb 7 Bit 6 Mcellb 6 Bit 5 Mcellb 5 Bit 4 Mcellb 4 Bit 3 Mcellb 3 Bit 2 Mcellb 2 Bit 1 Mcellb 1 Bit 0 Mcellb 0
Note: Bit Definitions: Write Register: Load MCellB7-MCellB0 with 0 or 1. Read Register: Read MCellB7-MCellB0 output status.
Table 17. Mask Macrocells A Register
B it 7 Mcella 7 Bit 6 Mcella 6 Bit 5 Mcella 5 Bit 4 Mcella 4 Bit 3 Mcella 3 Bit 2 Mcella 2 Bit 1 Mcella 1 Bit 0 Mcella 0
Note: Bit Definitions: McellA_Prot 0 = Allow MCellA flip-flop to be loaded by MCU (default). McellA_Prot 1 = Prevent MCellA flip-flop from being loaded by MCU.
Table 18. Mask Macrocells B Register
B it 7 Mcellb 7 Bit 6 Mcellb 6 Bit 5 Mcellb 5 Bit 4 Mcellb 4 Bit 3 Mcellb 3 Bit 2 Mcellb 2 Bit 1 Mcellb 1 Bit 0 Mcellb 0
Note: Bit Definitions: McellB_Prot 0 = Allow MCellB flip-flop to be loaded by MCU (default). McellB_Prot 1 = Prevent MCellB flip-flop from being loaded by MCU.
Table 19. Flash Memory Protection Register
B it 7 Sec7_Prot Bit 6 Sec6_Prot Bit 5 Sec5_Prot Bit 4 Sec4_Prot Bit 3 Sec3_Prot Bit 2 Sec2_Prot Bit 1 Sec1_Prot Bit 0 Sec0_Prot
Note: Bit Definitions (Read-only register): Sec_Prot 1 = Primary Flash memory Sector is write protected. Sec_Prot 0 = Primary Flash memory Sector is not write protected.
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Table 20. Flash Boot Protection Register
B it 7 Security_Bit Bit 6 not used Bit 5 not used Bit 4 not used Bit 3 Sec3_Prot Bit 2 Sec2_Prot Bit 1 Sec1_Prot Bit 0 Sec0_Prot
Note: Bit Definitions: Sec_Prot 1 = Secondary Flash memory Sector is write protected. Sec_Prot 0 = Secondary Flash memory Sector is not write protected. Security_Bit 0 = Security Bit in device has not been set. Security_Bit 1 = Security Bit in device has been set.
Table 21. JTAG Enable Register
B it 7 not used Bit 6 not used Bit 5 not used Bit 4 not used Bit 3 not used Bit 2 not used Bit 1 not used Bit 0 JTAGEnable
Note: Bit Definitions: JTAGEnable 1 = JTAG Port is enabled. JTAGEnable 0 = JTAG Port is disabled.
Table 22. Page Register
B it 7 PGR 7 Bit 6 PGR 6 Bit 5 PGR 5 Bit 4 PGR 4 Bit 3 PGR 3 Bit 2 PGR 2 Bit 1 PGR 1 Bit 0 PGR 0
Note: Bit Definitions: Configure Page input to PLD. Default is PGR7-PGR0=0.
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Table 23. PMMR0 Register
B it 7 not used (set to '0') Bit 6 not used (set to '0') Bit 5 PLD MCells CLK Bit 4 PLD Array CLK Bit 3 PLD Turbo Bit 2 not used (set to '0') Bit 1 APD Enable Bit 0 not used (set to '0')
Note: The bits of this register are cleared to zero following Power-up. Subsequent Reset (Reset) pulses do not clear the registers. Note: Bit Definitions: APD Enable 0 = Automatic Power-down (APD) is disabled. 1 = Automatic Power-down (APD) is enabled. PLD Turbo 0 = PLD Turbo is on. 1 = PLD Turbo is off, saving power. PLD Array CLK 0 = CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo bit is off. 1 = CLKIN to the PLD AND array is disconnected, saving power. PLD MCells CLK 0 = CLKIN to the PLD Macrocells is connected. 1 = CLKIN to the PLD Macrocells is disconnected, saving power.
Table 24. PMMR2 Register
B it 7 not used (set to '0') Bit 6 PLD Array WRH Bit 5 PLD Array ALE Bit 4 PLD Array CNTL2 Bit 3 PLD Array CNTL1 Bit 2 PLD Array CNTL0 Bit 1 not used (set to '0') Bit 0 PLD Array Addr
Note: For Bit 4, Bit 3, Bit 2: See Table 34 for the signals that are blocked on pins CNTL0-CNTL2. Note: Bit Definitions: PLD Array Addr 0 = Address A7-A0 are connected to the PLD array. 1 = Address A7-A0 are blocked from the PLD array, saving power. (Note: in XA mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7-ADIO4) PLD Array CNTL2 0 = CNTL2 input to the PLD AND array is connected. 1 = CNTL2 input to the PLD AND array is disconnected, saving power. PLD Array CNTL1 0 = CNTL1 input to the PLD AND array is connected. 1 = CNTL1 input to the PLD AND array is disconnected, saving power. PLD Array CNTL0 0 = CNTL0 input to the PLD AND array is connected. 1 = CNTL0 input to the PLD AND array is disconnected, saving power. PLD Array ALE 0 = ALE input to the PLD AND array is connected. 1 = ALE input to the PLD AND array is disconnected, saving power. PLD Array WRH 0 = WRH/DBE input to the PLD AND array is connected. 1 = WRH/DBE input to the PLD AND array is disconnected, saving power.
Table 25. VM Register
B it 7 Peripheral mode Bit 6 not used (set to '0') Bit 5 not used (set to '0') Bit 4 FL_data Bit 3 Boot_data Bit 2 FL_code Bit 1 Boot_code Bit 0 SR_code
Note: On reset, Bit1-Bit4 are loaded to configurations that are selected by the user in PSDsoft Express. Bit0 and Bit7 are always cleared on reset. Bit0-Bit4 are active only when the device is configured in Philips 80C51XA mode. Note: Bit Definitions: SR_code 0 = PSEN cannot access SRAM in 80C51XA modes. 1 = PSEN can access SRAM in 80C51XA modes. Boot_code 0 = PSEN cannot access Secondary NVM in 80C51XA modes. 1 = PSEN can access Secondary NVM in 80C51XA modes. FL_code 0 = PSEN cannot access Primary Flash memory in 80C51XA modes. 1 = PSEN can access Primary Flash memory in 80C51XA modes. Boot_data 0 = RD cannot access Secondary NVM in 80C51XA modes. 1 = RD can access Secondary NVM in 80C51XA modes. FL_data 0 = RD cannot access Primary Flash memory in 80C51XA modes. 1 = RD can access Primary Flash memory in 80C51XA modes. Peripheral mode 0 = Peripheral mode of Port F is disabled. 1 = Peripheral mode of Port F is enabled.
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Table 26. Memory_ID0 Register
B it 7 S_size 3 Bit 6 S_size 2 Bit 5 S_size 1 Bit 4 S_size 0 Bit 3 F_size 3 Bit 2 F_size 2 Bit 1 F_size 1 Bit 0 F_size 0
Note: Bit Definitions: F_size[3:0]
0h = There is no Primary Flash memory 1h = Primary Flash memory size is 256 Kbit 2h = Primary Flash memory size is 512 Kbit 3h = Primary Flash memory size is 1 Mbit 4h = Primary Flash memory size is 2 Mbit 5h = Primary Flash memory size is 4 Mbit 6h = Primary Flash memory size is 8 Mbit S_size[3:0] 0h = There is no SRAM 1h = SRAM size is 16 Kbit 2h = SRAM size is 32 Kbit 3h = SRAM size is 64 Kbit 4h = SRAM size is 128 Kbit 5h = SRAM size is 256 Kbit
Table 27. Memory_ID1 Register
B it 7 not used (set to '0') Bit 6 not used (set to '0') Bit 5 B_type 1 Bit 4 B_type 0 Bit 3 B_size 3 Bit 2 B_size 2 Bit 1 B_size 1 Bit 0 B_size 0
Note: Bit Definitions: B_size[3:0] 0h = There is no Secondary NVM 1h = Secondary NVM size is 128 Kbit 2h = Secondary NVM size is 256 Kbit 3h = Secondary NVM size is 512 Kbit B_type[1:0] 0h = Secondary NVM is Flash memory 1h = Secondary NVM is EEPROM
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DETAILED OPERATION As shown in Figure 4, the PSD consists of six major types of functional blocks: Memory Blocks PLD Blocks MCU Bus Interface I/O Ports Power Management Unit (PMU) JTAG-ISP Interface The functions of each block are described in the following sections. Many of the blocks perform multiple functions, and are user configurable. Table 28. Memory Block Size and Organization
Primary Flash Memory Sector Number 0 1 2 3 4 5 6 7 Totals Sector Size (x16) 32K 32K 32K 32K 32K 32K 32K 32K 512KByte Sector Select Signal FS0 FS1 FS2 FS3 FS4 FS5 FS6 FS7 8 Sectors 32KByte 4 Sectors 8KByte Secondary Flash Memory Sector Size (x16) 4K 4K 4K 4K Sector Select Signal CSBOOT0 CSBOOT1 CSBOOT2 CSBOOT3 SRAM SRAM Size (x16) 4K SRAM Select Signal RS0
Mem ory Blocks The PSD has the following memory blocks: Primary Flash memory Secondary Flash memory S RA M The Memory Select signals for these blocks originate from the Decode PLD (DPLD) and are userdefined in PSDsoft Express. Table 28 sumamarizes the sizes and organisations of the memory blocks.
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Primary Flash Memory and Secondary Flash memory Description being erased. The output is a '1' (Ready) when no The primary Flash memory is divided evenly into 8 sectors. The secondary Flash memory is divided WRITE or Erase cycle is in progress. evenly into 4 sectors. Each sector of either memoMem ory Operation ry block can be separately protected from Program The primary Flash memory and secondary Flash and Erase cycles. memory are addressed through the MCU Bus InFlash memory may be erased on a sector-by-secterface. The MCU can access these memories in tor basis, and programmed word-by-word. Flash one of two ways: sector erasure may be suspended while data is The MCU can execute a typical bus WRITE or read from other sectors of the block and then reREAD operation just as it would if accessing a sumed after reading. RAM or ROM device using standard bus During a Program or Erase cycle in Flash memory, cycles. the status can be output on the Ready/Busy pin The MCU can execute a specific instruction (PE4). This pin is set up using PSDsoft Express. that consists of several WRITE and READ Mem ory Block Select Signals. The DPLD genoperations. This involves writing specific data erates the Select signals for all the internal memopatterns to special addresses within the Flash ry blocks (see the section entitled "PLDS", on page memory to invoke an embedded algorithm. 38). Each of the sectors of the primary Flash memThese instructions are summarized in Table ory has a Select signal (FS0-FS7) which can con29. tain up to three product terms. Each of the sectors Typically, the MCU can read Flash memory using of the secondary Flash memory has a Select sigREAD operations, just as it would read a ROM denal (CSBOOT0-CSBOOT3) which can contain up vice. However, Flash memory can only be erased to three product terms. Having three product terms and programmed using specific instructions. For for each Select signal allows a given sector to be example, the MCU cannot write a single byte dimapped in different areas of system memory. rectly to Flash memory as one would write a byte When using a MCU with separate Program and to RAM. To program a word into Flash memory, Data space (80C51XA), these flexible Select sigthe MCU must execute a Program instruction, then nals allow dynamic re-mapping of sectors from test the status of the Programming event. This staone memory space to the other before and after tus test is achieved by a READ operation or polling IAP. The SRAM block has a single Select signal Ready/Busy (PE4). (RS0). Flash memory can also be read by using special Ready/Busy (PE4). This signal can be used to instructions to retrieve particular Flash device inoutput the Ready/Busy status of the PSD. The outformation (sector protect status and ID). put is a '0' (Busy) when a Flash memory block is being written to, or when a Flash memory block is
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Table 29. Instructions
Instruction14 READ5 Read Main Flash ID6 Read Sector Protection6,8,13 Program a Flash Word13 Flash Sector Erase7,13 Flash Bulk Erase13 Suspend Sector Erase11 Resume Sector Erase12 Reset6 Unlock Bypass Unlock Bypass Program9 Unlock Bypass Reset10 FS0-FS7 or CSBOOT0CSBOOT3 1 1 Cycle 1 "Read" RD @ RA AAh@ XAAAh AAh@ XAAAh AAh@ XAAAh AAh@ XAAAh AAh@ XAAAh B0h@ XXXXh 30h@ XXXXh F0h@ XXXXh AAh@ XAAAh A0h@ XXXXh 90h@ XXXXh 55h@ X554h PD@ PA 00h@ XXXXh 20h@ XAAAh 55h@ X554h 55h@ X554h 55h@ X554h 55h@ X554h 55h@ X554h 90h@ XAAAh 90h@ XAAAh A0h@ XAAAh 80h@ XAAAh 80h@ XAAAh Read ID @ XX02h Read 00h or 01h @ XX04h PD@ PA AAh@ XAAAh AAh@ XAAAh 55h@ X554h 55h@ X554h 30h@ SA 10h@ XAAAh 30h7@ next SA Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7
1
1 1 1 1 1 1 1 1 1
Note: 1. All bus cycles are WRITE bus cycles, except the ones with the "Read" label 2. All values are in hexadecimal: X = Don't Care. Addresses of the form XXXXh, in this table, must be even addresses RA = Address of the memory location to be read RD = Data read from location RA during the READ cycle PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR, CNTL0). PA is an even address for PSD in word programming mode. PD = Data word to be programmed at location PA. Data is latched on the rising edge of Write Strobe (WR, CNTL0) SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector to be erased, or verified, must be Active (High). 3. Sector Select (FS0 to FS7 or CSBOOT0 to CSBOOT3) signals are active High, and are defined in PSDsoft Express. 4. Only address bits A11-A0 are used in instruction decoding. 5. No Unlock or instruction cycles are required when the device is in the READ mode 6. The Reset instruction is required to return to the READ mode after reading the Flash ID, or after reading the Sector Protection Status, or if the Error Flag Bit (DQ5/DQ13) goes High. 7. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80s. 8. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and (A1,A0)=(1,0) 9. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction. 10. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass mode. 11. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle. 12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode. 13. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the Sector Protection Status of the primary Flash memory. 14. All WRITE bus cycles in an instruction are byte WRITE to an even address (XA4Ah or X554h). A Flash memory Program bus cycle writes a word to an even address.
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INSTRUCTIONS An instruction consists of a sequence of specific operations. Each received byte is sequentially decoded by the PSD and not executed as a standard WRITE operation. The instruction is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the time-out period. Some instructions are structured to include READ operations after the initial WRITE operations. The instruction must be followed exactly. Any invalid combination of instruction bytes or time-out between two consecutive bytes while addressing Flash memory resets the device logic into READ mode (Flash memory is read like a ROM device). The PSD supports the instructions summarized in Table 29: Erase memory by chip or sector Suspend or resume sector erase Program a Word R eset to READ mode R ead primary Flash Identifier value R ead Sector Protection Status B y pas s These instructions are detailed in Table 29., page 27. For efficient decoding of the instructions, the first two bytes of an instruction are the coded cycles and are followed by an instruction byte or confirmation byte. The coded cycles consist of writing the data AAh to address XAAAh during the first cycle and data 55h to address X554h during the second cycle (unless the Bypass instruction feature is used, as described later). Address signals A15A12 are Don't Care during the instruction WRITE cycles. However, the appropriate Sector Select signal (FS0-FS7, or CSBOOT0-CSBOOT3) must be selected. The primary and secondary Flash memories have the same instruction set (except for Read Primary Flash Identifier). The Sector Select signals determine which Flash memory is to receive and execute the instruction. The primary Flash memory is selected if any one of its Sector Select signals (FS0-FS7) is High, and the secondary Flash memory is selected if any one of its Sector Select signals (CSBOOT0-CSBOOT3) is High.
Power-up Condition The PSD internal logic is reset upon Power-up to the READ mode. Sector Select (FS0-FS7 and CSBOOT0-CSBOOT3) must be held Low, and Write Strobe (WR/WRL, CNTL0) High, during Power-up for maximum security of the data contents and to remove the possibility of data being written on the first edge of Write Strobe (WR/WRL, CNTL0). Any WRITE cycle initiation is locked when VCC is below VLKO. Reading Flash Memory Under typical conditions, the MCU may read the primary Flash memory, or secondary Flash memory, using READ operations just as it would a ROM or RAM device. Alternately, the MCU may use READ operations to obtain status information about a Program or Erase cycle that is currently in progress. Lastly, the MCU may use instructions to read special data from these memory blocks. The following sections describe these READ functions. Read Memory Contents Primary Flash memory and secondary Flash memory are placed in the READ mode after Power-up, chip reset, or a Reset Flash instruction (see Table 29). The MCU can read the memory contents of the primary Flash memory, or the secondary Flash memory by using READ operations any time the READ operation is not part of an instruction. Read Primary Flash Identifier The primary Flash memory identifier is read with an instruction composed of 4 operations: 3 specific WRITE operations and a READ operation (see Table 29). The identifier for the primary Flash memory is E8h. The secondary Flash memory does not support this instruction. Read Memory Sector Protection Status The Flash memory Sector Protection Status is read with an instruction composed of four operations: three specific WRITE operations and a READ operation (see Table 29). The READ operation produces 01h if the Flash memory sector is protected, or 00h if the sector is not protected. The sector protection status for all NVM blocks (primary Flash memory, or secondary Flash memory) can be read by the MCU accessing the Flash Protection and Flash Boot Protection registers in PSD I/O space. See the section entitled "Flash Memory Sector Protect", on page 34, for register definitions.
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Reading the Erase/Program Status Bits The PSD provides several status bits to be used by the MCU to confirm the completion of an Erase or Program cycle of Flash memory. These status bits minimize the time that the MCU spends performing these tasks and are defined in Table 30. The status byte resides in an even location, and can be read as many times as needed. Also note
that DQ15-DQ8 is an even byte for Motorola MCUs with a 16-bit data bus. For Flash memory, the MCU can perform a READ operation to obtain these status bits while an Erase or Program instruction is being executed by the embedded algorithm. See the section entitled "PROGRAMMING FLASH MEMORY", on page 31, for details.
Table 30. Status Bits
DQ7 Data Polling DQ6 Toggle Flag DQ5 Error Flag DQ4 X DQ3 Erase Timeout DQ2 X DQ1 X DQ 0 X
Table 31. Status Bits for Motorola
DQ15 Data Polling DQ14 Toggle Flag DQ13 Error Flag DQ12 X DQ11 Erase Timeout DQ10 X DQ9 X DQ 8 X
Note: 1. X = Not guaranteed value, can be read either 1 or 0. 2. DQ15-DQ0 represent the Data Bus bits, D15-D0. 3. FS0-FS7/CSBOOT0-CSBOOT3 are active High.
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Data Polling (DQ7) - DQ15 for Motorola When erasing or programming in Flash memory, the Data Polling Bit (DQ7/DQ15) outputs the complement of the bit being entered for programming/ writing on the DQ7/DQ15 Bit. Once the Program instruction or the WRITE operation is completed, the true logic value is read on the Data Polling Bit (DQ7/DQ15, in a READ operation). D ata Polling is effective after the fourth WRITE pulse (for a Program instruction) or after the sixth WRITE pulse (for an Erase instruction). It must be performed at the address being programmed or at an address within the Flash memory sector being erased. D uring an Erase cycle, the Data Polling Bit (DQ7/DQ15) outputs a '0.' After completion of the cycle, the Data Polling Bit (DQ7/DQ15) outputs the last bit programmed (it is a '1' after erasing). If the location to be programmed is in a protected Flash memory sector, the instruction is ignored. If all the Flash memory sectors to be erased are protected, the Data Polling Bit (DQ7/ D Q15) is reset to '0' for about 100s, and then returns to the value from the previously addressed location. No erasure is performed. Toggle Flag (DQ6) - DQ14 for Motorola The PSD offers another way for determining when the Flash memory Program cycle is completed. During the internal WRITE operation and when either FS0-FS7 or CSBOOT0-CSBOOT3 is true, the Toggle Flag Bit (DQ6/DQ14) bit toggles from 0 to '1' and 1 to '0' on subsequent attempts to read any word of the memory. When the internal cycle is complete, the toggling stops and the data read on the Data Bus D0-D7 is the value from the addressed memory location. The device is now accessible for a new READ or WRITE operation. The cycle is finished when two successive READs yield the same output data.
The Toggle Flag Bit (DQ6/DQ14) is effective after the fourth WRITE pulse (for a Program instruction) or after the sixth WRITE pulse (for an Erase instruction). If the location to be programmed belongs to a protected Flash memory sector, the instruction is ignored. If all the Flash memory sectors selected for erasure are protected, the Toggle Flag Bit (DQ6/DQ14) toggles to '0' for about 100s and then returns to the value from the previously addressed location. Error Flag (DQ5) - DQ13 for Motorola During a normal Program or Erase cycle, the Error Flag Bit (DQ5/DQ13) is reset to '0.' This bit is set to '1' when there is a failure during a Flash memory Program, Sector Erase, or Bulk Erase cycle. In the case of Flash memory programming, the Error Flag Bit (DQ5/DQ13) indicates the attempt to program a Flash memory bit, or bits, from the programmed state, 0, to the erased state, 1, which is not a valid operation. The Error Flag Bit (DQ5/ DQ13) may also indicate a Time-out condition while attempting to program a word. In case of an error in a Flash memory Sector Erase or Word Program cycle, the Flash memory sector in which the error occurred or to which the programmed location belongs must no longer be used. Other Flash memory sectors may still be used. The Error Flag Bit (DQ5/DQ13) is reset after a Reset instruction. A Reset instruction is required after detecting an error on the Error Flag Bit (DQ5/ DQ13). Erase Time-out Flag (DQ3) - DQ11 for Motorola The Erase Time-out Flag Bit (DQ3/DQ11) reflects the time-out period allowed between two consecutive Sector Erase instructions. The Erase Time-out Flag Bit (DQ3/DQ11) is reset to '0' after a Sector Erase cycle for a period of 100s + 20% unless an additional Sector Erase instruction is decoded. After this period, or when the additional Sector Erase
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PROGRAMMING FLASH MEMORY Flash memory must be erased prior to being programmed. The MCU may erase Flash memory all at once or by-sector. Although erasing Flash memory occurs on a sector or device basis, programming Flash memory occurs on a word basis. The primary and secondary Flash memories require the MCU to send an instruction to program a word or to erase sectors (see Table 29). Once the MCU issues a Flash memory Program or Erase instruction, it must check the status bits for completion. The embedded algorithms that are invoked inside the PSD support several means to provide status to the MCU. Status may be checked using any of three methods: Data Polling, Data Toggle, or Ready/Busy (PE4) signal. Data Polling Polling on the Data Polling Bit (DQ7/DQ15) is a method of checking whether a Program or Erase cycle is in progress or has completed. Figure 6 shows the Data Polling algorithm. When the MCU issues a Program instruction, the embedded algorithm within the PSD begins. The MCU then reads the location of the word to be programmed in Flash memory to check the status. The Data Polling Bit (DQ7/DQ15) becomes the complement of the corresponding bit of the original data word to be programmed. The MCU continues to poll this location, comparing data and monitoring the Error Flag Bit (DQ5/DQ13). When the Data Polling Bit (DQ7/DQ15) matches the corresponding bit of the original data, and the Error Flag Bit (DQ5/DQ13) remains 0, the embedded algorithm is complete. If the Error Flag Bit (DQ5/DQ13) is 1, the MCU should test the Data Polling Bit (DQ7/ DQ15) again since the Data Polling Bit (DQ7/ DQ15) may have changed simultaneously with the Error Flag Bit (DQ5/DQ13, see Figure 6). The Error Flag Bit (DQ5/DQ13) is set if either an internal time-out occurred while the embedded algorithm attempted to program the location or if the MCU attempted to program a '1' to a bit that was not erased (not erased is logic 0). It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed, to compare the word that was written to the Flash memory with the word that was intended to be written. When using the Data Polling method during an Erase cycle, Figure 6 still applies. However, the Data Polling Bit (DQ7/DQ15) is 0 until the Erase
cycle is complete. A '1' on the Error Flag Bit (DQ5/ DQ13) indicates a time-out condition on the Erase cycle, a '0' indicates no error. The MCU can read any even location within the sector being erased to get the Data Polling Bit(DQ7/DQ15) and the Error Flag Bit (DQ5/DQ13). PSDsoft Express generates ANSI C code functions that implement these Data Polling algorithms. Figure 6. Data Polling Flowchart
START
READ DQ5 and DQ7 (DQ13 and DQ15) at Valid Even Address
DQ7 (DQ15) = Data7 (Data15) No
Yes
No
DQ5 (DQ13) =1 Yes READ DQ7 (DQ15)
DQ7 (DQ15) = Data7 (Data15) No Program or Erase Cycle failed
Yes
Program or Erase Cycle is complete
Issue RESET instruction
AI04920
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Data Toggle Checking the Toggle Flag Bit (DQ6/DQ14) is another method of determining whether a Program or Erase cycle is in progress or has completed. Figure 7 shows the Data Toggle algorithm. When the MCU issues a Program instruction, the embedded algorithm within the PSD begins. The MCU then reads the location to be programmed in Flash memory to check the status. The Toggle Flag Bit (DQ6/DQ14) toggles each time the MCU reads this location until the embedded algorithm is complete. The MCU continues to read this location, checking the Toggle Flag Bit (DQ6/DQ14) and monitoring the Error Flag Bit (DQ5/DQ13). When the Toggle Flag Bit (DQ6/DQ14) stops toggling (two consecutive READs yield the same value), and the Error Flag Bit (DQ5/DQ13) remains 0, the embedded algorithm is complete. If the Error Flag Bit (DQ5/DQ13) is 1, the MCU should test the Toggle Flag Bit (DQ6/DQ14) again, since the Toggle Flag Bit (DQ6/DQ14) may have changed simultaneously with the Error Flag Bit (DQ5/DQ13, see Figure 7). The Error Flag Bit (DQ5/DQ13) is set if either an internal time-out occurred while the embedded algorithm attempted to program, or if the MCU attempted to program a '1' to a bit that was not erased (not erased is logic 0). It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed, to compare the word that was written to Flash memory with the word that was intended to be written. When using the Data Toggle method after an Erase cycle, Figure 7 still applies. the Toggle Flag Bit (DQ6/DQ14) toggles until the Erase cycle is complete. A '1' on the Error Flag Bit (DQ5/DQ13) indicates a time-out condition on the Erase cycle, a '0' indicates no error. The MCU can read any even location within the sector being erased to get the Toggle Flag Bit (DQ6/DQ14) and the Error Flag Bit (DQ5/DQ13). PSDsoft Express generates ANSI C code functions which implement these Data Toggling algorithms. Unlock Bypass The Unlock Bypass instruction allows the system to program words to the Flash memories faster than using the standard Program instruction. The Unlock Bypass mode is entered by first initiating two Unlock cycles. This is followed by a third WRITE cycle containing the Unlock Bypass command, 20h (as shown in Table 29). The Flash memory then enters the Unlock Bypass mode. A two-cycle Unlock Bypass Program instruction is all that is required to program in this mode. The first cycle in this instruction contains the Unlock Bypass Program command, A0h. The second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispense with the initial two Unlock cycles required in the standard Program instruction, resulting in faster total programming time. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset instructions are valid. To exit the Unlock Bypass mode, the system must issue the two-cycle Unlock Bypass Reset instruction. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are Don't Care for both cycles. The Flash memory then returns to READ mode. Figure 7. Data Toggle Flowchart
START
READ DQ5 and DQ6 (DQ13 and DQ14) at Valid Even Address
DQ6 (DQ14) = Toggle Yes
No
No
DQ5 (DQ13) =1 Yes READ DQ6 (DQ14)
DQ6 (DQ14) = Toggle Yes Program or Erase Cycle failed
No
Program or Erase Cycle is complete
Issue RESET instruction
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ERA SING FLASH MEMORY Flash Bulk Erase The Flash Bulk Erase instruction uses six WRITE operations followed by a READ operation of the status register, as described in Table 29. If any byte of the Bulk Erase instruction is wrong, the Bulk Erase instruction aborts and the device is reset to the Read Memory mode. During a Bulk Erase, the memory status may be checked by reading the Error Flag Bit (DQ5/ DQ13), the Toggle Flag Bit (DQ6/DQ14), and the Data Polling Bit (DQ7/DQ15), as detailed in the section entitled "PROGRAMMING FLASH MEMORY", on page 31. The Error Flag Bit (DQ5/DQ13) returns a '1' if there has been an Erase Failure (maximum number of Erase cycles have been executed). It is not necessary to program the memory with 00h because the PSD automatically does this before erasing to 0FFh. During execution of the Bulk Erase instruction, the Flash memory does not accept any instructions. Flash Sector Erase. The Sector Erase instruction uses six WRITE operations, as described in Table 29. Additional Flash Sector Erase confirm commands and Flash memory sector addresses can be written subsequently to erase other Flash memory sectors in parallel, without further coded cycles, if the additional commands are transmitted in a shorter time than the time-out period of about 100s. The input of a new Sector Erase command restarts the time-out period. The status of the internal timer can be monitored through the level of the Erase Time-out Flag Bit (DQ3/DQ11). If the Erase Time-out Flag Bit (DQ3/ DQ11) is 0, the Sector Erase instruction has been received and the time-out period is counting. If the Erase Time-out Flag Bit (DQ3/DQ11) is 1, the time-out period has expired and the PSD is busy erasing the Flash memory sector(s). Before and during Erase time-out, any instruction other than Suspend Sector Erase and Resume Sector Erase, abort the cycle that is currently in progress, and reset the device to READ mode. It is not necessary to program the Flash memory sector with 00h as the PSD does this automatically before erasing. During a Sector Erase, the memory status may be checked by reading the Error Flag Bit (DQ5/ DQ13), the Toggle Flag Bit (DQ6/DQ14), and the Data Polling Bit (DQ7/DQ15), as detailed in the section entitled "PROGRAMMING FLASH MEMORY", on page 31.
During execution of the Erase cycle, the Flash memory accepts only Reset and Suspend Sector Erase instructions. Erasure of one Flash memory sector may be suspended, in order to read data from another Flash memory sector, and then resumed. Suspend Sector Erase When a Sector Erase cycle is in progress, the Suspend Sector Erase instruction can be used to suspend the cycle by writing 0B0h to any even address when an appropriate Sector Select (FS0FS7 or CSBOOT0-CSBOOT3) is High. (See Table 29). This allows reading of data from another Flash memory sector after the Erase cycle has been suspended. Suspend Sector Erase is accepted only during the Flash Sector Erase instruction execution and defaults to READ mode. A Suspend Sector Erase instruction executed during an Erase time-out period, in addition to suspending the Erase cycle, terminates the time out period. The Toggle Flag Bit (DQ6/DQ14) stops toggling when the PSD internal logic is suspended. The status of this bit must be monitored at an address within the Flash memory sector being erased. The Toggle Flag Bit (DQ6/DQ14) stops toggling between 0.1s and 15s after the Suspend Sector Erase instruction has been executed. The PSD is then automatically set to READ mode. If an Suspend Sector Erase instruction was executed, the following rules apply: Attempting to read from a Flash memory sector that was being erased outputs invalid data. R eading from a Flash memory sector that was not being erased is valid. The Flash memory cannot be programmed, and only responds to Resume Sector Erase and Reset instructions (READ is an operation and is allowed). If a Reset instruction is received, data in the Flash memory sector that was being erased is invalid. Resume Sector Erase If a Suspend Sector Erase instruction was previously executed, the Erase cycle may be resumed with this instruction. The Resume Sector Erase instruction consists of writing 030h to any even address while an appropriate Sector Select (FS0FS7 or CSBOOT0-CSBOOT3) is High. (See Table 29. )
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SPECIFIC FEATURES Flash Memory Sector Protect Each sector of Primary or Secondary Flash memory can be separately protected against Program and Erase cycles. Sector Protection provides additional data security because it disables all Program or Erase cycles. This mode can be activated (or deactivated) through the JTAG-ISP Port or a Device Programmer. Sector protection can be selected for each sector using the PSDsoft Express program. This automatically protects selected sectors when the device is programmed through the JTAG Port or a Device Programmer. Flash memory sectors can be unprotected to allow updating of their contents using the JTAG Port or a Device Programmer. The MCU can read (but cannot change) the sector protection bits. Any attempt to program or erase a protected Flash memory sector is ignored by the device. The Verify operation results in a READ of the protected data. This allows a guarantee of the retention of the Protection status. The sector protection status can be read by the MCU through the Flash memory protection and Secondary Flash memory protection registers (in the CSIOP block) or use the Read Sector Protection instruction. See Table 19 to Table 20. RESET The RESET instruction consists of one WRITE cycle (see Table 29). It can also be optionally pre-
ceded by the standard two WRITE decoding cycles (writing AAh to AAAh, and 55h to 554h). The Reset instruction must be executed after: R eading the Flash Protection Status or Flash ID An Error condition has occurred (and the device has set the Error Flag Bit (DQ5/DQ13) to '1') during a Flash memory Program or Erase cycle. The Reset instruction immediately puts the Flash memory back into normal READ mode. However, if there is an error condition (with the Error Flag Bit (DQ5/DQ13) set to '1') the Flash memory will return to the READ mode in 25 s after the Reset instruction is issued. The Reset instruction is ignored when it is issued during a Program or Bulk Erase cycle of the Flash memory. The Reset instruction aborts any on-going Sector Erase cycle, and returns the Flash memory to the normal READ mode in 25 s. Reset (RESET) Pin A pulse on the Reset (RESET) pin aborts any cycle that is in progress, and resets the Flash memory to the READ mode. When the reset occurs during a Program or Erase cycle, the Flash memory takes up to 25 s to return to the READ mode. It is recommended that the Reset (RESET) pulse (except for Power On Reset, as described on page 74) be at least 25s so that the Flash memory is always ready for the MCU to fetch the bootstrap instructions after the Reset cycle is complete.
SRA M The SRAM is enabled when SRAM Select (RS0) from the DPLD is High. SRAM Select (RS0) can contain up to three product terms, allowing flexible memory mapping. The SRAM can be backed up using an external battery. The external battery should be connected to the Voltage Stand-by (VSTBY, PE6) line. If you have an external battery connected to the PSD, the contents of the SRAM are retained in the event of a power loss. The contents of the SRAM are retained so long as the battery voltage remains at 2V or greater. If the supply voltage falls below the bat-
tery voltage, an internal power switch-over to the battery occurs. PE7 can be configured as an output that indicates when power is being drawn from the external battery. This Battery-on Indicator (VBATON, PE7) signal is High when the supply voltage falls below the battery voltage and the battery on Voltage Stand-by (VSTBY, PE6) is supplying power to the internal SRAM. SRAM Select (RS0), Voltage Stand-by (VSTBY, PE6) and Battery-on Indicator (VBATON, PE7) are all configured using PSDsoft Express.
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MEMORY SELECT SIGNALS The Primary Flash Memory Sector Select (FS0FS7), Secondary Flash Memory Sector Select (CSBOOT0-CSBOOT3) and SRAM Select (RS0) signals are all outputs of the DPLD. They are defined using PSDsoft Express. The following rules apply to the equations for these signals: 1. Primary Flash memory and secondary Flash memory Sector Select signals must not be larger than the physical sector size. 2. Any primary Flash memory sector must not be mapped in the same memory space as another Flash memory sector. 3. A secondary Flash memory sector must not be mapped in the same memory space as another secondary Flash memory sector. 4. SRAM, I/O, and Peripheral I/O spaces must not overlap. 5. A secondary Flash memory sector may overlap a primary Flash memory sector. In case of overlap, priority is given to the secondary Flash memory sector. 6. SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority is given to the SRAM, I/O, or Peripheral I/O. Example FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from 8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0 always accesses the SRAM. Any address in the range of CSBOOT0 greater than 87FFh (and less than 9FFFh) automatically addresses secondary Flash memory segment 0. Any address greater than 9FFFh accesses the primary Flash memory segment 0. You can see that half of the primary Flash memory segment 0 and one-fourth of secondary Flash memory segment 0 cannot be accessed in this example. Also note that an equation that defined FS1 to anywhere in the range of 8000h to BFFFh would not be valid. Figure 8 shows the priority levels for all memory components. Any component on a higher level can overlap and has priority over any component on a lower level. Components on the same level must not overlap. Level 1 has the highest priority and level 3 has the lowest.
Mem ory Select Configuration for MCUs with Separate Program and Data Spaces The 80C51XA and compatible family of MCUs, can be configured to have separate address spaces for Program memory (selected using Program Select Enable (PSEN, CNTL2)) and Data memory (selected using Read Strobe (RD, CNTL1)). Any of the memories within the PSD can reside in either space or both spaces. This is controlled through manipulation of the VM register that resides in the CSIOP space. The VM register is set using PSDsoft Express to have an initial value. It can subsequently be changed by the MCU so that memory mapping can be changed on-the-fly. For example, you may wish to have SRAM and primary Flash memory in the Data space at Boot-up, and secondary Flash memory in the Program space at Boot-up, and later swap the secondary Flash memory and primary Flash memory. This is easily done with the VM register by using PSDsoft Express to configure it for Boot-up and having the MCU change it when desired. Table 25 describes the VM Register. Figure 8. Priority Level of Memory and I/O Components
Highest Priority
Level 1 SRAM, I/O, or Peripheral I/O Level 2 Secondary Non-Volatile Memory Level 3 Primary Flash Memory Lowest Priority
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Separate Space Modes Program space is separated from Data space. For example, Program Select Enable (PSEN, CNTL2) is used to access the program code from the primary Flash memory, while Read Strobe (RD, CNTL1) is used to access data from the secondary Flash memory, SRAM and I/O Port blocks. This configuration requires the VM register to be set to 0Ch (see Figure 9). Combined Space Modes The Program and Data spaces are combined into one memory space that allows the primary Flash memory, secondary Flash memory, and SRAM to be accessed by either Program Select Enable (PSEN, CNTL2) or Read Strobe (RD, CNTL1). For example, to configure the primary Flash memory in Combined space, Bits 2 and 4 of the VM register are set to '1' (see Figure 10). 80C51XA Memory Map Example See the Application Notes for examples.
Figure 9. 8031 Memory Modules - Separate Space
DPLD
RS0 CSBOOT0-3 FS0-FS7
Primary Flash Memory
Secondary Flash Memory
SRAM
CS OE
CS OE
CS OE
PSEN RD
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Figure 10. 8031 Memory Modules - Combined Space
DPLD
RS0 CSBOOT0-3 FS0-FS7
Primary Flash Memory
Secondary Flash Memory
SRAM
RD
CS OE
CS OE
CS OE
VM REG BIT 3
VM REG BIT 4
PSEN
VM REG BIT 1
VM REG BIT 2
RD
VM REG BIT 0
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PAGE REGISTER The 8-bit Page Register increases the addressing capability of the MCU by a factor of up to 256. The contents of the register can also be read by the MCU. The outputs of the Page Register (PGR0PGR7) are inputs to the DPLD decoder and can be included in the Sector Select (FS0-FS7, CSBOOT0-CSBOOT3), and SRAM Select (RS0) equations. If memory paging is not needed, or if not all eight page register bits are needed for memory paging, Figure 11. Page Register
RESET
these bits may be used in the CPLD for general logic. See Application Note AN1154. Table 22 and Figure 11 show the Page Register. The eight flip-flops in the register are connected to the internal data bus (D0-D7). The MCU can write to or read from the Page Register. The Page Register can be accessed at address location CSIOP + E0h.
D0 D1 D0 - D7 D2 D3 D4 D5 D6 R/W D7
Q0 Q1 Q2 Q3 Q4 Q5
PGR0 PGR1 PGR2 PGR3 PGR4 PGR5 PGR6 DPLD AND CPLD
INTERNAL SELECTS AND LOGIC
Q6 PGR7 Q7
PAGE REGISTER
PLD
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MEMORY ID REGISTERS The 8-bit Read-only Memory Status Registers are included in the CSIOP space. The user can determine the memory configuration of the PSD device
by reading the Memory ID0 and Memory ID1 registers. The content of the registers is defined as shown in Table 26 and Table 27.
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PLDS The PLDs bring programmable logic functionality to the PSD. After specifying the logic for the PLDs using PSDsoft Express, the logic is programmed into the device and available upon Power-up. The PSD contains two PLDs: the Decode PLD (DPLD), and the Complex PLD (CPLD). The PLDs are briefly discussed in the next few paragraphs, and in more detail in the following sections. Figure 12 shows the configuration of the PLDs. The DPLD performs address decoding for internal components, such as memory, registers, and I/O ports Select signals. The CPLD can be used for logic functions, such as loadable counters and shift registers, state machines, and encoding and decoding logic. These logic functions can be constructed using the 16 Output Macrocells (OMC), 24 Input Macrocells (IMC), and the AND Array. The CPLD can also be used to generate External Chip Select (ECS0ECS2) signals. The AND Array is used to form product terms. These product terms are specified using PSDsoft Express. An Input Bus consisting of 82 signals is connected to the PLDs. The signals are shown in Table 32. The Turbo Bit in PSD The PLDs in the PSD4235G2 can minimize power consumption by switching to standby when inputs remain unchanged for an extended time of about 70 ns. Resetting the Turbo Bit to '0' (Bit 3 of the PMMR0 register) automatically places the PLDs into standby if no inputs are changing. Turning the Turbo mode off increases propagation delays while reducing power consumption. See the section entitled "Power Management", on page 70, on how to set the Turbo Bit. Additionally, five bits are available in the PMMR2 register to block MCU control signals from entering
the PLDs. This reduces power consumption and can be used only when these MCU control signals are not used in PLD logic equations. Each of the two PLDs has unique characteristics suited for its applications. They are described in the following sections. Table 32. DPLD and CPLD Inputs
Input Source MCU Address Bus1 MCU Control Signals Reset Power-down Port A Input Macrocells Port B Input Macrocells Port C Input Macrocells Port D Inputs Port F Inputs Page Register Macrocell A Feedback Macrocell B Feedback Flash memory Program Status Bit Input Name A15-A0 CNTL0-CNTL2 RST PDN PA7-PA0 PB7-PB0 PC7-PC0 PD3-PD0 PF7-PF0 PGR7-PGR0 MCELLA.FB7-FB0 MCELLB.FB7-FB0 Ready/Busy Number of Signals 16 3 1 1 8 8 8 4 8 8 8 8 1
Note: 1. The address inputs are A19-A4 in 80C51XA mode.
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8
Figure 12. PLD Diagram
DATA BUS
PAGE REGISTER
DECODE PLD
PRIMARY FLASH MEMORY SELECTS SECONDARY NON-VOLATILE MEMORY SELECTS SRAM SELECT CSIOP SELECT PERIPHERAL SELECTS JTAG SELECT 82 4 3 1 2 1
8
PLD INPUT BUS
16
OUTPUT MACROCELL FEEDBACK
DIRECT MACROCELL ACCESS FROM MCU DATA BUS
CPLD
16 OUTPUT MACROCELL PT ALLOC. 82
MACROCELL ALLOC.
MCELLA TO PORT A MCELLB TO PORT B I/O PORTS
8
24 INPUT MACROCELL (PORT A,B,C)
8 8 EXTERNAL CHIP SELECTS TO PORT C or PORT F
DIRECT MACROCELL INPUT TO MCU DATA BUS 24 INPUT MACROCELL & INPUT PORTS
12
PORT D and PORT F INPUTS
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DEC ODE PLD (DPLD) The DPLD, shown in Figure 13, is used for decoding the address for internal and external components. The DPLD can be used to generate the following decode signals: 8 Sector Select (FS0-FS7) signals for the primary Flash memory (three product terms each) 4 Sector Select (CSBOOT0-CSBOOT3) signals for the secondary Flash memory (three product terms each) Figure 13. DPLD Logic Array
3 3 3 3 (INPUTS) I /O PORTS (PORT A,B,F) MCELLAB.FB [7:0] (FEEDBACKS) MCELLBC.FB [7:0] (FEEDBACKS) PGR0 - PGR7 A[15: 0] * PD[3: 0] (ALE,CLKIN,CSI) PDN (APD OUTPUT) CNTRL[2:0] (READ/WRITE CONTROL SIGNALS) RESET RD_BSY (32) 3 (8) 3 (8) 3 (8) 3 (16) 3 (4) 3 (1) 3 (3) (1) 3 (1) 1 1 1 1 CSIOP PSEL0 PSEL1 JTAGSEL
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1 internal SRAM Select (RS0) signal (three product terms) 1 internal CSIOP Select (PSD Configuration Register) signal 1 JTAG Select signal (enables JTAG-ISP on Port E) 2 internal Peripheral Select signals (Peripheral I/O mode).
CSBOOT 0 CSBOOT 1 CSBOOT 2 CSBOOT 3
3
FS0 FS1 FS2 FS3 FS4 FS5 FS6 FS7 8 PRIMARY FLASH MEMORY SECTOR SELECTS
RS0
SRAM SELECT I/O DECODER SELECT PERIPHERAL I/O MODE SELECT
Note: 1. The address inputs are A19-A4 when in 80C51XA mode 2. Additional address lines can be brought ino the PSD via Port A, B, C, D, or F.
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COMPLEX PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift registers, system mailboxes, handshaking protocols, state machines, and random logic. The CPLD can also be used to generate eight External Chip Select (ECS0-ECS7), routed to Port C or Port F. Although External Chip Select (ECS0-ECS7) can be produced by any Output Macrocell (OMC), these eight External Chip Select (ECS0-ECS7) on Port C or Port F do not consume any Output Macrocells (OMC). As shown in Figure 12, the CPLD has the following blocks: 24 Input Macrocells (IMC) 16 Output Macrocells (OMC) Product Term Allocator Figure 14. Macrocell and I/O Port
PLD INPUT BUS
PRODUCT TERMS FROM OTHER MACROCELLS
MCU ADDRESS / DATA BUS
AND Array capable of generating up to 196 product terms Four I/O Ports. Each of the blocks are described in the sections that follow. The Input Macrocells (IMC) and Output Macrocells (OMC) are connected to the PSD internal data bus and can be directly accessed by the MCU. This enables the MCU software to load data into the Output Macrocells (OMC) or read data from both the Input and Output Macrocells (IMC and OMC). This feature allows efficient implementation of system logic and eliminates the need to connect the data bus to the AND Array as required in most standard PLD macrocell architectures.
CPLD MACROCELLS
PT PRESET PRODUCT TERM ALLOCATOR MCU DATA IN
DATA LOAD CONTROL
I/O PORTS
LATCHED ADDRESS OUT DATA WR I/O PIN D Q
MCU LOAD
MUX
AND ARRAY
UP TO 10 PRODUCT TERMS
POLARITY SELECT PR PT CLOCK D/T DI LD Q
MUX
MACROCELL OUT TO MCU
CPLD OUTPUT
SELECT
COMB. /REG SELECT
PLD INPUT BUS
GLOBAL CLOCK CLOCK SELECT PT CLEAR
MUX
D/T/JK FF SELECT
CK CL
PDR
INPUT
D WR
Q
DIR REG.
PT OUTPUT ENABLE (OE) MACROCELL FEEDBACK I/O PORT INPUT
INPUT MACROCELLS
MUX
QD
MUX
PT INPUT LATCH GATE/CLOCK ALE/AS
QD G
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Output Macrocell (OMC) Eight of the Output Macrocells (OMC) are connected to Ports A pins and are named as McellA0McellA7. The other eight Macrocells are connected to Ports B pins and are named as McellB0McellB7. The Output Macrocell (OMC) architecture is shown in Figure 15. As shown in the figure, there are native product terms available from the AND Array, and borrowed product terms available (if unused) from other Output Macrocells (OMC). The polarity of the product term is controlled by the XOR gate. The Output Macrocell (OMC) can implement either sequential logic, using the flip-flop element, or combinatorial logic. The multiplexer
selects between the sequential or combinatorial logic outputs. The multiplexer output can drive a port pin and has a feedback path to the AND Array inputs. The flip-flop in the Output Macrocell (OMC) block can be configured as a D, T, JK, or SR type in the PSDsoft Express program. The flip-flop's clock, preset, and clear inputs may be driven from a product term of the AND Array. Alternatively, the external CLKIN (PD1) signal can be used for the clock input to the flip-flop. The flip-flop is clocked on the rising edge of CLKIN (PD1). The preset and clear are active High inputs. Each clear input can use up to two product terms.
Table 33. Output Macrocell Port and Data Bit Assignments
Outp ut Macrocell McellA0 McellA1 McellA2 McellA3 McellA4 McellA5 McellA6 McellA7 McellB0 McellB1 McellB2 McellB3 McellB4 McellB5 McellB6 McellB7 Port Assignment Port A0 P |
