ST7LITE0xY0, ST7LITESxY0
8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, timers, SPI
Memories 1K or 1.5 Kbytes single voltage Flash Program memory with read-out protection, In-Circuit and In-Application Programming (ICP and IAP). 10 K write/erase cycles guaranteed, data retention: 20 years at 55 C. 128 bytes RAM. 128 bytes data EEPROM with read-out protection. 300K write/erase cycles guaranteed, data retention: 20 years at 55 C. Clock, Reset and Supply Management 3-level low voltage supervisor (LVD) and auxiliary voltage detector (AVD) for safe poweron/off procedures Clock sources: internal 1MHz RC 1% oscillator or external clock PLL x4 or x8 for 4 or 8 MHz internal clock Four Power Saving Modes: Halt, Active-Halt, Wait and Slow Interrupt Management 10 interrupt vectors plus TRAP and RESET 4 external interrupt lines (on 4 vectors) I/O Ports 13 multifunctional bidirectional I/O lines 9 alternate function lines 6 high sink outputs 2 Timers One 8-bit Lite Timer (LT) with prescaler including: watchdog, 1 realtime base and 1 input capture.
DIP16
SO16 150"
QFN2 0 One 12-bit Auto-reload Timer (AT) with output compare function and PWM
1 Communication Interface SPI synchronous serial interface A/D Converter 8-bit resolution for 0 to VDD Fixed gain Op-amp for 11-bit resolution in 0 to 250 mV range (@ 5V VDD) 5 input channels Instruction Set 8-bit data manipulation 63 basic instructions with illegal opcode detection 17 main addressing modes 8 x 8 unsigned multiply instruction Development Tools Full hardware/software development package
Device Summary
Features
Program memory - bytes RAM (stack) - bytes Data EEPROM - bytes Peripherals Operating Supply CPU Frequency Operating Temperature Packages
ST7LITESxY0 (ST7SUPERLITE) ST7LITES2Y 0 ST7LITE S5Y0
ST7LITE02Y0
ST7LITE0xY0 ST7LITE05Y0
ST7LITE09Y0
1K 1K 1.5K 128 (64) 128 (64) 128 (64) LT Timer w/ Wdg, LT Timer w/ Wdg, LT Timer w/ Wdg, AT Timer w/ 1 PWM, AT Timer w/ 1 PWM, AT Timer w/ 1 PWM, SPI SPI, 8-bit ADC SPI 2.4V to 5.5V 1MHz RC 1% + PLLx4/8MHz -40C to +85C SO16 150", DIP16, QFN20
1.5K 1.5K 128 (64) 128 (64) 128 LT Timer w/ Wdg, AT Timer w/ 1 PWM, SPI, 8-bit ADC w/ Op-Amp
Rev 6
November 2007 1/124
1
Table of Contents
ST7LITE0xY0, ST7LITESxY0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 4.3 4.4 4.5 4.6 4.7 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 5.3 5.4 5.5 5.6 5.7 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DATA EEPROM READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 6.3 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 INTERNAL RC OSCILLATOR ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 7.3 7.4 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2 8.3 8.4 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.2 9.3 9.4 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 . 38 ... ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2/124
2
Table of Contents
10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.3 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.6 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.1 LITE TIMER (LT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.2 12-BIT AUTORELOAD TIMER (AT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.3 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.4 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 13.7 EMC (ELECTROMAGNETIC COMPATIBILITY) CHARACTERISTICS . . . . . . . . . . . . . 93 13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 13.10 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 102 13.11 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 14.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 112 15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 114 15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 16 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 16.1 EXECUTION OF BTJX INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 16.2 IN-CIRCUIT PROGRAMMING OF DEVICES PREVIOUSLY PROGRAMMED WITH HARDWARE WATCHDOG OPTION 121 16.3 IN-CIRCUIT DEBUGGING WITH HARDWARE WATCHDOG . . . . . . . . . . . . . . . . . . . 121 16.4 RECOMMENDATIONS WHEN LVD IS ENABLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 16.5 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE . . . . . . . . . . . . 121 17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
3/124
3
Table of Contents
To obtain the most recent version of this datasheet, please check at www.st.com
Please also pay special attention to the Section "KNOWN LIMITATIONS" on page 121.
4/124
1
ST7LITE0xY0, ST7LITESxY0
1 DESCRIPTION
The ST7LITE0x and ST7SUPERLITE (ST7LITESx) are members of the ST7 microcontroller family. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. The ST7LITE0x and ST7SUPERLITE feature FLASH memory with byte-by-byte In-Circuit Programming (ICP) and In-Application Programming (IAP) capability. Under software control, the ST7LITE0x and ST7SUPERLITE devices can be placed in WAIT, SLOW, or HALT mode, reducing power consumption when the application is in idle or standby state. Figure 1. General Block Diagram The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. For easy reference, all parametric data are located in section 13 on page 81.
1 MHz. RC OSC + PLL x 4 or x 8
LVD/AVD VDD VSS RESET POWER SUPPLY
Internal CLOCK
LITE TIMER w/ WATCHDOG PORT A
ADDRESS AND DATA BUS
PA7:0 (8 bits)
CONTROL 8-BIT CORE ALU FLASH MEMORY (1 or 1.5K Bytes)
12-BIT AUTORELOAD TIMER
SPI PB4:0 (5 bits)
PORT B
8-BIT ADC RAM (128 Bytes)
DATA EEPROM (128 Bytes)
5/124
1
ST7LITE0xY0, ST7LITESxY0
2 PIN DESCRIPTION
Figure 2. 20-Pin QFN Package Pinout
PA0 (HS)/LTIC
17 e0 16 15 14 13 12 ei2 ei1 11 7 8 9 10
PB0/SS/AIN0
VDD
20 19 18
VS S
RESET NC NC NC MISO/AIN2/PB2 SCK/AIN1/PB1
1 2 3 4 5 6
e3
PA1 (HS) PA2 (HS)/ATPWM0 PA3 (HS) NC PA4 (HS) PA5 (HS)/ICCDATA
MO SI/AIN3/PB3
CLKIN/AIN4/PB4
PA7
M CO/ICCCLK/PA6
(HS) 20mA High sink capability eix associated external interrupt vector
Figure 3. 16-Pin SO and DIP Package Pinout
k
VSS VDD RE SET SS/AIN0/PB0 SCK/AIN1/PB1 MIS O /A IN2/ PB2 MOSI/A IN3/PB3 CLKIN/AIN4/PB4
1 2 3 4 ei3 5 6 7 ei2 8
ei0 16 15 14 13 12 11 10 ei1 9
PA0 (HS)/LTIC PA1 (HS) PA2 (HS)/ATPWM0 PA3 (HS) PA4 (HS) PA5 (HS)/ICCDATA P A 6/MC O/ICCCLK P A7
(HS) 20mA high sink capability eix associated external interrupt vector
6/124
1
ST7LITE0xY0, ST7LITESxY0
PIN DESCRIPTION (Cont'd) Legend / Abbreviations for Table 1: Type: I = input, O = output, S = supply In/Output level: C= CMOS 0.15VDD/0.85VDD with input trigger CT= CMOS 0.3VDD/0.7VDD with input trigger Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration: Input: float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog Output: OD = open drain, PP = push-pull Table 1. Device Pin Description
Pin n SO 16/DIP16 Type Q F N20 Pin Name Level O u tput Input Port / Control Input float wpu ana int Output OD PP Main Function (after reset) Alternate Function
18 19 1 20
1 2 3 4
VS S VDD RESE T PB0/AIN0/SS
S S I/O I/O CT CT X X ei3 X X X X
Ground Main power supply Top priority non maskable interrupt (active low) Port B0 ADC Analog Input 0 or SPI Slave Select (active low) ADC Analog Input 1 or SPI Clock Caution: No negative current injection allowed on this pin. For details, refer to section 13.2.2 on page 82 ADC Analog Input 2 or SPI Master In/ Slave Out Data ADC Analog Input 3 or SPI Master Out / Slave In Data ADC Analog Input 4 or External clock input Main Clock Output/In Circuit Communication Clock. Caution: During normal operation this pin must be pulled- up, internally or externally (external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up In Circuit Communication Data
6
5
PB1/AIN1/SCK
I /O
CT
X
X
X
X
X
Port B1
5 7 8 9
6 7 8 9
PB2/AIN2/MISO PB3/AIN3/MO SI PB4/AIN4/CLKIN PA7
I/O I/O I /O I/O
CT CT CT CT
X X X X
X ei2 X ei1
X X X
X X X X
X X X X
Port B2 Port B3 Port B4 Port A7
10 10
PA6 /MCO/ IC CCLK
I/O
CT
X
X
X
X
Port A6
11 11
PA5/ IC CDATA
I/O CT HS I / O CT H S I / O CT H S
X X X
X X X
X X X
X X X
Port A5 Port A4 Port A3
12 12 PA4 14 13 PA3
7/124
1
ST7LITE0xY0, ST7LITESxY0
Pin n SO16/DIP16 Type QFN 20 Pin Name Level O u tput Input Port / Control Input float w pu ana int Output OD PP Main Function (after reset) Alternate Function
15 14 PA2/ATPWM 0 16 15 PA1 17 16 PA0/LTIC
I / O CT H S I / O CT H S I / O CT H S
X X X
X X ei0
X X X
X X X
Port A2 Port A1 Port A0
Auto-Reload Timer PWM0
Lite Timer Input Capture
Note: In the interrupt input column, "eix" defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input.
8/124
1
ST7LITE0xY0, ST7LITESxY0
3 REGISTER & MEMORY MAP
As shown in Figure 4 and Figure 5, the MCU is capable of addressing 64K bytes of memories and I/ O registers. The available memory locations consist of up to 128 bytes of register locations, 128 bytes of RAM, 128 bytes of data EEPROM and up to 1.5 Kbytes of user program memory. The RAM space includes up to 64 bytes for the stack from 0C0h to 0FFh. The highest address bytes contain the user reset and interrupt vectors. The size of Flash Sector 0 is configurable by Option byte. IMPORTANT: Memory locations marked as "Reserved" must never be accessed. Accessing a reserved area can have unpredictable effects on the device.
Figure 4. Memory Map (ST7LITE0x)
0000h 007Fh 0080h 00FFh 0100h
HW Registers (see Table 2) RAM (128 Bytes) Reserved
0080h
Short Addressing RAM (zero page)
00BFh 00C0h
64 Bytes Stack
00FFh 1000h
0FFFh 1000h 107Fh 1080h
RC CR0 R CCR1
Data EEPROM (128 Bytes)
1001h
see section 7.1 on page 24
1.5K FLASH PROGRAM MEMORY
Reserved
F9FFh FA00h
FA00h
Flash Memory (1. 5 K)
FFDFh FFE0h
FBFFh FC00h FFFFh
0.5 Kbytes SECTOR 1 1 Kbytes SECTOR 0 FFDEh
Interrupt & Reset Vectors (see Table 6)
RCC R0 RCC R1
FFFFh
FFDFh
see section 7.1 on page 24
9/124
1
ST7LITE0xY0, ST7LITESxY0
REGISTER AND MEMORY MAP (Cont'd) Figure 5. Memory Map (ST7SUPERLITE)
0000h 007Fh 0080h 00FFh 0100h
HW Registers (see Table 2) RAM (128 Bytes)
0080h
Short Addressing RAM (zero page)
00BFh 00C0h
64 Bytes Stack
00FFh
Reserved
1K FLASH PROGRAM MEMORY FBFFh FC00h
FC00h
Flash Memory (1K)
FFDFh FFE0h
FDFFh FE00h FFFFh
0.5 Kbytes SECTOR 1 0.5 Kbytes SECTOR 0
Interrupt & Reset Vectors (see Table 6)
FFDEh
RCCR0 RCCR1
FFFFh
FFDFh
see section 7.1 on page 24
10/124
1
ST7LITE0xY0, ST7LITESxY0
REGISTER AND MEMORY MAP (Cont'd) Legend: x=undefined, R/W=read/write Table 2. Hardware Register Map
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h to 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h to 0016h 0017h 0018h 0019h to 002Eh 0002Fh 00030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h F LASH EE PROM SPI FCSR EECSR SPID R SPIC R SPIC S R ADCCSR ADCDR ADCAMP EICR MCCSR RCCR AUTO -RELO AD DCR0H TIMER DCR0L LITE TIMER LTCSR LTICR Block Register Label PADR PADDR PAOR PBDR PBDDR PBOR Register Name Port A Data Register Port A Data Direction Register Port A Option Register Port B Data Register Port B Data Direction Register Port B Option Register Reserved area (5 bytes) Lite Timer Control/Status Register Lite Timer Input Capture Register Timer Control/Status Register Counter Register High Counter Register Low Auto-Reload Register High Auto-Reload Register Low PWM Output Control Register PWM 0 Control/Status Register Reserved area (3 bytes) PWM 0 Duty Cycle Register High PWM 0 Duty Cycle Register Low Reserved area (22 bytes) Flash Control/Status Register Data EEPROM Control/Status Register SPI Data I/O Register SPI Control Register SPI Control/Status Register A/D Control Status Register A/D Data Register A/D Amplifier Control Register External Interrupt Control Register Main Clock Control/Status Register RC oscillator Control Register 00h 00h xxh 0xh 00h 00h 00h 00h 00h 00h FFh R/W R/W R/W R/W R/W R/W Read Only R/W R/W R/W R/W 00h 00h R/W R/W xxh xxh 00h 00h 00h 00h 00h 00h 00h R/W Read Only R/W Read Only Read Only R/W R/W R/W R/W Reset Status 00h1) 00h 40h E0h 1) 00h 00h R e ma r k s R/W R/W R/W R/W R/W R/W2)
Port A
Port B
ATCSR CNTRH CNTRL AUTO -RELO AD ATRH TIMER ATRL PWM C R PWM 0 CSR
ADC ITC CLOCKS
11/124
1
ST7LITE0xY0, ST7LITESxY0
Address 003Ah 003Bh to 007Fh
Block SI
Register Label SICS R
Register Name System Integrity Control/Status Register Reserved area (69 bytes)
Reset Status 0xh
R e ma r k s R/W
Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value.
12/124
1
ST7LITE0xY0, ST7LITESxY0
4 FLASH PROGRAM MEMORY
4.1 Introduction The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. The XFlash devices can be programmed off-board (plugged in a programming tool) or on-board using In-Circuit Programming or In-Application Programming. The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 Main Features
ICP (In-Circuit Programming) IAP (In-Application Programming) ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM Sector 0 size configurable by option byte Read-out and write protection
4.3 PROGRAMMING MODES The ST7 can be programmed in three different ways: Insertion in a programming tool. In this mode, FLASH sectors 0 and 1, option byte row and data EEPROM can be programmed or erased. In-Circuit Programming. In this mode, FLASH sectors 0 and 1, option byte row and data EEPROM can be programmed or erased without removing the device from the application board. In-Application Programming. In this mode, sector 1 and data EEPROM can be programmed or erased without removing the device from the application board and while the application is running.
4.3.1 In-Circuit Programming (ICP) ICP uses a protocol called ICC (In-Circuit Communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in three steps: Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters ICC mode, it fetches a specific RESET vector which points to the ST7 System Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface. Download ICP Driver code in RAM from the ICCDATA pin Execute ICP Driver code in RAM to program the FLASH memory Depending on the ICP Driver code downloaded in RAM, FLASH memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 In Application Programming (IAP) This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode). This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.) IAP mode can be used to program any memory areas except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.
13/124
1
ST7LITE0xY0, ST7LITESxY0
FLASH PROGRAM MEMORY (Cont'd) 4.4 ICC interface ICP needs a minimum of 4 and up to 6 pins to be connected to the programming tool. These pins are: RESET: device reset VSS: device power supply ground ICCCLK: ICC output serial clock pin ICCDATA: ICC input serial data pin CLKIN: main clock input for external source VDD: application board power supply (optional, see Note 3) Notes: 1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values. 2. During the ICP session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at Figure 6. Typical ICC Interface
PROGRAMMING TOOL ICC CONNECTOR ICC Cable ICC CONNECTOR HE10 CONNECTOR TYPE OPTIONAL (See Note 4) APPLICATION BOARD
high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset management IC with open drain output and pull-up resistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session. 3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual. 4. Pin 9 has to be connected to the CLKIN pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. Caution: During normal operation, ICCCLK pin must be pulled- up, internally or externally (external pull-up of 10K mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up.
(See Note 3)
9 10
7 8
5 6
3 4
1 2
APPLICATION RESET SOURCE See Note 2
APPLICATION POWER SUPPLY
See Note 1 and Caution APPLICATION I/O See Note 1 CLKIN RESET ICCCLK VDD ICCDATA
ST7
14/124
1
ST7LITE0xY0, ST7LITESxY0
FLASH PROGRAM MEMORY (Cont'd) 4.5 Memory Protection There are two different types of memory protection: Read Out Protection and Write/Erase Protection which can be applied individually. 4.5.1 Read out Protection Readout protection, when selected provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. Both program and data E2 memory are protected. In flash devices, this protection is removed by reprogramming the option. In this case, both program and data E2 memory are automatically erased, and the device can be reprogrammed. Read-out protection selection depends on the device type: In Flash devices it is enabled and removed through the FMP_R bit in the option byte. In ROM devices it is enabled by mask option specified in the Option List. 4.5.2 Flash Write/Erase Protection Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. It does not apply to E2 data. Its purpose is to provide advanced security to applications and prevent any change being made to the memory content. Warning: Once set, Write/erase protection can never be removed. A write-protected flash device is no longer reprogrammable. Table 3. FLASH Register Map and Reset Values
Address (Hex.) 002Fh Register Label FC SR Reset Value 0 0 0 0 0 7 6 5 4 3 2 OP T 0 1 LAT 0 0 PGM 0
Write/erase protection is enabled through the FMP_W bit in the option byte. 4.6 Related Documentation For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual. 4.7 Register Description FLASH CONTROL/STATUS REGISTER (FCSR) Read / Write Reset Value: 000 0000 (00h) 1st RASS Key: 0101 0110 (56h) 2nd RASS Key: 1010 1110 (AEh)
7 0 0 0 0 0 OPT LAT 0 PGM
Note: This register is reserved for programming using ICP, IAP or other programming methods. It controls the XFlash programming and erasing operations. When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically.
15/124
1
ST7LITE0xY0, ST7LITESxY0
5 DATA EEPROM
5.1 INTRODUCTION The Electrically Erasable Programmable Read Only Memory can be used as a non-volatile backup for storing data. Using the EEPROM requires a basic access protocol described in this chapter. 5.2 MAIN FEATURES
Up to 32 bytes programmed in the same cycle EEPROM mono-voltage (charge pump) Chained erase and programming cycles Internal control of the global programming cycle duration WAIT mode management Read-out protection
Figure 7. EEPROM Block Diagram
HIGH VOLTAGE PUMP
EECSR
0
0
0
0
0
0
E2LAT E2PGM
ADDRESS DECODER
4
ROW DECODER
EEPROM MEMORY MATRIX (1 ROW = 32 x 8 BITS)
128 DATA MULTIPLEXER 4
128 32 x 8 BITS DATA LATCHES
4
ADDRESS BUS
DATA BUS
16/124
1
ST7LITE0xY0, ST7LITESxY0
DATA EEPROM (Cont'd) 5.3 MEMORY ACCESS The Data EEPROM memory read/write access modes are controlled by the E2LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in Figure 8 describes these different memory access modes. Read Operation (E2LAT = 0) The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR register is cleared. On this device, Data EEPROM can also be used to execute machine code. Take care not to write to the Data EEPROM while executing from it. This would result in an unexpected code being executed. Write Operation (E2LAT = 1) To access the write mode, the E2LAT bit has to be set by software (the E2PGM bit remains cleared). When a write access to the EEPROM area occurs, Figure 8. Data EEPROM Programming Flowchart the value is latched inside the 32 data latches according to its address. When PGM bit is set by the software, all the previous bytes written in the data latches (up to 32) are programmed in the EEPROM cells. The effective high address (row) is determined by the last EEPROM write sequence. To avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same high address: Only the five Least Significant Bits of the address can change. At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously. Note: Care should be taken during the programming cycle. Writing to the same memory location will over-program the memory (logical AND between the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of the E2LAT bit. It is not possible to read the latched data. This note is illustrated by the Figure 10.
READ MODE E2LAT = 0 E2PGM = 0
WRITE MODE E2LAT = 1 E2PGM = 0
READ BYTES IN EEPROM AREA
WRITE UP TO 32 BYTES IN EEPROM AREA (with the same 11 MSB of the address)
START PROGRAMMING CYCLE E2LAT=1 E2PGM=1 (set by software)
0 CLEARED BY HARDWARE
E2LAT
1
17/124
1
ST7LITE0xY0, ST7LITESxY0
DATA EEPROM (Cont'd) Figure 9. Data E2PROM Write Operation
Row / Byte R OW DEFINITION 0 1 ... N Read operation impossible 0 1 2 3 ... 30 31 Physical Address
00h...1Fh 20h...3Fh Nx20h...Nx20h+1Fh
Read operation possible
Byte 1
Byte 2 PH ASE 1
Byte 32
Programming cycle PHASE 2
Writing data latches E2LAT b it
Set by USER application
Waiting E2PGM and E2LAT to fall
Cleared by hardware
E2PG M b it
Note: If a programming cycle is interrupted (by RESET action), the integrity of the data in memory will not be guaranteed.
18/124
1
ST7LITE0xY0, ST7LITESxY0
DATA EEPROM (Cont'd) 5.4 POWER SAVING MODES Wait mode The DATA EEPROM can enter WAIT mode on execution of the WFI instruction of the microcontroller or when the microcontroller enters Active Halt mode.The DATA EEPROM will immediately enter this mode if there is no programming in progress, otherwise the DATA EEPROM will finish the cycle and then enter WAIT mode. Active Halt mode Refer to Wait mode. Halt mode The DATA EEPROM immediately enters HALT mode if the microcontroller executes the HALT instruction. Therefore the EEPROM will stop the function in progress, and data may be corrupted. 5.5 ACCESS ERROR HANDLING If a read access occurs while E2LAT = 1, then the data bus will not be driven. If a write access occurs while E2LAT = 0, then the data on the bus will not be latched. If a programming cycle is interrupted (by RESET action), the integrity of the data in memory will not be guaranteed. 5.6 DATA EEPROM READ-OUT PROTECTION The read-out protection is enabled through an option bit (see option byte section). When this option is selected, the programs and data stored in the EEPROM memory are protected against read-out (including a re-write protection). In Flash devices, when this protection is removed by reprogramming the Option Byte, the entire Program memory and EEPROM is first automatically erased. Note: Both Program Memory and data EEPROM are protected using the same option bit.
Figure 10. Data EEPROM Programming Cycle
READ OPERATION NOT POSSIBLE INTERNAL PROGRAMMING VOLTAGE ERASE CYCLE WRITE OF DATA LATCHES WRITE CYCLE
READ OPERATION POSSIBLE
tPROG
LAT
PGM
19/124
1
ST7LITE0xY0, ST7LITESxY0
DATA EEPROM (Cont'd) 5.7 REGISTER DESCRIPTION EEPROM CONTROL/STATUS REGISTER (EECS R) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 0 0 0 E2LAT E2PGM
Bits 7:2 = Reserved, forced by hardware to 0. Bit 1 = E2LAT Latch Access Transfer This bit is set by software. It is cleared by hardware at the end of the programming cycle. It can only be cleared by software if the E2PGM bit is cleared. 0: Read mode 1: Write mode Bit 0 = E2PGM Programming control and status This bit is set by software to begin the programming cycle. At the end of the programming cycle, this bit is cleared by hardware. 0: Programming finished or not yet started 1: Programming cycle is in progress Note: If the E2PGM bit is cleared during the programming cycle, the memory data is not guaranteed. Table 4. DATA EEPROM Register Map and Reset Values
Address (Hex.) 0030h Register Label E ECSR Reset Value 0 0 0 0 0 0 7 6 5 4 3 2 1 E2LAT 0 0 E2PGM 0
20/124
1
ST7LITE0xY0, ST7LITESxY0
6 CENTRAL PROCESSING UNIT
6.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 6.2 MAIN FEATURES
63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit index registers 16-bit stack pointer Low power modes Maskable hardware interrupts Non-maskable software interrupt
6.3 CPU REGISTERS The six CPU registers shown in Figure 11 are not present in the memory mapping and are accessed by specific instructions. Figure 11. CPU Registers
7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 0 0 0
Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 111HI 0 NZC CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value
21/124
1
ST7LITE0xY0, ST7LITESxY0
CPU REGISTERS (Cont'd) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx
7 1 1 1 H I N Z 0 C
because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions. Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test inst ructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions.
The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 3 = I Interrupt mask. This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible
22/124
1
ST7LITE0xY0, ST7LITESxY0
CPU REGISTERS (Cont'd) Stack Pointer (SP) Read/Write Reset Value: 00 FFh
15 0 7 1 1 SP5 S P4 SP3 SP2 SP 1 0 0 0 0 0 0 8 0 0 SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 12). Since the stack is 64 bytes deep, the 10 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP5 to SP0 bits are set) which is the stack higher address. Figure 12. Stack Manipulation Example
CALL Subroutine @ 00C0h Interrupt event P USH Y
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 12. When an interrupt is received, the SP is decremented and the context is pushed on the stack. On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area.
PO P Y
IRET
RET or RSP
SP SP CC A X PC H SP PCH @ 00FFh PCL P CL PCH PCL Y CC A X PCH PCL PCH PC L SP CC A X PCH PCL PCH PCL SP PCH PCL SP
Stack Higher Address = 00FFh Stack Lower Address = 00C0h
23/124
1
ST7LITE0xY0, ST7LITESxY0
7 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. Main features
RC CR
Conditions VDD= 5 V T A =25C f RC=1MH z V DD =3.0V T A =25C f RC= 7 0 0 K H z
ST7FLITE09 Address 1000h and FFDEh 1001h andFFDFh
ST7FLITE05/ ST7FLITES5 Address FFDEh
R CCR0
Clock Management 1 MHz internal RC oscillator (enabled by option byte) External Clock Input (enabled by option byte) PLL for multiplying the frequency by 4 or 8 (enabled by option byte) Reset Sequence Manager (RSM) System Integrity Management (SI) Main supply Low voltage detection (LVD) with reset generation (enabled by option byte) Auxiliary Voltage detector (AVD) with interrupt capability for monitoring the main supply (enabled by option byte)
R CCR1
FFDFh
7.1 INTERNAL RC OSCILLATOR ADJUSTMENT The ST7 contains an internal RC oscillator with an accuracy of 1% for a given device, temperature and voltage. It must be calibrated to obtain the frequency required in the application. This is done by software writing a calibration value in the RCCR (RC Control Register). Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), i.e. each time the device is reset, the calibration value must be loaded in the RCCR. Predefined calibration values are stored in EEPROM for 3.0 and 5V VDD supply voltages at 25C, as shown in the following table. Notes: See "ELECTRICAL CHARACTERISTICS" on page 81. for more information on the frequency and accuracy of the RC oscillator. To improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device.
These two bytes are systematically programmed by ST, including on FASTROM devices. Consequently, customers intending to us e FASTROM service must not use these two bytes. RCCR0 and RCCR1 calibration values will be erased if the read-out protection bit is reset after it has been set. See "Read out Protection" on page 15. Caution: If the voltage or temperature conditions change in the application, the frequency may need to be recalibrated. Refer to application note AN1324 for information on how to calibrate the RC frequency using an external reference signal. 7.2 PHASE LOCKED LOOP The PLL can be used to multiply a 1MHz frequency from the RC oscillator or the external clock by 4 or 8 to obtain fOSC of 4 or 8 MHz. The PLL is enabled and the multiplication factor of 4 or 8 is selected by 2 option bits. The x4 PLL is intended for operation with VDD in the 2.4V to 3.3V range The x8 PLL is intended for operation with VDD in the 3.3V to 5.5V range Refer to Section 15.1 for the option byte description. If the PLL is disabled and the RC oscillator is enabled, then fOSC = 1MHz. If both the RC oscillator and the PLL are disabled, fOSC is driven by the external clock.
24/124
1
ST7LITE0xY0, ST7LITESxY0
Figure 13. PLL Output Frequency Timing Diagram LOCKED bit set 4/8 x input freq. tSTAB Output freq. t LOCK t STARTUP Bit 0 = SMS Slow Mode select This bit is read/write by software and cleared by hardware after a reset. This bit selects the input clock fOSC or fOSC/32. 0: Normal mode (fCPU = fOSC 1: Slow mode (fCPU = fOSC/32) t When the PLL is started, after reset or wakeup from Halt mode or AWUFH mode, it outputs the clock after a delay of tSTARTUP. When the PLL output signal reaches the operating frequency, the LOCKED bit in the SICSCR register is set. Full PLL accuracy (ACCPLL) is reached after a stabilization time of tSTAB (see Figure 13 and 13.3.4 Internal RC Oscillator and PLL) Refer to section 8.4.4 on page 36 for a description of the LOCKED bit in the SICSR register. 7.3 REGISTER DESCRIPTION MAIN CLOCK CONTROL/STATUS REGISTER (MCCSR ) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 0 0
MCO
Bit 1 = MCO Main Clock Out enable This bit is read/write by software and cleared by hardware after a reset. This bit allows to enable the MCO output clock. 0: MCO clock disabled, I/O port free for general purpose I/O. 1: MCO clock enabled.
RC CONTROL REGISTER (RCCR) Read / Write Reset Value: 1111 1111 (FFh)
7 CR7 CR6 CR5 CR4 CR3 CR2 CR1 0 CR0
Bits 7:0 = CR[7:0] RC Oscillator Frequency Adjustment Bits These bits must be written immediately after reset to adjust the RC oscillator frequency and to obtain an accuracy of 1%. The application can store the correct value for each voltage range in EEPROM and write it to this register at start-up. 00h = maximum available frequency FFh = lowest available frequency Note: To tune the oscillator, write a series of different values in the register until the correct frequency is reached. The fastest method is to use a dichotomy starting with 80h.
0
SMS
Bits 7:2 = Reserved, must be kept cleared.
Table 5. Clock Register Map and Reset Values
Address (Hex.) 0038h 0039h Register Label M CCSR Reset Value R CCR Reset Value 0 C R7 1 0 CR6 1 0 CR5 1 0 CR4 1 0 CR3 1 0 CR 2 1 7 6 5 4 3 2 1 M CO 0 CR1 1 0 SMS 0 CR0 1
25/124
1
ST7LITE0xY0, ST7LITESxY0
SUPPLY, RESET AND CLOCK MANAGEMENT (Cont'd)
Figure 14. Clock Management Block Diagram
CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
RCCR 1M Hz 8MHz
Tunable 1% RC Oscillator Option byte CLKIN /2 DIVIDER
PLL 1MHz -> 8MHz PLL 1MHz -> 4MHz
fOSC 4MHz 0 to 8 MHz
Option byte
8-BIT LITE TIMER COUNTER fOSC fOSC/32 1
fLTIMER (1ms timebase @ 8 MHz fOSC)
/32 DIVIDER
fCPU fOSC 0 TO CPU AND PERIPHERALS (except LITE TIMER)
MCO SMS MCCSR
7
0
fCPU
M CO
26/124
1
ST7LITE0xY0, ST7LITESxY0
7.4 RESET SEQUENCE MANAGER (RSM) 7.4.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 16: External RESET source pulse Internal LVD RESET (Low Voltage Detection) Internal WATCHDOG RESET Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to section 11.2.1 on page 53 for further details. These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases as shown in Figure 15: Active Phase depending on the RESET source 256 CPU clock cycle delay RESET vector fetch Figure 16.Reset Block Diagram The 256 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The RESET vector fetch phase duration is 2 clock c ycles. If the PLL is enabled by option byte, it outputs the clock after an additional delay of tSTARTUP (see Figure 13). Figure 15. RESET Sequence Phases
RESET
Active Phase INTERNAL RESET 256 CLOCK CYCLES FETCH VECTOR
VDD
RO N
RESET
FILTER INTERNAL RESET
PULSE GENERATOR
WATCHDOG RESET ILLEGAL OPCODE RESET 1) LVD RESET
Note 1: See "Illegal Opcode Reset" on page 78. for more details on illegal opcode reset conditions.
27/124
1
ST7LITE0xY0, ST7LITESxY0
RESET SEQUENCE MANAGER (Cont'd) 7.4.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details. A RESET signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized (see Figure 17). This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode. The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. 7.4.3 External Power-On RESET If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency. Figure 17. RESET Sequences VDD
VIT+(LVD) VIT-(LVD)
A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin. 7.4.4 Internal Low Voltage Detector (LVD) R ESET Two different RESET sequences caused by the internal LVD circuitry can be distinguished: Power-On RESET Voltage Drop RESET The device RESET pin acts as an output that is pulled low when VDD
LVD RESET
EXTERNAL RESET
WATCHDOG RESET
RUN
ACTIVE PHASE
RUN
ACTIVE PHASE
RUN
ACTIVE PHASE
RUN
th(RSTL)in
EXTERNAL RESET SOURCE
tw(RSTL)out
RESET PIN
WATCHDOG RESET WATCHDOG UNDERFLOW INTERNAL RESET (256 TCPU) VECTOR FETCH
28/124
1
ST7LITE0xY0, ST7LITESxY0
8 INTERRUPTS
The ST7 core may be interrupted by one of two different methods: Maskable hardware interrupts as listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 18. The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). Note: After reset, all interrupts are disabled. When an interrupt has to be serviced: Normal processing is suspended at the end of the current instruction execution. The PC, X, A and CC registers are saved onto the stack. The I bit of the CC register is set to prevent additional interrupts. The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping Table for vector addresses). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit is cleared and the main program resumes. Priority Management By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine. In the case when several interrupts are simultaneously pending, an hardware priority defines which one will be serviced first (see the Interrupt Mapping Table). Interrupts and Low Power Mode All interrupts allow the processor to leave the WAIT low power mode. Only external and specifically mentioned interrupts allow the processor to leave the HALT low power mode (refer to the "Exit from HALT" column in the Interrupt Mapping Table). 8.1 NON MASKABLE SOFTWARE INTERRUPT This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. It is serviced according to the flowchart in Figure 18. 8.2 EXTERNAL INTERRUPTS External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the HALT low power mode. The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of a NANDed source (as described in the I/O ports section), a low level on an I/O pin, configured as input with interrupt, masks the interrupt request even in case of risingedge sensitivity. 8.3 PERIPHERAL INTERRUPTS Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: The I bit of the CC register is cleared. The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by: Writing "0" to the corresponding bit in the status register or Access to the status register while the flag is set followed by a read or write of an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for being enabled) will therefore be lost if the clear sequence is executed.
29/124
1
ST7LITE0xY0, ST7LITESxY0
INTERRUPTS (Cont'd) Figure 18. Interrupt Processing Flowchart
FROM RESET I BIT SET? Y N
N
INTERRUPT PENDING? Y
FETCH NEXT INSTRUCTION
N
IRET? Y
STACK PC, X, A, CC SET I BIT LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK THIS CLEARS I BIT BY DEFAULT
Table 6. Interrupt Mapping
N Source Block RES ET TRAP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 SI AT TIMER LITE TIMER S PI e i0 ei1 ei2 ei3 Reset Software Interrupt Not used External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 Not used Not used AVD interrupt AT TIMER Output Compare Interrupt AT TIMER Overflow Interrupt LITE TIMER Input Capture Interrupt LITE TIMER RTC Interrupt SPI Peripheral Interrupts Not used SICSR P WM 0 C S R ATCSR LTCSR LTCSR SPICS R Lowest Priority no no yes no yes yes N/A yes Description Register Label Priority Order Highest Priority Exit from HALT yes no Address Vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h FFE2h-FFE3h FFE0h-FFE1h
30/124
1
ST7LITE0xY0, ST7LITESxY0
INTERRUPTS (Cont'd) EXTERNAL INTERRUPT CONTROL REGISTER (EICR) Read / Write Reset Value: 0000 0000 (00h)
7 IS31 IS30 IS21 IS20 IS11 IS10 IS01 0 IS00
Notes: 1. These 8 bits can be written only when the I bit in the CC register is set. 2. Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts. Refer to section "External interrupt function" on page 42. Table 7. Interrupt Sensitivity Bits
I S x1 ISx0 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
Bit 7:6 = IS3[1:0] ei3 sensitivity These bits define the interrupt sensitivity for ei3 (Port B0) according to Table 7. Bit 5:4 = IS2[1:0] ei2 sensitivity These bits define the interrupt sensitivity for ei2 (Port B3) according to Table 7. Bit 3:2 = IS1[1:0] ei1 sensitivity These bits define the interrupt sensitivity for ei1 (Port A7) according to Table 7. Bit 1:0 = IS0[1:0] ei0 sensitivity These bits define the interrupt sensitivity for ei0 (Port A0) according to Table 7.
31/124
1
ST7LITE0xY0, ST7LITESxY0
8.4 SYSTEM INTEGRITY MANAGEMENT (SI) The System Integrity Management block contains the Low voltage Detector (LVD) and Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register. Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to section 12.2.1 on page 78 for further details. 8.4.1 Low Voltage Detector (LVD) The Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT-(LVD) reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The VIT-(LVD) reference value for a voltage drop is lower than the VIT+(LVD) reference value for poweron in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD Reset circuitry generates a reset when VDD is below: VIT+(LVD)when VDD is rising VIT-(LVD) when VDD is falling The LVD function is illustrated in Figure 19. The voltage threshold can be configured by option byte to be low, medium or high. See section 15.1 on page 112. Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-(LVD), the MCU can only be in two modes: under full software control in static safe reset In these conditions, secure operation is always ensured for the application without the need for external reset hardware. During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Notes: The LVD is an optional function which can be selected by option byte. See section 15.1 on page 112. It allows the device to be used without any external RESET circuitry. If the LVD is disabled, an external circuitry must be used to ensure a proper power-on reset. It is recommended to make sure that the VDD supply voltage rises monotonously when the device is exiting from Reset, to ensure the application functions properly. Caution: If an LVD reset occurs after a watchdog reset has occurred, the LVD will take priority and will clear the watchdog flag. Figure 19. Low Voltage Detector vs Reset
VDD
Vhys V I T + (LVD) VIT-(LVD)
RESET
32/124
1
ST7LITE0xY0, ST7LITESxY0
Figure 20. Reset and Supply Management Block Diagram
WATCHDOG TIMER (WDG)
STATUS FLAG
SYSTEM INTEGRITY MANAGEMENT RESET SEQUENCE RESET MANAGER (RSM) SICSR 0 7 0 0 D 0 LOC LVF AVD AIVD KED R F E 0 AVD Interrupt Request
LOW VOLTAGE VSS VDD DETECTOR (LVD)
AUXILIARY VOLTAGE DETECTOR (AVD)
33/124
1
ST7LITE0xY0, ST7LITESxY0
SYSTEM INTEGRITY MANAGEMENT (Cont'd) 8.4.2 Auxiliary Voltage Detector (AVD) The Voltage Detector function (AVD) is based on an analog comparison between a VIT-(AVD) and VIT+(AVD) reference value and the VDD main supply voltage (VAVD). The VIT-(AVD) reference value for falling voltage is lower than the VIT+(AVD) reference value for rising voltage in order to avoid parasitic detection (hysteresis). The output of the AVD comparator is directly readable by the application software through a real time status bit (AVDF) in the SICSR register. This bit is read only. Caution: The AVD functions only if the LVD is enabled through the option byte. Figure 21. Using the AVD to Monitor VDD VDD Early Warning Interrupt (Power has dropped, MCU not not yet in reset)
Vh y s t
8.4.2.1 Monitoring the VDD Main Supply The AVD voltage threshold value is relative to the selected LVD threshold configured by option byte (see section 15.1 on page 112). If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the VIT+(LVD) or VIT-(AVD) threshold (AVDF bit is set). In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing software to shut down safely before the LVD resets the microcontroller. See Figure 21. The interrupt on the rising edge is used to inform the application that the VDD warning state is over
VIT+(AVD) VIT-(AVD) VIT+(LVD) VIT-(LVD)
AVDF bit AVD INTERRUPT REQUES T IF AVDIE bit = 1
0
1
RES ET
1
0
INTERRUPT Cleared by reset
INTERRUPT Cleared by hardware
LVD RESET
34/124
1
ST7LITE0xY0, ST7LITESxY0
SYSTEM INTEGRITY MANAGEMENT (Cont'd) 8.4.3 Low Power Modes
Mode WAIT H AL T Description No effect on SI. AVD interrupts cause the device to exit from Wait mode. The SICSR register is frozen. The AVD remains active but the AVD interrupt cannot be used to exit from Halt mode. Interrupt Event AVD event Enable Event Control Flag Bit AVDF A VDIE Exit from Wait Yes Exit from Halt No
set and the interrupt mask in the CC register is reset (RIM instruction).
8.4.3.1 Interrupts The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is
35/124
1
ST7LITE0xY0, ST7LITESxY0
SYSTEM INTEGRITY MANAGEMENT (Cont'd) 8.4.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read / Write If the AVDIE bit is set, an interrupt request is generated when the AVDF bit is set. Refer to Figure Reset Value: 0000 0x00 (0xh) 21 for additional details 0: VDD over AVD threshold 7 0 1: VDD under AVD threshold
0 0 0 0
LOCK ED LVDRF AVDF AVDIE
Bit 7:4 = Reserved, must be kept cleared. Bit 3 = LOCKED PLL Locked Flag This bit is set by hardware. It is cleared only by a power-on reset. It is set automatically when the PLL reaches its operating frequency. 0: PLL not locked 1: PLL locked Bit 2 = LVDRF LVD reset flag This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag description in Section 11.1 for more details. When the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined. Bit 1 = AVDF Voltage Detector flag This read-only bit is set and cleared by hardware.
Bit 0 = AVDIE Voltage Detector interrupt enable This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag is set. The pending interrupt information is automatically cleared when software enters the AVD interrupt routine. 0: AVD interrupt disabled 1: AVD interrupt enabled Application notes The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can be detected by software while an external reset can not.
Table 8. System Integrity Register Map and Reset Values
Address (Hex.) 003Ah Register Label SICSR Reset Value 0 0 0 0 7 6 5 4 3 LOC KED 0 2 LVDR F x 1 AVDF 0 0 AVD IE 0
36/124
1
ST7LITE0xY0, ST7LITESxY0
9 POWER SAVING MODES
9.1 INTRODUCTION To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 22): SLOW, WAIT (SLOW WAIT), ACTIVE HALT and HALT. After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency (fOSC). From RUN mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. Figure 22. Power Saving Mode Transitions
High RUN
fOSC/32 fOSC
9.2 SLOW MODE This mode has two targets: To reduce power consumption by decreasing the internal clock in the device, To adapt the internal clock frequency (fCPU) to the available supply voltage. SLOW mode is controlled by the SMS bit in the MCCSR register which enables or disables Slow mode. In this mode, the oscillator frequency is divided by 32. The CPU and peripherals are clocked at this lower frequency. Notes: SLOW-WAIT mode is activated when entering WAIT mode while the device is already in SLOW mode. SLOW mode has no effect on the Lite Timer which is already clocked at FOSC/32. Figure 23. SLOW Mode Clock Transition
SLOW WAIT SLOW WAIT
fCPU
fOSC
SMS
ACTIVE HALT
NORMAL RUN MODE REQUEST
HALT Low PO WER CONS UMPTION
37/124
1
ST7LITE0xY0, ST7LITESxY0
POWER SAVING MODES (Cont'd) 9.3 WAIT MODE WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the `WFI' instruction. All peripherals remain active. During WAIT mode, the I bit of the CC register is cleared, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or RESET occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 24. Figure 24. WAIT Mode Flow-chart
OSCILLATOR PERIPHERALS CP U I BI T ON ON OFF 0
WFI I N S T R U C T I O N
N RE SET N INTERRUP T Y OSCILLATOR PERIPHERALS CP U I BI T ON OFF ON 0 Y
256 CPU C LOCK CYCLE DELAY
OSCILLATOR PERIPHERALS CP U I BI T
ON ON ON X 1)
FETC H RES ET VEC TOR OR SERVICE INTERRUPT
Note: 1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
38/124
1
ST7LITE0xY0, ST7LITESxY0
POWER SAVING MODES (Cont'd) 9.4 ACTIVE-HALT AND HALT MODES ACTIVE-HALT and HALT modes are the two lowest power consumption modes of the MCU. They are both entered by executing the `HALT' instruction. The decision to enter either in ACTIVE-HALT or HALT mode is given by the LTCSR/ATCSR register status as shown in the following table:.
ATCSR LTCSR ATCSR ATCSR OVFIE TBIE bit CK1 bit CK0 bit bit 0 0 0 1 x x 0 1 x 1 x x 1 x 0 0 x 1 x 1 AC TIVE-HALT mode enabled AC TIVE-HALT mode disabled H A L T INSTR UCTIO N (Active Halt enabled) Meaning
Figure 25. ACTIVE-HALT Timing Overview
RUN ACTIVE HA LT 256 CPU CYCLE DELAY 1) RESET OR INTER RUPT RUN
HA LT IN STRUCTION [Active Halt Enabled]
FE TCH VECTOR
Figure 26. ACTIVE-HALT Mode Flow-chart
OSCILLATOR ON PERIPHERALS 2) OFF CP U OFF I BI T 0
9.4.1 ACTIVE-HALT MODE ACTIVE-HALT mode is the lowest power consumption mode of the MCU with a real time clock available. It is entered by executing the `HALT' instruction when active halt mode is enabled. The MCU can exit ACTIVE-HALT mode on reception of a Lite Timer / AT Timer interrupt or a RESET. When exiting ACTIVE-HALT mode by means of a RESET, a 256 CPU cycle delay occurs. After the start up delay, the CPU resumes operation by fetching the reset vector which woke it up (see Figure 26). When exiting ACTIVE-HALT mode by means of an interrupt, the CPU immediately resumes operation by servicing the interrupt vector which woke it up (see Figure 26). When entering ACTIVE-HALT mode, the I bit in the CC register is cleared to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In ACTIVE-HALT mode, only the main oscillator and the selected timer counter (LT/AT) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). Caution: As soon as ACTIVE-HALT is enabled, executing a HALT instruction while the Watchdog is active does not generate a RESET if the WDGHALT bit is reset. This means that the device cannot spend more than a defined delay in this power saving mode.
N RE SET N Y INTERRUPT 3) Y OSCILLATOR ON PERIPHERALS 2) OFF CP U ON I BI T X 4) 256 CPU C LOCK CYCLE DELAY OSCILLATOR PERIPHERALS CP U I BI T S ON ON ON X 4)
FETC H RES ET VEC TOR OR SERVICE INTERRUPT
Notes: 1. This delay occurs only if the MCU exits ACTIVEHALT mode by means of a RESET. 2. Peripherals clocked with an external clock source can still be active. 3. Only the Lite Timer RTC and AT Timer interrupts can exit the MCU from ACTIVE-HALT mode. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
39/124
1
ST7LITE0xY0, ST7LITESxY0
POWER SAVING MODES (Cont'd) 9.4.2 HALT MODE The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the `HALT' instruction when active halt mode is disabled. The MCU can exit HALT mode on reception of either a specific interrupt (see Table 6, "Interrupt Mapping," on page 30) or a RESET. When exiting HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 256 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 28). When entering HALT mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes immediately. In HALT mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of Watchdog operation with HALT mode is configured by the "WDGHALT" option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see section 15.1 on page 112 for more details). Figure 27. HALT Timing Overview
RUN HA LT 256 CPU CYC LE D ELAY RESET OR INTER RUPT FE TCH VECTOR RUN
Figure 28. HALT Mode Flow-chart
H AL T INSTRUCTION (Active Halt disabled) ENABLE W D GH A L T 1 ) 1 W ATCHDO G RE SET OSCILLATOR OFF PERIPHERALS 2) OFF CP U OFF I BI T 0 N RE SET N Y INTERRUPT 3) Y OSCILLATOR PERIPHERALS CP U I BI T ON OFF ON X 4) 0 W ATCHDOG DISABLE
256 CPU C LOCK CYCLE DELAY OSCILLATOR PERIPHERALS CP U I BI T S ON ON ON X 4)
FETC H RES ET VEC TOR OR SERVICE INTERRUPT
HA LT IN STRUCTION [Active Halt disabled]
Notes: 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 6, "Interrupt Mapping," on page 30 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. 5. If the PLL is enabled by option byte, it outputs the clock after a delay of tSTARTUP (see Figure 13).
40/124
1
ST7LITE0xY0, ST7LITESxY0
POWER SAVING MODES (Cont'd) 9.4.2.1 HALT Mode Recommendations Make sure that an external event is available to wake up the microcontroller from Halt mode. When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as "Input Pull-up with Interrupt" before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure. The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E. As the HALT instruction clears the I bit in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt).
41/124
1
ST7LITE0xY0, ST7LITESxY0
10 I/O PORTS
10.1 INTRODUCTION The I/O ports offer different functional modes: transfer of data through digital inputs and outputs and for specific pins: external interrupt generation alternate signal input/output for the on-chip peripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 10.2 FUNCTIONAL DESCRIPTION Each port has 2 main registers: Data Register (DR) Data Direction Register (DDR) and one optional register: Option Register (OR) Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is shown in Figure 29 10.2.1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Note: Writing the DR register modifies the latch value but does not affect the pin status. External interrupt function When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the EICR register. Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt source, these are logically ANDed. For this reason if one of the interrupt pins is tied low, it may mask the others. External interrupts are hardware interrupts. Fetching the corresponding interrupt vector automatically clears the request latch. Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts. Spurious interrupts When enabling/disabling an external interrupt by setting/resetting the related OR register bit, a spurious interrupt is generated if the pin level is low and its edge sensitivity includes falling/rising edge. This is due to the edge detector input which is switched to '1' when the external interrupt is disabled by the OR register. To avoid this unwanted interrupt, a "safe" edge sensitivity (rising edge for enabling and falling edge for disabling) has to be selected before changing the OR register bit and configuring the appropriate sensitivity again. Caution: In case a pin level change occurs during these operations (asynchronous signal input), as interrupts are generated according to the current sensitivity, it is advised to disable all interrupts before and to reenable them after the complete previous sequence in order to avoid an external interrupt occurring on the unwanted edge. This corresponds to the following steps: 1. To enable an external interrupt: set the interrupt mask with the SIM instruction (in cases where a pin level change could occur) select rising edge enable the external interrupt through the OR register select the desired sensitivity if different from rising edge reset the interrupt mask with the RIM instruction (in cases where a pin level change could occur) 2. To disable an external interrupt: set the interrupt mask with the SIM instruction SIM (in cases where a pin level change could occur) select falling edge disable the external interrupt through the OR register select rising edge
42/124
1
ST7LITE0xY0, ST7LITESxY0
reset the interrupt mask with the RIM instruction (in cases where a pin level change could occur) Output Modes The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status:
DR 0 1 Push-pull VS S VDD Open-drain Vss Floating
Note: When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output.
10.2.2 Alternate Functions When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming under the following conditions: When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin must be configured in floating input mode. In this case, the pin state is also digitally readable by addressing the DR register. Notes: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.
43/124
1
ST7LITE0xY0, ST7LITESxY0
I/O PORTS (Cont'd) Figure 29. I/O Port General Block Diagram
REGISTER ACCESS ALTERNATE O UT PUT 1 0 ALTERNATE EN ABLE DR
VDD
P-BUFFER (see table below) PULL-UP (see table below) VDD
DDR PULL-UP CON DITION If implemented OR SEL N-BUFFER DDR SEL CMOS SCHMITT TRIG GER ANALO G INPUT DIO D ES (see table below) PA D
OR
EXTE RNAL INTERR UPT SOURCE (eix)
Table 9. I/O Port Mode Options
Configuration Mode Input O u tput Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) Pull-Up Off On Off P-Buffer Off On Off On On Diodes to VDD t o VS S
Legend: NI - not implemented Off - implemented not activated On - implemented and activated
44/124
DATA BUS
DR SEL
1 0
ALTERNATE INPUT FROM OTHE R BITS
POLA RITY SELECTION
1
ST7LITE0xY0, ST7LITESxY0
I/O PORTS (Cont'd) Table 10. I/O Port Configurations
Hardware Configuration
VDD RPU PAD PULL-UP CONDITION DR REGISTER ACCESS
DR REGISTER
W DATA BUS R
INPUT 1)
ALTERNATE INPUT FROM OTHER PINS INTERRUPT CONDITION POLARITY SELECTION ANALOG INPUT EXTERNAL INTERRUPT SOURCE (eix)
OPEN-DRAIN O UTPUT 2 )
VDD RPU PAD
DR REGISTER ACCESS
DR REGISTER
R/W
DATA BUS
ALTERNATE ENABLE
ALTERNATE OUTPUT
P U S H - P U L L OU T P U T 2 )
VDD RPU PAD
DR REGISTER ACCESS
DR REGISTER
R/W
DATA BUS
ALTERNATE ENABLE
ALTERNATE OUTPUT
Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.
45/124
1
ST7LITE0xY0, ST7LITESxY0
I/O PORTS (Cont'd) CAUTION: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin. WARNING: The analog input voltage level must be within the limits stated in the absolute maximum ratings. 10.3 UNUSED I/O PINS Unused I/O pins must be connected to fixed voltage levels. Refer to Section 13.8. 10.4 LOW POWER MODES
Mode WAIT H AL T Description No effect on I/O ports. External interrupts cause the device to exit from WAIT mode. No effect on I/O ports. External interrupts cause the device to exit from HALT mode. 01
INPUT floating/pull-up interrupt
10.5 INTERRUPTS The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the interrupt mask in the CC register is not active (RIM instruction).
Interrupt Event External interrupt on selected external event Enable Event Control Flag Bit DDRx OR x Exit from Wait Yes Exit from Halt Yes
10.6 I/O PORT IMPLEMENTATION The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 30 Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. Figure 30. Interrupt I/O Port State Transitions
00
INPUT floating (reset state)
10
OUTPUT open-drain
11
OUTPUT push-pull
XX
= DDR, OR
The I/O port register configurations are summarised as follows. Table 11. Port Configuration
Port Pin name
PA7 Port A PA6:1 PA0 PB4 PB3 PB2:1 PB0
Input (DDR=0) OR = 0 OR = 1
floating floating floating floating floating floating floating pull-up interrupt pull-up pull-up interrupt pull-up pull-up interrupt pull-up pull-up interrupt
Output (DDR=1) OR = 0 OR = 1
open drain open drain open drain open drain open drain open drain open drain push-pull push-pull push-pull push-pull push-pull push-pull push-pull
Port B
46/124
1
ST7LITE0xY0, ST7LITESxY0
I/O PORTS (Cont'd) Table 12. I/O Port Register Map and Reset Values
Address (Hex.) 0000h 0001h 0002h 0003h 0004h 0005h Register Label P ADR Reset Value P ADDR Reset Value P A OR Reset Value P BDR Reset Value P BDDR Reset Value P B OR Reset Value 7 M SB 0 M SB 0 M SB 0 M SB 1 M SB 0 M SB 0 6 5 4 3 2 1 0 LSB 0 LSB 0 LSB 0 LSB 0 LSB 0 LSB 0
0 0 1 1 0 0
0 0 0 1 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
47/124
1
ST7LITE0xY0, ST7LITESxY0
11 ON-CHIP PERIPHERALS
11.1 LITE TIMER (LT) 11.1.1 Introduction The Lite Timer can be used for general-purpose timing functions. It is based on a free-running 8-bit upcounter with two software-selectable timebase periods, an 8-bit input capture register and watchdog function. 11.1.2 Main Features Realtime Clock 8-bit upcounter 1 ms or 2 ms timebase period (@ 8 MHz fOSC) Maskable timebase interrupt Input Capture 8-bit input capture register (LTICR) Maskable interrupt with wakeup from Halt Mode capability Figure 31. Lite Timer Block Diagram
fLTIMER
To 12-bit AT TImer
Watchdog Enabled by hardware or software (configurable by option byte) Optional reset on HALT instruction (configurable by option byte) Automatically resets the device unless disable bit is refreshed Software reset (Forced Watchdog reset) Watchdog reset status flag
fWDG fOSC/32 8-bit UPCOUNTER /2 fLTIMER 1
WA TCHDOG
WATCHDOG RESET
Timebase 1 or 2 ms 0 (@ 8 MHz fOSC)
LTICR
8
LTIC
8-bit INPUT CAPTURE REGISTER LTCSR
ICIE 7 ICF TB TBIE TBF WDG RF WDGE WDGD 0
LTTB INTERRUPT REQUEST LTIC INTERRUPT REQUEST
48/124
1
ST7LITE0xY0, ST7LITESxY0
LITE TIMER (Cont'd) 11.1.3 Functional Description The value of the 8-bit counter cannot be read or written by software. After an MCU reset, it starts incrementing from 0 at a frequency of fOSC/32. A counter overflow event occurs when the counter rolls over from F9h to 00h. If fOSC = 8 MHz, then the time period between two counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the LTCSR register. When the timer overflows, the TBF bit is set by hardware and an interrupt request is generated if the TBIE is set. The TBF bit is cleared by software reading the LTCSR register. 11.1.3.1 Watchdog The watchdog is enabled using the WDGE bit. The normal Watchdog timeout is 2ms (@ = 8 MHz fOSC), after which it then generates a reset. To prevent this watchdog reset occuring, software must set the WDGD bit. The WDGD bit is cleared by hardware after tWDG. This means that software must write to the WDGD bit at regular intervals to prevent a watchdog reset occurring. Refer to Figure 32. If the watchdog is not enabled immediately after reset, the first watchdog timeout will be shorter than 2ms, because this period is counted starting from reset. Moreover, if a 2ms period has already elapsed after the last MCU reset, the watchdog reset will take place as soon as the WDGE bit is set. For these reasons, it is recommended to enable the Watchdog immediately after reset or else to set the WDGD bit before the WGDE bit so a watchdog reset will not occur for at least 2ms. A Watchdog reset can be forced at any time by setting the WDGRF bit. To generate a forced
watchdog reset, first watchdog has to be activated by setting the WDGE bit and then the WDGRF bit has to be set. The WDGRF bit also acts as a flag, indicating that the Watchdog was the source of the reset. It is automatically cleared after it has been read. Caution: When the WDGRF bit is set, software must clear it, otherwise the next time the watchdog is enabled (by hardware or software), the microcontroller will be immediately reset. Hardware Watchdog Option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGE bit in the LTCSR is not used. Refer to the Option Byte description in the "device configuration and ordering information" section. Using Halt Mode with the Watchdog (option) If the Watchdog reset on HALT option is not selected by option byte, the Halt mode can be used when the watchdog is enabled. In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the Lite Timer stops counting and is no longer able to generate a Watchdog reset until the microcontroller receives an external interrupt or a reset. If an external interrupt is received, the WDG restarts counting after 256 CPU clocks. If a reset is generated, the Watchdog is disabled (reset state). If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT instruction), it is recommended before executing the HALT instruction to refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
49/124
1
ST7LITE0xY0, ST7LITESxY0
LITE TIMER (Cont'd) Figure 32. Watchdog Timing Diagram
HARDWARE CLEARS WDGD BIT
fWDG WDGD BIT INTERN AL WATCHDOG RESET
tWDG (2ms @ 8 MHz fOSC)
SOFTWARE SETS WDGD BIT
WATCHDOG RESET
50/124
1
ST7LITE0xY0, ST7LITESxY0
LITE TIMER (Cont'd) Input Capture The 8-bit input capture register is used to latch the free-running upcounter after a rising or falling edge is detected on the LTIC pin. When an input capture occurs, the ICF bit is set and the LTICR register contains the value of the free-running upcounter. An interrupt is generated if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register. The LTICR is a read only register and always contains the data from the last input capture. Input capture is inhibited if the ICF bit is set. 11.1.4 Low Power Modes
M ode SLOW W A IT ACTIVE HALT HALT Description No effect on Lite timer (this peripheral is driven directly by fOSC/32) No effect on Lite timer No effect on Lite timer Lite timer stops counting
11.1.5 Interrupts
Interrupt Event Timebase Event IC Event Event Flag TBF ICF Enable Control Bit TBIE ICIE Exit Exit from from Wait Halt Yes No Exit from ActiveHalt Yes No
Note: The TBF and ICF interrupt events are connected to separate interrupt vectors (see Interrupts chapter). Timebase and IC events generate an interrupt if the enable bit is set in the LTCSR register and the interrupt mask in the CC register is reset (RIM instruction).
Figure 33. Input Capture Timing Diagram
4s (@ 8 MHz fOSC)
fCPU fOSC/32 CLEA RED BY S/W READING LTIC REGISTER
8-bit COUNTER
01h
02h
03h
04h
05h
06h
07h
LTIC PIN ICF FLAG LTIC R R EGIST E R xxh 04h 07h
t
51/124
1
ST7LITE0xY0, ST7LITESxY0
LITE TIMER (Cont'd) 11.1.6 Register Description LITE TIMER CONTROL/STATUS REGISTER (LTCSR) Read / Write Reset Value: 0x00 0000 (x0h)
7 ICIE ICF TB TBIE TBF 0 WDGR WDGE WDGD
0: No counter overflow 1: A counter overflow has occurred Bit 2 = WDGRF Force Reset/ Reset Status Flag This bit is used in two ways: it is set by software to force a watchdog reset. It is set by hardware when a watchdog reset occurs and cleared by hardware or by software. It is cleared by hardware only when an LVD reset occurs. It can be cleared by software after a read access to the LTCSR register. 0: No watchdog reset occurred. 1: Force a watchdog reset (write), or, a watchdog reset occurred (read). Bit 1 = WDGE Watchdog Enable This bit is set and cleared by software. 0: Watchdog disabled 1: Watchdog enabled Bit 0 = WDGD Watchdog Reset Delay This bit is set by software. It is cleared by hardware at the end of each tWDG period. 0: Watchdog reset not delayed 1: Watchdog reset delayed LITE TIMER INPUT CAPTURE REGISTER (LTICR) Read only Reset Value: 0000 0000 (00h)
7 ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 0 ICR0
Bit 7 = ICIE Interrupt Enable This bit is set and cleared by software. 0: Input Capture (IC) interrupt disabled 1: Input Capture (IC) interrupt enabled Bit 6 = ICF Input Capture Flag This bit is set by hardware and cleared by software by reading the LTICR register. Writing to this bit does not change the bit value. 0: No input capture 1: An input capture has occurred Note: After an MCU reset, software must initialise the ICF bit by reading the LTICR register Bit 5 = TB Timebase period selection This bit is set and cleared by software. 0: Timebase period = tOSC * 8000 (1ms @ 8 MHz) 1: Timebase period = tOSC * 16000 (2ms @ 8 MHz) Bit 4 = TBIE Timebase Interrupt enable This bit is set and cleared by software. 0: Timebase (TB) interrupt disabled 1: Timebase (TB) interrupt enabled Bit 3 = TBF Timebase Interrupt Flag This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect.
Bit 7:0 = ICR[7:0] Input Capture Value These bits are read by software and cleared by hardware after a reset. If the ICF bit in the LTCSR is cleared, the value of the 8-bit up-counter will be captured when a rising or falling edge occurs on the LTIC pin.
Table 13. Lite Timer Register Map and Reset Values
Address (Hex.) 0B 0C Register Label LTC SR Reset Value LTICR Reset Value 7 ICIE 0 ICR7 0 6 ICF x ICR6 0 5 TB 0 ICR5 0 4 TBIE 0 ICR4 0 3 TBF 0 ICR3 0 2 WDG R F 0 ICR2 0 1 WDG E 0 ICR1 0 0 W D GD 0 ICR0 0
52/124
1
ST7LITE0xY0, ST7LITESxY0
11.2 12-BIT AUTORELOAD TIMER (AT) 11.2.1 Introduction The 12-bit Autoreload Timer can be used for general-purpose timing functions. It is based on a freerunning 12-bit upcounter with a PWM output channel. 11.2.2 Main Features 12-bit upcounter with 12-bit autoreload register (ATR) Maskable overflow interrupt Figure 34. Block Diagram
7 ATCSR 0 0 0 CK1 CK 0 0 OVF O V F I E C M P I E OVF INTERRUPT REQUEST
PWM signal generator Frequency range 2KHz-4MHz (@ 8 MHz fCPU) Programmable duty-cycle Polarity control Maskable Compare interrupt Output Compare Function
fLTIMER (1 ms timebase @ 8MHz) f CPU
CMPF0 fCOUNTER CNTR 12-BIT UPCOUNTER
CMP INTERRUPT REQUEST
Update on OVF Event
12-BIT AUTORELOAD VALUE
ATR OE0 bit PWM GENERATION OE0 bit CMPF0 bit 0 COM PPARE OP0 bit fPWM POLARITY OUTPUT CONTROL DCR0H DCR0L
Preload
Preload on OVF Event IF OE0=1
PW M0
1
12-BIT DUTY CYCLE VALUE (shadow)
53/124
1
ST7LITE0xY0, ST7LITESxY0
12-BIT AUTORELOAD TIMER (Cont'd) 11.2.3 Functional Description PWM Mode This mode allows a Pulse Width Modulated signals to be generated on the PWM0 output pin with minimum core processing overhead. The PWM0 output signal can be enabled or disabled using the OE0 bit in the PWMCR register. When this bit is set the PWM I/O pin is configured as output pushpull alternate function. Note: CMPF0 is available in PWM mode (see PWM0CSR description on page 57). PWM Frequency and Duty Cycle The PWM signal frequency (fPWM) is controlled by the counter period and the ATR register value. fPWM = fCOUNTER / (4096 - ATR) Following the above formula, if fCPU is 8 MHz, the maximum value of fPWM is 4 Mhz (ATR register value = 4094), and the minimum value is 2 kHz (ATR register value = 0). Note: The maximum value of ATR is 4094 because it must be lower than the DCR value which must be 4095 in this case. At reset, the counter starts counting from 0. Software must write the duty cycle value in the DCR0H and DCR0L preload registers. The DCR0H register must be written first. See caution below.
When a upcounter overflow occurs (OVF event), the ATR value is loaded in the upcounter, the preloaded Duty cycle value is transferred to the Duty Cycle register and the PWM0 signal is set to a high level. When the upcounter matches the DCRx value the PWM0 signals is set to a low level. To obtain a signal on the PWM0 pin, the contents of the DCR0 register must be greater than the contents of the ATR register. The polarity bit can be used to invert the output signal. The maximum available resolution for the PWM0 duty cycle is: Resolution = 1 / (4096 - ATR) Note: To get the maximum resolution (1/4096), the ATR register must be 0. With this maximum resolution and assuming that DCR=ATR, a 0% or 100% duty cycle can be obtained by changing the polarity . Caution: As soon as the DCR0H is written, the compare function is disabled and will start only when the DCR0L value is written. If the DCR0H write occurs just before the compare event, the signal on the PWM output may not be set to a low level. In this case, the DCRx register should be updated just after an OVF event. If the DCR and ATR values are close, then the DCRx register shouldbe updated just before an OVF event, in order not to miss a compare event and to have the right signal applied on the PWM output.
Figure 35. PWM Function
4095 DUTY CYCLE R EGIST ER (DCR0)
COUNTER
AUT O-RELO A D RE GISTER (ATR) 000
t
PWM0 OUTPUT
WITH OE0=1 AND OP0=0 WITH OE0=1 AND OP0=1
54/124
1
ST7LITE0xY0, ST7LITESxY0
12-BIT AUTORELOAD TIMER (Cont'd) Figure 36. PWM Signal Example
fCOUNTER ATR= FFDh PWM0 OUTPUT WITH OE0=1 AND OP0=0 COUNTER FFDh FFEh FFFh FFDh FF Eh FFFh FFDh FFEh
DCR0=FFEh
t
Output Compare Mode To use this function, the OE bit must be 0, otherwise the compare is done with the shadow register instead of the DCRx register. Software must then write a 12-bit value in the DCR0H and DCR0L registers. This value will be loaded immediately (without waiting for an OVF event). The DCR0H must be written first, the output compare function starts only when the DCR0L value is written. When the 12-bit upcounter (CNTR) reaches the value stored in the DCR0H and DCR0L registers, the CMPF0 bit in the PWM0CSR register is set and an interrupt request is generated if the CMPIE bit is set. Note: The output compare function is only available for DCRx values other than 0 (reset value). Caution: At each OVF event, the DCRx value is written in a shadow register, even if the DCR0L value has not yet been written (in this case, the shadow register will contain the new DCR0H value and the old DCR0L value), then: If OE=1 (PWM mode): the compare is done between the timer counter and the shadow register (and not DCRx) if OE=0 (OCMP mode): the compare is done between the timer counter and DCRx. There |
