STS1DNC45
DUAL N-CHANNEL 450V - 4.1 - 0.4A SO-8 SuperMESHTM POWER MOSFET
TYPE STS1DNC45
s s
V DS S 450 V
RDS(on) < 4.5
ID 0.4 A
s
TYPICAL RDS(on) = 4.1 STANDARD OUTLINE FOR EASY AUTOMATED SURFACE MOUNT ASSEMBLY GATE CHARGE MINIMIZED
DESCRIPTION The SuperMESH TM series is obtained through an extreme optimization of ST's well established stripbased PowerMESHTM layout. In addition to pushing on-resistance significantly dow n, special care is taken to ensure a very good dv/dt ca pab ility for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmeshTM products.
SO-8
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS SWITCH MODE LOW POWER SUPPLIES (SMPS) s DC-DC CONV E RTE RS s LOW P O WE R, LOW CO S T CFL (COM P AC T FLUORESCEN T LAMPS) s LOW P O WE R B A TT E RY CHA RGE RS
s
ABSOLUTE MAXIMUM RA TINGS
Symbol VDS VD G R V GS ID I DM ( ) PTOT dv/dt(1) Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Dual Operation Total Dissipation at TC = 25C Single Operation Peak Diode Recovery voltage slope Value 4 50 4 50 30 0.40 0.25 1.6 1.6 2 3
(1)ISD 0.4 A, di/dt 100A/s, VDD V(BR)DSS, Tj TJMAX.
Unit V V V A A A W W V/ns
(q ) Pulse width limited by safe operating area
June 2003
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THERMAL DATA
Rthj-amb(#) Tj Tstg Thermal Resistance Junction-ambient Max Single Operation Thermal Resistance Junction-ambient Max Dual Operation Max. Operating Junction Temperature Storage Temperature 62.5 78 150 65 to 150 C/W C/W C C
(#) When Mounted on FR4 board (Steady State)
AVA LANCHE CHARACTERISTICS
Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 C, ID = IAR, VDD = 50 V) Max Value 0.4 30 Unit A mJ
ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPEC IFIED) OFF
Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C VGS = 30V Min. 450 1 50 100 Typ. Max. Unit V A A nA
ON ( 1 )
Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS, ID = 250A VGS = 10 V, ID = 0.5 A Min. 2.3 Typ. 3 4.1 Max. 3.7 4.5 Unit V
DYN AMIC
Symbol gfs (1) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS = 25 V, ID = 0.5 A VDS = 25 V, f = 1 MHz, VGS = 0 Min. Typ. 1.1 160 27.5 4.7 Max. Unit S pF pF pF
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STS1DNC45
ELECTRICAL CHARACTERISTICS (CONTINUED) SW ITCHIN G ON
Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 225 V, ID = 0.5 A RG = 4.7 VGS = 10 V (see test circuit, Figure 3) VDD = 360 V, ID = 1.5 A, VGS = 10 V Min. Typ. 6.7 4 7 1.3 3.2 10 Max. Unit ns ns nC nC nC
SW ITCHIN G OFF
Symbol tr(off) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Conditions VDD = 360 V, ID = 1.5 A RG = 4.7, VGS = 10 V (see test circuit, Figure 5) Min. Typ. 8.5 12 18 Max. Unit ns ns ns
SOURCE DR AIN DIODE
Symbol ISD ISDM (2) VSD (1) tr r Q rr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 0.4 A, VGS = 0 ISD = 0.4 A, di/dt = 100A/s, VDD = 100 V, Tj = 150C (see test circuit, Figure 5) 225 530 4.7 Test Conditions Min. Typ. Max. 0.4 1.6 1.6 Unit A A V ns nC A
Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. 2. Pulse width limited by safe operating area.
Safe Operating A rea
Thermal Impedance
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STS1DNC45
Output Characteristics Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
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STS1DNC45
Normalized Gate Threshold Voltage vs Temp. Normalized On Resistance vs Temperature
Source-drain Diode Forward Characteristics
Normalized B VDSS vs Temperature
Max Id Current vs Tc
Maximum Avalanche Energy vs Temperature
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STS1DNC45
Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuit For Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times
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STS1DNC45
SO-8 MECHANICAL DATA
DIM. MIN. A a1 a2 a3 b b1 C c1 D E e e3 F L M S 3.8 0.4 4.8 5.8 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.14 0.015 5.0 6.2 0.65 0.35 0.19 0.25 0.1 mm TYP. MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45 (typ.) 0.188 0.228 0.050 0.150 0.157 0.050 0.023 0.196 0.244 0.025 0.013 0.007 0.010 0.003 MIN. inch TYP. MAX. 0.068 0.009 0.064 0.033 0.018 0.010 0.019
0016023
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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