LNBP21
LNBP SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACE
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C OMPLETE INTERFACE BETWEEN LNB AND I2CTM BUS BUILT-IN DC/DC CONTROLLER FOR SINGLE 12V SUPPLY OPERATION ACCUR ATE BUILT-IN 22KHz TONE OSCILLATOR SUITS WIDELY ACCEPTED STANDARDS FAST OSCILLATOR START-UP FACILITATES DiSEqCTM ENCODING BUILT-IN 22KHz TONE DETECTOR SUPPORTS BI-DIRECTIONAL DiSEqCTM LOOP-THROUGH FUNCTION FOR SLAVE OPERATION LNB SHORT CIRCUIT PROTECTION AND DIAGNOSTIC C ABLE LENGTH DIGITAL COMPENSATION INTERNAL OVER TEMPERATURE PROTECTION ESD RATING 4KV ON POWER INPUT-OUTPUT PINS
PowerSO-20
SO-20
DESCRIPTION Intended for analog and digital satellite STB receivers/SatTV, sets/PC cards, the LNBP21 is a monolithic voltage regulator and interface IC, assembled in SO-20 and PowerSO-20, specifically designed to provide the power and the 13/18V, 22KHz tone signalling to the LNB down converter in the antenna or to the multiswitch box. In this application field, it offers a complete solution with extremely low component count, low
Figure 1: Block Diagram
Gate Sense
Step -u p Co ntrolle r
LNBP21 LT1
Feedb ack
LT2 Vup Vcc Byp
OUT
Prere gul.+ U.V.lo cko ut +P.ON res. Enable I Select V Select Line ar Post-reg +Modulator +Protections
EXTM
SDA SCL ADDR DSQIN
I ēC interf. 22 KH z Oscill.
Di agno stics
DETIN
Tone Detector
DSQOUT
October 2004
Rev. 3
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LNBP21
power dissipation together with simple design and I2CTM standard interfacing. This IC has a built in DC/DC step-up controller that, from a single supply source ranging from 8 to 15V, generates the voltages that let the linear post-regulator to work at a minimum dissipated power. An UnderVoltage Lockout circuit will disable the whole circuit when the supplied VCC drops below a fixed threshold (6.7V typically). The internal 22KHz tone generator is factory trimmed in accordance to the standards, and can be controlled either by the I2CTM interface or by a dedicated pin (DSQIN) that allows immediate DiSEqCTM data encoding (*). All the functions of this IC are controlled via I2CTM bus by writing 6 bits on the System Register (SR, 8 bits). The same register can be read back, and two bits will report the diagnostic status. When the IC is put in Stand-by (EN bit LOW), the power blocks are disabled and the loop-through switch between LT1 and LT2 pins is closed, thus leaving all LNB powering and control functions to the Master Receiver (**). When the regulator blocks are active (EN bit HIGH), the output can be logic controlled to be 13 or 18 V (typ.) by mean of the VSEL bit (Voltage SELect) for remote controlling of non-DiSEqC LNBs. Additionally, it is possible to increment by 1V (typ.) the selected voltage value to compensate for the excess voltage drop along the coaxial cable (LLC bit HIGH). In order to minimize the power dissipation, the output voltage of the internal step-up converter is adjusted to allow the linear regulator to work at minimum dropout. Another bit of the SR is addressed to the remote control of non-DiSEqC LNBs: the TEN (Tone ENable) bit. When it is set to HIGH, a continuous 22KHz tone is generated regardless of the DSQIN pin logic status. The TEN bit must be set LOW when the DSQIN pin is used for DiSEqCTM encoding. The fully bidirectional DiSEqCTM interfacing is completed by the built-in 22KH z tone detector. Its input pin (DETIN) must be AC coupled to the DiSEqCTM bus, and the extracted PWK data are available on the DSQOUT pin (*). In order to improve design flexibility and to allow implementation of newcoming LNB remote control standards, an analogic modulation input pin is available (EXTM). An appropriate DC blocking capacitor must be used to couple the modulating signal source to the EXTM pin. When external modulation is not used, the relevant pin can be left o pen. The current limitation block has two thresholds that can be selected by the ISEL bit of the SR; the lower threshold is between 400 and 550mA (ISEL=HIGH), while the higher threshold is between 500 and 650mA (ISEL=LOW ). The current protection block is SOA type. This limits the short circuit current (ISC) typically at 200mA with ISEL=HIGH and at 300mA with ISEL=LOW when the output port is connected to ground. It is possible to set the Short Circuit Current protection either statically (simple current clamp) or dynamically by the PCL bit of the SR; when the PCL (Pulsed Current Limiting) bit is set to LOW, t he overcurrent protection circuit works dynamically: as soon as an overload is detected, the output is shut-down for a time toff, typically 900ms. Simultaneously the OLF bit of the System Register is set to HIGH. After this time has elapsed, the output is resumed for a time ton=1/ 10toff (typ.). At the end of ton, if the overload is still detected, the protection circuit will cycle again through Toff and Ton. At the end of a full Ton in which no overload is detected, normal operation is resumed and the OLF bit is reset to LOW. Typical Ton+Toff time is 990ms and it is determined by an internal timer. This dynamic operation can greatly reduce the power dissipation in short circuit condition, still ensuring excellent power-on start up in most conditions (**). However, there could be some cases in which an highly capacitive load on the output may cause a difficult start-up when the dynamic protection is chosen. This can be solved by initiating any power start-up in static mode (PCL=HIGH) and then switching to the dynamic mode (PCL=LOW) after a chosen amount of time. When in static mode, the OLF bit goes HIGH when the current clamp limit is reached and returns LOW when the overload condition is cleared. This IC is also protected against overheating: when the junction temperature exceeds 150C (typ.), the step-up converter and the linear regulator are shut off, the loop-trough switch is opened, and the OTF bit of the SR is set to HIGH. Normal operation is resumed and the OTF bit is reset to LOW when the junction is cooled down to 140C (typ.).
(*): External components are needed to comply to bi-directional DiSEqCTM bus hardware requirements. Full compliance of the whole application to DiSEqCTM specifications is not implied by the use of this IC. (**): The current limitation circuit has no effect on the loop-through switch. When EN bit is LOW, the current flowing from LT1 to LT2 must be externally limited.
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LNBP21
Table 1: Ordering Codes
TYPE LNBP21 SO-20 (Tube) LNBP21D2 SO-20 (Tape & Reel) LNBP21D2-TR PowerSO-20 (Tube) LNBP21PD PowerSO-20 (Tape & Reel) LNBP21PD-TR
Table 2: Absolute Maximum Ratings
Symbol VCC VUP IO VO VI VDETIN VOH ILT VLT IGATE VSENSE Tstg Top DC Input Voltage DC Input Voltage Output Current DC Output Pin Voltage Logic Input Voltage (SDA, SCL, DSQIN) Detector Input Signal Amplitude Logic High Output Voltage (DSQOUT) Bypass Switch ON Current Bypass Switch OFF Voltage Gate Current Current Sense Voltage Storage Temperature Range Operating Junction Temperature Range Parameter Value 16 25 20 Internally Limited -0.3 to 22 -0.3 to 7 2 7 900 20 400 -0.3 to 1 -0.3 to 7 -40 to +150 -40 to +125 Unit V V V mA V V VPP V mA V mA V V C C
VLT1, VLT2 DC Input Voltage
VADDRESS Address Pin Voltage
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
Table 3: Thermal Data
Symbol Rthj-case Parameter Thermal Resistance Junction-case SO-20 15 PowerSO-20 2 Unit C/W
Figure 2: Pin Configuration (top view)
S O- 2 0
PowerSO-20
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LNBP21
Table 4: Pin Description
PIN NUMBER vs. PACKAGE SO-20 VCC Supply Input 8V to 15V supply. A 220F bypass capacitor to GND with a 470nF (ceramic) in parallel is recommended External MOS switch Gate connection of the step-up converter Current Sense comparator input. Connected to current sensing resistor Input of the linear post-regulator. The voltage on this pin is monitored by internal step-ut controller to keep a minimum dropout across the linear pass transistor Output of the linear post regulator modulator to the LNB. See truth table for voltage selections. Bidirectional data from/to I2C bus. Clock from bus. When the TEN bit of the System Register is LOW, this pin will accept the DiSEqC code from the main controller. The LNBP21 will use this code to modulate the internally generated 22kHz carrier. Set to GND this pin if not used. 22kHz Tone Detector Input. Must be AC coupled to the DiSEqC bus. Open collector output of the tone Detector to the main controller for DiSEqC data decoding. It is LOW when tone is detected. External Modulation Input. Need DC decoupling to the AC source. If not used, can be left open. Pins to be connected to ground. Needed for internal pre regulator filtering In standby mode the power switch between LT1 and LT2 is closed. Max allowed current is 900mA. this pin can be left open if loopthrough function is not needed. Same as above bus addresses available by setting the Four Address Pin level voltage I2C I2C 19 PowerSO-20 18
SYMBOL
NA ME
FUNC TION
GATE SENSE Vup
External Switch Gate Current Sense Input Step-up Voltage
17 14 20
17 16 19
OUT SDA SCL DSQIN
Output Port Serial Data Serial Clock DiSEqC Input
1 11 12 13
2 12 13 14
DETIN
Detector In
9 10
9 15
DSQOUT DiSEqC Output
EXTM GND BYP LT1
External Modulator Ground Bypass Capacitor Loop Through Switch
4 5, 6, 15, 16 8 3
5 1, 6, 10, 11, 20 8 4
LT2 ADDR
Loop Through Switch Address Setting
2 7
3 7
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LNBP21
Figure 3: Typical Application Circuit
D1 1N4001 IC1
Master STB
Vup C2 220F C3 470nF
Ceramic
LT1 C7 10nF
IC2 (Note 3)
STS4DNFS30L
LT2 270H Gate
LNBP21
Vo C8 10nF D2 BAT43 15 ohm
to LNB
see Note 2
L1=22H
s R1 c 0.
Sense (Note 4)
DETIN (Note 1) Byp
C6 10nF
Vcc
Vin 12V
C1 220F
C4 470nF
Ceramic
C5 470nF EXTM ADDRESS GND DSQOUT B 0
DSQIN(Note 1) SCL SDA
(*) Set to GND if not used (**) filter to be used according to EUTELSAT recommendation to implement the DiSEqCTM 2.x, not needed if bidirectional DiSEqCTM 2.x is not implemented (see DiSEqC implementation note) (***) IC2 is a ST Fettky, STS4DNFS30L, that includes both the schottky diode and the N-Channel MosFet, needed for the DC/DC converter, in a So-8 package. It can be replaced by a schottky diode (STPS2L3A or similar) and a N-Channel MosFet (STN4NF03L or similar)
I2C BUS INTERFACE Data transmission from main P to the LNBP21 and viceversa takes place through the 2 wires I2C bus interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be externally connected). DA TA VALIDITY As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is L OW . START AND STOP CONDITIONS As shown in fig. 4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP conditions must be sent before each START condition. BYTE FORMAT Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an ac-knowledge bit. The MSB is transferred first.
A C K N OW L E D GE The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 4). The peripheral (LNBP21) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The peripheral which has been addressed has to generate an acknowledge after the reception of each byte, other-wise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. The LNBP21 won't generate the acknowledge if the VCC supply is below the Undervoltage Lockout threshold (6.7V typ.). TRANSMISSION WITHOUT ACKNOWLEDGE Avoiding to detect the acknowledge of the LNBP21, the P can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity.
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LNBP21
Figure 4: Data Validity On The I2C BUS
Figure 5: Timing Diagram On I2C Bus
Figure 6: Acknowledge On I2C Bus
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LNBP21
LNBP1 SOFTWARE DESCRIPTION INTERFACE PROTOCOL The interface protocol comprises: - A start condition (S)
CHIP ADDRESS MSB 0 LSB MSB R/W ACK
- A chip address byte = hex 10 / 11 (the LSB bit determines read(=1)/write(=0) transmission) - A sequence of data (1 byte + acknowledge) - A stop condition (P)
DATA LSB A CK P
S
0
0
1
0
0
0
ACK= Acknowledge S= Start P= Stop R/W= Read/Write
SYSTEM REGISTER (SR, 1 BYTE)
MS B R, W PCL R, W ISEL R, W TEN R, W LLC R, W VSEL R, W EN R OTF LSB R OLF
R,W= read and write bit R= Read-only bit All bits reset to 0 at Power-On
TRANSMITTED DATA (I2C BUS WRITE MODE) W hen the R/W bit in the chip address is set to 0, the main P can write on the System Register (SR) of the LNBP21 via I2C bus. Only 6 bits out of
PCL ISEL TEN LLC VSEL 0 0 1 1 0 1 0 1 0 1 X 0 1 0 1 EN 1 1 1 1 1 1 1 1 1 1 0 OTF X X X X X X X X X X X OLF X X X X X X X X X X X
the 8 available can be written by the P, since the remaining 2 are left to the diagnostic flags, and are read-only.
Function VOUT=13V, VUP=16V Loopthrough switch open VOUT=18V, VUP=21V Loopthrough switch open VOUT=14V, VUP=17V Loopthrough switch open VOUT=19V, VUP=22V Loopthrough switch open 22KHz tone is controlled by DSQIN pin 22KHz tone is ON, DSQIN pin disabled IOUT(min)=500mA, IOUT(max)=650mA ISC=300mA IOUT(min)=400mA, IOUT(max)=550mA ISC=300mA Pulsed (dynamic) current limiting is selected Static current limiting is selected Power blocks disabled, Loopthrough switch closed
X
X
X
X
X= don't care. Values are typical unless otherwise specified
RECEIVED DATA (I2C bus READ MODE) The LNBP21 can provide to the Master a copy of the SYSTEM REGISTER information via I2C bus in read mode. The read mode is Master activated by sending the chip address with R/W bit set to 1. At the following master generated clocks bits, the LNBP21 issues a byte on the SDA data bus line (MSB transmitted first). At the ninth clock bit the MCU master can:
- acknowledge the reception, starting in this way the transmission of another byte from the LNBP21; - no acknowledge, stopping the read mode communication. W hile the whole register is read back by the P, only the two read-only bits OLF and OTF convey diagnostic informations about the LNBP21.
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LNBP21
PCL
ISEL
TEN
LLC VSEL
EN
OTF 0
OLF
Function TJ<140C, normal operation TJ>150C, power block disabled, Loopthrough switch open
These bits are read exactly the same as they were left after last write operation
Values are typical unless otherwise specified
1 0 1
IOUTIOMAX, overload protection triggered
POWER-ON I2C INTERFACE RESET The I2C interface built in the LNBP21 is automatically reset at power-on. As long as the VCC stays be-low the UnderVoltage Lockout threshold (6.7V typ.), the interface will not respond to any I2C command and the System Register (SR) is initialized to all zeroes, thus keeping the power blocks disabled. Once the VCC rises above 7.3V, the I2C interface becomes operative and the SR can be configured by the main P. This is due to About 500mV of hysteresis provided in the UVL threshold to avoid false retriggering of the Power-On reset circuit. DiSEqCTM IMPLEMENTATION The LNBP21 helps the system designer to implement the bidirectional (2.x) DiSEqC protocol by allowing an easy PWK modulation/ demodulation of the 22KHz carrier. The PWK data are exchanged between the LNBP21 and the main P using logic levels that are compatible with both 3.3 and 5V microcontrollers. This data exchange is made through two dedicated pins, DSQIN and DSQOUT, in order to maintain the timing relationships between the PWK data and the PWK modulation as accurate as possible. These two pins should be directly connected to two I/O pins of the P, thus leaving to the resident firmware the task of encoding and decoding the
PW K data in accordance to the DiSEqC protocol. Full compliance of the system to the specification is thus not implied by the bare use of the LNBP21. The system designer should also take in consideration the bus hardware requirements, that include the source impedance of the Master Transmitter measured at 22KHz. To limit the attenuation at carrier frequency, this impedance has to be 15ohm at 22KHz, dropping to zero ohm at DC to allow the power flow towards the peripherals. This can be simply accomplished by the LR termination put on the OUT pin of the LNBP, as shown in the Typical Application Circuit on page 5. Unidirectional (1.x) DiSEqC and non-DiSEqC systems normally don't need this termination, and the OUT pin can be directly connected to the LNB supply port of the Tuner. There is also no need of Tone Decoding, thus, it is recommended to connect the DETIN and DSQOUT pins to ground to avoid EMI. AD DRESS PIN Connecting this pin to GND the Chip I2C interface address is 0001000, but, it is possible to choice among 4 different addresses simply setting this pin at 4 fixed voltage levels (see table on page 1 0) .
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LNBP21
Table 5: Electrical Characteristics For LNBP Series (TJ = 0 to 85C, EN=1, LLC=0, TEN=0, ISEL=0, PCL=0, DSQIN=0, VIN=12V, IOUT=50mA, unless otherwise specified. See software description section for I2C access to the system register)
Symbol VIN VLT1 IIN VO VO VO VO IMAX ISC tOFF tON fTONE ATONE DTONE tr, tf VEXTM ZEXTM VLT fSW fDETIN VDETIN ZDETIN V OL IOZ VIL VIH IIH Parameter Supply Voltage LT1 Input Voltage Supply Current Output Voltage Output Voltage Line Regulation Load Regulation Output Current Limiting Output Short Circuit Current Dynamic Overload protection OFF Time Dynamic Overload protection ON Time Tone Frequency Tone Amplitude Tone Duty Cycle Tone Rise and Fall Time External Modulation Input Voltage External Modulation Impedance Loopthrough Switch Voltage Drop (lt1 to LT2) DC/DC Converter Switch Frequency Tone Detector Frequency Capture Range Tone Detector Input Amplitude Tone Detector Input Impedance DSQOUT Pin Logic LOW DSQOUT Pin OFF State Leakage Current DSQIN Input Pin Logic LOW DSQIN Input Pin Logic HIGH DSQIN Pins Input Current PCL=0 PCL=0 TEN=1 TEN=1 TEN=1 TEN=1 VOUT/VEXTM, AC Coupling f = 10Hz to 50KHz EN=0, 19V ILT=300mA, VMI=12 or 260 0.35 220 0.4Vpp sinewave fIN=22kHz sinewave 18 0.2 150 Tone present Tone absent IOL=2mA VOH = 6V 0.3 0.5 10 0.8 2 VIH = 5V 15 24 1.5 0.6 f = 10Hz to 40KHz Output Shorted Output Shorted 20 0.55 40 5 EN=1 EN=0 IO = 500 mA VSEL=1 LLC=0 LLC=1 IO = 500 mA VSEL=0 LLC=0 LLC=1 VIN1=15 to 18V VSEL=0 VSEL=1 VSEL=0 or 1 IOUT = 50 to 500mA ISEL=1 ISEL=0 ISEL=1 ISEL=0 IO = 0mA TEN=VSEL=LLC=1 20 2.5 18 19 13 14 5 5 Test Conditions IO = 500 mA TEN=VSEL=LLC=1 Min. 8 Typ. Max. 15 20 40 5 18.7 13.5 40 60 200 550 650 200 300 900 tOFF/10 22 0.72 50 10 6 400 mVpp V kHz kHz Vpp k V A V V A 9/24 24 0.9 60 15 Unit V V mA mA V V V V mV mV mV mA mA mA mA ms ms KHz Vpp % s
17.3 12.5
400 500
GEXTM External Modulation Gain
LNBP21
Symbol IOBK TSHDN
Parameter Output Backward Current EN=0
Test Conditions VOBK = 18V
Min.
Typ. -4 150 15
Max. -10
Unit mA C C
Temperature Shutdown Threshold TSHDN Temperature Shutdown Hysteresis
Table 6: Gate And Sense Electrical Characteristics (TJ = 0 to 85C, VIN=12V)
Symbol Parameter Test Conditions IGATE=-100mA IGATE=100mA Min. Typ. 4.5 4.5 200 Max. Unit mV
RDSON-L Gate LOW RDSON RDSON-H Gate LOW RDSON VSENSE Current Limit Sense Voltage
Table 7: I2C Electrical Characteristics (TJ = 0 to 85C, VIN=12V)
Symbol VIL VIH IIH VIL fMAX Parameter LOW Level Input Voltage HIGH Level Input Voltage Input Current SDA, SCL SDA, SCL SDA, SCL, VIN= 0.4 to 4.5v 2 -10 10 0.6 500 Test Conditions Min. Typ. Max. 0.8 Unit V V A V KHz
DSQIN Input Pin Logic SDA (open drain), IOL = 6mA LOW Maximum Clock Frequency SCL
Table 8: Address Pin Characteristics (TJ = 0 to 85C, VIN=12V)
Symbol Parameter Test Conditions Min. 0 1.3 2.3 3.3 Typ. Max. 0.7 1.7 2.7 5 Unit V V V V
VADDR-1 "0001000" Addr Pin Voltage VADDR-2 "0001001" Addr Pin Voltage VADDR-3 "0001010" Addr Pin Voltage VADDR-4 "0001011" Addr Pin Voltage
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LNBP21
Figure 7: Test Circuit
1N4001
ILT Vup
STPS2L30A 220F 470nF
VMI, VOBK
LT1
10nF
A V
VLT
Scope Probe
STN4NF03L
Gate
L1 =22 H
LT2 IO , IOBK
10nF
Sense
Rsc
0 .1
Vin
IIN
OUT Vcc
A
VOUT
Load
A
220F 470n F
LNBP21 V
20F
From I2C Master
{
EXTM
SDA SCL
SDA SCL DETIN DSQIN
470nF
10nF
VEXTM, VDETIN
Pulse Gen.
BYP ADDRESS
DSQOUT VOL
A V
IOZ / IOL VOH / IOL
TYPICAL CHARACTERISTICS (unless otherwise specified Tj = 25C) Figure 8: Output Voltage vs Temperature Figure 9: Output Voltage vs Temperature
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LNBP21
Figure 10: Line Regulation vs Temperature Figure 13: Load Regulation vs Temperature
Figure 11: Line Regulation vs Temperature
Figure 14: Supply Current vs Temperature
Figure 12: Load Regulation vs Temperature
Figure 15: Supply Current vs Temperature
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LNBP21
Figure 16: Dynamic Overload Protection ON Time vs Temperature Figure 19: Output Current Limiting vs Temperature
Figure 17: Dynamic Overload Protection OFF Time vs Temperature
Figure 20: Tone Frequency vs Temperature
Figure 18: Output Current Limiting vs Temperature
Figure 21: Tone Amplitude vs Temperature
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LNBP21
Figure 22: Tone Duty Cycle vs Temperature Figure 25: Loopthrought Switch Drop Voltage vs Temperature
Figure 23: Tone Rise Time vs Temperature
Figure 26: Loopthrought Switch Drop Voltage vs Temperature
Figure 24: Tone Fall Time vs Temperature
Figure 27: Loopthrought Switch Drop Voltage vs Loopthrought Current
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LNBP21
Figure 28: Loopthrought Switch Drop Voltage vs Loopthrought Current Figure 31: Output Backward Current vs Temperature
Figure 29: DSQOUT Pin Logic Low vs Temperature
Figure 32: DC/DC Converter Efficiency vs Temperature
Figure 30: Undervoltage Lockout Threshold vs Temperature
Figure 33: Current Limit Sense vs Temperature
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LNBP21
Figure 34: 22kHz Tone Figure 37: DSQIN Tone Disable Transient Response
VCC=12V, IO=50mA, EN=TEN=1
VCC=12V, IO=50mA, EN=1, TEN=0
Figure 35: DSQIN Tone Enable Transient Response
Figure 38: Output Voltage Transient Response from 13V to 18V
VCC=12V, IO=50mA, EN=1, TEN=0
VCC=12V, IO=50mA, VSEL=from 0 to 1, EN=1
Figure 36: DSQIN Tone Enable Transient Response
Figure 39: Output Voltage Transient Response from 13V to 18V
VCC=12V, IO=50mA, EN=1, TEN=0
VCC=12V, IO=50mA, VSEL=from 1 to 0, EN=1
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LNBP21
THERMAL DESIGN NOTES During normal operation, this device dissipates some power. At maximum rated output current (500mA), the voltage drop on the linear regulator lead to a total dissipated power that is of about 1.7W . The heat generated requires a suitable heatsink to keep the junction temperature below the over temperature protection threshold. Assuming a 40C temperature inside the Set-Top-Box case, the total Rthj-amb has to be less than 50C/W. While this can be easily achieved using a through-hole power package that can be attached to a small heatsink or to the metallic frame of the receiver, a surface mount power package must rely on PCB solutions whose thermal efficiency is often limited. The simplest solution is to use a large, continuous copper area of the GND layer to dissipate the heat coming from the IC body. The SO-20 package of this IC has 4 GND pins that are not just intended for electrical GND connection, but also to provide a low thermal resistance path between the silicon chip and the PCB heatsink. Given an Rthj-c equal to 15C/W, a maximum of 35C/W are left to the PCB heatsink. This figure is achieved if a minimum of 25cm2 copper area is placed just below the IC body. This area can be the inner GND layer of a multi-layer PCB, or, in a dual layer PCB, an unbroken GND area even on the opposite side where the IC is placed. In both cases, the thermal path between the IC GND pins and the dissipating copper area must exhibit a low thermal resistance. In figure 40, it is shown a suggested layout for the SO-20 package with a dual layer PCB, where the IC Ground pins and the square dissipating area are thermally connected through 32 vias holes, filled by solder. This arrangement, when L=50mm, achieves an Rthc-a of about 25C/W. Different layouts are possible, too. Basic principles, however, suggest to keep the IC and its ground pins approximately in the middle of the dissipating area; to provide as many vias as possible; to design a dissipating area having a shape as square as possible and not interrupted by other copper traces. Due to presence of an exposed pad connected to GND below the IC body, the PowerSO-20 package has a Rthj-c much lower than the SO-20, only 2C/W. As a result, much lower copper area must be provided to dissipate the same power and minimum of 12cm2 copper area is enough, see figure 41.
Figure 40: SO-20 Suggested PCB Heatsink Layout
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LNBP21
Figure 41: PowerSO-20 Suggested PCB Heatsink Layout
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LNBP21
SO-20 MECHANICAL DATA
DIM. A A1 B C D E e H h L k ddd 10.00 0.25 0.4 0 mm. MIN. 2.35 0.1 0.33 0.23 12.60 7.4 1.27 10.65 0.75 1.27 8 0.100 0.394 0.010 0.016 0 TYP M AX. 2.65 0.30 0.51 0.32 13.00 7.6 MIN. 0.093 0.004 0.013 0.009 0.496 0.291 0.050 0.419 0.030 0.050 8 0.004 inch TYP. M AX . 0.104 0.012 0.020 0.013 0.512 0.299
0016022D
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LNBP21
PowerSO-20 MECHANICAL DATA
DIM. A a1 a2 a3 b c D (1) E e e3 E1 (1) E2 G h L N S T 0 10.0 0.80 0 10.90 0 0.40 0.23 15.80 13.90 1.27 11.43 11.10 2.90 0.10 1.10 1.10 0.0314 0 0.3937 0.0000 0.4291 0.10 mm. MIN. TYP MAX. 3.60 0.30 3.30 0.10 0.53 0.32 16.00 14.50 0 0.0157 0.0090 0.6220 0.547 2 0.0500 0.4500 0.4370 0.1141 0.0039 0.0433 0.0433 10 8 0.0039 MIN. inch TYP. MAX. 0.1417 0.0118 0.1299 0.0039 0.0209 0.0013 0.630 0.5710
10
8
(1) "D and E1" do not include mold flash or protusions - Mold flash or protusions shall not exceed 0.15mm (0.006")
N
N a2 A
R
c a1 DETAIL B E
b DETAIL A D e3
e
led a
DETAIL A
20
11
a3 DETAIL B E2 T E1
Gage Plan e 0.35
slug
- C-
S
L
SEATI G PLANE N GC (COPLANARITY)
1
1
0
PSO20MEC
h x 45
0056635
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LNBP21
Tape & Reel SO-20 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 10.8 13.2 3.1 3.9 11.9 12.8 20.2 60 30.4 11 13.4 3.3 4.1 12.1 0.425 0.520 0.122 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 1.197 0.433 0.528 0.130 0.161 0.476 MIN. TYP. MAX. 12.99 2 0.519 inch
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LNBP21
Tape & Reel PowerSO-20 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P W 15.1 16.5 3.8 3.9 23.9 23.7 12.8 20.2 60 30.4 15.3 16.7 4.0 4.1 24.1 24.3 0.594 0.650 0.149 0.153 0.941 0.933 TYP MAX. 330 13.2 0.504 0.795 2.362 1.197 0.602 0.658 0.157 0.161 0.949 0.957 MIN. TYP. MAX. 12.99 2 0.519 inch
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LNBP21
Table 9: Revision History
Date 07-Jul-2004 05-Oct-2004 Revision 2 3 Description of Changes Typing error on text. Mistake Pin 6 Power SO-20 - Table 4.
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LNBP21
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