M41T0
Serial real-time clock
Features
Counters for seconds, minutes, hours, day, date, month, years, and century 32 KHz crystal oscillator integrating load capacitance (12.5 pF) providing exceptional oscillator stability and high crystal series resistance operation Oscillator stop detection monitors clock operation Serial interface supports I2C bus (400 kHz protocol) Low standby current 0.9 A (typ at 3 V) 2.0 to 5.5 V clock operating voltage Special software programmable output Software clock calibration to compensate crystal deviation due to temperature Operating temperature of 40 to 85C SO8 (M)
8 1
May 2008
Rev 6
1/22
www.st.com 1
Contents
M41T0
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Star t data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 2.3
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 3.2 3.3 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Oscillator stop detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 5 6 7 8
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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M41T0
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SO8 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . . 19 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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List of figures
M41T0
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Alternate READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AC testing input/output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SO8 8-lead plastic small outline, 150 mils body width, package mechanical drawing. . . 19
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M41T0
Description
1
Description
The M41T0 real-time clock is a low power serial real-time clock with a built-in 32.768 kHz oscillator (external crystal controlled). Eight registers are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. Addresses and data are transferred serially via a two-line bidirectional bus. The built-in address register is incremented automatically after each WRITE or READ data byte. The M41T0 is supplied in 8-lead plastic small outline package. Figure 1. Logic diagram
VCC
OSCI SCL M41T0
OSCO SDA OUT
VSS
AI07028
Figure 2.
SOIC connections
M41T0 OSCI OSCO NF(1) VSS 1 2 3 4 8 7 6 5
AI07029
VCC OUT SCL SDA
1. NF pin must be tied to VSS.
Table 1.
OSCI OCSO OUT SDA SCL NF
(1)
Signal names
Oscillator input Oscillator output Output driver (open drain) Serial data address input / output Serial clock No function Supply voltage Ground
VCC VSS
1. NF pin must be tied to VSS.
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Description Figure 3.
OSCI OSCILLATOR 32.768 kHz OSCO OUT DIVIDER
M41T0 Block diagram
1 Hz SECONDS MINUTES CENTURY/HOURS CONTROL LOGIC DAY DATE MONTH SCL SERIAL BUS INTERFACE YEAR ADDRESS REGISTER CONTROL
VCC VSS
SDA
AI07030
6/22
M41T0
Operation
2
Operation
The M41T0 clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 8 bytes contained in the device can then be accessed sequentially in the following order: 1. 2. 3. 4. 5. 6. 7. 8. Seconds register Minutes register Century/hours register Day register Date register Month register Years register Control register
2.1
2-wire bus characteristics
This bus is intended for communication between different ICs. It consists of two lines: one bidirectional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined:
Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is High. Changes in the data line while the clock line is High will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
2.1.1
Bus not busy
Both data and clock lines remain high.
2.1.2
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the START condition.
2.1.3
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the STOP condition.
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Operation
M41T0
2.1.4
Data valid
The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the High period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition, a device that gives out a message is called "transmitter", the receiving device that gets the message is called "receiver". The device that controls the message is called "master". The devices that are controlled by the master are called "slaves".
2.1.5
Acknowledge
Each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte. Also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable Low during the High period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case, the transmitter must leave the data line high to enable the master to generate the STOP condition. Figure 4. Serial bus data transfer sequence
DATA LINE STABLE DATA VALID
CLOCK
DATA
START CONDITION
CHANGE OF DATA ALLOWED
STOP CONDITION
AI00587
8/22
M41T0 Figure 5. Acknowledgement sequence
Operation
START SCLK FROM MASTER 1 2 8
CLOCK PULSE FOR ACKNOWLEDGEMENT 9
DATA OUTPUT BY TRANSMITTER
MSB
LSB
DATA OUTPUT BY RECEIVER
AI00601
Figure 6.
SDA
Bus timing requirements sequence
tBUF
tHD:STA tR tF
tHD:STA
SCL tHIGH P S tLOW tSU:DAT tHD:DAT tSU:STA SR P tSU:ST
AI00589
1. P = STOP and S = START
9/22
Operation Table 2.
Symbol fSCL tLOW tHIGH tR tF tHD:STA tSU:STA tSU:DAT tHD:DAT(2) tSU:STO tBUF
M41T0 AC characteristics
Parameter(1) SCL clock frequency Clock low period Clock high period SDA and SCL rise time SDA and SCL fall time START condition hold time (after this period the first clock pulse is generated) START condition setup time (only relevant for a repeated start condition) Data setup time Data hold time STOP condition setup time Time the bus must be free before a new transmission can start 600 600 100 0 600 1.3 Min 0 1.3 600 300 300 Typ Ma x 400 Unit kHz s ns ns ns ns ns ns s ns s
1. Valid for ambient operating temperature: TA = 40 to 85C; VCC = 2.0 to 5.5 V (except where noted). 2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max.) of the falling edge of SCL.
2.2
READ mode
In this mode, the master reads the M41T0 slave after setting the slave address (see Figure 7). Following the WRITE mode control bit (R/W = 0) and the acknowledge bit, the word address An is written to the on-chip address pointer. Next the START condition and slave address are repeated, followed by the READ mode control bit (R/W = 1). At this point, the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. The address pointer is only incremented on reception of an acknowledge bit. The M41T0 slave transmitter will now place the data byte at address An+1 on the bus. The master receiver reads and acknowledges the new byte and the address pointer is incremented to An+2. This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter. An alternate READ mode may also be implemented, whereby the master reads the M41T0 slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure 9 on page 12).
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M41T0
Operation
2.3
WRITE mode
In this mode the master transmitter transmits to the M41T0 slave receiver. Bus protocol is shown in Figure 10 on page 12. Following the START condition and slave address, a logic '0' (R/W = 0) is placed on the bus and indicates to the addressed device that word address An will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the RAM on the reception of an acknowledge clock. The M41T0 slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address and again after it has received the word address and each data byte (see Figure 7).
Figure 7.
Slave address location
R/W
START
SLAVE ADDRESS
A
MSB
1
1
0
1
0
0
LSB 0
AI00602
Figure 8.
READ mode sequence
START START R/W R/W
BUS ACTIVITY: MASTER
SDA LINE
S
WORD ADDRESS (An)
ACK
S
DATA n
DATA n+1
ACK
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
SLAVE ADDRESS
STOP
DATA n+X
P
AI00899
NO ACK
ACK
11/22
Operation Figure 9. Alternate READ mode sequence
START BUS ACTIVITY: MASTER SDA LINE R/ W STOP DATA n ACK ACK DATA n+1 ACK ACK DATA n+X P NO ACK
AI00895
M41T0
S
BUS ACTIVITY: SLAVE ADDRESS
Figure 10. WRITE mode sequence
START
BUS ACTIVITY: MASTER
R/W
SDA LINE
S
WORD ADDRESS (An)
ACK ACK
DATA n
DATA n+1
DATA n+X
P
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
AI00591
12/22
ACK
STOP
M41T0
Clock operation
3
Clock operation
The M41T0 is driven by a quartz controlled oscillator with a nominal frequency of 32.768 kHz. The accuracy of the real-time clock depends on the frequency of the quartz crystal that is used as the time-base for the RTC. The M41T0 is tested to meet 35 ppm with nominal crystal. The eight-byte clock register (see Table 3 on page 14) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Seconds, minutes, and hours are contained within the first three registers. Bits D6 and D7 of clock register 2 (hours register) contain the CENTURY ENABLE bit (CEB) and the CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0', CB will not toggle. Bits D0 through D2 of register 3 contain the day (day of week). Registers 4, 5 and 6 contain the date (day of month), month and years. The final register is the control register. Bit D7 of register 0 contains the STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts within four seconds (typically one second). The seven clock registers may be read one byte at a time, or in a sequential block. The control register (address location 7) may be accessed independently. Provision has been made to assure that a clock update does not occur while any of the seven clock addresses are being read. If a clock address is being read, an update of the clock registers will be delayed by 250 ms to allow the READ to be completed before the update occurs. This will prevent a transition of data during the READ.
Note:
This 250 ms delay affects only the clock register update and does not alter the actual clock time.
3.1
Output driver pin
The OUT pin is an output driver that reflects the contents of D7 of the control register. In other words, when D7 of location 7 is a '0' then the OUT pin will be driven low.
Note:
The OUT pin is open drain which requires an external pull-up resistor.
3.2
Oscillator stop detection
If the oscillator fail (OF) bit is internally set to a '1,' this indicates that the oscillator has either stopped, or was stopped for some period of time and can be used to judge the validity of the clock and date data. This bit will be set to '1' any time the oscillator stops. The following conditions can cause the OF bit to be set:
The first time power is applied (defaults to a '1' on power-up). The voltage present on VCC is insufficient to support oscillation. The ST bit is set to '1.' External interference or removal of the crystal.
This bit will remain set to '1' until written to logic '0.' The oscillator must start and have run for at least 4 seconds before attempting to reset the OF bit to '0.' This function operates both under normal power and in battery backup.
13/22
Clock operation
M41T0
3.3
Initial power-on defaults
Upon initial application of power to the device, the OUT bit and OF bit will be set to a '1,' while the ST bit will be set to '0.' All other register bits will initially power-on in a random state. Table 3.
Address D7 0 1 2 3 4 5 6 7 OUT ST OF CEB (2) X X X CB X X X D6 D5 10 seconds 10 minutes 10 hours X X X D4 D3 D2 D1 D0 Seconds Minutes Hours Day Date Month Years X X X X X
Register map(1)
Data Function/range BCD format Seconds Minutes Centur y/hours Day Date Month Year Control 00-59 00-59 0-1/00-23 01-07 01-31 01-12 00-99
10 date X 10 M.
10 years 0 X
1. Keys: ST = STOP bit OUT = Output level X = Don't care 0 = Must be set to '0.' CEB = Century enable bit CB = Century bit OF = Oscillator fail bit 2. When CEB is set to '1', CB toggles from '0' to '1' or from '1' to '0' at the turn of the century (dependent upon the initial value set). When CEB is set to '0', CB does not toggle.
14/22
M41T0
Maximum ratings
4
Maximum ratings
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4.
Symbol TSTG VCC TSLD(1) VIO IO PD
1.
Absolute maximum ratings
Parameter Storage temperature (VCC off, oscillator off) Supply voltage Lead solder temperature for 10 seconds Input or output voltages Output current Power dissipation Value 55 to 125 0.3 to 7 260 0.3 to VCC + 0.3 20 1 Unit C V C V mA W
Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds).
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DC and AC parameters
M41T0
5
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 5. Operating and AC measurement conditions(1)
Parameter Supply voltage (VCC) Ambient operating temperature (TA) Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages
1. Output Hi-Z is defined as the point where data is no longer driven.
M41T0 2.0 to 5.5 40 to 85 100 5 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC
Unit V C pF ns V V
Figure 11. AC testing input/output waveform
0.8VCC
0.7VCC 0.3VCC
AI02568
0.2VCC
Table 6.
Symbol CIN COUT(3) tLP
Capacitance
Parameter(1)(2) Input capacitance (SCL) Output capacitance (SDA, OUT) Low-pass filter input time constant (SDA and SCL) Min M ax 7 10 50 Unit pF pF ns
1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested 2. At 25C, f = 1 MHz. 3. Outputs deselected.
16/22
M41T0 Table 7.
Sym ILI ILO ICC1
DC and AC parameters DC characteristics
Parameter Input leakage current Output leakage current Supply current Test condition(1) 0V VIN VCC 0V VOUT VCC 3.0 V Frequency (SCL) = 400 kHz 5.5 V All inputs = VCC 0.2 V Frequency (SCL) = 0 Hz 3.0 V 5.5 V 0.3 0.7 VCC IOL = 3 mA IOL = 10 mA 130 0.9 200 1.2 31 0.3 VCC VCC + 0.3 0.4 0.4 A A A V V V V 35 Min Typ Max 1 1 55 Unit A A A
ICC2(2) Supply current (standby) VIL VIH VOL Input low voltage Input high voltage Output low voltage Output low voltage (open drain)
1. Valid for ambient operating temperature: TA = 40 to 85C; VCC = 2.0 to 5.5 V (except where noted). 2. At 25C.
Table 8.
Symbol
fO
Crystal electrical characteristics
Parameter(1)(2) Resonant frequency Series resistance Load capacitance 12.5 Min Typ 32.768 60(3) Max Unit kHz K pF
RS CL
1. These values are externally supplied. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp for further information on this crystal type. 2. Load capacitors are integrated within the M41T0. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account. 3. RS = 40 k when VCC 2.5 V.
17/22
Package mechanical information
M41T0
6
Package mechanical information
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
18/22
M41T0
Package mechanical information Figure 12. SO8 8-lead plastic small outline, 150 mils body width, package mechanical drawing
h x 45 A2 b e 0.25 mm GAUGE PLANE k
8
A ccc c
D
E1
1
E A1 L L1
SO-A
1. Drawing is not to scale.
Table 9.
SO8 8-lead plastic small outline, 150 mils body width, package mechanical data
millimeters inches Max 1.75 0.10 1.25 0.28 0.17 0.48 0.23 0.10 4.90 6.00 3.90 1.27 4.80 5.80 3.80 0.25 0 0.40 1.04 5.00 6.20 4.00 0.50 8 1.27 0.041 0.193 0.236 0.154 0.050 0.189 0.228 0.150 0.010 0 0.016 0.25 0.004 0.049 0.011 0.007 0.019 0.009 0.004 0.197 0.244 0.157 0.020 8 0.050 Typ Min Max 0.069 0.010
Symbol Typ A A1 A2 b c ccc D E E1 e h k L L1 Min
19/22
Part numbering
M41T0
7
Part numbering
Table 10.
Example:
Ordering information scheme
M41T 0 M 6 F
Device type M41T
Supply voltage and write protect voltage 0: VCC = 2.0 to 5.5 V
Package M = SO8 (150 mils width)
Temperature range 6 = 40 to 85C
Shipping method E = ECOPACK package, tubes F = ECOPACK package , tape & reel
For a list of additional options (e.g., speed, package) or for further information on any aspect of this device, please contact the ST sales office nearest to you.
20/22
M41T0
Revision history
8
Revision history
Table 11.
Date Feb-2003 18-Feb-2003 01-Apr-2003 10-Apr-2003 30-Oct-2003 30-Jun-2004 23-Jul-2004
Document revision history
Revision 1.0 1.1 1.2 1.3 1.4 2.0 3.0 First issue Add Pb-free information (Table 4, Table 10); update package information (Features, Figure 12; Table 10) Fix package outline and data (Features, Figure 12, Table 10) Rever t to previous package (Features, Figure 12, Table 10) Remove footnote (Table 4) Shipping method options updated and Note 1 removed from Table 10: Ordering information scheme. Datasheet put in new template. Content corrected from M41T80 to M41T0. Changed document to new template; amalgamated diagrams in Features; updated Package mechanical data in Section 6: Package mechanical information; Table 10 ecopack compliant; small text changes for entire document Updated packaging information that only SO8 package available (cover page and Table 10: Ordering information scheme). Updated Figure 12, Table 4. Changes
22-Aug-2006
4
04-Apr-2007 13-May-2008
5 6
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M41T0
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