ST7538
FSK POWER LINE TRANSCEIVER
1
FEATURES
HALF DUPLEX FREQUENCY SHIFT KEYING (FSK) TRANSCEIVER INTEGRATED POWER LINE DRIVER WITH PROGRAMMABLE VOLTAGE AND CURRENT CONTROL PROGRAMMABLE INTERFACE: SYNCHRONOUS ASYNCHRONOUS SINGLE SUPPLY VOLTAGE (FROM 7.5 UP TO 12.5V) VERY LOW POWER CONSUMPTION (Iq=5 mA) INTEGRATED 5V VOLTAGE REGULATOR (UP TO 100mA) WITH SHORT CIRCUIT PROTECTION 8 PROGRAMMABLE TRANSMISSION FREQUENCIES PROGRAMMABLE BAUD RATE UP TO 4800BPS RECEIVING SENSITIVITY 250VRMS SUITABLE TO APPLICATION IN ACCORDANCE WITH EN 50065 CENELEC SPECIFICATIONS CARRIER OR PREAMBLE DETECTION BAND IN USE DETECTION PROGRAMMABLE REGISTER WITH SECURITY CHECKSUM MAINS ZERO CROSSING DETECTION AND SYNCHRONIZATION
Figure 1. Package
TQFP44 Slug Down
Table 1. Order Codes
Part Number ST7538P Package TQFP44 (Slug down)
WATCHDOG TIMER
2
DESCRIPTION
Figure 2. Block Diagram
O
bs
let o
CD/PD
Pr e
DVdd
du o
AVdd PLL
(s) ct
DVss AVss DIGITAL FILTER
so Ob TEST1 TEST2 TEST3 BU
The ST7538 is a Half Duplex synchronous/asynchronous FSK Modem designed for power line communication network applications. It operates from a single supply voltage and integrates a line driver and a 5V linear regulator. The device operation is controlled by means of an internal register, programmable through the synchronous serial interface. Additional functions as watchdog, clock output, output voltage and current control, preamble detection, time-out, band in use are included. Realized in Multipower BCD5 technology that allows to integrate DMOS, Bipolar and CMOS structures in the same chip.
te le
ro P
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s) t(
RxFo
CARRIER DETECTION
TEST
BU AGC
RxD FSK DEMOD IF FILTER FILTER AMPL RAI SERIAL INTERFACE FILTER CONTROL REGISTER CURRENT CONTROL TX FILTER VOLTAGE CONTROL PLI CL
CLR/T
REG/DATA RxTx TxD
FSK MODULATOR
DAC
ALC
Vsense ATO ATOP1 ATOP2
REGOK
OSC
TIME BASE
ZC
OP-AMP
+ VREG
PAVcc Vdc PG
XOut
XIn
WD
TOUT
RSTO
MCLK ZCout
ZCin
C_OUT
CMINUS
CPLUS
D03IN1407A
November 2005
Rev. 5 1/30
ST7538
Figure 3. Pin Connection (Top view)
REG_DATA C_MINUS
C_OUT
C_PLUS
REG_OK
GND
TEST1
35
N.C.
PG
44
43
42
41
40
N.C.
39
38
37
36
CD_PD DVSS RXD RxTx TXD GND TOUT CLR/T BU DVDD MCLK
N.C.
34 33 32 31 30 29 28 27 26 25 24 23
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
VDC RAI RXFO TEST2 VSENSE AVDD XIN XOUT SGND ATO CL
D01IN1312
Table 2. Pin Description
N 1 Nam e CD_P D Type Digital/Output
2 3 4
DVss RxD RxTx
Supply Digital/Output Digital/Input with internal pull-up
5 6 7
TxD
bs O
8 9 10 11 12
let o
G ND TOUT BU DVdd MCLK RSTO
ro P e
Supply
uc d
(s) t
Carrier or Preamble Detect Output. "1" No Carrier or Preamble Detected "0" Carrier or Preamble Detected
Digital Ground
so Ob -
te le
ro P
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RSTO
TEST3
ZCOUT
ZCIN
N.C.
DVSS
ATOP1
PAVSS
ATOP2
PAVCC
s) t(
WD
Description
RX Data Output. Rx or Tx mode selection input. "1" - RX Session "0" - TX Session
Digital/Input with internal pull-down
TX Data Input. Substrate Ground (same function as PIN 41) TX Time Out Event Detection "1" - Time Out Event Occurred "0" - No Time-out Event Occurred Synchronous Mains Access Clock or Control Register Access Clock Band in use Output. "1" Signal within the Programmed Band "0" No Signal within the Programmed Band Digital Supply Voltage Master Clock Output Power On or Watchdog Reset Output
Digital/Output
CLR/T
Digital/Output Digital/Output
Supply Digital/Output Digital/Output
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ST7538
Table 2. Pin Description (continued)
N 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Nam e TEST 3 WD ZCOUT ZCIN1 NC DVss ATOP1 PAVss ATOP2 PAVCC CL
2
Type Digital/Input with internal pull-down Digital/Input with internal pull-up Digital/Output Analog/Input Floating Supply Power/Output Supply Power/Output Supply Analog/Input Analog/Output Supply Analog I/O Analog Input Supply
3
Description Test Input. Must be connected to DVss during Normal Operation Watchdog input. The Internal Watchdog Counter is cleared on the falling edges. Zero Crossing Detection Output Zero Crossing AC Input. Must be connected to DVss. Digital Ground Power Line Driver Output Power Analog Ground Power Line Driver Output Power Supply Voltage Current Limiting Feedback. A resistor between CL and AVss sets the PLI Current Limiting Value Small Signal Analog Transmit Output Analog Signal Ground Cr ystal Output- External Clock Input Cr ystal Oscillator Input Analog Power supply. Test Input must be connected SGND Receiving Filter Output Receiving Analog Input
ATO SGND XOUT X IN AVdd Vsense RxFO RA I VDC NC TEST1 REGOK TEST2
Analog/Input Analog/Input Analog/Output Analog/Input Power floating Digital/Input with internal pull-down Digital/Output
Output Voltage Sensing input for the voltage control loop
5V Voltage Regulator Output Must Be connected to DVss.
37 38 39 40 41 42
C_MINUS4 Analog/Input C_PLUS 5 NC
O
bs
43 44
let o
GND PG NC
C_OUT
Pr e
floating Supply
Analog/Input
du o
(s) ct
Test input. Must Be connected to DVss. Security checksum logic output "1" - Stored data Corrupted "0" - Stored data OK
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Op-amp Inverting Input. Op-amp Not Inverting Input. Must Be connected to DVss Op-amp Output Substrate Ground (same function as PIN 6) Power Good logic Output "1" - VDC is above 4.5V "0" - VDC is below 4.25V Mains or Control Register Access Selector "1" - Control Register Access "0" - Mains Access Must be connected to DVss.
Analog/Output
Digital/Output
REG_DATA Digital/Input with internal pull-down floating
<1> <2> <3> <4> <5>
If not used this pin must be connected to VDC Cannot be left floating Cannot be left floating If not used this pin must be connected to VDC If not used this pin must be tied low (SGND or PAVss or DVss)
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ST7538
Table 3. Absolute Maximum Ratings
Symbol PAVCC AVdd DVdd AVss/DVss VI VO IO Vsense, XIN, C_MINUS, C_PLUS, CL RAI, ZCIN ATO, RxFO, C_OUT, XOUT ATOP1,2 ATOP Tamb Tstg ATOP1 Pin ATOP2 Pin Other pins Power Supply Voltage Analog Supply Voltage Digital Supply Voltage Voltage between AVss and DVss Digital input Voltage Digital output Voltage Digital Output Current Voltage Range at Vsense, XIN, C_MINUS, C_PLUS, CL Inputs Parameter Value -0.3 to +14 -0.3 to +5.5 -0.3 to +5.5 -0.3 to +0.3 DVss - 0.3 to DVdd +0.3 DVss - 0.3 to DVdd +0.3 -2 to +2 AVss - 0.3 to AVdd+0.3 Unit V V V V V V mA V
Voltage Range at RAI, ZCIN Inputs Voltage range at ATO, RxFO, C_OUT, XOUT Outputs
-AVdd - 0.3 to AVdd +0.3 AVss - 0.3 to AVdd +0.3
V
Voltage range at Powered ATO Output Powered ATO Output Current (*) Operating ambient Temperature Storage Temperature Maximum Withstanding Voltage Range Test Condition: CDF-AEC-Q100-002- "Human Body Model" Acceptance Criteria: "Normal Performance"
AVss - 0.3 to +PAVcc +0.3
(*) This current is intended as not repetitive pulse current
Table 4. Thermal Data
Symbol Rth-j-amb1 Rth-j-amb2
Maximum Thermal Resistance Junction-Ambient Steady State(*) Maximum Thermal Resistance Junction-Ambient Steady State(**)
(*) Mounted on Multilayer PCB with a dissipating surface on the bottom side of the PCB (**) It's the same condition of the point above, without any heatsinking surface on the board.
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Pr e
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Parameter
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400
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V V mArms C C V V V
-40 to +85 -50 to 150 1500 1000 2000
TQFP44 with slug 35 50
Unit C/W C/W
4/30
ST7538
Table 5. Electrical Characteristcs (AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40C Tamb 85C, Fc = 86kHz, other Control Register parameters as default value, unless otherwise specified).
Symbol AVCC, DVCC Parameter Supply Voltages DVCC < 4.75V AVCC < 4.75V Test Condition Min. 4.75 0.1 0.1 7.5 Typ. 5 Max. 5.25 1 .2 1 .2 12.5 100 Transmission & Receiving mode TX mode (no load) RX mode Maximum total current Digital I/O VIH VIL VOH VOL R dow n Rup Oscillator XOUTSWING XOUT Input Voltage Swing XOUTOFFSET XOUT Input Voltage Offset DC Xtal XtalESR XtalCL Transmitter IATO VATO XTAL Clock Duty Cycle Crystal Oscillator frequency External Oscillator Esr Resistance High Logic Level Input Voltage Low Logic Level input Voltage High Logic Level Output Voltage IOH= -2mA Low Logic Level Output Voltage IOL= 2mA Pull Down Resistor Pull up Resistor 2 3.5 5 30 0.5 7 50 1 370 Unit V V V V V /m s mA mAr ms mA mAr ms V
PAVCC - DVCC PAVCC and DVCC Relation during Power-Up Sequence PAVCC - AVCC PAVCC and DVCC Relation during Power-Up Sequence PAVcc Power Supply Voltage Max allowed slope during Power-Up AICC + DICC I PAVCC Input Supply Current Powered Analog Supply Current
External Clock (see par. 3.8)
External Oscillator Stabilization Capacitance Output Transmitting Current on ATO
O
bs
VATODC
let o
Pr e
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ct u
(s)
External Clock
Ob -
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1
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3
s) t(
V V
0.8 0 .4
V k k V V % M Hz pF
100
100
1.5 40 16
2 .5 60 40 16
1 1.75 1 .7 VATO = 2VPP 2.3 2.1 -55 -52 Vsense connected though a 100pF cap to GND; Rcl=1.85k; RLOAD =1 (as in fig. 17) 3.5 2 .5 - 42 - 49
mAr ms VPP V dB dB
Max Carrier Output AC Voltage RCL = 1.75k Vsense (AC) = 0V
Output DC Voltage on ATO Second Harmonic Distortion on ATO Third Harmonic Distortion on ATO Output Transmitting Current in programmable current limiting
HD2ATO HD3ATO IATOP
250
310
370
mAr ms
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ST7538
Table 5. Electrical Characteristcs (continued) (AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40C Tamb 85C, Fc = 86kHz, other Control Register parameters as default value, unless otherwise specified).
Symbol VATOP(AC) Parameter Max Carrier Output AC Voltage for each ATOP1 and ATOP2 pins Output DC Voltage on ATOP1 and ATOP2 pins Second Harmonic Distortion on each ATOP1 and ATOP2 pins Differential Second Harmonic Distortion HD3ATOP Third Harmonic Distortion on each ATOP1 and ATOP2 pins Differential Third Harmonic Distortion VATOP G STEP DRNG VCLTH VCLHYST CCLTH CCLHYST Accuracy with Voltage Control Loop Active ALC Gain Step Control loop gain step ALC Dynamic Range Voltage control loop reference threshold on Vsense pin Hysteresis on Voltage loop reference threshold Current control loop reference threshold on Csense pin Hysteresis on Current loop reference threshold VSENSE Input Impedance Carrier Activation Time Figure 15 Figure 15 VATOP = 4VPP , PAVCC = 10V No Load VATOP = 4VPP , PAVCC = 10V RLOAD =50 (Differential) Carrier Frequency: 132.5KHz VATOP = 4VPP , PAVCC = 10V No Load. VATOP = 4VPP , PAVCC = 10V RLOAD =50 (Differential) Carrier Frequency: 132.5KHz RCL = 1.75k; Vsense (AC) = 0V -1 0.6 Test Condition RCL = 1.75k ; Vsense (AC) = 0V VATO P( AC) P A V c c ----------------------------------- + 7.5 V 2 Min. 3.5 Typ. 4 .6 Max. 7 Unit V pp
VATOP(DC) HD2ATOP
3.5
4 .2 -55 -65
5 - 42 - 53
V dB dB
-56 -65
- 49 - 52
dB dB
Figure 15
VSENSE (DC) Output DC Voltage on VSENSE VSENSE TRxTx
bs O
TST VIN VIN
let o
od Pr e
ct u
(s)
Figure 15
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1
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+1
s) t(
GSTEP dB dB
1 .4
30 200
160
180 18
mV P K mV
1.80 210
1.90 250 1.865 36
2.00 290
V mV V K
Figure 18 - 600 Baud Xtal=16MHz Figure 18- 1200 Baud Xtal=16MHz Figure 18- 2400 Baud Xtal=16MHz Figure 18- 4800 Baud Xtal=16MHz Figure 18. Xtal =16MHz Figure 18 Xtal =16MHz
0.01 0.01 0.01 0.01
1.6 800 400 200 3.2
ms s s s ms
TALC
Carrier Stabilization Time From STEP 16 to zero or From step 16 to step 31, Tstep
200
s
Receiver Input Sensitivity (Normal Mode) Input Sensitivity (High Sens.) Maximum Input Signal 0.5 250 2 2 mVrms Vrms Vr m s
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ST7538
Table 5. Electrical Characteristcs (continued) (AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40C Tamb 85C, Fc = 86kHz, other Control Register parameters as default value, unless otherwise specified).
Symbol RIN VCD Parameter Input Impedance Carrier Detection Sensitivity (Normal Mode) Carrier Detection Sensitivity (High Sensitivity Mode) VBU Band in Use Detection Level Test Condition Min. 80 Typ. 100 0.5 250 77 85 Max. 140 2 Unit k mVrms Vrms dB / Vr ms V V mV
Voltage Regulator VDC Linear Regulator Output Voltage -25
Other Functions
TOFFD
bs O
TCD
let o
Time Out OFF Time
RxTx 0->1 vs. TOUT Delay Carrier Detection Time selectable by register Control Register bit 9 and bit10 Figure 12 Figure 12 Control Register bit 15 and bit 16 see table 11 Control Register bit 3 and bit 4 see table 11 500 1 3 5 300 fclock fclock/2 fclock/4 600 1200 2400 4800
Pr e
od
ct u
(s)
See Figure 22; Xtal=16MHz See Figure 22
Ob -
so
Pr te le
4.3 50 3.5 TWD + 3.5
od
180 3 .9 340 4 .5 250
uc
75
s) t(
V V
mV mA
210 4.1
mV 4.7
mV ms ms 1490 1.5 ms s s ms 20 s s ms ms ms 500 s MHz B aud
Control Register Bit 7 and Bit 8 See Figure 21 See Figure 21 125
1 3
T DCD
CD_PD Propagation Delay Master Clock Output Selectable by register Baud rate
M C LK
BAUD
7/30
ST7538
Table 5. Electrical Characteristcs (continued) (AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40C Tamb 85C, Fc = 86kHz, other Control Register parameters as default value, unless otherwise specified).
Symbol TB Parameter Baud rate Bit Time (=1/BAUD) Test Condition Control Register bit 3 and bit 4 see table 11 Min. Typ. 1667 833 417 208 1 Max. Unit s
Zero Crossing Detection ZCDEL Zero Crossing Detection delay (delay between the ZCIN and ZCOUT signals) Zero Crossing Detection Low Threshold Zero Crossing Detection High Threshold Figure 23 s
ZC(LOW) ZC(HIGH)
-45 5 -20 15 -30 -38 6 28
-5 +45 +20 45
mV mV mV
ZC(OFFSET) Zero Crossing Offset Operational Amplifier COUT(Sync) Max Sync Current COUT(Source) Max Source Current CIN(Offset) GBWP Ts TH TCR TCC TDS TDH T CRP Input Terminals OFFSET Gain Bandwidth Product Setup Time Hold Time CLR/T vs. REG_DATA or RxTx CLR/T vs. CLR/T Setup Time Hold Time see figure 6, 7, 8, 9 & 10 see figure 6, 7, 8, 9 & 10 see figure 6, 7, 8, 9 & 10
-20 7
Serial Interface
see figure 6, 7, 8, 9 & 10 see figure 6, 7, 8, 9 & 10
bs O
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Pr e
du o
(s) ct
see figure 6, 7, 8, 9 & 10
so Ob -
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9 5 2
- 10
s) t(
mA mV
mA
+38
MHz ns ns
TB/4 TB TB/4 TB/4 TH 2*TB TB/2 TB/2 TB/2
8/30
ST7538
3
FUNCTIONAL DESCRIPTION
3.1 Carrier Frequencies ST7538 is a multi frequency device: eight programmable Carrier Frequencies are available (see table 6). Only one Carrier at a time can be used; anyway, it's possible to switch the communication channel during the normal working Mode. Selecting the desired frequency in the Control Register the Transmission and Reception filters are accordingly tuned. Table 6. ST7538 Channels List
FCarrier F0 F1 F2 F3 F4 F5 F6 F7(1) F (KHz) 60 66 72 76 82.05 86 110 132.5
3.2 Baud Rates
ST7538 is a multi Baud rate device: four Baud Rate are available (See table 7).
Table 7. ST7538 mark and space tones frequency distance Vs Baud Rate and Deviation
Baud Rate [Baud] 600 1200 2400( 1) 4800
Note: 1. 2. 3. 4. Default value Frequency deviation. Deviation = F / (Baud Rate) Deviation 0.5 Not Allowed
F (2)(Hz) 600
bs O
let o
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(s)
Ob 1200(1) 2400 2400 4800
600 1200
so
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1(4) 0.5 1 0.5 1 0.5 1
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Deviation (3)
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ST7538
3.3 Mark and Space Frequencies Mark and Space Communication Frequencies are defined by the following formula: F ("0") = FCarrier + [F]/2 F ("1") = FCarrier - [F]/2 F(Frequency Deviation) = Deviation*BAUD rate. Here follows a table listing the correlation between frequency parameters and actual tones frequencies. Table 8. ST7538 synthesized frequencies
Carrier Frequency (KHz) 60 Baud Rate 600 1200 2400 4800 66 600 1200 2400 4800 72 600 1200 2400 Deviation -1 0.5 1 0.5 1 0.5 1 -1 0.5 1 0.5 1 0.5 1 -1 0.5 1 0.5 1 1 1 0.5 1 2400 4800 0.5 1 0.5 1 0.5 -75684 75684 75358 75358 74870 74870 73568 76335 76335 76660 76660 77148 77148 78451 4800 2400 1200 65755 65755 65430 65430 64779 64779 63639 71777 71452 71452 70801 70801 69661 66243 66243 66569 66569 67220 68359 72266 72266 72591 73242 73242 74382 132.5 600 4800 1200 2400 72591 67220 59733 59733 59408 59408 58757 58757 57617 60221 60221 60547 60547 61198 61198 62337 86 4800 600 2400 1200 Exact Frequency [Hz] (Clock=16MHz) " 1" " 0" Carrier Frequency (KHz) 82.05 Baud Rate 600 Deviation -1 0.5 1 0.5 1 0.5 1 1 1 1 4800 600 0.5 1 -1 0.5 1 0.5 1 0.5 1 -1 0.5 1 0.5 1 0.5 1 132161 132161 131836 131836 131348 131348 130046 132813 132813 133138 133138 133626 133626 134928 109701 109701 109375 109375 108724 108724 107585 110352 110352 110677 110677 111165 111165 112467 -81706 81706 81380 81380 80892 80892 82357 82357 Exact Frequency [Hz] (Clock=16MHz) "1" "0"
bs O
76
let o
4800 600
Pr e
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71777
(s) t
Ob -
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Pr te le
1200 2400 0.5 0.5
od
79590 85775
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82682 82682 83171 83171 84473 86263 86263 86589 86589 87240 87240 88379
85775 85449 85449 84798 84798 83659
110
1200
10/30
ST7538
3.4 Host Processor Interface ST7538 exchanges data with the host processor thorough a serial interface. The data transfer is managed by REG_DATA and RxTx Lines, while data are exchanged using RxD, TxD and CLR/T lines. Four are the ST7538 working modes: Data Reception
Data Transmission Control Register Read Control Register Write
REG_DATA and RxTx lines are level sensitive inputs. Table 9. Data and Control register access bits configuration
REG_DATA Data Transmission Data Reception Control Register Read Control Register Write 0 0 1 1 RxTx 0 1
Mains Access ST7538 features two type of communication interfaces: - Asynchronous - Synchronous
The selection can be done through the internal Control Register. Figure 4. Synchronous and Asynchronous ST7538/Host Controller interfaces
bs O
let o
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du
Asynchronous Data Interface
(s) ct
RxD TxD RxTx CLR/T
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1 0
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Synchronous Data Interface RxD TxD RxTx CLR/T REG_DATA
REG_DATA
Host Controller
ST7538
Host Controller
D03IN1415
ST7538
Asynchronous Mode. ST7538 allows to interface the Host Controller using a 3 line interface (RXD,TXD & RxTx). Data are exchange without any auxiliary Clock reference in an Asynchronous mode without adding any protocol bits. The host controller has to recover the clock reference in receiving Mode and control the Bit time in transmission mode. RxD line is forced to a low logic level when no carrier is detected.
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ST7538
Synchronous mode. ST7538 allows to interface the host Controller using a four lines synchronous interface (RXD,TXD, CLR/ T & RxTx). ST7538 is always the master of the communication and provides the clock reference on CLR/ T line. When ST7538 is in receiving mode an internal PLL recovers the clock reference. Data on RxD line are stable on CLR/T rising Edge. When ST7538 is in transmitting mode the clock reference is internally generated and data are read on TxD line on CLR/T rising Edge. If RxTx line is set to "1" & REG_DATA="0" (Data Reception), ST7538 enters in an Idle State and CLR/T line is forced Low. After Tcc time the modem starts providing received data on RxD line. If RxTx line is set to "0" & REG_DATA="0" (Data Transmission), ST7538 enters in an Idle State and transmission circuitry is switched on. After Tcc time the modem starts transmitting data present on TXD line (figure 6) . Figure 5. Receiving and transmitting data/recovered clock timing
Receiving Bit Synchronization Transmitting Bit Synchronization
CLR/T
CLR/T
RxD
TxD
D03IN1416
Figure 6. Data Reception -> Data Transmission -> Data reception
TCC CLR_T TB RXD REG_DATA
RxTx
TXD
3.5 Control Register Access
bs O
The communication with ST7538 Control Register is always synchronous. The access is achieved using the same lines of the Mains interface (RxD, TxD and CLR/T) plus REG_DATA Line. With REG_DATA = 1 and RxTx=0, the data present on TxD are loaded into the Control Register MSB first. The ST7538 samples the TxD line on CLR/T rising edges. The control Register content is updated at the end of the register access section (REG_DATA falling edge). If more than 24 bits are transferred to ST7538 only the latest 24 bits are stored inside the Control Register.
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Pr e
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TCR
(s) ct
TS
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TCR
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TCC
TS TH
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TDS
TDH
TH
BIT23
D03IN1402
With REG_DATA = 1 and RxTx=1, the content of the Control Register is sent on RxD port. The Data on RxD are stable on CLR/T rising edges MSB First.
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ST7538
Figure 7. Data Reception Control Register read Data Reception Timing Diagram
TCC CLR_T TDS RXD TCR TDH TDS TDH BIT22 TCR TB TCC
BIT23
REG_DATA
RxTx
D03IN1404
Figure 8. Data Reception Control Register write Data Reception Timing Diagram
TCC CLR_T TDS RXD TCR REG_DATA TCR RxTx TS TXD TH BIT22 TCR TCR TDH TB TCC
BIT23
Figure 9. Data Transmission Control Register read Data Reception Timing Diagram
TC C CLR_T TB RXD
BIT23
REG_DATA
TC R
TC R RxTx TS TXD TH
Figure 10. Data Transmission Control Register Write Data Reception Timing Diagram
bs O
CLR_T TXD RxTx RXD
let o
TS TH
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(s) t
Ob TD S BIT22
TD H
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TDS
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D03IN1403
TC C TD H
TC R
D03IN1405
TCC TS TH BIT22 TCR
TCC
TB
BIT23
REG_DATA TCR TCR
TDS
TDH
D03IN1401
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ST7538
3.6 Receiving Mode The receive section is active when RxTx Pin ="1" and REG_DATA=0. The input signal is read on RAI Pin using SGND as ground reference and then pre-filtered by a Band pass Filter (62kHz max. bandwidth at -3dB). The Pre-Filter can be removed setting one bit in the Control Register. The Input Stage features a wide dynamic range to receive Signal with a Very Low Signal to Noise Ratio. The Amplitude of the applied waveform is automatically adapted by an Automatic Gain Control block (AGC) and then filtered by a Narrow Band Band-Pass Filter centered around the Selected Channel Frequency (14kHz max. bandwidth at -3dB). The resulting signal is down-converted by a mixer using a sinewave generated by the FSK Modulator. Finally an Intermediate Frequency Band Pass-Filter (IF Filter) improves the Signal to Noise ration before sending the signal to the FSK demodulator. The FSK demodulator then send the signal to the RX Logic for final digital filtering. Digital filtering Removes Noise spikes far from the BAUD rate frequency and Reduces the Signal Jitter. RxD Line is forced at logic level "0" when neither mark or space frequencies are detected on RAI Pin. Mark and Space Frequency in Receiving Mode must be distant at least BaudRate/2 to have a correct demodulation. While ST7538 is in Receiving Mode (RxTx pin ="1"), the transmit circuitry, Power Line Interface included, are turned off. This allows the device to achieve a very low current consumption (5 mA typ). In Receiving mode ATOP2 pin is internally connected to PAVSS. High Sensitivity Mode It is possible to increase ST7538 Receiving Sensitivity setting to "1" the High Sensitivity Bit of Control Register. This Function allows to increase the communication reliability when the ST7538 sensitivity is the limiting factor.
Synchronization Recovery System (PLL) ST7538 embeds a Clock Recovery System to feature a Synchronous data exchange with the Host Controller. The clock recovery system is realized by means of a second order PLL. Data on the data line (RxD) are stable on CLR/T line rising edge (CLR/T Falling edge synchronized to RxD line transitions LOCK-IN Range). The PLL Lock-in and Lock-out Range is /2. When the PLL is in the unlock condition, CLR/T and RxD lines are forced to a low logic level. When PLL is in unlock condition it is sensitive to RxD Rising and Falling Edges. The maximum number of transition required to reach the lock-in condition is 5. When in lock-in condition the PLL is sensitive only to RxD rising Edges to reduce the CLR/T Jitter. ST7538 PLL is forced in the un-lock condition, when more than 32 equal symbols are received. Due to the fact that the PLL, in lock-in condition, is sensitive only to RxD rising edge, sequences equal or longer than 15 equal symbols can put the PLL into the un-lock condition.
Figure 11. ST7538 PLL lock-in range
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Pr e
RxD
du o
(s) ct
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CLR/T
D03IN1417
LOCK-IN RANGE
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ST7538
Carrier/Preamble Detection The Carrier/Preamble Block is a digital Frequency detector Circuit. It can be used to manage the MAINS access and to detect an incoming signal. Two are the possible setting: - Carrier Detection - Preamble Detection CARRIER DETECTION: The Carrier/Preamble detection Block notifies to the host controller the presence of a Carrier when it detects on the RAI Input a signal with an harmonic component close to the programmed Carrier Frequency. The CD_PD signal sensitivity is identical to the data reception sensitivity (0.5mVrms Typ. in Normal Sensitivity Mode). The CD_PD line is forced to a logic level low when a Carrier is detected. PREAMBLE DETECTION: The Carrier/Preamble detection Block notifies to the host controller the presence of a Carrier modulated at the Programmed Baud Rate for at least 4 Consecutive Symbols ("1010" or "0101" are the symbols sequences detected). CD_PD line is forced low till a Carrier signal is detected and PLL is in the lock-in range. To reinforce the effectiveness of the information given by CD_PD Block, a digital filtering is applied on Carrier or Preamble notification signal (See Control Register Paragraph). The Detection Time Bits in the Control Register define the filter performance. Increasing the Detection Time reduced the false notifications caused by noise on main line. The Digital filter adds a delay to CD_PD notification equal to the programmed Detection Time. When the carrier frequency disappears, CD_PD line is held low for a period equal to the detection time and then forced high.
Figure 12. CD_PD Timing during RX
TDCD TCD
CD_PD
RAI
Figure 13. Receiving Path Block Diagram
3 RxD
bs O
CLR/T CD_PD BU
let o
8 1 9
Bit 3,4 &14-21
Pr e
Bit 3,4
du o
(s) ct
Bit 3,4
so Ob MIXER
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RXFO 31 Bit 0-2 AGC Band Pass Band Pass CHANNEL FILTER LOCAL OSC Bit 0 -2 Carrier Detection GAIN CONTROL Band Pass PRE-FILTER Bit 23 32 RAI
Low Pass DIGITAL FILTER FSK DEMODULAOR
IF FILTER
PLL
Bit 9 & 10
Bit 12 & 13 CARRIER/ PREAMBLE DETECTION
Low Pass
BAND IN USE
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ST7538
3.7 Transmission Mode The transmit mode is set when RxTx Pin ="0" and REG_DATA Pin ="0". In transmitting mode the FSK Modulator and the Power Line Interface are turned ON. The transmit Data (TXD) enter synchronously or asynchronously to the FSK modulator. Host Controller Synchronous Communication Mode: on CLR/T rising edge, TXD Line Value is read and sent to the FSK Modulator. ST7538 Manage the Transmission timing according to the BaudRate Selected Host Controller Asynchronous Communication Mode: TXD data enter directly to the FSK Modulator.The Host Controller Manages the Transmission timing In both conditions no Protocol Bits are added by ST7538. The FSK frequencies are synthesized in the FSK modulator from a 16 MHz crystal oscillator by direct digital synthesis technique. The frequencies Table in different Configuration is reported in Table 8. The frequencies precision is same as external crystal one's. In the analog domain, the signal is filtered in order to reduce the output signal spectrum and to reduce the harmonic distortion. The transition between a symbol and the following is done at the end of the on-going half FSK sinewave cycle. Figure 14. Transmitting Path Block Diagram
Bit 7 & 8 TIMER 7 TOUT THERMAL SENSOR Bit 14 5 TxD Bit 0-5
D-TYPE FLIP FLOP 8 CLR/T
ZCOUT
O
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let o
15
Pr e
du o
FSK MODULATOR
(s) ct
DAC
Ob -
Bit 0-2
so
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ALC
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PLI
uc d
29 23
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VOLTAGE LOOP
Vsense
CURRENT LOOP
CL
19
ATOP1
Band Pass TRANSMISSION FILTER PLI 21 ATOP2
ZERO CROSSING
PLI
24
ATO
CLR/T GENERATOR 16 ZCIN
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ST7538
Automatic Level Control (ALC) The Automatic Level Control Block (ALC) is a variable gain amplifier (with 32 non linear discrete steps) controlled by two analog feed backs acting at the same time. The ALC gain range is 0dB to 30 dB and the gain change is clocked at 5KHz. Each step increases or reduces the voltage of 1dB (Typ). Two are the control loops acting to define the ALC gain: - A Voltage Control loop - A Current Control Loop The Voltage control loop acts to keep the Peak-to-Peak Voltage constant on Vsense. The gain adjustment is related to the result of a peak detection between the Voltage waveform on Vsense and two internal Voltage references. - If Vsense < VCLTH - VCLHYST - If VCLTH - VCLHYST < Vsense < VCLTH + VCLHYST - If Vsense > VCLTH + VLCHYST The next gain level is increased by 1 step No Gain Change The next gain level is decreased by 1 step
The Current control loop acts to limit the maximum Peak Output current inside ATOP1 and ATOP2. The current control loop acts through the voltage control loop decreasing the Output Peak-to-Peak Amplitude to reduce the Current inside the Power Line Interface. The current sensing is done by mirroring the current in the High side MOS of the Power Amplifier (not dissipating current Sensing). The Output Current Limit (up to 370mArms), is set by means of an external resistor (RCL) connected between CL and PAVss. The resistor converts the current sensed into a voltage signal. The Peak current sensing block works as the Output Voltage sensing Block: - If V(CL) < CCLTH - CCLHYST - If CCLTH - CCLHYST < V(CL) < CCLTH + CCLHYST - If V(CL) > CCLTH + CLCHYST Voltage Control Loop Acting No Gain Change The next gain level is decreased by 1 step
Figure 15 shows the typical connection of Current anVoltage control loops. Figure 15. Voltage and Current Feedback external interconnection Example
ALC
O
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let o
od Pr e
VOLTAGE LOOP
ct u
(s)
so Ob Vout R1 5.6nF R2
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ATOP/ATO
VoutPK
Vsense VCLHYST VCLTH CL RCL AVss AVSS 100pF CCLHYST CCLTH 1.865V (Typ)
CURRENT LOOP
D03IN1421
Voltage Control Loop Formula
R1 + R2 V o u t P K -------------------- ( V C LT H V C LH Y S T ) R2
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ST7538
Table 10. Vout vs. R1 & R2 resistors value
Vout (Vrms) 0.150 0.250 0.350 0.500 0.625 0.750 0.875 1.000 1.250 1.500 Vout (dBV) 103.5 108.0 110.9 114.0 115.9 117.5 118.8 120.0 121.9 123.5 (R1+R2)/R2 1 .1 1 .9 2 .7 3 .7 4.7 5.8 6.6 7.6 9.5 10.8 R2 (K) 7.5 5.1 3.6 3.3 3.3 2.7 2.0 1.6 1.6 1.6 R1 (K) 1 .0 3 .9 5 .6 8 .2 11.0 12.0 11.0 10.0 13.0 15.0
Notes: The rate of R2 takes in account the input resistance on the SENSE pin (36 K). 5.6nF capacitor effect has been neglected.
Figure 16. Typical Output Current vs. Rcl
Ir ms (mA)
325 300 275 250 225 200 175 150 125 100
D01IN1311
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Integrated Power Line Interface (PLI) The Power Line Interface (PLI) is a double CMOS AB Class Power Amplifier with the two outputs (ATOP1 and ATOP2) in opposition of phase. Two are the possible configuration: - Single Ended Output (ATOP1). - Bridge Connection The Bridge connection guarantee a Differential Output Voltage to the load with twice the swing of each individual Output. This topology virtually eliminates the even harmonics generation. The PLI requires, to ensure a proper operation, a regulated and well filtered Supply Voltage. PAVcc Voltage must fulfil the following formula to work without clipping phenomena:
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2 2.5
so Ob 3 3.5 4
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4.5
Rcl(K)
V A T O P( A C) P A V c c ----------------------------------- + 7.5 V 2
To allow the driving of an external Power Line Interface, the output of the ALC is available even on ATO pin. ATO output has a current capability much lower than ATOP1 and ATOP2.
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ST7538
Figure 17. PLI Bridge Topology
VoutPK
INVERTER
ATOP2
2*VoutPK
LOAD ATOP1 Vout
ALC
R1 VOLTAGE LOOP Vsense 5.6nF R2
VoutPK
CURRENT LOOP
CL RCL PAVss 100pF
D03IN1422
Figure 18. PLI Startup Timing Diagram
RX/TX
TRXTX
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let o
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ATOP2
du
4V
(s) ct
TST
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0V STEP NUMBER 16 17 18 31
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ST7538
3.8 Crystal Oscillator ST7538 integrates a sub-threshold driver circuit to realize a 16MHz crystal oscillator. This circuit is able to drive a maximum load capacitance of 16pF with typical quartz ESR of 40. If the internal driver circuit is used, only one external crystal quartz and two external load capacitors (C1 e C2) are needed to realize the oscillator function (fig.19). Figure 19. Typical crystal configuration if ST7538 internal crystal driver circuit is used
ST7538 ST7538 XIN XOUT
Quartz C1 C2
If an external oscillator is used, XIN must be connected to DVss, while XOUT must satisfy the specifications given in table 5 (see also fig.20). Figure 20. XOUT waveforms if an external oscillator is used (see table 8 for parameter values)
XOUTSWING
XIN = DVSS
3.9 Control Register
bs O
The ST7538 is a multi-channel and multifunction transceiver. An internal 24 Bits Control Register allows to manage all the programmable parameters (table 11). The programmable functions are: Channel Frequency Baud Rate Deviation Watchdog Transmission Timeout Frequency Detection Time
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XOUT XOUTOFFSET
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Zero Crossing Synchronization Detection Method Mains Interfacing Mode Output Clock Input Pre-Filter Sensitivity Mode
Table 11. Control Register Functions
Function 0 to 2 Frequencies 60 KHz 66 KHz 72 KHz 76 KHz 82.05 KHz 86 KHz 110 KHz 132.5 KHz 3 to 4 Baud Rate 600 1,200 2,400 4,800 5 Deviation 0.5 1 6 Watchdog Disabled Enabled (1.5 s) 7 to 8 Transmission Time Out Value Selection Bit2 0 0 0 0 1 1 1 1 Bit 4 0 0 1 1 Bit 5 Bit1 0 0 1 1 0 0 1 1 Bit0 0 1 0 1 0 1 0 1 Bit 3 0 1 0 1 132.5 kHz Note Default
9 to 10
bs O
11
let o
Frequency detection time
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Disabled 1s 3s Not Used
(s) ct
Ob Bit 6 0 1 Bit 8 0 0 1 1 Bit 10
0 1
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2400
0.5
Enabled
Bit 7 0 1 0 1 Bit 9 0 1 0 1 1 ms 1 sec
500 s 1 ms 3 ms 5 ms
0 0 1 1 Bit 11
Zero Crossing Synchronization
Disabled Enabled Bit 13
0 1 Bit 12
Disabled
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ST7538
Table 11. Control Register Functions (continued)
Function 12 to 13 Detection Method Value Carrier detection without conditioning Selection 0 0 Note Carrier Detection Notification on CD_PD Line CLR/T and RxD signal always Present CLR/T and RxD lines are forced to "0" when Carrier is not detected Preamble Detection Notification on CD_PD Line CLR/T and RxD signal always Present Preamble Detection Notification on CD_PD Line CLR/T and RxD lines are forced to "0" when Preamble has not been detected or PLL is in Unlock condition Default Preamble detection without conditioning
Carrier detection with conditioning Preamble detection without conditioning
0
1
1
0
Preamble detection with conditioning
1
1
Bit 14 14 Mains Interfacing Mode Synchronous Asynchronous Bit 16 15 to 16 Output Clock 16 MHz 8 MHz 4 MHz Not Used 0 0 1 1 0 1 Bit 15 0 1 0 1
17 to 20 21
Not Used Reser ved
22
Sensitivity Mode
23
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let o
Input Filter
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Normal Sensitivity High Sensitivity
du
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4 MHz
Asynchronous
1001 Do not modify the default value 0
Nor m al
Disabled Enabled
Disabled
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ST7538
4
AUXILIARY ANALOG AND DIGITAL FUNCTIONS
4.1 Band In Use The Band in Use Block has a Carrier Detection like function but with a different Input Sensibility (77dBV Typ.) and with a different BandPass filter Selectivity (40dB/Dec). BU line is forced High when a signal in band is detected. To prevent BU line false transition, BU signal is conditioned to Carrier Detection Internal Signal. 4.2 Time Out Time Out Function is a protection against a too long data transmission. When Time Out function is enabled after 1 or 3 second of continuos transmission the transceiver is forced in receiving mode. This function allows ST7538 to automatically manage the CENELEC Medium Access specification. When a time-out event occur, TOUT is forced high, and is held high for at least 125 ms. To Unlock the Time Out condition RxTx should be forced High. During the time out period only register access or reception mode are enabled. During Reset sequence if RxTx line ="0" & REG_DATA line ="0", TIMEOUT protection is suddendly enabled and ST7538 must be configured in data reception after the reset event before starting a new data transmission. Time Out time is programmable using Control Register bits 7 and 8 (table 11). Figure 21. Time-out Timing and Unlock Sequence
RxTx TOUT
TOUT
4.3 Reset & Watchdog
RSTO Output is a reset generator for the application circuitry. During the ST7538 startup sequence is forced low. RSTO becomes high after a TRSTO delay from the end of oscillator startup sequence. Inside ST7538 is also embedded a watchdog function. The watchdog function is used to detect the occurrence of a software fault of the Host Controller. The watchdog circuitry generates an internal and external reset (RSTO low for TRSTO time) on expiry of the internal watchdog timer. The watchdog timer reset can be achieved applying a negative pulse on WD pin Fig 22. Figure 22. Reset and Watchdog Timing
O
bs
WD
let o
Pr e
du o
(s) ct
so Ob -
TOFF TOFFD
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TRSTO
TWO
TRSTO
RSTO TWD
TWM
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ST7538
4.4 Zero Crossing Detection The Mains Voltage Zero Crossing can be detected, through a proper connection of ZCIN to the Mains. ZCIN comparator has a threshold fixed at SGND. ZCOUT is a TTL Output forced High after a positive zero-crossing transition, and low after a negative one. Setting the Bit 11 inside the Control Register to "1" the transmission is automatically synchronized to the mains positive zero-crossing transition. This function is achieved turning on the PLI when RX/TX is low and delaying the CLR/T first transition until the first zero-crossing event. The automatic synchronization procedure can work only if the synchronous interface is programmed. If asynchronous interface is in use the Zero Crossing synchronization can be achieved managing the ZCOUT line. Figure 23. Synchronous Zero-Crossing Transmission
ZCIN
t
RxTx
CLR/T
TxD
ZCDEL ZCOUT
4.5 Output Clock
MCLK is the master clock output. The clock frequency sourced can be programed through the control register to be a ratio of the crystal oscillator frequency (Fosc, Fosc/2 Fosc/4). The transition between one frequency and another is done only at the end of the ongoing cycle. 4.6 Reg OK
REGOK allows to detect an accidental corruption of the Control Register content. If a register content corruption is detected, REGOK goes to "1". REGOK function is disabled during a control register writing session.
bs O
4.7 Under Voltage Lock Out The UVLO function turns off the device if the PAVdd voltage falls under 4V. Hysteresis is 340mV typically. 4.8 Thermal Shutdown The ST7538 is provided of a thermal protection which turn off the PLI when the junction temperature exceeds 170C 10% . Hysteresis is around 30C. When shutdown threshold is overcome, PLI interface is switched OFF. Thermal Shutdown event is notified to the HOST controller using TIMEOUT line. When TIMEOUT line is High, ST7538 junction temperature exceed the shutdown threshold (Not Lached).
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ST7538
4.9 5V Voltage Regulator and Power Good Function ST7538 has an embedded 5V linear regulator externally available to supply the application circuitry. The linear regulator has a very low quiescent current (50A) and a current capability of 100mA. The regulator is protected against short circuitry events. When the regulator Voltage is above the power good threshold (VPG), Power Good line is forced high, while is forced low at startup and when VDC falls below VPG - VPGHYS Voltage. Figure 24. Power Good Function
VD C
4.5V 250mV
Time
PG PG OK
D03IN1411
Time
4.10 Power-Up Procedure
To ensure ST7538 proper power-Up sequence, PAVcc, AVss and DVss Supply has to fulfil the following rules: 1) PAVcc rising slope must not exceed 100V/ms. 2) When DVdd and AVdd are below 5V (externally supplied): 100mV < PAVcc-AVdd , PAVcc-DVdd < 1.2V. When AVdd and DVdd supply are connected to VDC, with load < 100mA and filtering capacitor on VDC < 100uF, the second rule can be ignored. Figure 25. Power-UP Sequence
Voltage
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let o
PAVcc-AVdd PAVcc-DVdd
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5V
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(s) t
so Ob -
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PAVcc
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100V/ms
DVdd, AVdd
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Time
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N.C. SGND 17 22 40 38 37 21 24 32 LOAD ATOP1 R1 RAI AC LINE ATO ATOP2 No External Components for POWER LINE DRIVER C_MINUS C_PLUS C_OUT PAVCC AC/DC Conver ter SINGLE SUPPY 25 39 34 N.C. N.C. N.C. VDC 33 44 DVdd 10 13 30 35 14 42 36 7 9 15 1 3 5 4 8 31 16 27 11 12 20 PAVSS DVSS DVSS 18 2 GND 6 GND 41 26 43 RxFO RCL 23 CL R2 29 Vsense 19 C1 WD PG BU
ST7538
let o Pr e
28 AVdd
5V Supply for Host Controller
du o (s) ct
ST7538
TEST3
TEST2
TEST1
REGOK
TOUT
ZCOUT
so Ob -
HOST CONTROLLER RxD TxD
CD/PD
Voltage Regulation & Current Protection C2
Mains Coupling reference circuit
te le
RX/TX
Figure 26. Application Schematic Example with Coupling Tranformer.
CLR/T
REG/DATA
ro P
ZCIN
5 Lines Serial Interface
XIN
MCLK
Zero Crossing Transmission Synchronization XOUT
RSTO
uc d
Clock & Reset for Host Controller
s) t(
D03IN1412A
ST7538
5
PACKAGE INFORMATION
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 5.1 Thermal and Soldering Information Best thermal performance is acheived when slug is soldered to PCB. It is recomended to have five solder dots (See fig. 28) without resist to connect the Copper slug to the ground layer on the soldering side. Moreover it is recomeded to connect the ground layer on the soldering side to another ground layer on the opposite side with 15 to 20 vias. It is suggested to not use the PCB surface below the slug area to interconnect any pin except groung pins. Figure 27. ST7538 Slug Drawing
Copper Slug Solder plated
Figure 28. Soldering Information
Cu plate
bs O
let o
Pr e
A L
du o
B
Solder dots
(s) ct
L
so Ob -
Lead frame
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0.10mm 0.05
D03IN1414
Package Sizes A
L1
10x10x1.4mm 2.00 mm 1.00 mm 6.00 mm 10.00 mm
B L L1 (Copper plate)
L1
D03IN141 3
If PCB with ground layer, connect copper plate with 15 to 20 vias
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ST7538
Figure 29. TQFP44 (Slug Down) Mechanical Data & Package Dimensions
mm DIM. MIN. A A1 A2 b c D D1 D3 e E E1 E3 H L L1 S S1 K ccc 6.00 6.00 0.45 11.80 9.80 0.05 1.35 0.30 0.09 11.80 9.80 12.00 10.00 8.00 0.80 12.00 10.00 8.00 5.89 0.60 1.00 0.236 0.236 0 (min.), 3.5 (typ.), 7(max.) 0.10 0.004 0.75 0.018 12.20 10.20 0.464 0.386 1.40 0.37 TYP. MAX. 1.60 0.15 1.45 0.45 0.20 12.20 10.20 0.002 0.053 0.012 0.003 0.464 0.386 0.472 0.394 0.315 0.031 0.472 0.394 0.315 0.232 0.024 0.039 0.030 0.480 0.401 0.055 0.014 MIN. TYP. MAX. 0.063 0.006 0.057 0.018 0.008 0.480 0.401 inch
OUTLINE AND MECHANICAL DATA
TQFP44 (10x10x1.40mm) with Slug Down
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0049510 D
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Table 12. Revision History
Dat e Januar y 2004 24-Nov-2005 Revision 4 5 Description of Changes Migration from ST-Press to EDOCS DMS. Removed "Packet Mode" function. Inser ted new Paragraph 3.8. on Crystal Oscillator. Added ECOPACK information.
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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