STP80NS04ZB
N-CHANNEL CLAMPED 7.5m - 80A TO-220 FULLY PROTECTED MESH OVERLAYTM MOSFET
PRELIMINARY DATA TYPE STP80NS04ZB
s s s s
VDSS CLAMPED
RDS(on) <0.008
ID 80 A
TYPICAL RDS(on) = 0.0075 100% AVALANCHE TESTED LOW CAPACITANCE AND GATE CHARGE 175 oC MAXIMUM JUNCTION TEMPERATURE
1
3 2
DESCRIPTION
This fully clamped Mosfet is produced by using the latest advanced Company's Mesh Overlay process which is based on a novel strip layout. The inherent benefits of the new technology coupled with the extra clamping capabilities make this product particularly suitable for the harshest operation conditions such as those encountered in the automotive environment. Any other application requiring extra ruggedness is also recommended.
TO-220
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS s A BS , SOLENOID DRIVERS s M OTO R CONTROL s DC-DC CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Symbol V DS VDG VGS ID ID IDG IG S IDM(·) Ptot VESD(G-S) VESD(G-D) VESD(D-S) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Gate Current (continuous) Gate SourceCurrent (continuous) Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Gate-Source ESD (HBM - C = 100pF, R=1.5 k) Gate-Drain ESD (HBM - C = 100pF, R=1.5 k) Drain-source ESD (HBM - C = 100pF, R=1.5 k) Storage Temperature Max. Operating Junction Temperature Value CLAMPED CLAMPED CLAMPED 80 60 50 50 320 200 1.33 4 4 4 -65 to 175 -40 to 175 Unit V V V A A mA mA A W W/C kV kV kV C C
(·) Pulse width limited by safe operating area. May 2003
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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THERMAL DATA
Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Maximum Lead Temperature For Soldering Purpose Max Max 0.75 62.5 300 C/W C/W C
AVA LANCHE CHARACTERISTICS
Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 C, ID = IAR, VDD = 30 V) Max Value 80 500 Unit A mJ
ELECTRICAL CHARACTERISTICS (Tcase = 25 C unless otherwise specified) OFF
Symbol V(BR)DSS Parameter Clamped Voltage Test Conditions ID = 1 mA, VGS = 0 -40 < TJ < 175 oC VDS = 16 V VDS = 16 V VDS = 16 V VGS = 10 V VGS = 16 V IGS = 100 A Tc=25 oC TJ =150 oC TJ =175 oC TJ =175 oC TJ =175 oC 18 Min. 33 Typ. Max. Unit V
IDSS
Zero Gate Voltage Drain Current (VGS = 0)
10 50 100 50 150
A A A A A V
IGSS VGSS
Gate-body Leakage Current (VDS = 0) Gate-Source Breakdown Voltage
ON (*)
Symbol VGS(th) RDS(on) ID(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance On State Drain Current Test Conditions VDS = VGS ID = 1 mA -40 < TJ < 150 oC VGS = 10 V VGS = 16 V ID = 40 A ID = 40 A 80 Min. 1.7 Typ. 3 8 7.5 Max. 4.2 9 8 Unit V m m A
VDS > ID(on) x RDS(on)max, VGS = 10V
DYN AMIC
Symbol gfs (*) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS>ID(on)xRDS(on)max ID=40A VDS = 25V, f = 1 MHz, VGS = 0 Min. 30 Typ. 50 2700 1275 285 3300 1600 350 Max. Unit S pF pF pF
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STP80NS04ZB
ELECTRICAL CHARACTERISTICS (continued) SW ITCHIN G ON
Symbol Qg Qgs Qgd Parameter Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD= 20 V ID= 80 A VGS= 10V Min. Typ. 80 20 27 Max. 105 Unit nC nC nC
SW ITCHIN G OFF
Symbol tr(Voff) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Conditions ID = 80 A Vclamp = 30 V RG = 4.7, VGS = 10 V (Inductive Load, Figure 5) Min. Typ. 115 80 210 Max. 150 105 280 Unit ns ns ns
SOURCE DRAIN DIODE
Symbol ISD ISDM (·) VSD (*) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 80 A VGS = 0 90 0.18 4 Test Conditions Min. Typ. Max. 80 320 1.5 Unit A A V ns C A
di/dt = 100A/s ISD = 80 A VDD = 25 V Tj = 150C (see test circuit, Figure 5)
(*)Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. (·)Pulse width limited by safe operating area.
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Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times
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TO-220 MECHANICAL DATA
DIM. MIN. A C D D1 E F F1 F2 G G1 H2 L2 L4 L5 L6 L7 L9 DIA. 13.0 2.65 15.25 6.2 3.5 3.75 0.49 0.61 1.14 1.14 4.95 2.4 10.0 16.4 14.0 2.95 15.75 6.6 3.93 3.85 0.511 0.104 0.600 0.244 0.137 0.147 4.40 1.23 2.40 1.27 0.70 0.88 1.70 1.70 5.15 2.7 10.40 0.019 0.024 0.044 0.044 0.194 0.094 0.393 0.645 0.551 0.116 0.620 0.260 0.154 0.151 mm TYP. MAX. 4.60 1.32 2.72 MIN. 0.173 0.048 0.094 0.050 0.027 0.034 0.067 0.067 0.203 0.106 0.409 inch TYP. MAX. 0.181 0.051 0.107
A
C
D1
L2
F1
D
G1
E
Dia. L5 L7 L6 L4
P011C
L9
F2
F
G
H2
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics 2003 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http ://www.st.com
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