ST7 FAMILY
ICC PROTOCOL REFERENCE MANUAL
INTRODUCTION
This document is an advanced technical reference manual. It has been written for engineers who want to build their own ST7 programming, testing or debugging tools using the In-Circuit Communication (ICC) protocol. This document does not target engineers who only use standard development tools such as ST programming boards or debuggers. This manual describes how to communicate with an ST7 microcontroller using the In-Circuit Communication protocol. For implementation details such as register or stack top address, refer to product datasheets. T h e In-Circuit Communication (ICC) protocol enables an ST7 microcontroller to communicate with an External Controller (e.g. PC with ICC interface board) with only 4 wires including VSS. This protocol is used to download a program into the RAM for execution. To perform the ICC communication, the ST7 executes an ICC Monitor stored into the write protected ST7 System Memory. Consequently, the ICC protocol performs three different applications described below: ICP: In-Circuit Programming is an ST7 FLASH programming method using the ICC communication protocol. ICP is used to update the entire contents of the FLASH memory (including option bytes). For more details, see "FLASH Programming" reference and quick reference manuals. ICT: In-Circuit Testing is a flexible method of performing production test routines that can be easily modified and extended without affecting the content of the FLASH program memory (see Section 10). ICD: In-Circuit Debugging is the ability to debug a FLASH device using the ICC protocol. This feature allows the implementation of a low cost emulator strategy (see Section 9). This manual describes the In-Circuit Communication (ICC) protocol and its implementation with an External Controller for performing In-Circuit Programming (ICP) or In-Circuit Testing (ICT) of ST7 FLASH microcontrollers (MCUs) or for performing In-Circuit Debug (ICD) with the ST72F264 for example. ST72Cxxx devices do not feature ICC protocol. In these devices, the In-Situ Programming (ISP) method with a different protocol is used. ISP is not described in this document. For more information on programming ST72Cxxx devices, refer to the AN1179 application note. Related Documentation

Flash Programming Reference Manual Flash Programming Quick Reference Manual1 Debug Module Reference Manual

1T h e

Quick Reference manual provides device-specific tables included in the previous revision of the Flash Progamming and ICC reference manuals.
Rev. 3
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Table of Contents
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 N GLOSSARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.1 IMPLEMENTED ICC FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2 COMMUNICATION TIMINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3 ENTERING ICC MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.1 CONTROLLED WINDOW ICC MODE ENTRY METHOD . . . . . . . . . . . . . . . . . .10 3.2 FIXED 256 TCPU WINDOW ICC MODE ENTRY METHOD . . . . . . . . . . . . . . . .12 3.3 EXTERNAL CLOCK/APPLICATION CLOCK ICC MODES . . . . . . . . . . . . . . . . .13 3.3.1 Special Case of Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . .13 4 ICC BYTE EXCHANGE PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.1 BYTE EXCHANGE FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.2 BIT EXCHANGE FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.2.1 Next Bit is to be RECEIVED by the ST7 Device . . . . . . . . . . . . . . . . . . . . .15 4.2.2 Next Bit to be SENT by the ST7 Device . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.2.3 Switching from ICC Receive to ICC Send . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.3 BEGINNING OF AN ICC SESSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 5 ICC COMMAND LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 5.1 5.2 5.3 5.4 5.5 IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 ST7 PRODUCT IDENTIFIER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 RAM AND CPU REGISTERS USED BY AN ICC SESSION . . . . . . . . . . . . . . . .20 AUTOMATIC CONTEXT SAVING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 COMMAND DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 5.5.1 Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 5.5.2 Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 5.5.3 Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 5.5.4 Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 5.5.5 ICC Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

6 ICC MONITOR CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 7 USING THE ST7 ICC MONITOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 8 BUILDING AN ICC INTERFACE TO A PC PARALLEL PORT . . . . . . . . . . . . . . . . . .28 8.1 HARDWARE INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 9 8.1.1 Basic PC Interface Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6. . . .28 8.1.2 Board ICC Mode Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

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8.1.3 Board Communication Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 8.1.4 ICCCLK and ICCDATA pull-ups for open-drain communication . . . . . . . . .34 8.1.5 RESET Pull-ups for Open-drain Communication . . . . . . . . . . . . . . . . . . . . .35 8.2 ICC SIGNALS AND PC SOFTWARE INTERFACE EXAMPLE . . . . . . . . . . . . . .36 9 IN-CIRCUIT DEBUGGING (ICD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 9.1 ST7 DEVICES WITH DEBUG MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 9.1.1 ICC Monitor Call on DM Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 9.1.2 ICD Implementation with XFlash devices . . . . . . . . . . . . . . . . . . . . . . . . . .42 9.1.3 ICD Implementation with HDFlash Devices . . . . . . . . . . . . . . . . . . . . . . . . .45 9.2 ST7 DEVICES WITHOUT DEBUG MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . .46 9.3 ICD GENERAL LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 10 IN-CIRCUIT TESTING (ICT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 10.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 10.2 ICT EXAMPLE: INTERRUPT VECTOR 8-BIT CHECKSUM . . . . . . . . . . . . . . . .49 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

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GLOSSARY
This chapter gives a brief definition of all new acronyms and names linked to the ICC protocol as a quick reference: XFlash (Extended): Extended FLASH memory is based on EEPROM technology. The XFlash provides extended features such as byte-by-byte re-programming (by means of byte erasing) and data EEPROM capability. The XFlash devices are available between 1k and 16kbytes. HDFlash (High Density): High density FLASH memory is based on FLASH technology. The high density of the HDFlash cell is used for devices with 4k up to 60kbytes FLASH memory. This HDFlash is programmed byte per byte but erased by sector. IAP (In-Application Programming): The IAP is the ability to re-program the FLASH memory of a microcontroller while the device is already plugged-in to the application and the application is running. ICC (In-Circuit Communication): The ICC is either an ST7 mode or a software protocol stored by ST7 micrcontrollers in the System Memory. The ICC software protocol is used to download programs into RAM and execute them. It is used for ICP. It is accessed by entering ICC Mode after a dedicated reset sequence. ICC Monitor: The ICC Monitor is the ST7 software which manages the ICC protocol. It is located in System Memory. ICC Mode: The ICC Mode is a special ST7 run mode which executes the ICC Monitor after a reset sequence. It is entered by means of the RESET pin and with a specific reset sequence. This mode remains active until the next reset sequence. ICC Session: An ICC Session takes place when the ST7 ICC Monitor is executed in USER or ICC Mode. ICP (In-Circuit Programming): The ICP is the ability to program the FLASH memory of a microcontroller using ICC protocol while the device is already plugged-in to the application. ICT (In-Circuit Testing): The ICT is a flexible method of performing production test routines that can be easily modified and extended without affecting the content of the FLASH program memory. ICD (In-Circuit Debugging): The ICD is the ability to debug a FLASH device using the ICC protocol. This feature allows low cost emulator strategy. USER Mode: The USER Mode is the standard user application run mode in the ST7. It is entered by means of the RESET pin and without any specific reset sequence. This mode remains active until the next reset sequence. RESET Phase: The ST7 RESET phase is the time spent between the rising edge of the RESET pin and the execution of the first instruction Embedded Commands: The Embedded Commands are the software drivers used by the USER application to program or erase HDFlash devices. System Memory: The System Memory is a write-protected part of the memory which contains the ICC Monitor. The HDFlash System Memory also contains the Embedded Command software. The XFlash System Memory is accessible when the USER application is executed. However, this is not the case for HDFlash System Memory.
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1 OVERVIEW
ICC defines a half-duplex synchronous serial communication protocol with an automatic adaptation to the speed of the slower device (see Section 4). The communication is ensured by two lines: ICCCLK and ICCDATA. Data is exchanged byte by byte. The bytes sent by the External Controller are commands for the ST7 to execute, following an higher-level protocol. The command library allows a wide range of actions (see Section 5). To initialize the ST7 to be able to manage this protocol, a special ST7 functional mode has to be entered. This mode is called "ICC Mode". When this mode is selected, the ST7 executes an ICC Monitor program which allows the ST7 to receive commands to be executed using the ICC protocol (implemented as a software communication peripheral). The flowchart shown in Figure 1 gives an overview of the ICC management.
Note: With XFlash and ROM ST7 devices, the ICC Monitor can also be executed in "USER Mode". See section 6 on page 26 for more details.

Figure 1. ICC Protocol Flowchart
ST7 receives ICC command from External Controller or co mmand ST7 executes requested code else ST7 executes ICC command

RESET or TRAP

The ICC protocol can be divided into four different layers on the ST7 side and five on the External Controller side, as shown in Figure 2. Caution: During ICC Mode, the I/O, TLI and peripheral interrupt vectors are not available. Consequently, they cannot be used. Only the HDFlash embedded command non-maskable interrupt is available.

For an overview of the Application Board hardware description, refer to the device datasheet or Figure 19 "PC to ICC Interface Board - ICCCLK and ICCDATA Signals" on page 35.

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Figure 2. ICC Protocol Layers ST7
ICC Command Interpreter (see Section 5) ICC Monitor ICC Software Layers ICC Byte Send and Receive (see Section 4.1) ICC_send_byte ICC_receive_byte

External Controller
Application user interface to pilot the ST7 using ICC ICC Command Interpreter

ICC Bit Send BSET/RES PxD(D)R,#ICCCLK and Receive #ICCDATA ICCCLK (see Section 4.2)
ICCDATA

ICC Software Layers ICC Byte Send (see and Receive Section 8.2) ICC Bit Send and Receive

Example: PC Parallel port ICC driver

ICC Physical ICCCKL and ICCDATA Layer (2 I/Os with open-drain output and input capability)

ICC ICC board able to manage the ICCCLK and Physical ICCDATA signals by the External Controller Layer

1.1 IMPLEMENTED ICC FEATURES Refer to the FLASH Programming Quick Reference Manual for a table of implemented ICC features and their main characteristics for each ST7 device. The data mentioned in this table is described in detail later on in this document.

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2 COMMUNICATION TIMINGS
Description ICC receive Baud rate 1) 1KByte transfer time 2) Baud rate 1) 1KByte transfer time 2) fCPU=8MHz 3) 50 133 / 16.6 69 Conditions Min. Max. 181 / 22.6 Unit kbps / kBps ms kbps / kBps ms

ICC transmit

Commands are simple in order to be fast. For example, in the same conditions as above, the External Controller can read or write directly into the ST7 RAM or registers at around 15 kBps.
Notes: 1. This maximum baud rate is the fastest communication speed at bit transmission level. It is given in bits per second (bps) and bytes per second (Bps). 2. This transfer time takes into account the added transferred bytes for the ICC command management. 3. The speeds and timings given in this table are proportional to ST7 fCPU frequency and assume that the External Controller is faster than the ST7. fCPU = 8MHz is given as an example.

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3 ENTERING ICC MODE
Two different sequences exist for making the ST7 enter ICC Mode depending on the selected device. Both methods are based on a pulse counter in the ST7 which determine whether the microcontroller enters ICC Mode or not. Refer to the implemented ICC features table in the FLASH Programming Quick Reference Manual to know which method has to be applied to the ST7 devices. 3.1 CONTROLLED WINDOW ICC MODE ENTRY METHOD To make the ST7 enter ICC Mode, three steps have to be performed:

First the pulse counter must be reset: to do this, RESET must be kept low while ICCCLK is kept high or ICCSEL is kept low depending on the device (refer to the implemented ICC features table in the FLASH Programming Quick Reference Manual for more details). Then keeping RESET low, N pulses must be performed on ICCDATA while ICCCLK is kept low or ICCSEL is kept high depending on the device. At the end of the pulse sequence, ICCCLK and ICCDATA must be kept low (refer to the implemented ICC features table in the FLASH Programming Quick Reference Manual) . Finally RESET is released (high state) to start the ICC Monitor execution after the ST7 internal reset phase (256 or 4096 tCPU periods).

Special case: Devices without ICCSEL pin When ICCCLK is used to reset the pulse counter (and not ICCSEL), the ST7 ICCCLK pin is configured as a pull-up input as long as RESET is in low state. This guarantees that the ST7 enters USER Mode when the ICCCLK pin is unconnected or only connected to high impedance outputs. Caution: In the above case, the ICCCLK pin must always be pulled up. This is to avoid entering ICC mode unexpectedly during normal application operation.

In this case, the ST7 ICCSEL pin is always configured as a floating input. The ST7 ICCDATA pin is configured as a standard I/O (floating input) as long as RESET is in low state and during the ST7 reset phase. The pulse sequence is totally independent from the ST7 CPU clock (fully asynchronous ICC Mode entry). The selected ST7 mode (USER or ICC) depends on the pulse counter value when RESET returns to high state. Figure 3 shows a typical sequence for entering ICC Mode.

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Figure 3. Entering ICC Mode with Controlled Window
RESET ICCSEL 3) tsu(pulse) ICCCLK th(pulse) ICCDATA th(iccclkH) Pulse Counter Reset tw(pulseL) N Pulses ST7 Reset Phase 256 or 4096 CPU Cycles ICC Monitor Execution tsu(iccclk)

Symbol th(iccclkH) tw(pulseL) tw(pulseH) tsu(pulse) th(pulse) tsu(iccclk)

Min 20 1) 62.5

Max

Unit s ns

tw(pulseH)

0.5 1

t CPU s

Notes: 1. This hold time, required to reset the pulse counter, is directly linked to the RESET pad filter characterized by th(RSTL)in (see device datasheet for more details). 2. A glitch on ICCSEL or ICCCLK (depending on the device, refer to the implemented ICC features table in the FLASH Programming Quick Reference Manual) while RESET is pulled low could reset the pulse counter. A glitch on ICCDATA pad could be interpreted as a pulse during the "N Pulses" phase. Therefore, noise must be avoided on these pins. 3. On dual voltage HDFlash devices, ICCSEL and VPP (FLASH programming voltage) are on the same pin.

Caution:

After the RESET phase, ICCSEL(/VPP) pin must be kept high (VDD or 12V for HDFlash) to avoid ICC communication issues.

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3.2 FIXED 256 TCPU WINDOW ICC MODE ENTRY METHOD A pulse sequence is sent by an External Controller to the ICCSEL/VPP ST7 pin within a time window of 256 tCPU after releasing the RESET pin. To make the ST7 enter ICC Mode, the External Controller must generate 38 pulses on the ICCSEL/VPP line. The ST7 pulse counter is reset when the RESET pin is pulled low. The pulse sequence is dependent from the ST7 CPU clock. Note: In devices with no RESET pin (such as the ST7SCR), the start of the pulse sequence must be synchronized with VDD. Refer to the Flash Programming Quick Reference Manual for device-related data. Figure 4 shows a typical sequence for entering ICC Mode. Figure 4. Entering ICC Mode with Fixed tCPU Window
th(reset) RESET ICCDATA ICCCLK fOSC/2 th(VppH) ICCSEL/VPP 38 Pulses within ST7 internal reset phase 4096 tCPU ICC monitor execution

Symbol tw(pulseL) tsu(pulse) th(pulse) tw(pulseH) tw(pulseL) tw(pulseH) th(VppH) tsu(pulse) th(pulse) th(reset)

Min 62.5

Max

Unit

ns

0.5 256 30

tCPU s

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3.3 EXTERNAL CLOCK/APPLICATION CLOCK ICC MODES As shown in "Implemented ICC Features" table in the FLASH Programming Quick Reference Manual, on some devices, depending on the number of pulses counted for ICC mode entry, ICC mode is either in External Clock or Application Clock mode.

In External clock mode, the user option byte settings are ignored, In Application clock mode, the user option byte settings are taken into account.

In External clock mode, reserved Flash locations (which may contain internal oscillator calibration data for example) are not write protected, and could be corrupted if you program the device using a wrong address. In Application clock mode, reserved Flash locations are write protected, so it is safer than External clock mode. 3.3.1 Special Case of Hardware Watchdog Option If the hardware watchdog option has been enabled in the device to be reprogrammed, a reset occurs after the watchdog timeout, preventing the successful completion of programming. This issue has been solved for most devices, a modification to their design causes them to automatically switch the hardware watchdog option to software watchdog in ICC mode. The only device exceptions to this are shown in the "Implemented ICC Features" table in the FLASH Programming Quick Reference Manual. For these devices, the ST7 has to enter external clock mode in order to be able to reprogram devices with hardware watchdog enabled. To select external clock mode, send 35 pulses instead of the 38 as shown in the same table. In the case of the ST72F651, the effect of sending 35 pulses will cause the watchdog setting to be ignored, but other user options are taken into account, so it is not identical to external clock mode as defined in Section 3.3.

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4 ICC BYTE EXCHANGE PROTOCOL
The ICC protocol defines a synchronous serial communication where both interlocutors are partial masters of the clock. The purpose of such a protocol is to allow communication even if the clock frequencies of both devices are different. ICCCLK carries the clock signal and ICCDATA the data signal: the logic level on ICCDATA is valid only when ICCCLK is low. T h i s communication is based on an open-drain line approach. Both lines are always connected to a pull-up resistor located inside the External Controller. For the Controller, "releasing" ICCCLK or ICCDATA means connecting the line only to this resistor. 4.1 BYTE EXCHANGE FLOW Data is transmitted byte by byte, with the most significant bit being sent first as shown in Figure 5. Figure 5. ICC Byte Definition time bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 This means that the transmission direction is the same for 8 consecutive bits. So, the emitting device does not need to release ICCDATA between two bit transmissions. Actually, in the ICC Monitor, the ST7 releases ICCDATA only after sending the last bit of the byte, i.e. the LSB. I n the following Figure 6 and Figure 7, ICCDATA is always released between two bit transmissions, for figure clarity. 4.2 BIT EXCHANGE FLOW The following describes how a bit is transmitted from one device to another during an ICC Session. During the interval between two bit exchanges, both lines are released by both devices, so they are both in high state. The exchange is always initiated by the ST7 when it is ready to receive or send the bit, and when it has detected that ICCCLK is high. The signal sequence depends on the transmission direction. Transmission direction and the end of ICC Session are determined by the ICC command protocol level, described in Section 5. To understand in detail how the ST7 follows this physical protocol, refer to the ICC Monitor code in Section 6. Notice that the External Controller must respect certain time constraints imposed by the ST7. Section 8 describes an example of hardware implementation that meets these constraints.
Note: In each of the following state diagrams, the data processing state corresponds to the transition between two bit exchanges. The protocol works even if this state lasts for a long time. When the ST7 is in this state, ICCCLK can be low or high. When the Controller is in this state, ICCCLK is always low.

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4.2.1 Next Bit is to be RECEIVED by the ST7 Device If the next bit is to be received by the ST7, the MCU starts by tying the clock low. See Figure 6. In reaction to this falling edge, the External Controller outputs the data bit on ICCDATA and ties the clock low. After a td(iccdata) delay, the ST7 reads the data bit on ICCDATA. Then it releases the clock (trh(st7iccclkL) after the ICCCLK falling edge). When the External Controller is ready to receive or send the next bit, it releases the clock. When ICCCLK returns to high state, the External Controller releases ICCDATA (see Section 4.1 Byte Exchange Flow). Then the next bit exchange is possible. Figure 6. ICC Bit Exchange when Bit is received by the ST7
ST7 quicker than Controller
trh(st7iccclkL) trh(st7iccclkH)

Controller quicker than ST7

ST7 Action on ICCCLK Controller Action on ICCCLK ICCCLK IC CD ATA

Release Release

Tie low Tie low
trh(iccclkL)

Release Release

Tie low Tie low
trh(iccclkL)

Re leas e Re leas e

bit p
td(iccdata) td(iccdata)

bit p-1
(see note)

S T 7 r e a d s bi t p

ST7 reads bit p-1 Release

ST7 Action on ICCDATA Controller Action on ICCDATA ST7 STATE DIAGRAM
Reception requested Wait for ICCCLK=1 ICCCLK = 1 Data Proce ssin g Tie I CCCLK l ow Release Output bit p

Release

output bit p-1

Release

CONTROLLER STATE DIAGRAM
Tran smission requ este d Wait for next falling edge on ICCCLK ICCCLK = 0 Output bit on ICCDATA R e l e a s e I C C C L K a n d I C C D A TA ICCCLK = 0 Data Processing
Min 28 16 trh(st7iccclkL) 15 t CPU

Release ICCCLK ICCCLK = 0 Read ICCDATA

ICCCLK = 0

ICCCLK = 0

Symbol trh(st7iccclkL) trh(st7iccclkH) trh(iccclkL) td(iccdata)

Description Period that the ST7 ties ICCCLK low Period that the ST7 releases ICCCLK Period during which the External Controller must detect ICCCLK low and tie it to low Delay between the falling edge of ICCCLK and when the ST7 reads ICCDATA

Max

Unit

Note: Even if the Controller has already released ICCCLK, it still outputs the data bit on ICCDATA so that the ST7 can read it.

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4.2.2 Next Bit to be SENT by the ST7 Device If the next bit is to be sent by the ST7, the MCU outputs the data bit on ICCDATA. See Figure 7. Then it ties the clock low. In reaction to this falling edge, the External Controller ties the clock low and reads the data bit on ICCDATA. After tsh(st7iccclkL), the ST7 releases the clock. When the External Controller is ready to receive or send the next bit, it releases the clock. When ICCCLK returns to high state, the ST7 releases ICCDATA (see Section 4.1 Byte Exchange Flow). Then the next bit exchange is possible. Figure 7. ICC Bit Exchange when Bit is sent by the ST7
ST7 quicker than Controller
tsh(st7iccclkL) tsh(st7iccclkH)

Controller quicker than ST7

ST7 Action on ICCCLK Controller Action on I CCCLK

Release Rel ease

Tie low T ie low
tsh(iccclkL)

Release Release

Tie l ow Tie low
tsh(iccclkL)

Re l e a s e Release

ICCCLK ICCDATA
bit p
(see note)

bit p-1

Controller Action on IC CDATA ST7 Action on ICCDATA ST7 STATE DIAGRAM
Transmission requested Wait for ICCCLK=1 Release

Controller reads bit p R e lease Output bit p Release

C o n t r o l l e r r e a d s b i t p-1

output bit p - 1

Release

CONTROLLER STATE DIAGRAM
Reception requested ICCCLK = 0 Release I CCCLK

ICCCLK = 1 Data Processing Output bit on ICCDATA

Wait for next falling edge on ICCCLK Data Processing

Release ICCCLK and ICCDATA ICCCLK = 0
Symbol tsh(st7iccclkL) tsh(st7iccclkH) tsh(iccclkL)

ICCC LK = 1 ICCCLK = 0 Read ICCDATA

ICCCLK = 0

Tie ICCCLK low

Description Period that the ST7 ties ICCCLK low Period that the ST7 releases ICCCLK Period during which the External Controller must detect ICCCLK low and tie it to low

Min 17 43

Max

Unit

t CPU tsh(st7iccclkL)

Note: Even if the ST7 has already released ICCCLK, it still outputs the data bit on ICCDATA so that the Controller can read it.

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4.2.3 Switching from ICC Receive to ICC Send The Figure 8 describes how ICCCLK and ICCDATA are managed when switching from a bit received by the ST7 to a bit to be sent by the ST7. The Figure 9 describes how ICCCLK and ICCDATA are managed when switching from a bit sent by the ST7 to a bit to be received by the ST7. Figure 8. Switching from ICC Receive to ICC Send
td(iccclkHdataHL)

ICCCLK ICCDATA
bit 0 bit 7

D AT A SE T BY THE CO NTROLLER

DATA LIN E RELEAS ED

DATA SET BY T H E ST 7

Symbol

Description

Value 42

Unit tCPU

td(iccclkHdataHL) Delay between the ST7 detects ICCCLK high and when the ST7 sets the data on ICCDATA

Figure 9. Switching from ICC Send to ICC Receive
td(iccclkHdataHZ)

ICCCLK ICCDATA
bit 0 bit 7

D AT A SE T BY T H E ST 7

DATA LIN E RELEAS ED

DATA SET BY THE C ONTROLLE R

Symbol

Description

Value 11

Unit tCPU

td(iccclkHdataHZ) Delay between the ST7 detects ICCCLK high and when the ST7 releases ICCDATA

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4.3 BEGINNING OF AN ICC SESSION The ST7 RESET phase is the time spent between the rising edge of the RESET pin and the execution of the first instruction (see Section 3 for more details). When the ST7 has finished its RESET phase, it jumps into the ICC Monitor if ICCDATA is forced low by the Controller. So the External Controller must tie low ICCDATA while the ST7 is still in RESET phase. Then the ST7 waits for a high level on ICCCLK. So the External Controller may release ICCCLK while the ST7 is still in RESET phase or afterwards. The protocol works in both cases. To make sure both devices are synchronized, the first bit exchanged is a dummy, i.e. during a single clock period (a falling and a rising edge on ICCCLK), the ICCDATA value is ignored. So the External Controller can release ICCDATA line at any time while it ties ICCCLK low. After this synchronization bit, the ST7 receives the first valid data bit from the Controller which corresponds to the MSB of the first ICC command (see Section 5). The beginning of the ICC Session following an ICC Mode entry is shown in Figure 6. Other methods of starting an ICC Session exist, see Section 9 for more details. Figure 10. Beginning of ICC Session when the ICC Monitor is called by ICC Mode Entry
ST7 RESET Phase ICC Monitor Execution

RESET ST7 Action on ICCCLK Controller Action on ICCCLK
Release Tie low

tdh(st7iccclkL)

Tie low Tie low

Release R e lease

Tie low Tie low

Release Release

Release

Falling edge indicating the start of the ICC Monitor.

tdh(iccclkL) (see note)

sync bit

ICCCLK ICCDATA
1st bit (MSB)

ST7 reads 1st bit

ST7 Action on ICCDATA Controller Action on ICCDATA
Symbol tdh(st7iccclkL) tdh(iccclkL)

Release Pulse Tie low R e lease Output 1st bit
Min 16 tdh(st7iccclkL) Max

Release
Unit tCPU

Description Period that the ST7 ties ICCCLK low Period during which the External Controller must detect ICCCLK low and tie it to low

Note: The External Controller must tie the ICCCLK line low before a delay of tdh(iccclkL). This delay corresponds to the minimum time needed by the ST7 to release the ICCCLK line.

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5 ICC COMMAND LIBRARY
5.1 IMPLEMENTATION The ICC is a command-based protocol. After a reset, following the sync bit, the ICC Monitor waits for a byte from the External Controller. This byte represents the code of a command. The ST7 executes this command. This may imply other byte exchanges, in both directions. After the ST7 has executed the command, it waits for another one. If the command code does not correspond to any command, the ST7 ignores it and waits for the next one (It reads all the following bytes until it finds a valid command code). T r a n s i t i o n between two ICC commands: After sending or receiving a byte, the ST7 continues to execute the ICC Monitor when ICCCLK is released after the least significant bit. Therefore at the end of an ICC command, as the External Controller must keep the ICCCLK line low until it has prepared the first bit of the next command to be sent, the current ICC command can remain unexecuted by the ST7. To solve this issue, a dummy ICC command (FFh code for example) could be sent after the ICC command to be executed (see "ST7 action" description in section 5.5 on page 23 for more details). ST has defined 3 variants of ICC Monitors, with a different set of commands as shown in Table 1: The "Basic" variant is used in small XFlash devices without a debug module and HDFlash devices to optimize the System Memory size; the "Medium" variant is used in ROM devices to support easy memory dump; the "Advanced" variant is used only in XFlash devices which embed a debug module. To know which variant is used in a device, refer to the implemented ICC features table in the FLASH Programming Quick Reference Manual . Table 1. ICC Monitor Commands
Name Write memory Byte Coding 0xxx xxx xb ICC Monitor Variant Basic Medium Advanced (minimum for ICP) (optimum for ICP) (required for ICD) X X X X X X X 3) X X X

ICC Go 10xxx xxx b Commands Go new context 1) Read memory 110xxx xxb Automatic context saving 2) Notes:

1. If both the ST7 and the External Controller try to read a byte at the same time, they both read FFh (because ICCDATA stays high; see Section 4.2 Bit Exchange Flow for details). This behaviour is used to handle the application reset during ICD management (see section 9.1.2 on page 42 for more details). 2. "Automatic Context Saving" is a method to reduce as much as possible the RAM, stack and CPU resources used by the ICC Monitor. For more details, refer to Section 5.4 Automatic Context Saving. 3. With the "Advanced" variant, the first "10xx xxxx" command after ST7 RESET is a command. Then all other ones are commands.

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5.2 ST7 PRODUCT IDENTIFIER The ST7 product type can be automatically recognized by the External Controller by means of a two byte product identifier. This identifier is stored by the ICC Monitor at the address 0080h/ 0081h when the first command after RESET is executed. The first 3 nibbles of this identifier give the ST7 product while the fourth one gives the System Memory version for this product. ST7 Product identifier0080h [7:0], 0081h [7:4] System Memory version0081h [3:0] 5.3 RAM AND CPU REGISTERS USED BY AN ICC SESSION To execute the ICC Monitor, the ST7 needs to use standard RAM and stack locations, and CPU register resources as shown in Figure 12 and explained in this section. To reduce this impact, the advanced ICC variant includes the "Automatic Context Saving" feature described in Section 5.4 Automatic Context Saving. The ST7 enters the ICC Monitor just like a TRAP interrupt routine: PC, X, A and CC registers are stacked. The and commands perform an IRET (Interrupt Return) instruction. With the command, the External Controller can directly modify the contents of the stack. This way, when a or command is executed, the ST7 core registers can be loaded with any given value. A useful application of this method is entering a certain value in the Program Counter, which makes the ST7 jump to a given program location in ROM or in RAM. Executing a command uses one layer of subroutine calls, i.e. two stack locations. This means that the ICC Monitor could occupy up to seven bytes in the stack (see Figure 12). In ICD, stack occupation is critical. Consequently, the ICC Monitor starts the ICC Session with an automatic context saving: the ST7 unstacks the two last registers (A and CC) and sends them to the Controller. At the end of the session, the command retrieves the registers from the Controller and restacks them before performing the IRET. This way, only five bytes are necessary. The and commands modify the Y register. They also overwrite two zeropage RAM addresses: 0080h and 0081h. The automatic context saving sends the values of these three resources to the External Controller. The command retrieves these values from the Controller before performing the IRET.

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Figure 11. RAM used by an ICC Monitor Execution

RAM S tart@ 0080h 0081h

RAM used by user Application RAM used f or read and write commands RAM used by user Application 2 bytes (basic and medium variants) see note

0100h

U SED STACK

Stack u sed b y ICC monitor Stack used by user Application RAM used by user Application

7 b ytes (basic and medium variants) 5 bytes (advanced variants)

Stack top = 01FFh

RAM End@

Note: With the "Advanced" ICC Monitor variant, addresses 0080h and 0081h are corrupted only after a RESET phase and a command. Then, after a command these two RAM location are no longer corrupted by the ICC Monitor.

Unless otherwise specified, an ICC command modifies all the ST7 core registers except Y but they are restored when exiting the ICC Monitor with a command. Figure 12. Stack Manipulation without Automatic Context Saving
in the Stack ICC Monitor Entry ICC Monitor Subroutine Call

SP PCHicc SP CC0 A0 X0 PCH0 SP PCL0 PCLicc CC0 A0 X0 PCH0 PCL0

SP PCHicc PCLicc CC0 A0 X0 PCH0 PCL0 SP CC1 A1 X1 PCH1 PCL1 SP

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5.4 AUTOMATIC CONTEXT SAVING When using ICC for In-Circuit Debugging (ICD), as few resources as possible have "to be stolen" from the user application in order to be as close as possible to the final software application. "Automatic Context Saving" is a method which has been implemented in the advanced ICC variant in order to support ICD management. When automatic context saving is available, after an ICD abort or a breakpoint, the ST7 starts the ICC Session by sending a 6-byte header (see definition below). Then it waits for the first command code. The command allows the ST7 to exit this ICC Session and receive the 6 bytes previously sent. Following a reset sequence, the ICC Session does not manage automatic context saving (i.e. the command is available instead of the command). Definition: The ST7 sends the contents of its Y register to the External Controller. Then it retrieves the two last register bytes (CC and A) from the stack that were saved when the ST7 entered ICC Monitor (see Figure 13), and sends them to the Controller. Finally, it sends the contents of the 0080h and 0081h zeropage RAM addresses and the current stack pointer value (S). At the end of the ICC Session, the context is restored receiving the 6 bytes previously sent (see Section 5.5.3 Command for more details).
Direction Data ST7 Action Note: Automatic context saving modifies the Y register after sending its previous value to the Controller. Y CC ST7 Controller A Data (0081h) Data (0080h) S

Figure 13. Stack Manipulation with Automatic Context Saving
ICC Monitor Entry Automatic Context Saving ICC Monitor Subroutine Call in the Stack

SP CC0 A0 X0 PCH0 SP PCL0 SP X0 PCH0 PCL0

SP PCHicc PCLicc X0 PCH0 PCL0

SP PCHicc PCLicc X0 PCH0 PCL0 SP X1 PCH1 PCL1 SP

SP returned value

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5.5 COMMAND DESCRIPTIONS 5.5.1 Command The External Controller writes up to 129 adjacent bytes anywhere in the ST7 addressing space.
Direction Data Controller ST7 Command @ @ Code MSByte LSByte N-1 [0xxxxxxxb] Data (@+N-1) Data (@+N-2)
in memory at address @+N-1

...

Data (@)
in memory at address @+N-2

Data write Data write ST7 Action

Data write

in memory at address @

The address transmitted after the command code is the lowest address written. The data bytes are written starting at the highest address. In the table above, N is the number of data bytes written. It must not exceed 129 (N-1=80h). Resource impact (other than the command function): Temporarily needs two stack locations. Modifies the Y register. Overwrites the 0080h and 0081h zeropage RAM addresses. So, make sure that these two addresses are not written to. Caution: To make the ST7 write the last data byte at address "@" of the device, the Controller must release ICCCLK. To do this, the next ICC command or a dummy command (FFh for example) may be sent by the External Controller.

5.5.2 Command The ST7 performs an IRET instruction. This makes it quit the ICC Monitor and execute code at an address which can be located anywhere in memory (i.e. in RAM or in user program memory). This address where the code is executed has to be previously stored in the stack (where the program counter is located) using a command. The CC, A and X registers can be also updated by writing the new value at the corresponding addresses in the stack. After the execution of this command, the ST7 remains in the mode selected by the reset sequence (USER or ICC).
Direction Data ST7 Action Controller ST7 Command Code [10xxx xxx b] Perform IRET instruction

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Resource impact (other than the command function): Temporarily needs two stack locations in addition to the five locations unstacked. Caution: To make the ST7 execute the IRET instruction, the Controller must release ICCCLK.

5.5.3 Command The Controller restores the context previously stored during the automatic context saving. To do this, it fills in the 0080h and 0081h zeropage RAM addresses. Then it fills the S stack pointer (this update allows the Controller application to modify the stack pointer value). Following this stack initialization, the Controller stores two bytes in the stack in order to fill in the A and CC registers at the next interrupt return. Thirdly, it fills in the Y register. Finally, the ST7 performs an IRET instruction. This makes it quit the ICC Monitor and execute code at an address which can be located anywhere in memory (i.e. in RAM or in program memory). This address where the code is executed has to be previously stored into the stack (where the program counter is located) using the command. The X register can be also updated by writing the new value at the corresponding address in the stack. After the execution of this command the ST7 remains in the mode selected by the reset sequence (USER or ICC).
Direction Data Command Data Code (0081h) [10xx xxx xb] Controller ST7 Data (0080h)
in memor y at address 0081h

S

A

CC

Y A & CC Y updated
pushed into the stack

Data write Data write Stack pointer ST7 Action
in memory at address 0080h updated

and IRET instruction is performed

Resource impact (other than the command function): S stack pointer can be modified. Two stack bytes included in the five bytes stacked by the ICC Monitor entry. Caution: To make the ST7 execute the IRET instruction, the Controller must release ICCCLK.

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5.5.4 Command T h e External Controller reads up to 129 adjacent bytes in the ST7, regardless of its addressing space.
Direction Data Controller ST7 Command @ @ Code N-1 MSByte LSByte [110xx xxx b] Data (@+N-1)
in memory at address @+N-1

ST7 Controller Data (@+N-2)
in memory at address @+N-2

...

Data (@) Data read
in memory at address @

Data read Data read ST7 Action

The address transmitted after the command code is the lowest address read. The data bytes are read starting at the highest address. In the table above, N is the number of data bytes read. It can not exceed 129 (N-1=80h). Resource impact (other than the command function): Temporarily needs two stack locations. Modifies the Y register. Overwrites the 0080h and 0081h zeropage RAM addresses. 5.5.5 ICC Command Summary
[0xxxxxxxb]
[10xxxxxxb]

@ MSByte

@ LSByte

N-1

Data(@+N-1)

...

Data(@)

Data(0081h) Data(0080h) [10xxxxxxb] [110xxxxxb] Automatic context saving Legend:
Data sent by the External Controller to the ST7 Data sent by the ST7 to the External Controller

S

A

CC

Y

@ MSByte

@ LSByte

N-1

Data(@+N-1)

...

Data(@)

Y

CC

A

Data(0081h) Data(0080h)

S

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6 ICC MONITOR CODE
When the ST7 enters ICC Mode, the reset vector points to the ICC_monitor_reset routine. For more details on ICD, refer to section 9 on page 39. With XFlash and ROM products, the System Memory is accessible either in USER or ICC Modes. Its address is given in a device-specific table in the Flash Programming Quick Reference Manual. Please also refer to section 5.2 on page 20. The assembler source code of the ICC Monitor is described in APPENDIX 1 on page 51.

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7 USING THE ST7 ICC MONITOR
On all ST7 microcontrollers featuring ICC, an ICC Monitor is included in a write protected memory called System Memory. On XFlash devices (e.g. ST72F264) as well as ROM devices, the System Memory is part of the ST7 standard addressing space. On HDFlash devices (e.g. ST72F521), the basic ICC Monitor is embedded in a System Memory located on a parallel addressing space. Consequently it is not accessible while the user application is running. The ST7 executes this monitor on different occasions. This occurs mainly after the External Controller resets the ST7 in a specific mode called ICC Mode. This is done by driving a specific signal sequence on ICC lines while the RESET pin is pulled low. For devices featuring a Debug Module, the ICC Monitor can also be called after an external abort signal on one of the ICC lines, or after a hardware breakpoint (see Section 9 IN-CIRCUIT DEBUGGING (ICD) for more details). The System Memory also contains a dedicated set of interrupt vectors for ST internal use. When the ST7 enters ICC Mode, this dedicated set of vectors is valid and not those of the USER Mode, i.e. the reset vector refers to the ICC Monitor and not to the user application. On the ST7s featuring the basic ICC Monitor, only 2 commands are available. As explained in Section 5 ICC COMMAND LIBRARY, it can be useful to make the ST7 understand more commands. To do so, the External Controller must upload an upgraded monitor (medium variant for example), write it into the ST7 RAM and then execute it (using the command which is always available). On the ST7s featuring a Debug Module, the embedded monitor is the most advanced one, with all the commands, plus an automatic context saving at the beginning of the ICC Session. Refer to the implemented ICC features table in the FLASH Programming Quick Reference Manual.

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8 BUILDING AN ICC INTERFACE TO A PC PARALLEL PORT
This example shows that ICC protocol can easily be used to communicate between an ST7 and a standard Personal Computer, even if the PC is slower than the MCU or is slowed down by multiprocessing. 8.1 HARDWARE INTERFACE 8.1.1 Basic PC Interface Board The ICC pins cannot be directly connected to a PC parallel port connector due to ICC protocol requirements, e.g. on the External Controller side, bidirectional I/Os can be connected to pullup resistors. So an additional hardware interface is required. This hardware is also necessary to meet the time constraints imposed by the physical protocol. Figure 15 "Example of PC Parallel Port to ICC Connection Interface Board" on page 29 shows an example of a circuit schematic diagram for such an interface board when the application is supplied with a voltage between 4.5V and 5.5V. This schematic can easily be implemented with a few ST components such as the 74HCT (or 74FCT) and 74ACT series (TTL input, CMOS output), ST662A 12V charge pump and transistors. Make sure that these components are compatible with the ST7 logic levels (CMOS input and output). The interface between the External Controller and the ST7 application board is made of up to 7 lines. Figure 14 recommends a standard implementation of these lines with an HE10 type connector. This connector is used by ST Microelectronics software development tools and most of the third party tools. The interface between the External Controller and the PC is made of a standard parallel port interface. Up to 8 output lines, 2 input lines and 8 ground lines are used as shown in Figure 14. Figure 14. Recommended Standard ICC Connectors
PC_vpppulse PC_dataout PC_vpp12v PC_datain PC_vppon PC_pulse

PC_ack

PC_init

GND 1 GND 3 GND 5
12 24 25 13
2)

2 ICCDATA 4 ICCCLK 6 RES ET 8 ICCSEL/VPP 1 0 GN D

1 14 PC_reset

2 15 PC_status

3 16

4 17

5 18

6 19

7 20

8 21

9

10 22 23

11

1)

VDD 7

OSC_CLK 9

GND

PC // Port: Female DB25 (back side view)

HE10 Type ICC Connector

Notes: 1. For the board example defined in this section, the VDD line (7) is used to supply the Controller board. However, this line must be connected to the application VDD with most of STMicroelectronics development tools (for communication level adaptation for example); refer to ST programming tool manual. 2. The OSC_CLK line (9) has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available in the application or if the external clock option is programmed in the option byte.

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Figure 15. Example of PC Parallel Port to ICC Connection Interface Board
VDD VDD
14

74HCT14 ic1 Y A
2 8

r2 4.7K
9

r1

ICC7 VDD ICC4 ICCCLK

4.7K

PC15 PC_status

3

74ACT00 ic5
7

c10 22pF

1

VSS
74HCT14 ic1 Y A
10 1 14

PC25:18 GND

VSS VDD VSS
CLEAR VCC 74HCT14 ic1 A Y
4 2

11

74HCT14 ic1 Y A
12

13

Y A ic1 74HCT14

6

D

PC2 PC_ack

VSS

3

3

Q 74HCT74 ic3A Q CK
4 7

5 6

clk_ack
13

PRESET GND

VDD

74HCT125 ic2

CLEAR
12

D

VDD
4.7K r4 PC4 PC_init

11

VSS

Q 74HCT74 ic3B Q CK
10

9 8

PRESET

clk_release

5 6

Y C A
5

4

VDD
13

VSS

niccclk
12

CLEAR D
11

PC3 PC_dataout

12

74HCT125 ic2 A Y 11 C
13

r5 47

Q 74HCT74 ic4B Q CK
10

9 8

iccdataout

ICC1,3,5,10 GND

VSS

PRESET

VDD
4.7K PC6 PC_pulse

VDD VDD
14 2 2 VCC 14 VCC 1

r3

A
GND 7

C

Y

3

PC11 PC_datain PC14 PC_reset PC7 PC_vppon PC8 PC_vpp12 PC1 PC_vpppulse

Y

A
GND 7

1

ic1 74HCT14

ic2 74HCT125

ICC2 ICCDATA

VSS
ICC Mode entry RESET, CLOCK and VPP management (see Figure 16 and Figure 18 for more details)

VSS
ICC6 RESET ICC8 ICCSEL/VPP ICC9 OSC_CLK

IC Coupling Capacitors c1 c2 c3 c4 c5 1 00nF 100n F 1 00nF 100n F 100nF ic1 ic2 ic3 ic4 ic5

VDD

PC Parallel Port Connector

Recommended Standard ICC Connector (see Figure 14 for more details)

VSS

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8.1.2 Board ICC Mode Entry As described in Section 3 ENTERING ICC Mode, there are two different ICC Mode entry methods. Consequently two hardware implementation examples are proposed:

Section 8.1.2.1 describes a hardware which supports only the controlled window ICC Mode entry (the associated schematic is shown in Figure 16). Section 8.1.2.2 shows a hardware which support both mode entry sequences (controlled and fixed 256TCPU window (the associated schematic is shown in Figure 18).

Both hardware proposals provide the programming voltage capability (VPP) for dual voltage HDFlash. They are also compatible with ICC STMicroelectronics development tool software. Please also refer to the STICK manufacturing files for information on building hardware for devices which supports controlled window ICC mode entry 8.1.2.1 Hardware for Controlled Window ICC Mode Entry The schematic diagram is shown in Figure 16. The PC uses the PC_pulse signal to drive asynchronous pulses on ICCDATA. This signal is used when entering ICC Mode (see section 3.1 on page 10) and also for generating an ABORT external interrupt (see section 9.1 on page 39). The PC uses the PC_vpp12 and PC_vppon to drive three different voltages on the VPP pin.
PC_vpp12 PC_vppon X 0 1 0 1 1 VPP 0V 5V 12V Remarks Applied during ICC Mode entry sequence when ICCSEL pin is used for counter reset Standard voltage to be applied during ICC Mode Programming voltage for dual voltage HDFlash

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Figure 16. Hardware Implementation Example for Controlled Window ICC Mode Entry
c12 220nF
PC8 PC_vpp12
5

VDD
1 2

C1ST662A ic5 C1+ C2C2+

SHDN GND VOUT VCC

8 7 6 5

J1*

HD X&ROM

VDD V SS
t1

74ACT00 ic5

6

3 4

c14=4.7F + c15=100nF

ic9 Coupling Capacitors

c9 100nF

4

VS S
STT3PF30L or BSS110 or VP0610 BSS100 or BS108
ICC8 ICCSEL/VPP

c13 220nF

VDD VS S
VCC 16MHz XTAL ic9
PC7 PC_vppon

SHDN=0VOUT=12V SHDN=1VOUT=5V

VDD
t2 + c16 4.7F

GND

VS S
FOUT
13

VS S
STT3PF30L or BSS110 or VP0610
74HCT125 ic2 A Y 8 C
10

VDD
t3

ICC9 OSC_CLK

74ACT00 ic5

11

12 10

74ACT00 ic5

8

9

9

ICC6 RESET

VSS

PC14 PC_reset

Note: The J1 jumper is used to protect the ICCSEL/VPP pin of XFlash and ROM devices against unwanted 12V. The ST662A input voltage must be sufficient to ensure a VOUT of 11.7V min.

8.1.2.2 Hardware Compatible with all ICC Mode Entry Types The schematic diagram is shown in Figure 18. When the 256 tCPU fixed window ICC Mode entry is used, the rising time of the ST7 RESET pin fixes the start time of the fixed window. Therefore the interface hardware must ensure a sharp edge on this RESET pin, while avoiding any conflict with the output capability of this RESET pin. This is why the proposed hardware is based on a momentary push-pull output (using transistor t3), before switching back in high-impedance mode (after 29s; see Figure 17 for timing analysis). Note also that this hardware implies no capacitance constraint on the RESET pin. ICCDATA is kept low to let the ST7 recognize ICC Mode by using the same circuitry as the Controlled Window ICC Mode Entry. The hardware described in Figure 18 can be also used to enter ICC Mode with a controlled window keeping the PC_vpppulse signal low. The proposed hardware allows different working modes summarized in the table below.
PC_vpp12 PC_vppon PC_vpppulse X 0 0 0 1 1 X 0 1 VPP 0V 5V Remarks Pull-down by NMOS transistor Pull-up by PMOS transistor

0V / 5V Pulsed ICCSEL/VPP pin for fixed 256 tCPU window ICC Mode entry

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P C _ v p p 1 2 PC _ v p p o n P C _ v p p p u l s e 1 1 X

VPP 12V

Remarks Programming voltage for dual voltage HDFlash

Figure 17. Pulse Counter Timings for ICC Mode Entry
PC14 - PC_RESET ic7 COUNTER ic7 CO/ZD ic8 COUNTER ic8 CO/ZD 24s ICC6 - RESET ICC8 - ICCSEL/VPP for fixed 256TCPU windows (PC_vpppulse=1) ICC8 - ICCSEL/VPP for controlled windows (PC_vpppulse=0) 5s 0 38 38 37 1 0 191 191 190 1 0

38 pulses

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Figure 18. Hardware Implementation Example for all ICC Mode Entry Types
c12 220nF
PC8 PC_vpp12
5 1 2 8 7 6 5

J1*

C1C1+ C2C2+ ST662A ic10

SHDN GND VOUT VCC

HD X&ROM

VDD VSS
BSS110 or VP0610 t1 t2 BSS100 or BS108
ICC8 ICCSEL/VPP

74ACT00 ic5

6

3 4

c14=4.7F + c15=100nF

4

c13 220nF

SHDN=0VOUT=12V SHDN=1VOUT=5V

VDD
+ c16 4.7F

VDD
VCC 16MHz XTAL ic9 FOUT GND

V SS VDD VDD
2 1 2 14 5 6 1 7 4 14

VS S
ICC9 OSC_CLK

VS S
CLEAR VCC D
3

74ACT00 ic6

3

5

74ACT00 ic6

6 13

Q 74HCT74 ic4A Q CK
7 4

74ACT00 ic5

11

VS S

12

GND PRESET PC1 PC_vpppulse PC7 PC_vppon 74HC40103 ic7
1 2 4

VSS VDD
16 8

VDD
74ACT00 ic6
9 16

74HC40103 ic8
1 2 4 5 6 7 10 11 12 13

VDD

5 6 7 10 11 12 13

VS S

VCC CLK CLR P0 CO/ZD P1 CI/CE P2 P3 P4 P5 SPE P6 P7 GND APE
8

10 14

12

74ACT00 ic6

11

14

13 3 3

VS S VDD
15 9

VDD
15

9

CLK CLR CO/ZD P0 P1 P2 CI/CE P3 P4 P5 SPE P6 APE GND P7
8

VCC

VDD

VS S VDD

JP12 ST7FLite0 JP23 other ST7
1 2 3

VS S VD D

VS S

IC Coupling Capacitors c6 c7 c8 c9 100nF 100nF 100nF 100nF ic6 ic7 ic8 ic9

10

74ACT00 ic5

BSS110 or VP0610
8

t3
74HCT125 ic2 A Y 8 C
10

9

VS S
9

ICC6 RESET

VS S
PC14 PC_reset

Note: The J1 jumper is used to protect the ICCSEL/VPP pin of XFlash and ROM devices against unwanted 12V.

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8.1.3 Board Communication Interface The following explanations refer to Figure 15 "Example of PC Parallel Port to ICC Connection Interface Board" on page 29. Two cases are distinguished:

When ICCCLK is used to reset the pulse counter when entering ICC Mode During this phase, the ST7 is in RESET state and does not drive ICCCLK. The PC can therefore tie ICCCLK low by applying a pulse on PC_init and can release ICCCLK by applying a pulse on PC_ack. The PC can check the state of ICCCLK by reading PC_status because the ST7 is not driving ICCCLK. When ICCCLK is used as clock to sample ICCDATA The ST7 initializes communication by applying a falling edge on ICCCLK; this falling edge presets the ic3b latch. Consequently, the ic3B latch ties/keeps ICCCLK low through the tristate buffer. The PC is informed of this communication start by reading PC_status. Following this stage, four configurations exist: The PC is receiving bits: First, the PC must make sure that PC_dataout and PC_pulse are high in order to release ICCDATA. Then the PC reads the data on PC_datain and then it releases ICCLCK by applying a pulse on PC_ack to get the next bit. The PC is sending bits: The PC prepares the next bit communication on PC_dataout and then it releases ICCLCK by applying a pulse on PC_ack to be ready for next bit to be sent. The PC is receiving the last bit of a byte and then sends a byte: First, the PC reads the data on PC_datain, then it prepares the next bit on PC_dataout. Finally it releases ICCLCK by applying a pulse on PC_ack to be ready for next bit to be sent. The PC is sending the last bit of a byte and then receives a byte: The PC gets the ICCDATA ready for received byte by setting PC_dataout high. Then it releases ICCLCK by applying a pulse on PC_ack to be ready for next bit to be received.

As long as ICCCLK is in high state, the board releases ICCDATA. PC_data_out is sampled on ICCCLK falling edge. The PC sets PC_dataout high either for a receive or a "send one" operation. It ties PC_dataout low only for a "send zero" operation when ICCCLK is low. F o r a receive operation, the PC reads the bit on PC_data_in. The 3-inverter delay line prevents a glitch from occurring on ICCDATA when the transmission direction switches from a send to a receive operation. 8.1.4 ICCCLK and ICCDATA pull-ups for open-drain communication In the schematic diagram (Figure 15 "Example of PC Parallel Port to ICC Connection Interface Board" on page 29), the two pull-up resistors (r1 and r3) can be replaced by current sources to guarantee the correct voltage levels when the application board contains serial resistors as suggested in the device datasheet (see Figure 19). If the application board does not contain a serial resistor or if the "Other application devices" do not force the ICC lines (floating or pull-up input, open-drain output released...), the interface board will only need a pull-up resistor.

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Figure 19. PC to ICC Interface Board - ICCCLK and ICCDATA Signals
VDD VDD Interface Board 4.7k
ICCCLK (idem for ICCDATA)

Other application devices
>15k

VDD
1.2k 3.9k

Interface Board

Other application devices
>2.7k

330

OR
ST7

i

ICCCLK (idem for ICCDATA)

ST7 Application Board

Application Board

Important Note:

To avoid issues on ICCDATA and ICCCLK high level drives, the application should use these two ST7 pins as outputs. So no serial resistor is needed to isolate the application.

8.1.5 RESET Pull-ups for Open-drain Communication In the schematic diagram (Figure 18), when the jumper is set between 2 and 3, the RESET signal output from the interface board is temporary configured in push-pull output to guarantee accurate timings for 256 tCPU fixed window ICC Mode Entry. During ICC Session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and an application reset circuitry driving more than 5mA at high level (push pull output or pull-up resistor <1K). A Schottky diode can be used in that case to isolate the application RESET circuit. When using a classical RC network with R>1K or a power on RESET management IC with open drain output, no additional components are needed (see Figure 20). If the application RESET circuit drives more than 5mA, the user must ensure that no external RESET is generated by the application during the ICC Session. Figure 20. PC to ICC Interface Board - RESET Signal
Interface Board VDD V DD
100nF RESET

RES E T c ir cuit

Optional Shottky diode (see above chapter)

S T7 VS S
100nF

VS S

Application Board

Important Note:

The user must ensure that the external RESET is not driven (to VDD or VSS) by the application during ICC Session. See above section for more details.

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8.2 ICC SIGNALS AND PC SOFTWARE INTERFACE EXAMPLE This section gives chronogram examples of the ICC interface from the PC side, using the ICC connection interface board shown in Figure 15. To generate and manage the PC_xxx signals described in Figure 15, you can use the MSDOS PC software driver routines (running on Windows95/98) proposed in APPENDIX 2 on page 59.
Note: The following chronograms assume that the PC side is much slower than the ST7.

Figure 21. Controlled Window ICC RESET Phase Timings
PC_vpp12 PC_vpppulse PC_vppon ICCSEL/VPP PC_reset RESET PC_dataout PC_init PC_ack PC_pulse PC_status ICCCLK ICCDATA PC_datain sync bit

Delay applied by the controller 1)

ST7 reaction time 2)

Notes: 1. Delay applied by the controller to be sure that the RESET is taken into account by the device. This delay is needed due to the embedded RESET filter. 2. The controller waits for PC_status line high. This event means that ST7 as released ICCCLK to 1 and then force it back to 0.

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Figure 22. Fixed 256 tCPU Window ICC RESET Phase Timings
PC_vpp12 PC_vpppulse PC_vppon ICCSEL/VPP PC_reset RESET PC_dataout PC_init PC_ack PC_pulse PC_status ICCCLK ICCDATA PC_datain sync bit

Delay applied by the controller 1)

ST7 reaction time 2)

Notes: 1. Delay applied by the controller to be sure that the RESET is taken into account by the device. This delay is needed due to the embedded RESET filter. 2. The controller waits for PC_status line high. This event means that ST7 as released ICCCLK to 1 and then force it back to 0.

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Figure 23. ICC Send Byte Timings (PC ST7)
PC_dataout PC_init PC_ack PC_pulse PC_status ICCCLK ICCDATA PC_datain D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 ST7 reaction time to detect ICCCLK=1 and then force it to 0 D7 D6 D5 D4 D3 D2 D1 D0

Figure 24. ICC Receive Byte Timings (ST7 PC)
PC_dataout PC_init PC_ack PC_pulse PC_status ICCCLK ICCDATA PC_datain D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 ST7 reaction time to detect ICCCLK=1 set ICCDATA line and then force ICCCLK to 0

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9 IN-CIRCUIT DEBUGGING (ICD)
In-Circuit Debugging is the ability to identify and eliminate anomalies in a program stored in a FLASH device using the ICC protocol. This feature is used to design low-cost emulators. ICD can be managed in two different ways depending if the Debug Module (DM) is included in the ST7 device (refer to the implemented ICC features table in the FLASH Programming Quick Reference Manual). This section describes how to easily manage the ICD.
C AUTIONS : 1. As this low-cost emulator controls the ST7 using the ICC protocol, it is not possible to use the two ICC pins (ICCCLK and ICCDATA) in the application. 2. When debugging using ICD, care must be taken in the application software to not access the Debug Module registers and the ICCCLK and ICCDATA I/O control/data registers (masking the bit for example). Otherwise the emulator can be lost.

9.1 ST7 DEVICES WITH DEBUG MODULE Some ST7 devices have an embedded Debug Module. This dedicated hardware and the ICC capability can be used for easy management of:

advanced hardware breakpoints on instruction, address or data instruction steps abort of the running application

Refer to the "Debug Module Reference Manual" for more details. 9.1.1 ICC Monitor Call on DM Request In addition to the dedicated ICC RESET sequence (described in Section 3 ENTERING ICC Mode), when the Debug Module is included in the device, there are two other ways to execute the ICC Monitor and they are described below. With or without the Debug Module, a third way to execute the ICC Monitor is a "Software Breakpoint" managed with a TRAP instruction (see section 9.2 on page 46 for more details). These three methods are available only in USER Mode. "Abort": If the Debug Module has been properly configured, it generates a non-maskable interrupt request as soon as the External Controller drives a falling edge on the ICCDATA pin. The interrupt vector corresponding to this interrupt request is the user software interrupt (TRAP) vector, so the ST7 starts an ICC Session provided the TRAP vector refers to the ICC Monitor. "Hardware Breakpoint": If the Debug Module has been properly configured, it generates a non-maskable interrupt (NMI) request when the ST7 complies with hardware breakpoint conditions. The interrupt vector corresponding to this interrupt request is the user software interrupt (TRAP) vector, so the ST7 starts an ICC Session provided the TRAP vector refers to the ICC Monitor.
Note: Refer to PC software routine examples defined in APPENDIX 2 on page 59 to manage the ICD Abort and Breakpoint capabilities with the ICC connection interface board described in section 8 on page 28.

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9.1.1.1 ICC Monitor called by an ICD Abort When this functionality is enabled in USER Mode (see Section 9.1.2 and Section 9.1.3 for more details), the ST7 jumps into the ICC Monitor when the External Controller drives a falling edge on ICCDATA (Figure 25). As long as the External Controller does not detect an ST7 reaction on ICCCLK, it keeps ICCDATA low. As the ST7 starts with the sync bit, it drives a falling edge on ICCCLK. This causes the External Controller to tie ICCCLK low. Then the External Controller releases ICCDATA. Finally, both devices release ICCCLK, and the system is ready for the first bit exchange. Figure 25. Start of an ICC Session when the ICC Monitor is called by an DM Abort
ST7 Application Interrupt Execution Entry
tdh(st7iccclkL)

ICC Monitor Execution

ST7 Action on ICCCLK Controller Action on I CCCLK
tdh(iccclkHabort)

Release Release

tie low

Release

Tie low Tie low

Release Release

tie low Release
tdh(iccclkL) 3)

ICCCLK
(1) ( 2 ) sync b it 1st bit ST7 sends 1st bit 4)

ICCDATA ST7 Action on ICCDATA C o n t r o l l e r A c t i o n on IC C D A T A
Release Tie low Release

Output 1s t b i t Release

Release

Symbol tdh(st7iccclkL)

Description Period that the ST7 ties ICCCLK low

Min 16 21

Max

Unit tCPU

tdh(iccclkHabort) Period between the release of ICCCLK by the ST7 and an ABORT tdh(iccclkL) Period during which the External Controller must detect ICCCLK low and tie it to low

tdh(st7iccclkL)

Notes: 1. Falling edge generating a non-maskable interrupt for the ST7. 2. Falling edge indicating the start of the ICC Monitor. When ICCCLK is low, ICCDATA is not taken into consideration by the ST7 device. 3. The External Controller must tie the ICCCLK line low before a delay of tdh(iccclkL). This delay corresponds to the minimum time needed by the ST7 to release the ICCCLK line. 4. The ST7 first sends 6 data bytes to the External Controller for automatic context saving.

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9.1.1.2 ICC Monitor called by an DM Hardware Breakpoint When this function is enabled in USER Mode (see Section 9.1.2 and Section 9.1.3 for more details), the ST7 jumps into the ICC Monitor after an internal breakpoint event. As it starts with the sync bit, it drives a falling edge on ICCCLK (see Figure 26). The External Controller detects this falling edge and knows that the ST7 has entered the ICC Monitor. It ties ICCCLK low. Then both devices release ICCCLK and the system is ready for the first bit exchange. Figure 26. Start of ICC Session when the ICC Monitor is called by an DM H/W Breakpoint
Application Execution Interrupt Entry (1)
tdh(st7iccclkL)

ICC Monitor Execution

ST7 Action on ICCCLK Controller Action on ICCCLK ICCCLK

Release Release
tdh(iccclkL) 3)

Tie low Tie low

Release Release

Tie low Tie low

Release Release

(2) sync bit

ICCDATA S T 7 A c t i o n on IC C D A T A C o n t r o l l e r A c t i o n on IC C D A T A
Symbol tdh(st7iccclkL) tdh(iccclkL) Description Period that the ST7 ties ICCCLK low Period during which the External Controller must detect ICCCLK low and tie it to low

1st bit ST7 sends 1st bit 4) Release Release Output 1st bit Release

Min 16

Max

Unit t CPU

tdh(st7iccclkL)

Notes: 1. Event generating a non-maskable interrupt inside the ST7. 2. Falling edge indicating the start of the ICC Monitor. When ICCCLK is low, ICCDATA is not taken into consideration by the ST7 device. 3. The External Controller must tie the ICCCLK line low before a delay of tdh(iccclkL). This delay corresponds to the minimum time needed by the ST7 to release the ICCCLK line. 4. The ST7 first sends 6 data bytes to the External Controller for automatic context saving.

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9.1.1.3 ICC Monitor called simultaneously by two DM events or a TRAP The ST7 jumps into the ICC Monitor after an internal event (software TRAP or hardware breakpoint), but at the same time the External Controller drives a falling edge on ICCDATA (abort). In this case, only one NMI is generated. As the first bit exchange is a dummy, this low level on ICCDATA is not taken into account, and the communication can be initiated as though it had not happened (see case above).
Note: The External Controller cannot know what caused the ICC Monitor to start only by reading the ICC signals. To obtain this information, the DMCSR register must be checked.

9.1.2 ICD Implementation with XFlash devices The chapter describes how to implement the ICD capability with a debugger and an ST7 device including a Debug Module (with Advanced ICC Monitor) and XFlash. In XFlash products, the System Memory is executable in USER Mode so the Advanced ICC Monitor does not need to be copied into the user XFlash area. Before starting In-Circuit Debugging, the debugger must configure the ST7 option bytes using ICP. The watchdog must always be configured as software (hardware watchdog has to be emulated using the WDG control bit of the DMCR register, see the "Debug Module Reference Manual" for more details). How to start ST7 ICD? This procedure is divided into 3 steps and its result in terms of memory organization is shown in Figure 27. Step 1: Debugger replaces the user application RESET and TRAP vectors by the ICC_mode and ICC_monitor_trap addresses located in the System Memory keeping the original vector in the PC memory. These addresses (refer to the system memory addresses table in the FLASH Programming Quick Reference Manual) allow the debugger to manage user RESET and TRAP. Step 2: Using ICP (ICC RESET sequence), the debugger programs the patched user application code in the XFlash. Step 3: To start the debugging phase, the debugger resets the device in USER Mode. This operation will make the ST7 fetch the ICC Monitor. The flowchart shown in Figure 28 describes an example using the PC driver routines defined in APPENDIX 2 on page 59.

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Figure 27. ICD Memory Organization for XFlash Products

REGISTERS 5 BYTES OF STACK ARE USED BYTHE ICC MONITOR

RAM

USER APPLICATION VARIABLES AND STACK USER APPLICATION VARIABLES ADVANCED ICC MONITOR USER APPLICATION CODE

DATA EEPROM SYSTEM MEMORY

XFLASH

USER INTERRUPT VECTORS ICC_monitor_trap@ ICC_mode@

INTERRUPT VECTORS TRAP RESET

Figure 28. ICD Implementation Flowchart

USER RESET sequence USER_Enter

Enter ICC Monitor 1)

ST7 receives ICC command from External Controller

GO 2) ICC_Cmd_Go ICC_Cmd_GoNewContext

READ ICC_Cmd_Read

WRITE 3) ICC_Cmd_Write

USER APPLICATION EXECUTION

AUTOMATIC CONTEXT SAVING ICD_WaitForAbortBreak

Notes: 1. "RESET" and "TRAP" vectors contain ICC Monitor entry points located in System Memory (see "How to start ST7 ICD?" for more details). 2. The command is executed after a RESET sequence. Following a Debug Module "Abort" or "Breakpoint", a command is executed. See section 5 on page 19 for more details. 3. For example, the command can be used to setup the Debug Module (Abort / Breakpoints) by writing to its registers or to write to the stack the address to where the next command must jump.

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How does the debugger control the ST7 ICD after the USER Mode RESET? This procedure is divided into 3 steps. Step 1: The debugger configures the Debug Module using ICC commands. Breakpoints and stepping can be set according to the user requirements. At least the abort function has to be enabled. Step 2: Using ICC commands, the debugger writes the user RESET address (previously stored in the PC memory) in the PCH and PCL stack locations and the CCR reset value (111x1xxxb) in the CCR stack location. Step 3: Start the user application using the ICC command.
Note: When the ST7 executes the ICC Monitor, the debugger can read or write the memory space (peripheral registers, RAM or FLASH) using ICC commands. The CPU registers can be accessed and modified through the stack and the "Automatic Context Saving".

How does the debugger manage the abort and breakpoints? When an abort is initiated by the debugger or a software or hardware breakpoint occurs, the ST7 stops the user application and enters the ICC Monitor program through the patched TRAP vector (refer to section 9.1.1 on page 39 for more details). Following that, the debugger performs 3 steps. Step 1: The debugger receives 6 ICC automatic context saving bytes and stores them into the PC memory (see section 5.4 on page 22). Step 2: The debugger determines why the user application has stopped by reading the DMCSR register bits. The software breakpoint (TRAP instruction) is detected if none of the DMCSR status bits are set. Step 3: The debugger is ready to receive the user debug commands thanks to a Graphical User Interface (GUI). If this command is "program resume", the debugger makes the user application resume using the ICC command (the 6 bytes to be sent are recovered from the ones previously stored in the PC memory). Caution: When an application RESET occurs while the External Controller is waiting for a breakpoint, both sides wait for an ICC byte reception (the ST7 waits for an ICC command and the External Controller waits for 6 automatic context saving bytes). In this case, the debugger and the ST7 resynchronize after getting 6 times FFh on ICCDATA (as FFh is an incorrect command for ST7, it waits for the next one).

How does the debugger manage the user application RESET? The user application RESET can be managed by the ICD if the application makes sure that this RESET never occurs while the ICC Monitor is executed. For the internal watchdog RESET source, this can be done by configuring the software watchdog (see the "Debug Module Reference Manual" for more details). For the other sources, a RESET is not allowed while the ICC Monitor is executed.

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9.1.3 ICD Implementation with HDFlash Devices This section describes how to implement the ICD capability with a debugger and an ST7 device including a Debug Module (with Basic ICC) and HDFlash. In HDFlash products, the System Memory is not accessible in USER Mode so the Advanced ICC Monitor must be copied into the user HDFlash area. Consequently when debugging HDFlash products, the memory size available for the user application is reduced by approximately 256-bytes. The flowchart shown in Figure 28 "ICD Implementation Flowchart" on page 43 describes an ICD implementation example using PC driver routines defined in APPENDIX 2 on page 59. How to start ST7 ICD? This procedure is divided into 4 steps and its result in terms of memory organization is shown in Figure 29. Step 1: The debugger adds the "Advanced ICC Monitor" to the user application code. Step 2: The debugger replaces the user application RESET and TRAP vectors by the ICC_mode and ICC_monitor_trap addresses located in the advanced ICC Monitor keeping the original vector in the PC memory. Step 3: Using ICP (ICC RESET sequence), the debugger programs the patched user application code and ICC Monitor in the HDFlash. Step 4: To start the debugging phase, the debugger resets the device in USER Mode. This operation will make the ST7 fetch the ICC Monitor. Debugging with ICD For information on how the debugger controls the ST7 ICD after the USER Mode RESET, how it manages the abort and breakpoints and how it manages the user application RESET, please refer to Section 9.1.2, which applies both to HDFlash and XFlash. Figure 29. ICD Memory Organization for HDFlash Products

REGISTERS 5 BYTES OF STACK ARE USED BYTHE ICC MONITOR

RAM

USER APPLICATION VARIABLES AND STACK ADVANCED ICC MONITOR USER APPLICATION CODE

EMBEDDED COMMANDS SYSTEM MEMORY BASIC ICC MONITOR Test Interrupt vectors ICC_mode@

HDFLASH

USER INTERRUPT VECTORS ICC_monitor_trap@ ICC_mode@

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9.2 ST7 DEVICES WITHOUT DEBUG MODULE If the ST7 device does not include a Debug Module but has XFlash, the ICC capability handles a simple form of ICD with only software breakpoints on instruction. The ICD implementation procedure is the same as the one described in section 9.1.3 on page 45 except the fact that the only way to stop the user application is a software breakpoint or a device RESET. Software Breakpoints To make a software breakpoint, the instruction where the ST7 must stop is patched with a TRAP instruction to enter the ICC Monitor. As this patch must be done byte by byte, this ICD can be implemented only in devices that support byte by byte erasing/programming (i.e. XFlash).
Note: Software breakpoints can be implemented in a debugger developed for ST7 devices with a Debug Module.

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9.3 ICD GENERAL LIMITATIONS This section describes the limitations for an ICD implementation.

ICCCLK and ICCDATA pins are reserved and cannot be used by the application. Therefore, in the user application software, associated register bits in the port registers MUST always be masked to avoid conflict with the debugger. Real time emulation is not available for RESET and TRAP events because the associated vectors are replaced with the ICC Monitor vectors in the user application. The user RESET and TRAP routines are executed following a debugger action. The hardware watchdog option can not be used because the time spent in the ICC Monitor is unpredictable. This function is emulated by the debugger with a software watchdog. User application RESET source is not supported by the ICD unless the application guarantees that the external RESET never happens while the ICC Monitor is running. For HDFlash devices, the ICC Monitor must be copied in the user FLASH memory area because the System Memory is not accessible in USER Mode. The memory size available for the user application is then reduced. Each HDFlash device provides only limited ICD capabilities because its FLASH memory can support only limited programming/erasing cycles.

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10 IN-CIRCUIT TESTING (ICT)
10.1 OVERVIEW In-Circuit Testing (ICT) is a flexible method of performing production test routines that can be easily modified and extended without affecting the content of the FLASH program memory. This method uses the ICC protocol to download and execute the test program. The flowchart shown in Figure 30 describes an ICT implementation using PC driver routines defined in APPENDIX 2 on page 59. This implementation is valid for all ST7 devices which include ICC as only the basic ICC version is required to execute this program. Figure 30. ICT Implementation Flowchart
ICC Mode RESET sequence ICC_Enter_CtrlWin ICC_Enter_FixedWin

ST7 receives ICC command from External Controller

GO ICC_Cmd_Go

WRITE

1)

ICC_Cmd_Write

TEST PROGRAM EXECUTION

ICC_receive ICC_send

"ICC_xxxxx" are the C library routines to be used for implementation

Note: 1. For example the "write" command can be used to write the test program in RAM and to write in the stack the address to where the next command must jump.

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10.2 ICT EXAMPLE: INTERRUPT VECTOR 8-BIT CHECKSUM The following ICT example describes how to implement a test program using the ICC interface board (see section 8 on page 28) and the PC software driver described in APPENDIX 2 on page 59. The purpose of this test program is to compute the 8-bit checksum of the user interrupt vector table (address FFF0h to FFFFh). The PC software can be summarized with the following C code:
// To make the ST7 enter ICC Mode // or ICC_Enter_FixedWin(); ICC_Cmd_Write(); // => Download the test program into RAM from address 0090h ICC_Cmd_Write(); // => Set the address 0090h at the top of the stack ICC_Cmd_Go(); // Start the execution of the test program CheckSum = ICC_receive(); // Get the result of the test program via ICC ICC_Enter_CtrlWin(Nb_Pulse);

The ST7 test program to be downloaded is shown below. The opcode bytes are downloaded sequentially into the RAM from 0090h to 00C7h using the ICC_Cmd_Write() driver routine. These bytes are marked in bold.
st7/ ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * * ; TITLE: ICTexample.asm ; AUTHOR: CMG_MCD Application Team ; DESCRIPTION: ICT example (interrupt vector 8-bit checksum) ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * * TITLE BYTES "ICTexample.asm"

; ST7 Product ICC I/O Definition ;---------------------------------------------0008 0009 0000 0000 PxDR EQU $08 ; I/O port register definition for ICC management PxDDR EQU $09 #DEFINE ICCCLK 0 ; Bit definitions for ICCCLK and #DEFINE ICCDATA 1 ; ICCDATA pin allocation ; Test program variable definition ;-------------------------------------------008F 008E 008D PTRL EQU $8F PTRH EQU $8E RES EQU $8D WORDS SEGMENT ; Two byte pointer to access the ; interrupt vector table ; Checksum of the interrupt vector table WORD AT 0090-00FF 'Ram'

.Test_Program ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * * 0090 0092 0094 0096 0098 009A 009D 009F 00A0 A6FF B78E 3F8F AE10 3F8D 92D68E BB8D 5A 2AF8 LD LD CLR LD CLR LD ADD DEC JRPL A,#$FF PTRH,A PTRL X,#16 RES A,([PTRH.w],X) A,RES X loop ; Set the interrupt vector start ; address (FF00h) in PTR pointer ; Init X register as byte counter ; Init the checksum value to 00h ; ; ; ; Get a interrupt vector table byte Compute the checksum Next byte to read & check if FF00h address has been already reached

.loop

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00A2 B68D 00A4 AD02 00A6 20FE

.end

LD A,RES CALLR ICC_send_byte JRT end

; Get the checksum result ; and send it via ICC

.ICC_send_byte ; LOW LEVEL ICC PROTOCOL SUBROUTINE ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * * ; ICC SEND subroutine used by the ST7 to send a byte on ICCDATA ; before start and after end of subroutine: ; ICCCLK = 1 as floating input ; ICCDATA as floating input ; before start of subroutine: ; Acc A = byte to send ; after end of subroutine: ; X=0 ; ICCCLK levels: 0 for 17 Tcpu ; 1 for 43 Tcpu minimum 00A8 AE08 00AA 1209 00AC 00AE 00AF 00B1 00B3 00B4 00B5 00B7 00B9 00BA 00BB 00BC 00BD 00BF 00C2 00C3 00C5 00C7 1208 49 2502 1308 4D 4D 1108 1009 4D 4D 4D 4D 1109 0108FD 5A 26E7 1309 81 LD X,#$08 ; X = BitCounter BSET PxDDR,#1 ; Define ICCDATA as open-drain output .icc_s1 BSET PxDR, #1 ; ICCDATA=1 because tying line to 0 is faster RLC A ; Copy bit to transmit into carry flag JRC icc_s2 ; Test bit to transmit BRES PxDR, #1 ; If "0" set ICCDATA = 0 .icc_s2 TNZ A ; Dummy instructions to get a 2x3Tcpu delay TNZ A ; to insure the ICCDATA level BRES PxDR ,#0 ; Because BSET/BRES ICCDATA may set ICCCLK DR BSET PxDDR,#0 ; => ICCCLK output = 0 TNZ A ; Dummy instructions to get a 4x3Tcpu delay TNZ A ; for External Controller reaction time TNZ A TNZ A BRES PxDDR,#0 ; Release ICCCLK after 5 Tcpu .icc_s3 BTJF PxDR ,#0,icc_s3 ; Wait until ICCCLK = 1 DEC X ; Ext. Controller already detected 1 (TTL input) JRNE icc_s1 ; Check if the whole byte is sent BRES PxDDR,#1 ; If yes, define ICCDATA as floating input RET ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * * END

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APPENDIX 1 (ICC MONITOR ASSEMBLER CODE)
The "ICC CONFIGURATION", "ASSEMBLER DEFINITIONS", "INTERRUPT VECTORS" and "SEGMENT" definitions are defined for each ST7 product (bold part of the software).
Note: The ICD_Available and No_Basic_ICC constant identifiers define a scale of different ICC Monitors, from the basic to the advanced one (see Table 1, "ICC Monitor Commands," on page 19).
st7/ ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * **** ; MODULE: icc_drv.asm ; AUTHOR: CMG_MCD Application Team ; UPDATE: July 3rd, 2001 ; DESCRIPTION: Generic In-Circuit Communication protocol ; to be adapted to each device: fill in the product specific ; informations (such as addresses, bit location, vectors...) ; The example given in this file refers to the ST72F264 product. ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * **** ; ICC Command Definitions ; --------------------------------------------------------------------------; Command Name | Command Definition ; --------------------------------------------------------------------------; Write memory | Write N memory bytes into ST7 addressing space ; | starting at MSB@:LSB@ address ; | MSbit first and MSbyte first ; --------------------------------------------------------------------------; Go | Perform an "IRET" instruction (die Id is stored at 0080h) ; --------------------------------------------------------------------------; Go new context | a) Fill in the 2 RAM addresses used by this ; | program as an address buffer ; | b) Update stack pointer value ; | c) Store 2 bytes in the stack in order to fill in the ; | A and CC registers at the next "IRET" instruction ; | d) Fill in the Y register ; | e) Perform an "IRET" instruction ; --------------------------------------------------------------------------; Read memory | Read N memory bytes from ST7 addressing space ; | starting at MSB@:LSB@ address ; | MSbit first and MSbyte first ; --------------------------------------------------------------------------; Automatic | ST7 send sequentially Y, CC, A, 0081h, 0080h, S when ; Context saving | entering advanced ICC Monitor following an ABORT or BKPT ; --------------------------------------------------------------------------; If the ST7 features ICD, the command is implemented ; instead of the command when entering the monitor with a breakpoint ; or an abort. ; ICC Command Protocol ; --------------------------------------------------------------------------; Command Name | Coding | Command Description ; | (cmd) | ; --------------------------------------------------------------------------; Write memory | 0xxxxxxx | >cmd >MSB@ >LSB@ >N-1 ; | | >D(@+N-1) >D(@+N-2) ... >D(@) ; Go | 10xxxxxx | >cmd ; Go New Context | 10xxxxxx | >cmd >D(buf@+1) >D(buf@) >A >CC >Y ; Read memory | 110xxxxx | >cmd >MSB@ >LSB@ >N-1 ; | | | 111xxxxx | >cmd

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; --------------------------------------------------------------------------; Legend: ; ; ; ; N > < @ buf@ is the number of bytes to send or receive ST7 receives from External Controller ST7 sends to External Controller is the address stored in the address buffer is the address of this buffer (the address of its LSByte)

; ICC used RAM space: 2 bytes (ADDRBUF and ADDRBUF+1) ; ICC used stack space: ; * minimum 5 bytes (CC, A, X, PCH, PCL at interrupt call) ; * no more than 5 bytes if the ST7 features ICD ; * 2 bytes when executing a command (1 call) ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * **** ;XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX ; ICC CONFIGURATION ;XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX ; --------------------------------------------#DEFINE ICD_Available 1 ; | 1 | 0 | 0 | #DEFINE Not_Basic_ICC 1 ; | 1 | 1 | 0 | ; --------------------------------------------; Write memory | x | x | x | (x <=> command available) ; Go |x|x|x| ; Go new context |x| | | ; Read memory |x|x| | ; Automatic context saving | x | | | ; --------------------------------------------; Software size [bytes] | 219 | 150 | 90 | ; Vector size [bytes] | 36 | 36 | 36 | ; --------------------------------------------TITLE "icc_drv.asm" ;XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX ; ASSEMBLER DEFINITIONS ;XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX BYTES ; ST7 Product Definition -----------------------------------------------------#DEFINE RAMBEG $80 ; RAM Start address definition #DEFINE DEVICE_ID #DEFINE ADDRBUF $8251 $80 ; ST72F264 Die identifier + System Memory version ; Address buffer for and ; commands (MUST ALWAYS BE $0080)

; ST7 Product ICC I/O Definition ---------------------------------------------PxDR EQU $08 PxDDR EQU $09 #DEFINE ICCCLK 0 #DEFINE ICCDATA 1 ; I/O port register definition for ICC management ; Bit definitions for ICCCLK and ICCDATA pin allocation

; ST7 Product ICD Definition -------------------------------------------------#IF {ICD_Available} DMCR EQU $60 ; ICD registers description if ICD available DMCSR EQU $61 ; (refer to product datasheet for more details) #DEFINE MTR 6 ; MTR bit position in the DMCR

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#DEFINE RST #ENDIF

4

; RST bit position in the DMCSR

;XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX ; ASSEMBLER SOFTWARE ;XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX WORDS SEGMENT byte at DF00-DFDB 'ICC_monitor_seg' ; ICC System Memory for instance ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * **** #IF {Not_Basic_ICC} .ICC_send_byte ; LOW LEVEL ICC PROTOCOL SUBROUTINE ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * **** ; ICC SEND subroutine used by the ST7 to send a byte on ICCDATA ; ; ; ; ; ; ; ; ; LD BSET .icc_s1 BSET RLC JRC BRES .icc_s2 TNZ TNZ BRES BSET TNZ TNZ TNZ TNZ BRES before start and after end of subroutine: ICCCLK = 1 as floating input ICCDATA as floating input before start of subroutine: Acc A = byte to send after end of subroutine: X=0 ICCCLK levels: 0 for 17 Tcpu 1 for 43 Tcpu minimum ; X = BitCounter ; Define ICCDATA as open-drain output ; ; ; ; ; ; ; ; ; ; ICCDATA=1 because tying line to 0 is faster Copy bit to transmit into carry flag Test bit to transmit If "0" set ICCDATA = 0 Dummy instructions to get a 2 x 3 Tcpu delay to insure the ICCDATA level Because BSET/BRES ICCDATA may set ICCCLK DR => ICCCLK output = 0 Dummy instructions to get a 4 x 3 Tcpu delay for External Controller reaction time

X,#$08 PxDDR,#ICCDATA PxDR, #ICCDATA A icc_s2 PxDR, #ICCDATA A A PxDR ,#ICCCLK PxDDR,#ICCCLK A A A A PxDDR,#ICCCLK

; Release ICCCLK after 5 Tcpu ; Wait until ICCCLK = 1 ; Ext. Controller already detected 1 (TTL input) ; Check if the whole byte is sent ; If yes, define ICCDATA as floating input

.icc_s3 BTJF PxDR ,#ICCCLK,icc_s3 DEC JRNE BRES JRH RET #ENDIF X icc_s1 PxDDR,#ICCDATA

#IF {ICD_Available} ;++++++++++++++++++++++++++++++ ICC_y_sent ; Return when Y auto saving context +++ #ENDIF ;+++++++++++++++++++++++++++++++++++++++++++

; Preprocessing for ICC_send_byte routine

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;++++++++++++++++++++++++++++++++++++++++++++++++ ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * **** .ICC_monitor_reset ; ICC reset vector destination ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * **** ; ICC Communication * External Controller = TTL INPUT / CMOS OUTPUT (HCT) ; * ST7 ICCCLK/ICCDATA pins = CMOS INPUT / CMOS OUTPUT ; I/O Configuration: ; ICCCLK as floating input (std default reset config.) ; ICCDATA as floating input (std default reset config.) BTJF PxDR, #ICCDATA, ICC_mode ; To enter ICC Mode, ICCDATA must be kept ; low after reset

.ST_Internal_Use CLR CLR CLR JP A X Y RAMBEG

.ICC_mode LD A,S SUB A,#5 LD S,A

; To init the Stack for future command

;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * **** .ICC_monitor_trap ; ICC trap vector destination ; ICC Monitor MAIN ROUTINE ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * **** BSET #IF {ICD_Available} ;++++++++++++++++++++++++++++++ DMCR, #MTR ; The ST7 is executing ICC Monitor ++++ #ENDIF ;+++++++++++++++++++++++++++++++++++++++++++ ICCCLK tied to 0 for 16 Tcpu

; ---------------------------; dummy bit synchronization: ; ---------------------------.synchro1 BTJF BRES BSET MUL

PxDR ,#ICCCLK,synchro1 ; Wait until ICCCLK = 1 ; Ext. Controller already detected 1 (TTL input) PxDR ,#ICCCLK PxDDR,#ICCCLK ; => ICCCLK output = 0 X,A ; Dummy instruction to get a tempo to be sure ; that Ext. Controller has detected 0 on ICCCLK ; Clear Half Carry bit for auto-context saving

BRES PxDDR,#ICCCLK ; Release ICCCLK .synchro2 BTJF PxDR ,#ICCCLK,synchro2 ; Wait until ICCCLK = 1 ; Ext. Controller already detected 1 (TTL input) #IF {ICD_Available} ;++++++++++ ; Automatic context saving +++ ;++++++++++++++++++++++++++++++ BTJT DMCSR,#RST,ICC_do_cmd ; No automatic saving context after reset

.ICC_autosave LD A,#$0F

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ADD A,#1 LD A,Y JRT ICC_send_byte .ICC_y_sent MUL X,A POP POP CALLR LD CALLR LD CALLR LD CALLR A Y ICC_send_byte A, Y ICC_send_byte A,{ADDRBUF+1} ICC_send_byte A,ADDRBUF ICC_send_byte

; Set half-carry flag ; Send Y reg. content to External Controller ; Clear half-carry flag ; Two sequential POP to use only 5 byte stack ; Send CC reg. previous content ; Send Acc previous content ; Send previous value of address buffer MSByte ; Send previous value of address buffer LSByte ; Send SP reg. previous value

LD A,S CALLR ICC_send_byte

#ENDIF ; Preprocessing for Automatic context saving ;+++++++++++++++++++++++++++++++++++++++++++++++++++ ; ---------------------------; command interpreter ; ---------------------------.ICC_do_cmd CALLR ICC_receive_byte RLC JRNC RLC JRNC RLC JRNC JRT A ICC_cmd_write A ICC_cmd_go ; Receive command from External Controller ; cmd="0xxxxxxx": command ; cmd="10xxxxxx": or cmd

#IF {Not_Basic_ICC} ;++++++++++++++++++++++++++++++++++++++++++++++++++ A ;+++ ICC_cmd_read ; cmd="110xxxxx": command +++ #ENDIF ;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ICC_do_cmd ; unknown command => Execute the next one

;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * **** .ICC_receive_byte ; LOW LEVEL ICC PROTOCOL SUBROUTINE ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * **** ; ICC RECEIVE subroutine used by the ST7 to receive a byte from ICCDATA pin ; before start and after end of subroutine: ; ICCCLK = 1 as floating input ; ICCDATA as floating input ; bit ICCCLK on Port x Data Register cleared ; after end of subroutine: ; Acc A = byte received ; X=0 ; ICCCLK levels: 0 for 28 Tcpu ; (delay time from ICCCLK low to ICCDATA valid = 15Tcpu) ; 1 for 16 Tcpu minimum LD .icc_r1 X,#$08 ; X = BitCounter

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BSET TNZ TNZ TNZ TNZ TNZ

PxDDR,#ICCCLK A A A A A

; => ICCCLK output = 0 ; Dummy instructions to get a 5 x 3 Tcpu delay ; to ensure that Ext. Controller has set the data

BTJF PxDR,#ICCDATA,icc_r2 .icc_r2 RLC A BRES PxDDR,#ICCCLK

; Update carry flag according to ICCDATA ; Save carry flag into Acc A ; Define ICCCLK as floating input ; Wait until ICCCLK = 1 ; Check if the whole byte is received

.icc_r3 BTJF PxDR ,#ICCCLK,icc_r3 DEC JRNE JRH X icc_r1

#IF {ICD_Available} ;++++++++++++++++++++++++++++++++++++++++++++++++++ ICC_y_received ; In this case, ICC_receive_byte is not a +++ ; subroutine but a mere sequence of instructions +++ #ENDIF ;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

RET ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * **** ; ICC COMMANDS LIBRARY ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * **** ; ---------------------------------------------------.ICC_cmd_write ; command execution ; ---------------------------------------------------LD #IF {Not_Basic_ICC} ;++++++++++++++++++++++++++++++++++++++++++ Y, #$FF ; Y reg is used as R/W cmd indicator: W=> Y=FFh +++ #ENDIF ;+++++++++++++++++++++++++++++++++++++++++++++++++++++++ ; Receive MSB@ from External Controller ; Store it into MSB@ ; Receive LSB@ from External Controller ; Store it into LSB@ ; Receive nb-1 of bytes to read or write ; (this number must be in the range 0..128) #IF {Not_Basic_ICC} ;+++++++++++++++++++++++++++++++++++++++++++++ Y ; Check if it is a read or write cmd +++ ICC_cmd_read_start ; R=> Y=00h / W=> Y=FFh +++ #ENDIF ;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Y,A ; Store into Y the number of bytes to write ; Receive data byte from External Controller ; Write data byte into the memory ; Next data byte

.ICC_cmd_rw CALLR ICC_receive_byte LD ADDRBUF,A CALLR ICC_receive_byte LD {ADDRBUF+1},A CALLR ICC_receive_byte TNZ JREQ LD

.ICC_cmd_write_cont CALLR ICC_receive_byte LD ([ADDRBUF.w],Y),A DEC Y JRPL ICC_cmd_write_cont .ICC_do_cmd2 JRT ICC_do_cmd

; Execute next command

; ---------------------------------------------------.ICC_cmd_go ; command execution

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; ---------------------------------------------------LD LD LD LD A,#DEVICE_ID.h {ADDRBUF},A A,#DEVICE_ID.l {ADDRBUF+1},A ; ; ; ; ; When exiting monitor after RESET: The device identifier is stored into the RAM at a fixed address for all products (0080h/0081h). This information allows to have dev. tools able to identify automatically the device.

#IF {ICD_Available} ;++++++++++ ; command +++ ;++++++++++++++++++++++++++++++ BTJT DMCSR,#RST,ICC_go ; Go new context if monitor not from RESET ; ; ; ; ; Receive address buffer MSByte from External Controller Store it at the right place in RAM Receive address buffer LSByte Store it at the right place in RAM

.ICC_go_newctx CALLR ICC_receive_byte LD {ADDRBUF+1},A CALLR ICC_receive_byte LD ADDRBUF,A CALLR ICC_receive_byte LD S, A CALLR ICC_receive_byte LD Y, A CALLR ICC_receive_byte PUSH Y PUSH A LD A,#1 ADD A,#$0F JRT ICC_receive_byte .ICC_y_received LD Y, A

; Receive new stack pointer (must be ; the same as the one send during ; automatic context saving for normal operation) ; Receive Acc future content ; Receive CC reg. future content ; Two sequential PUSH to use only 5 byte stack

; Set half-carry flag ; Receive Y reg. future content

#ENDIF ; Preprocessing for command ;+++++++++++++++++++++++++++++++++++++++++++++++++++ .ICC_go IRET ; Restore A, X, CC ; Execute selected address or Continue

; ---------------------------------------------------#IF {Not_Basic_ICC} .ICC_cmd_read ; command execution ; ---------------------------------------------------CLR Y JRT ICC_cmd_rw .ICC_cmd_read_start LD Y,A .ICC_cmd_read_cont LD A,([ADDRBUF.w],Y) CALL ICC_send_byte DEC Y JRPL ICC_cmd_read_cont JRT ICC_do_cmd2 ; Y reg is used as R/W cmd indicator: R=> Y=00h ; in ICC_cmd_rw ; Store into Y the number of bytes to read ; Read data byte from memory ; Send data byte to External Controller ; Next data byte ; Execute next command

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#ENDIF ;XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX REPEAT BYTE $00 val CEQU {$DFDC-*} UNTIL {val eq $0} ; ; ; ; Fill unused area with 00h

* * ** * ** * ** * ** * ** * ***** * SYSTEM AND INTERRUPT VECTORS * * * ** * ** * ** * ** * ** * *****

;* * *** ICD TRAP VECTOR * * ** * ** * ** * ** * ** * **** SEGMENT byte at DFDC-DFDD 'icd trap vector' DC.W ICC_monitor_trap ; Used for ICD management

;* * *** ROMDUMP VECTORS * * ** * ** * ** * ** * ** * **** SEGMENT byte at DFDE-DFDF 'romdump vector' DC.W $FFFF ; ST Internal use only

;* * *** INTERRUPT VECTORS * * ** * ** * ** * ** * ** * ** SEGMENT byte at DFE0-DFFF 'interrupt vectors' DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W DC.W END ;XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX {RAMBEG} {RAMBEG} {RAMBEG} {RAMBEG} {RAMBEG} {RAMBEG} {RAMBEG} {RAMBEG} {RAMBEG} {RAMBEG} {RAMBEG} {RAMBEG} {RAMBEG} {RAMBEG} {RAMBEG} ICC_monitor_reset ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ITUSER13 ITUSER12 ITUSER11 ITUSER10 ITUSER9 ITUSER8 ITUSER7 ITUSER6 ITUSER5 ITUSER4 ITUSER3 ITUSER2 ITUSER1 ITUSER0 TRAP RESET xxE0-xxE1h xxE2-xxE3h xxE4-xxE5h xxE6-xxE7h xxE8-xxE9h xxEA-xxEBh xxEC-xxEDh xxEE-xxEFh xxF0-xxF1h xxF2-xxF3h xxF4-xxF5h xxF6-xxF7h xxF8-xxF9h xxFA-xxFBh xxFC-xxFDh xxFE-xxFFh

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APPENDIX 2 (ICC PC SOFTWARE FOR DOS AND WINDOWS 95/98)
Example of PC DOS software routines for driving the ICC board described in Section 8. Note: These drivers cannot be used with Windows NT/2000/XP since these operating systems do not allow a user application to directly access the parallel port. Hence the calls to inportb(), outportb() in the software provided would not be accepted.
//* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * *** // MODULE icc_sw.c // AUTHOR CMG_MCD Application Team #define UPDATE "19/11/01" // DESCRIPTION: PC Parrallel Port interface for ST7 In-Circuit Commmunication // Compatible with ST7 Toolchain: programmer... //* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * *** #include #include #include #include #include #include "memtable.h" // Include file defining memtable (data to be downloaded)

//* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * *** // PC PARALLEL PORT & ICC INTERFACE DEFINITION //* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * *** // PC Parallel Port Definition . . .. . .. . .. . .. . .. . .. . .. . .. . .... // Pin Name Logic I/O Byte Bit // -------------------------------------#define PC_vpppulse 0 // 1 Strobe -1 O Ctl 0 #define PC_ack 0 // 2 D0 1 O Data 0 #define PC_dataout 1 // 3 D1 1 O Data 1 #define PC_init 2 // 4 D2 1 O Data 2 // 5 D3 1 O Data 3 #define PC_pulse 4 // 6 D4 1 O Data 4 #define PC_vppon 5 // 7 D5 1 O Data 5 #define PC_vpp12 6 // 8 D6 1 O Data 6 // 9 D7 1 O Data 7 // 10 Ack -1 I Stat 6 #define PC_datain 7 // 11 Busy -1 I Stat 7 // 12 Pe 1 I Stat 5 // 13 Select 1 I Stat 4 #define PC_reset 1 // 14 Auto feed-1 O Ctl 1 #define PC_status 3 // 15 Error -1 I Stat 3 // 16 Int +1 O Ctl 2 // 17 Select -1 O Ctl 3 // 18..25 GND // ---------------------------------------------------// Register address #define outdata(c) outportb(0x378,(c)) // Input status register. . .378h #define outctrl(c) outportb(0x37A,(c)) // Output control register...37Ah #define instatus() inportb(0x379) // Input status register. . .379h // --------------------------------------------------#define PC_Datain #define PC_Status ( (instatus()>>PC_datain) & 1 ) ( (instatus()>>PC_status) & 1 )

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//* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * *** // BASIC PC PARALLEL PORT INTERFACE ROUTINES //* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * *** /* ---------------------------------------------------------------------------ROUTINE NAME : SetD & ResD INPUT/OUTPUT : Bit to be modified / None DESCRIPTION : Set or reset a data PC parallel port pins. -----------------------------------------------------------------------------*/ unsigned char data; // This global variable contains PC parallel port image. void SetD (unsigned char bit) { data |= (1 << bit); outdata(data); } void ResD (unsigned char bit) { data &= ~(1 << bit); outdata(data); } /* ---------------------------------------------------------------------------ROUTINE NAME : SetC & ResC INPUT/OUTPUT : Bit to be modified / None DESCRIPTION : Set or reset a control PC parallel port pins. -----------------------------------------------------------------------------*/ unsigned char ctrl; // This global variable contains the control PC parallel port image. void SetC (unsigned char bit) { ctrl |= (1 << bit); outctrl(ctrl); } void ResC (unsigned char bit) { ctrl &= ~(1 << bit); outctrl(ctrl); } /* ---------------------------------------------------------------------------ROUTINE NAME : VPP_Voltage INPUT/OUTPUT : Input voltage (0V ,5V, 12V or other=pulses) / None DESCRIPTION : Set the VPP/ICCSEL pin configuration. -----------------------------------------------------------------------------*/ void VPP_Voltage (unsigned char voltage) { switch (voltage) { case 12: /* Vpp=12V -----------------------------*/ SetD(PC_vppon); /* and connect to VPP */ SetC(PC_vpppulse); SetD(PC_vpp12); /* 12V output from ST662A */ break; case 5: /* Vpp=5V -------------------------------*/ ResD(PC_vpp12); /* 5V output from ST662A */ SetC(PC_vpppulse); SetD(PC_vppon); /* and connect from VPP */ break; case 0: /* Vpp=0V -------------------------------*/ ResD(PC_vpp12); /* 5V output from ST662A */ ResD(PC_vppon); /* and disconnect from VPP */ break; default: /* Vpp pulse for Fixed 256Tcpu Window --*/ ResC(PC_vpp12); /* 5V output from ST662A */ ResC(PC_vpppulse); /* when RESET rising edge */

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} } //* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * *** // ICC COMMUNICATION ROUTINES //* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * *** /* ---------------------------------------------------------------------------ROUTINE NAME : ICC_send INPUT/OUTPUT : Byte to be sent / None DESCRIPTION : ICC send routine via PC parallel port. -----------------------------------------------------------------------------*/ void ICC_send (unsigned char byte) { unsigned char i; for (i=0; i<8; i++) { if (byte & 0x80) SetD(PC_dataout); else ResD(PC_dataout); byte = byte << 1; SetD(PC_ack); ResD(PC_ack); while (!PC_Status) { if (kbhit()) exit(1); } } SetD(PC_dataout); // Send bit by bit the byte to be sent // Release ICCDATA line (data bit to transmit) // Force ICCDATA line to 0 (data bit to transmit) // Next bit to be send is the MSB // To release ICCCLK to for next communication bit // Wait for PC_status line high (meaning that ST7 as // released ICCCLK to 1 and then force it back to 0) // If key pressed then exit // Release ICCDATA line

SetD(PC_vppon); /* and pulse generation on VPP */ break;

}

/* ---------------------------------------------------------------------------ROUTINE NAME : ICC_receive INPUT/OUTPUT : None / Received byte DESCRIPTION : ICC receive routine via PC parallel port. -----------------------------------------------------------------------------*/ unsigned char ICC_receive (void) { unsigned char i, byte = 0; for (i=0; i<8; i++) { SetD(PC_ack); ResD(PC_ack); byte = byte << 1; while (!PC_Status) { if (kbhit()) exit(1); } if (PC_Datain) byte |= else byte &= 0xFE; } return (byte); // Receive bit by bit the byte to be received // To release ICCCLK to for next communication bit // Prepare to receive next bit in the buffer // Wait for PC_status line high (meaning that ST7 as // released ICCCLK to 1 and then force it back to 0) // Data is then available on ICCDATA (and PC_datain) // If key pressed then exit 0x01; // > Received bit is a 1 // > Received bit is a 0 // Return received byte

}

//* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * *** // ICC MODE ENTRY ROUTINES //* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * *** /* ---------------------------------------------------------------------------ROUTINE NAME : ICC_Enter_CtrlWin INPUT/OUTPUT : Nb of pulse to be applied / None

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DESCRIPTION : ICC Mode entry with Controlled Window. -----------------------------------------------------------------------------*/ void ICC_Enter_CtrlWin (unsigned char pulse) { unsigned char i; VPP_Voltage(0); ResC(PC_reset); ResD(PC_dataout); SetD(PC_init); // // // // To reset pulse counter, when ICCSEL is used. RESET=5V: To get a low level pulse afterward Force ICCCLK to 0 and then initialized DATA latch to avoid conflict on ICCDATA during pulses

SetC(PC_reset); /