w
IMPORTANT NOTICE
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TN0012 Technical note
Differences between STw4810 and STw4811N/STw4811M devices
Pur pose
The purpose of this document is to describe all the device changes which have been introduced from STw4810 to STw4811N/STw4811M. STw4810 and STw4811N/STw4811M can be used as companion chip of STn8810. Only STw4811N/STw4811M can be used as companion chip of STn8815.
STw48xx - STn88xx compatibility
Compatibility STw4810 STw4811N/STw4811M STn8810 Yes Yes STn8815 No Yes
Reference documents
For more information on STw4810 and STw4811N/STw4811M devices refer to:
STw4810 datasheet STw4811N/STw4811M datasheet
September 2007
Rev 1
1/23
www.st.com
Contents
TN0012
Contents
1 Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 1. 2 Star t up behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.1 1.2.2 I2C interface modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 I2C interface data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1. 3
8-bit control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.1 1.3.2 1.3.3 1.3.4 USB EN register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Configuration 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Configuration 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Vcore_Sleep register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1. 4
16-bit indirect access register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.4.1 1.4.2 vio_vmem and vcore sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Vcore values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5
USB OTG module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.1 1.5.2 1.5.3 1.5.4 R_VBUS_SRP connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 IT_WAKE_UP ball . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 USBINTn ball . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 VBUS control in sleep mode (PWREN = 0) . . . . . . . . . . . . . . . . . . . . . . 19
1. 6
MMC feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.6.1 1.6.2 1.6.3 VMMC LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SD/MMC level shifters in off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SD/MMC APE interface at start up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/23
TN0012
Changes
1
1.1
Changes
Start up behavior
At start up, with STw4810, PWREN is masked until VDDOK ball is set to "1" level (see Figure 1) At start up, with STw4811N/STw4811M, PWREN is masked until PORn ball is set to "1" level (see Figure 2)
Figure 1.
STw4810 start up behavior
OFF VBAT PON ball
300s
9.38ms (11ms wc)
PDN__OSC
START_BIAS
START_PM
1ms
PDN_regulators VDDOK ball
7.77ms (9.46ms wc)
11*(1/32kHz)
CLK32K_IN ball PORn ball PWREN ball
(*)
RESET PWREN unmasked
Internal_OSC MASTER_CLK ball TCXO_EN ball REQUEST_MC ball
OFF2 VPLL / VIO_VMEM VCORE
"or"
RESET
INT_OSC
Voutput(s) ball
CLK32K ball Delays are worst case maximum delays (*) If 32 kHz available before VDDOK signal rising edge, OFF2 state duration is null
3/23
Changes Figure 2. STw4811N/STw4811M start up behavior
OFF VBAT
TN0012
PON ball
300s
9.38ms (11ms wc)
PDN__OSC PDN_regulators VDDOK ball
11*(1/32kHz) START_BIAS 7.77ms (9.46ms wc) START_PM 1ms
CLK32K_IN ball PORn ball PWREN ball
(*) RESET
Internal_OSC MASTER_CLK ball TCXO_EN ball REQUEST_MC ball
OFF2 VPLL / VIO_VMEM VCORE RESET "or" INT_OSC
Voutput(s) ball
CLK32K ball Delays are worst case maximum delays (*) If 32 kHz available before VDDOK signal rising edge, OFF2 state duration is null
4/23
TN0012
Changes
1.2
1.2.1
I2C interface
I2C interface modes
For I2C interface modes, STw4810 supports (see Figure 3): Write single byte Random address read single byte Random address read multi bytes Write single byte Write multi bytes Random address read single byte Random address read multi bytes
For I2C interface modes, STw4811N/STw4811M supports (see Figure 4):
Figure 3.
STw4810 control interface I2C format
DEVICE ADDRESS ACK ACK REGn ADDRESS REGn Data In ACK
WRITE SINGLE BYTE
01011010
START STOP
RANDOM ADDR READ SINGLE BYTE
DEVICE ADDRESS
ACK ACK REGn ADDRESS
DEVICE ADDRESS
ACK REGn Data Out
NO ACK
01011010
START
01011011
START
RANDOM ADDR READ MULTI BYTE DEVICE ADDRESS ACK ACK REGn ADDRESS ACK DEVICE ADDRESS ACK Reg n Data Out ACK
01011010
START
01011011
START
NO ACK Reg n + m Data Out STOP
m+1 data bytes
5/23
Changes Figure 4. STw4811N/STw4811M control interface I2C format
DEVICE ADDRESS ACK ACK REGn ADDRESS REGn Data In ACK
TN0012
WRITE SINGLE BYTE
01011010
START DEVICE ADDRESS ACK ACK REGn ADDRESS REGn Data In ACK STOP ACK REGn+m Data In STOP m+1 data bytes ACK
WRITE MULTI BYTE
01011010
START
RANDOM ADDR READ SINGLE BYTE
DEVICE ADDRESS
ACK ACK REGn ADDRESS
DEVICE ADDRESS
ACK REGn Data Out
NO ACK
01011010
START
01011011
START
RANDOM ADDR READ MULTI BYTE DEVICE ADDRESS ACK ACK REGn ADDRESS ACK DEVICE ADDRESS ACK Reg n Data Out ACK
01011010
START
01011011
START m+1 data bytes
NO ACK Reg n + m Data Out STOP
1.2.2
I2C interface data
With STw4810, if the data is toggled during the low period clock, the transmission stops (see Figure 5). With STw4811N/STw4811M, toggling the data during the low period clock does not stop the transmission. STw4810 I2C interface limitation
Figure 5.
SCL
SDA
Data changes when SCL is low
If SDA is toggled when SCL is low the transaction stops
6/23
TN0012
Changes
1.3
8-bit control registers
Some registers have been modified from STw4810 to STw4811N/STw4811M. Table 1 gives the new mapping of these registers for both devices:
Address 02h, product ID: STw4810: 10h, STw4811N/STw4811M: 11h Address 10h, USB EN register Address 11h and name have changed from SD MMC control register in STw4810 to configuration 1 register in STw4811N/STw4811M. Address 20h and name have changed from Twarning register in STw4810 to configuration 2 register in STw4811N/STw4811M. Address 21h, Vcore_Sleep register is a new STw4811N/STw4811M register.
Table 1.
STw4810 - STw4811N/STw4811M register mapping changes
Addr. 7 6 5 4 3 2 1 0
Register
STw4810 register mapping (only those with changes in STw4811N/STw4811M) Product ID USB EN 02h 10h 0 Not used pdn_ vaux monitori ng_vio_ vmem_ vcore 0 0 1 0 0 0 usb_en 0 not used pdn_ vmmc mask_ twarn
SD MMC control
11h
it_warn
gpo2
gpo1
sel_vmmc<1:0>
Twarning
20h
Not used
STw4811N/STw4811M register mapping (only those with changes compare to STw4810 Product ID USB EN 02h 10h 0 Not used 0 B_sess_ end 0 1 Not used monitori ng_vio_ mmc_ls_ vmem_ status vcore gpo2 vcore_ available gpo1 0 0 th_ Bdevice 0 usb_en 1 not used
Configuration 1
11h
pdn_ vaux
it_warn
vmmc_sel[2:0]
pdn_ vmmc
Configuration 2
20h
mask_ Reserved Reserved monitor_ sleep not used
mask_it_ external wake_up _vmmc vcore_sleep[3:0]
mask_ twarn
Vcore_Sleep
21h
7/23
Changes
TN0012
1.3.1
USB EN register
Bits "B_sess_end" and bit "th_Bdevice" are added to USB EN register for STw4811N/STw4811M (see Table 2). STw4811N/STw4811M USB EN register (address = 10h)
6 B_sess_ end R Name usb_en th_Bdevice Value 0 1 0 1 0 6 B_sess_end 1 Inactive Enable USB PHY threshold for vbus_valid = 4.4 V threshold for vbus_valid = 3.87 V Vbus voltage is below B_session_end threshold (0.2 to 0.8 V) Vbus voltage is above B_session_end threshold (0.2 to 0.8 V) 5 4 Not used 3 2 th_ Bdevice R/W Settings 1 usb_en R/W 0 not used Default 0 0
Table 2.
7 Not used Bits 1 2
0
1.3.2
Configuration 1 register
In STw4810 the register was named SD MMC control register. Other differences with configuration 1 register between STw4810 and STw4811N/STw4811M are listed below. Also, see Table 4.
"gpo1" and "gpo2" bits are removed and moved to configuration 2 register. "vmmc_sel2" bit is added to have the possibility to program VMMC output voltage with new values, 2.6 V, 2.7 V and 3.3 V. "mmc_ls_status" has been added to have the possibility to put in high impedance the MMC interface and in standby the MMC level shifters. This allows to put several cards on the same bus: one card on STw4811N/STw4811M output and one card between STw4811N/STw4811M and the application processor.
8/23
TN0012 Table 3.
7 pdn_ vaux R/W
Changes STw4810 configuration 1 register (11h)
6 5 monitoring _vio_ vmem_ vcore R(1) 4 3 2 1 0 pdn_ vmmc R/W
it_warn
gpo2
gpo1
sel_vmmc<1:0>
R(1)
R/W
R/W
R/W
1. These bits are reset (0) after reading
Bits 7
Name pdn_vaux
Value 0 1 0 1 0 1 0 1 0 1 00 01 10 11 0 1 Inactive Enable LDO vaux
Settings
Default 0
6
it_warn monitoring_vio_ vmem_vcore gpo2
Below temperature threshold Above temperature threshold Outputs in the good range Outputs lower than expected on vio_vmem or vcore Output GPO2 HZ Output GPO2 Low Output GPO1 HZ Output GPO1 low 1.8V selection 1.8V selection 2.85V selection 3V selection Inactive Enable SD/MMC or SDIO function.
0
5
0
4
0
3
gpo1
0
[2:1] sel_vmmc<1:0>
00
0
pdn_vmmc
0
9/23
Changes Table 4.
7 pdn_vaux R/W
TN0012 STw4811N/STw4811M configuration 1 register (11h)
6 it_warn R(1) 5 monitoring_vio_ vmem_vcore R(1) 4 mmc_ls_ status R/W 3 2 vmmc_sel[2:0] R/W 1 0 pdn_ vmmc R/W
1. These bits are reset (0) after reading
Bits 7
Name pdn_vaux
Value 0 1 0 1 0 1 0 Inactive Enable LDO vaux
Settings
Default 0
6
it_warn monitoring_vio_ vmem_vcore
Below temperature threshold Above temperature threshold Outputs in the good range Outputs lower than expected on vio_vmem or vcore Level shifters ON, if `pdn_vmmc' or `external_vmmc' = 1 Level shifters High Impedance, if `pdn_vmmc' or `external_vmmc' =1 1.8 V selection 1.8 V selection 2.85 V selection 3 V selection 1.85 V selection 2.6 V selection 2.7 V selection 3.3 V selection Inactive Enable SD/MMC/SDIO function.
0
5
0
4
mmc_ls_status 1 000 001 010 011 100 101 110 111 0 1
0
[3:1] vmmc_sel[2:0]
000
0
pdn_vmmc
0
STw4810 and STw4811N/STw4811M "monitoring_vio_vmem_vcore" bit behavior
STw4810 "monitoring_vio_vmem_vcore" bit is set to "1" on a falling edge of PWREN, which is a wrong behavior, as it indicates that VIO_VMEM or VCORE have not the right voltage.This has been corrected in STw4811N/STw4811M, where in the same condition, "monitoring_vio_vmem_vcore" bit stays at "0" level. STw4811N/STw4811M "monitoring_vio_vmem_vcore" bit controls VIO_VMEM and VCORE right output condition voltage in high power (normal) and in low power modes. In STw4810, this bit controls VIO_VMEM and VCORE right output condition voltage only in high power mode.
10/23
TN0012
Changes
1.3.3
Configuration 2 register
This register was named Twarning register in STw4810. In STw4811N/STw4811M and for configuration 2 register the following bits have been added (see Table 6):
"external vmmc", to have the possibility to supply both a card and the STw4811N/STw4811M level shifters with an external LDO (for example card current supply higher than 150 mA). "mask_it_wake_up", to mask IT_WAKE_UP ball. "gpo1" and "gpo2" bits, previously located in STw4810 SD MMC control register. "mask_monitor_sleep" to mask VCORE and VIO_VMEM monitoring when STw4811N/STw4811M is in sleep mode. STw4810 configuration 2 register (address = 20h)
6 5 4 Not used 3 2 1 0 mask_ twarn R/W Settings Inactive Mask TWARN interruption (it_twarn bit) through VDDOK Default
Table 5.
7
Bits
Name
Value 0 1
0
mask_twarn
0
Table 6.
7 Reserved Bits
STw4811N/STw4811M configuration 2 register (address = 20h)
6 Reserved Name 5 msk_ monitor_ sleep R/W Value 0 1 0 1 0 1 0 1 0 1 4 gpo2 R/W 3 gpo1 R/W 2 mask_it_ wake_up R/W Settings Inactive Mask TWARN interruption (it_twarn bit) through VDDOK Internal LDO VMMC is used External VMMC is used Inactive IT_WAKE_UP ball masked GPO1 in High impedance GPO1 at low level GPO2 in High impedance GPO2 at low level 1 external_ vmmc R/W 0 mask_ twarn R/W Default
0
mask_twarn
0
1 2 3 4
external_vmmc mask_it_wake _up gpo1 gpo2
0 0 0 0
11/23
Changes
TN0012
Bits
Name
Value 0
Settings Enable VCORE & VIO_VMEM monitoring in sleep mode Disable VCORE & VIO_VMEM monitoring in sleep mode Must be forced at "0" Must be forced at "0"
Default
5
mask_monitor _sleep Reserved Reserved
1 0 0
0
6 7
0 0
12/23
TN0012
Changes
1.3.4
Vcore_Sleep register
Vcore_Sleep is a new register in STw4811N/STw4811M(see Table 7):
"vcore_sleep[3:0]" bits are used to program VCORE to a different value in sleep mode than in active mode. "vcore_available" bit is used in high power mode when STw4811N/STw4811M VCORE supply is programmed to a higher or a lower value in run time,. This bit informs the processor when the new VCORE voltage is reached (see Figure 6). STw4810 default value of Vcore is 1.20 V (code 0100) and the maximum value (code 1111) is 1.50 V (see Table 7). STw4811N/STw4811M default value of Vcore is 1.26 V (code 0111) and the maximum value (code 1111) is 1.45 V (see Table 8). STw4811N/STw4811M VCORE_Sleep register (address = 21h)
7 6 5 4 vcore_ available R 3 2 1 0
Table 7.
Register Bit name Type
vcore_sleep[3:0] R/W
Bits
Name
Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 = 1.00V = 1.05V = 1.10V = 1.15V = 1.20V = 1.22V = 1.24V = 1.26V (default) = 1.28V = 1.30V = 1.32V = 1.34V = 1.36V = 1.38V = 1.40V = 1.45V
Settings
Default
[3:0] vcore_sleep[3:0]
0111
4
vcore_available
(1)
Inactive Reach the expected value when Vcore decreases or increases
0
1. read operation reset the value after status read operation from APE.
13/23
Changes Figure 6. STw4811N/STw4811M "vcore_available" bit behavior
TN0012
Vcore
vcore_available bit read operation to reset bit
1.4
1.4.1
16-bit indirect access register
vio_vmem and vcore sleep
The 16-bit indirect access register at address 1F/1E has been modified from STw4810 to STw4811N/STw4811M as follows:
at indirect address 09h, bit 2 and bit 1 are "reserved" in STw4810. These bits must be programmed at "1" in STw4811N/STw4811M (see Table 8) and are used for a new feature. bit 2, "vio_vmem_sleep" controls VIO_VMEM mode when PWREN = 0 bit 1, "vcore_sleep" controls VCORE mode when PWREN = 0 STw4811N/STw4811M power control register at address 09h
Address 1Fh Address 1Eh 9 0 8 1 7 0 6 0 5 1 4 vaux_ sleep 3 not used 2 1 0 EN
Table 8.
15
14
13
12
11
10
Not used
vio_ vcore_ vmem_ sleep sleep
Bits
Name
Value
Settings When PWREN is low: VAUX stays in normal mode VAUX goes in sleep mode When PWREN is low: VIO_VMEM stays in normal mode VIO_VMEM goes in sleep mode When PWREN is low: VCORE stays in normal mode VCORE goes in sleep mode
Default
4
vaux_sleep
0 1
1
2
vio_vmem_sleep
0 1
1
1
vcore_sleep
0 1
1
14/23
TN0012
Changes
1.4.2
Vcore values
STw4810 default value of Vcore is 1.20 V (code 0100) and the maximum value (code 1111) is 1.50 V (see Table 9). STw4811N/STw4811M default value of Vcore is 1.26 V (code 0111) and the maximum value (code 1111) is 1.45 V (see Table 10). STw4810 power control register at address 05h
Address 1Fh Address 1Eh 9 0 Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 =1.00V =1.05V =1.10V =1.15V =1.20V (default) =1.22V =1.24V =1.26V =1.28V =1.30V =1.32V =1.34V =1.36V =1.38V =1.40V =1.50V 8 0 7 1 6 0 5 1 4 3 2 1 0 EN Default
Table 9.
15
14
13
12
11
10
Not used Bits Name
vcore_sel[3:0] Settings
[4:1] vcore_sel[3:0]
0100
15/23
Changes Table 10. STw4811N/STw4811M power control register at address 05h
Address 1Fh 15 14 13 12 11 10 9 0 Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 =1.00V =1.05V =1.10V =1.15V =1.20V =1.22V =1.24V =1.26V (default) =1.28V =1.30V =1.32V =1.34V =1.36V =1.38V =1.40V =1.45V 8 0 7 1 6 0 5 1 4 Address 1Eh 3 2 1
TN0012
0 EN Default
Not used Bits Name
vcore_sel[3:0] Settings
[4:1] vcore_sel[3:0]
0111
16/23
TN0012
Changes
1.5
1.5.1
USB OTG module
R_VBUS_SRP connection
In STw4810, R_VBUS_SRP is connected between VBUS and VUSB (see Figure 7).
Figure 7.
STw4810 USB OTG transceiver block diagram
VBAT_USB CP CN
VBAT_DIG C LK VMINUS_DIG
USB_INTn
vbus_vld sess_vld dn_hi Interrupt dp_hi Control bdis_acon Register id_gnd_forced id_float cr_int usb_en usb_i2c_ctrl vbus_drv bdis_acon_en dn_pullup dp_pullup Control dn_pulldown Registers dp_pulldown id_gnd vbus_chrg vbus_dischrg speed uar t_en dat_se0 oe_int_en suspend
R EF
R_VBUS_SRP
R_VBUS_PD
CHARG E PUMP 5V - 100mA
vbus_drv
100 mA
VBUS RA_BUS_IN
VBUS_MONITOR VBUS > 4.4 V vbus_vld sess_vld
2V < VBUS < 4.4 V
vbus_chrg
VBUS < 0.8V
VBAT_USB
G ND VUSB_LDO
vbus_dischrg vbus_session_end
V US B
DP_MONITOR cr_int
DP
USBSCL
5.7 R
USBSDA
DP < [0.4 to 0.6] V
R
S CL
SDA
RXD RXD
TRANCEIVER
dn_pullup dp_pullup
RPU_DP
SW_RESETn
DAT_VP
Diff Tx
USBVM U S B OE n S E O_ V M OE _TP _ I N T
RP U_DN
USBVP
DP
out_diff_Rx Diff Rx suspend
RPD _DN US B RCV RCV DN RP D_DP
SINGLE ENDED DECODER
SE_DP VP dn_pulldown SE_DN
VM
VBAT_DIG
dp_pulldown
VBAT_USB
R
RID_PU 0. 85*I D ID
Plug detect Management
IT_WAKE_UP
id_float sess_vld id_gnd
4.7 R
OR ID Detector
R
0. 15*I D
id_gnd
17/23
Changes
TN0012 In STw4811N/STw4811M, R_VBUS_SRP is connected between VBUS and VBAT_USB, allowing SRP to start without starting VBUS LDO (see Figure 8).
Figure 8.
STw4811N/STw4811M USB OTG transceiver block diagram
VBAT_USB CP CN
VBAT_DIG VMINUS_DIG
USB_INTn
vbus_vld sess_vld dn_hi Interrupt dp_hi Control bdis_acon Register id_gnd_forced id_float cr_int usb_en usb_i2c_ctrl B_ sess_end vbus_drv bdis_acon_en dn_pullup dp_pullup Control dn_pulldown Registers dp_pulldown id_gnd vbus_chrg vbus_dischrg speed uar t_en dat_se0 oe_int_en suspend
CL K RE F
VBUS_MONITOR 4.4 V vbus_vld sess_vld B_ sess_end
1.9 V 0.6 V
R_VBUS_SRP
R_VBUS_PD
CHARGE PUMP 5V - 100mA
vbus_drv
100 mA
VBUS
RA_BUS_IN
vbus_chrg
VBAT_USB
G ND vbus_dischrg VUSB_LDO
V US B
DP_MONITOR cr_int
DP
USBSCL
5.7 R
USBSDA
DP < [0.4 to 0.6] V
R
S CL SDA
RXD RXD
TRANCEIVER
dn_pullup dp_pullup
RP U_DP
SW_RESETn
DAT_VP
Diff Tx
USBVM U S B OE n S E O_ V M OE _TP _ I N T
RP U_DN
USBVP
DP
out_diff_Rx Diff Rx suspend
RP D_DN US B RCV RCV DN RP D_DP
SINGLE ENDED DECODER
SE_DP VP dn_pulldown SE_DN
VM
dp_pulldown
VBAT_USB
R
RID_PU 0. 85*I D ID
Plug detect Management
IT_WAKE_UP
id_float sess_vld id_gnd
4.7 R
Open Drain OR
0. 15*I D
id_gnd
ID Detector
R
18/23
TN0012
Changes
1.5.2
IT_WAKE_UP ball
In STw4810, IT_WAKE_UP ball has an internal pull-up connected to VBAT In STw4811N/STw4811M, IT_WAKE_UP is an open drain which supports voltage values up to VBAT.
This allows more flexibility in the use of this feature (for example it can be used to refer to a processor VIO supply). In STw4811N/STw4811M it is possible to mask IT_WAKE_UP ball when PON = 1 and the transceiver is not activated (see also Section 1.3.3: Configuration 2 register).
1.5.3
USBINTn ball
In STw4810, USBINTn ball is activated only when PWREN = 1 In STw4811N/STw4811M, USBINTn ball is activated independently of PWREN level. When PWREN = 0, USBINTn ball goes to low level if a USB interrupt source is detected. In sleep mode PWREN = 0, an interrupt source is detected only if unmasked before PWREN goes to low level.
1.5.4
VBUS control in sleep mode (PWREN = 0)
In STw4811N/STw4811M, if VBUS is set "ON" by the processor before its goes to sleep mode, PWREN transition goes from high to low level and VBUS remains ON. In STw4810, VBUS is not usable when PWREN = 0
1.6
1.6.1
MMC feature
VMMC LDO
STw4810 VBAT_MMC input supply supports a battery voltage range from 2.7 V to 4.8 V. STw4811N/STw4811M VBAT_MMC input supply supports 5.5 V input voltage (2.7 V to 5.5 V range). STw4810 and STw4811N/STw4811M have different VMMC output voltages (see Table 3 and Table 4).
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1.6.2
Figure 9.
SD/MMC level shifters in off mode
STw4810 - STw4811N/STw4811M SD/MMC/SDIO block diagram
SD/ MMC/SDIO INTERFACE
VBAT_VMMC VMMC
LDO 150mA
MCCMDDIR MCDATA0DIR MCDATA2DIR MCDATA31DIR
MCCLK DRIVER
5 * RB VIO_VMEM3 * RA 3 * RA
CLKOUT
EMIF
Level
RC Rs
SD, MMC SDIO OR CARDS
Dz
Shifter M CCM D MCDATA0 MCDATA[3:1] MCFBCLK
RB
CM DOUT DATAOUT0 DATAOUT[3:1] LATCHCLK
Dz
In STw4811N/STw4811M, when the level shifters are OFF (set to "1" `mmc_ls_status' bits of Configuration 1 register): the APE interface MCDATA[3:0] and the MCCMD balls are set to high impedance and the pull up resistors are disconnected. the card interface DATAOUT[3:0] and the CMDOUT balls are set to "1" with an internal 1.5 Mohm pull up resistor the card clock, CLKOUT ball, is set to "0" and the APE feedback clock MCFBCLK ball is configured in high impedance.
In STw4810 this feature does not exist.
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1.6.3
SD/MMC APE interface at start up
In STw4810 and during start up, when VIO_VMEM increases, the MMC APE interface follows VIO_VMEM voltage until VDDOK rising edge (Figure 10).
Figure 10. STw4810 MMC APE interface behavior at start up
PON
VDDOK
MMC APE interface
VIO_VMEM
In STw4811N/STw4811M, MMC APE interface does not follow VIO_VMEM voltage and remains at low level.
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Revision history
TN0012
2
Revision history
Table 11.
Date 05-Sep-2007
Document revision history
Revision 1 Initial release. Changes
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