STPM01
USER MANUAL
Single Phase with Shunt
Release 1.0
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
"Partnership with ISKRAEMECO" ISKRAEMECO d.d. R&D-Microelectronics Savska Loka 4 4000 Kranj SLOVENIA
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1 1.1 1.2 2 2.1 2.2 3 3.1 3.2 3.2.1 3.2.2 3.2.3 3.3 3.3.1 3.3.2 3.3.3 3.3.4 4 4.1 4.2 5 5.1 6 INTRODUCTION . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . SAFETY RULES. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. CONVENTIONS . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. APPLICATION . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... STANDALONE . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... MICROPROCESSOR BASED . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... COMMUNICATION WITH THE MODULE . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. USAGE OF 2-WIRE OR 3-WIRE SPI. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... TASKS PERFORMED BY SPI . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... Remote reset request . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... Changing of system signals. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... Reading of data records . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... PROCESSING OF DATA RECORD . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . Data integrity checks . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... Unpacking of data records. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. Usage of energy values. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . Usage of other values. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... TECHNICAL PARAMETERS. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. ELECTRICAL PARAMETERS. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . MECHANICAL OUTLINES . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . APPENDIX . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... MIGRATE THE POWER LINE SYSTEM FROM 220V, 50 HZ INTO 110 V, 60 HZ. ... REVISON AND LEGAL INFORMATION . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 5 5 5 6 6 7 9 9 9 10 11 13 14 15 15 16 18 19 19 20 21 21 26
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STPM01 - SINGLE PHASE WITH SHUNT
1 - INTRODUCTION 1.1 - Safety rules This board can be connected to mains voltage (220V/110V). In case of improper use, wrong installation or malfunction, there is a danger of serious personal injury and damage to property. All operations such as transport, installation and commissioning as well as maintenance are to be carried out by skilled technical personnel (national accident prevention rules must be observed). Due to the risk of death when using this prototype on mains voltage (220V /110V), only "Skilled technical personnel", who are familiar with the installation, mounting, commissioning and operation of power electronic systems and have the qualifications needed to perform these functions, may use this prototype. 1.2 - Conventions In this user manual, a Bold typeface is used to indicate the NAME of the pin of the module or device or corresponding signal, while an Underlined typeface is used to indicate the NAME of the configuration signal. An Italic typeface is used to name software registers. The lowest analog and digital power supply voltage is named VSS. All voltage specifications for digital input/output pins refer to VSS. The highest OTP writing power supply voltage is named VOTP. The highest power supply voltage is named VCC. Positive currents flow into a pin. Sinking means that the current is flowing into the pin while sourcing means that the current is flowing out of the pin. Timing specifications of signals treated by the device are relative to the CLKOUT. This signal is fed from an on-board crystal oscillator 4.194 MHz. Timing specifications of signals of a SPI interface are relative to the SCLNLC, which need not to be in phase with CLKOUT. A positive logic convention is used in all equations.
February 2005
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2 - APPLICATION This metering module can be used to build a Class 0.5 Single-phase standalone or microprocesor based meter with or without Tamper detection for power line systems of UNOM=140 to 300VRMS, INOM/IMAX=2/20 ARMS, fLIN=45 to 65Hz and TAMB=-40 to +85 C. The connection of line signals to the module must be made as shown in Figure 1 1 the hot line voltage wire must be connected to pin N of the module. Normally, this wire is also connected to the hot line current wire but, during the production or verification phases, this wire may be connected to some line voltage source; 2 the neutral line voltage wire must be connected to pin F of the module. This wire is also connected to the neutral current wire which passes through the module; 3 the hot current wire must be connected to the pole of the Shunt which is close to pin N of the module using isolated 4 mm2 copper wire; 4 the hot load current wire must be connected to the pole of the Shunt which is close to the edge of the module using isolated 4 mm2 copper wire Figure 1 : Connection of module to the power line
2.1 - Standalone In standalone mode, a stepper motor display should be connected to pins W5 and W6. These pins are located between Shunt and connector P1 as shown in Figure 1. The on-board metering device STPM01 is capable of delivering more than 14mA to the stepper. A user can select the type of stepper or the constant of output pulse frequency by changing LVS or KMOT configurators respectively (see Table 4 below). The male connector P1, which is a collection of power and SPI signals, would normally be used during the production phase only to connect the module to some host system in order to access the configurators or to read the results of operations from the STPM01 device. But this does not mean that the use of P1 is restricted later. It can be used freely regardless of the fact that some SPI signals can also be used to drive three indicators. There are four small LED elements mounted close to connector P1 in such a way that they can be observed from the non component side of the module. The most important diode is named LED. The light pulse frequency which can be observed is proportional to the level of measured power. Therefore, this diode is used to calibrate or verify the accuracy of the module. The other three diodes are used as indicators: NLC lights when No Load Condition is detected, i.e. very low or zero load current is measured;
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TPR lights when Tamper is detected, i.e. line and neutral currents are very different from each other ((abs(iL)+abs(iN)) < 8(abs(iL-iN))); DIR lights when the measured energy is negative, most likely due to wrong connection. 2.2 - Microprocessor based In Microprocessor based mode, a control board with a microprocessor should be connected to the male connector P1 of the module using a 10-wire flat cable. below describes the signals corresponding to the pins of this connector. The four SPI signals are multi purpose pins and they actually reflect the functionality of corresponding pins of the on-board metering device. Using this connection, the control board can read data records or it can access mode or configurator signals of the STPM01 device by means of a dedicated protocol and it can draw up to 4mA at +3.0V from the module.. Table 1 : Pin number, signal name and signal description of connector P1
Pin 1 Name VOTP Functional description of signal Power IO of +15.0 V during permanent write to OTP cells if (no permanent write in progress), then VOTP is input, read as +2.3 V else VOTP is input for externally generated +15.0 V power level 2 3 4 SBS GND SDA Digital Out for SPI Bus Request signal A Host may assert this signal when it wants to become a SPI master Signal reference level 0 V and power supply return Digital IO for SPI data signal or TPR indicator if (SCS==1), then if (APL < 2), then SDA is input (idle, read as 1) else SDA is output for TPR active low indicator else if (SYN==0), then SDA is input for command stream else SDA is output for data record stream 5 SCS Digital In for SPI enable signal if (SCS==1), then SPI of the metering device is in idle state else SPI can receive command or transmit data record streams 6 SCL Digital IO for SPI clock signal or NLC indicator if (SCS==1), then if (APL < 2), then SCL is input (idle, read as 1) else SCL is output for NLC active low indicator else SCL is input for SPI data transfer clock signal 7 8 VDDA SYN Power Out of +3.0 V Up to 4 mA can be drawn from this pin Digital IO for SPI data direction or latch request or DIR indicator if (SCS==1), then if (APL < 2), then SYN is input (idle, read as 1) else SYN is output for DIR active low indicator else SYN is input for SDA data direction signal if ((SCS==1) & (SYN==0)), then the current results of computations are latched in the metering device in order to be transmitted via SPI 9 SBG Digital Input for SPI Bus Grant signal. It is tied to SBS because there is no SPI master on this module 10 -Not used
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Such an application may still use any LED elements of the module for the purposes described in Paragraph 2.1. or, it may generate an alternative set of signals from the control board. In this case, the control board may also recalibrate any result read from the module. Similarly, this is valid for pins W5 and W 6 too, but this is rarely the case because one of the main reasons for adding a control board is to use an LCD rather than a stepper. If a TSTD configurator has not been permanently written in the metering device on the module, an application may entirely modify its mode or configurator signal. This means that it can select either the permanently written configuration by clearing a mode signal RD or, it can, first, read the permanently written configuration, modify it, if necessary, then download the new one back to the metering device and set RD after every power up restart.
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3 - COMMUNICATION WITH THE MODULE As mentioned above, a host system can communicate with the module using SPI signals and connection via connector P1. Actually, it communicates with the metering device which is the key element of the module. This device always acts as an SPI slave while the host system acts as an SPI master. A control board of an application or some external system can be considered as a host. If an external system, for example, a PCB functional test system, is connected to the same connector P1 while a control board is also connected, the control board must act as an SPI slave too. There are two handshake pins on the connector P1, SBS and SBG. An external host system can request a serial bus for its needs, by asserting SBS=0. A local on-board host should put itself into SPI slave mode and respond by asserting SBG=0. Since there is no local host in this module, these handshake signals are shorted together and therefore, a user can ignore them. There is also a VOTP, a high-voltage power level pin on the connector P1. When a host wants to permanently write some configurators in the metering device, a +15V power level must be present on the VOTP. This level must be delivered from the host itself because the module does not have an on-board charge pump. 3.1 - Usage of 2-wire or 3-wire SPI A simple serial protocol is implemented into an SPI function block of the metering device which represents the service for a serial bus signal. As can be seen in the Table 1, the serial bus consists of four signals. Let us say that the SPI master is implemented as a microprocessor of the control board. In this case, SCS and SYN are normally driven from some parallel port, while SCL and SDA are normally driven from some port to which an internal SPI peripheral unit is connected. This means that the SPI peripheral unit of the microprocessor should operate as a 2-wire SPI. A 3-wire SPI peripheral can also be used because, most of the time, an SPI master is reading from a metering module, rarely during its production, is it also writing to a metering module. In this case, the SDA of P1 should be connected to SDI of the microprocessor. The writing functionality should be emulated or, a 3-state buffer, controlled by SYN, should be used in order to connect an SDO to the SDA. 3.2 - Tasks performed by SPI Three tasks can be performed with such an interface by a host: 1 send remote reset request to metering device, 2 send command byte to change a system signal, 3 read up to eight 4-byte data records. An idle state of SYN, SCS, SCL and SDA is logical 1. Any data transfer can occur only during asserted SCS = 0 when any combination of tasks listed above is possible. This means also that an SPI master can abort any task in any phase simply by dissertation of SCS. The SYN has two functions. If it is asserted in front of asserted SCS for at least 1s, it latches the internally generated results into transmission latches. This information can then be read out from the module, whenever SCS is asserted. If SYN is asserted within the asserted SCS, it disables the output driver of the SDA, i.e. the pin becomes an input with internal pull-up. This way a send task can be performed. Otherwise, if SYN is disserted within the asserted SCS, the output driver of the SDA is enabled and thus, the read task can be performed. If the module is configured as standalone, i.e. APL>1, a dummy send (SCS=0, SYN=0, SYN=1) should be performed before an actual read task because this should clear the incidentally incremented internal transmition clock counter due to switchover of the SCL function from indicator to SPI. Table 2 summarises the SPI operations..
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Table 2 : Collection of SPI operations
SYN 1 0 1 1 1 1 1 0 0 0 0 1 0 0 0 0 SCS 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 SCL 1 1 1 10 01 1 1 1 0 0 0 1 1 1 10 01 SDA Z Z X Description Idle state of SPI signals (no data transfer) Latch the results (6x28-bits) into transmitter latches Enable the SPI for read operation, SDA is output
X A New value is being placed on SDA by the module A Z X Z 1 01 10 X Z 1 1B B The value of SDA is stable, it is shifted into master End of any operation (reset the SPI and enter Idle state) Enable the SPI for read operation, SDA is output Enable the SPI for write operation, SDA is input Enable the SPI for remote reset, master drives the SDA If (arm==0) then arm=1 else rrr=1 No change of any state Enable the SPI for read operation, SDA is output Enable the SPI for write operation, SDA is input Master is controlling the SDA New value is being placed on SDA by the master The value of SDA is stable and is shifted into module
3.2.1 - Remote reset request The module has no reset pin. When its supply voltage is below +2.5V, an internal POR is generated. It clears all internal signals. The operation is restarted 120 ms after the voltage goes above +2.5V. When a host needs to reset the metering device, it can request a remote reset by assertion of SCS=SYN=SCL=0. If pulse to low is applied on SDA, an internal arm is set. If such a pulse on SDA is repeated, an internal rrr is generated. It clears all internal signals, except from mode signals, and terminates delay after POR. The next pulse on SDA clears the arm and rrr. If either SYN, SCS or SCL is disserted at any step, the remote reset sequence is aborted. See the Table 2 above and left side of Figure 2. Figure 2 : Remote restart request and command byte write
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3.2.2 - Changing of system signals In the metering device, there are 56 configuration signals, 16 test signals and 8 mode signals for a total of 80 system signals which can be accessed via SPI. An access means that the logic states of these signals can be changed or they can be read back. No one should change any test related signals (* in Table 3) because they are reserved for the production testing of the metering device. All others, i.e. 56 configuration plus PR, WE, RD and PUMP mode signals are free to be changed on a signal by signal basis. Such a change is performed by writing a certain command byte to the metering device. This byte consists of data bit, six address bits and an execute bit. The data bit is the most significant bit of the command byte and it should always be transferred first. See Figure 2 above. The addressed signal follows the value of the data bit. The 6-bit address field allows us to directly address 64 signals, configuration (lower 56 addresses) and mode signals (upper 8 addresses). See Table 3 below.. Table 3 : System commands
Bit pos. 76543210 DAAAAAAX D111000X D111001X D111010X D111011X D111100X D111101X D111110X X111111X Functional description of command for changing some system signal (X,D,A = {0,1}) if ((BANK==0) && (AAAAAA2 < 1110002)) then shadow=D if ((BANK==1) && (AAAAAA2 < 0100002)) then TSG=D * BANK=D,*(internal data bank selection signal) PUMP=D, (Charge Pump ON/OFF signal, not usable due to absent circuit TST0=D,*(internal test mode selection signal: TEST=TST1*2+TST0) TST1=D,*(internal test mode selection signal: TEST=TST1*2+TST0) TST2=D,*(force secondary current channel when tamper disabled) RD=D, (read disable of OTP block, CFG = (RD == 0)? OTP : shadow) WE=D, (write enable, WE = 1 execute permanent write to OTP cell) PR ** (PR command swaps the sequence of data record group read)
Every configuration signal is made up of two elements, one is called the shadow latch and its counterpart is an OTP antifuse. A host can change the addressed shadow signal directly by a command byte write, while its counterpart can only be permanently written indirectly by a special procedure described below. This means that the shadow latch may hold a different state to its counterpart. A host can select the source of the configuration signals. If RD has been set, the state of shadow latch defines the configuration signals otherwise this is determined by the states of the OTP antifuse. After Power On Restart (POR), the mode signals are cleared. This means that the configuration signals are controlled by the states of OTP antifuses after the power supply voltage for the metering device goes above +2.5V. A host may read these states by reading the 2.3. and 2.4. data record (see Table 5), modify it according to new needs, download it back to the metering device signal by signal and then activate it by setting RD. All this is possible if the metering device is not locked by permanent write to the first OTP antifuse (CFG0) which is named TSTD. Otherwise, only the PR command (** in Table 3) can be executed which means that no one can change any other system signal. Initially, all OTP antifuses are read as 0, after permanent write of 1 to any of them, those bits cannot be changed back to 0. Only one OTP antifuse can be written when WE is asserted. A permanent write procedure consists of the following steps: 1 assemble a list of addresses of those OTPs which should be permanently written; 2 clear all shadow latches by remote reset request or by clearing each shadow; 3 set RD; 4 apply +15.0V to VOTP from external source and wait 100 ms; 5 6 set the shadow from the list in order to address the counterpart; set WE, wait 1 ms, if (done) then VOTP < 3 V, clear WE, wait 10ms to restore VOTP;
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7 8 9 clear the shadow which was set in step 5; repeat steps 5 to 7 until all addresses from the list are exhausted; disapply +15.0V from VOTP, wait 100ms to let VOTP < 3 V;
10 clear RD and verify the configurators. The procedure above is slightly different, if one wants to permanently write the TSTD. Steps 1, 7 and 8 can be omitted, but the remaining ones must be conducted within one period of asserted SCS, otherwise the TSTD would effect at once which would clear all mode signals, abort the procedure and could destroy the device. Table 4 represents a collection and function of all configurators in the device. For multibit configurators the most significant bit address is underlined. In order to change these bits, one must make sure that BANK is cleared. Table 4 :
Address 0
Collection of configuration signals
Name TSTD Functional description of the configurator Test mode and OTP write disable: TSTD=0: testing and continuous precharge of OTP when in read mode, TSTD=1: normal operation and no more writes to OTP Measurement frequency range selection: MDIV=0: 4.000MHz - 4.194MHz, MDIV=1: 8.000MHz - 8.192MHz Type of internal oscillator selection: RC=0:crystal oscillator, RC=1:RC oscillator Application type selection: APL=0: peripheral, MOP:MON=ZeroCross:Reset, LED=pulses(X), APL=1: peripheral, MOP:MON=outs(u:i), LED=mux(current), APL=2: standalone, MOP:MON=stepper(P), LED=pulses(P) when SCS=1, SCL:SDA:SYN=indicators NLC:TPR:DIR APL=3: standalone, MOP:MON=stepper(P), LED=pulses(P/64), when SCS=1, SCL:SDA:SYN=indicators NLC:TPR:DIR Current channel sensor type, gain and tamper selection: PST=0:primary is coil x8/x161, secondary is not used, no tamper PST=1:primary is coil x24/x321, secondary is not used, no tamper PST=2:primary is CT x8, secondary is not used, no tamper PST=3:primary is shunt x32, secondary is not used, no tamper PST=4:primary is coil x8/x161, secondary is coil x8/x161, tamper PST=5:primary is coil x24/x321, secondary is coil x24/x321, tamper PST=6:primary is CT x8, secondary is CT x8, tamper PST=7:primary is CT x8, secondary is shunt x32, tamper Base frequency out of band influence to power calculation: FRS=0: if BFR then power=i*0, FRS=1: if BFR then power=i*u Bit sequence output during data record reading selection: MSBF=0:msb first, MSBF=1:lsb first Type0 active energy selection: FUND=0:type0 is wide band, FUND=1:type0 is fundamental Power accumulation type selection: ABS=0:signed accumulation, ABS=1:absolute accumulation No load condition threshold as % of nominal current selection: LTCH=0: 0.05%, LTCH=1: 0.1%, LTCH=2: 0.2%, LTCH=3: 0.4% Constant of stepper pulses/kWh selection when APL>1: If LVS==0 KMOT=0:1000, KMOT=1:500, KMOT=2:2000, KMOT=3:250 If LVS==1 KMOT=0:100, KMOT=1:50, KMOT=2:200, KMOT=3: 25 Selection of pulses(X) for LED when APL=0: KMOT=0: X=P, KMOT=1: X=P, KMOT=2: X=Q, KMOT=3: X=S
1 2 3..4
MDIV RC APL
5..7
PST
8 9 10 11 12..13 14..15
FRS MSBF FUND ABS LTCH KMOT
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Table 4 :
Address 16..19 20..23 24..31 32..39 40..47 48..49 50..51 52 53 54 55
Note
Collection of configuration signals
Name T CR CPH CHV CHP CHS CR C R NOM ADDG CRIT LVS ---R Functional description of the configurator BandGap temperature compensation selection 4-bit unsigned data for compensation of phase error, 0 +0.576 8-bit unsigned data for voltage channel calibration, 75 to 100% 8-bit unsigned data for pri. Curr. channel calibration, 75 to 100% 8-bit unsigned data for sec. Curr. channel calibration, 75 to 100% 2-bit unsigned data for calibration of RC oscillator, 0 to +20% 2-bit modifier of VRMSNOM for SingleWireMeter, NOM=0: 220, NOM=1: 240, NOM=2: 260, NOM=3: 280 Selection of adding current gain 8 (see 1 on PST above): ADDG=0: Gain+=0, ADDG=1: Gain+=8 Selection of tamper threshold: CRIT =0: 12,5%, CRIT =1: 6,25% Type of stepper selection: LVS=0: 10 poles, 30ms, 5V, LVS=1: 2 poles, 150ms, 3V
R
Reserved for the production EWS testing
1. Depend if ADDG is set.
3.2.3 - Reading of data records As already mentioned, some data can be read out from the module by means of SPI. Each data record consists of a parity nibble and 28-bit data field, which yields four bytes per data record. The data records have fixed positions of reading. This means, no addressing of records is necessary. It is up to a host to decide how many records should read out from the device. There are two groups of four data records. Table 5 shows the groups position within the default sequence of reading, and the name and assembly of data records, Table 6 shows the meaning of status bits in the 1.1. data record. Normally, a host would start to read the 1.1. data records but, if a PR command was sent (see Table 3) to the module prior to the reading task, the 2.1. data record would be read first. This way, a much faster reading of momentary values is possible Table 5 : Groups, names and assembly description of data records
G.R. 1.1. 1.2. 1.3. 1.4. 2.1. 2.2. 2.3. 2.4. Name DAP DRP DSP DFP DEV DMV CFL CFH Description of assembly of 28-bit data field (from msb down to lsb) 20-bit type0 active energy, 8-bit status (see Table 6) 20-bit reactive energy, 0, 1, 6-bit upper f(u) 20-bit apparent energy, 8-bit lower f(u) 20-bit type1 active energy, 8-bit mode signals 1-bit padding, 11-bit uRMS, 16-bit iRMS 1-bit padding, 11-bit uMOM, 16-bit iMOM (momentary values) 28-bit lower part of configurators 28-bit upper part of configurators
The metering device computes wide-band active energy, up to 50th harmonics, which is type0 by default and fundamental harmonic active energy. The FUND should be used to select which becomes type0 or type1. Signals for stepper are always generated by the type0 active energy.
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Table 6 : Meaning of status bits in the 1.1. data records
G.R. 0 1 2 3 4 5 6 7 Name BIL BCF BFR BIT MU X LIN PIN HLT Meaning of status bit value 0 no load condition not detected both signals alive fCLKOUT /217 < f(u) < fCLKOUT/215 Meaning of status bit value 1 no load condition detected one or both signals stacked f(u) out of limits tamper is detected selected secondary current channel negative half period of u at least one pin differs from data retarded restart in progress
tamper is not detected selected primary current channel positive half period of u output pins follow data data are valid
Before the reading task, a host should request the latching of all internal results (energies, RMS, MOM and frequency values plus status) into internal transmission latches as values for the first six data records. A reading task should start after an assertion of SCS=0. If it would be completed or aborted, it could be repeated until a next latching is requested. The reading task can be aborted at any time by some send task or by dissertation of SCS. The actual data reading is performed when SCS=0, SYN=1 by applying eight SCL clocks per byte of data on SDA. By default, the byte is serialized with the most significant bit (msb) first, unless MSBF is set, when the least significant bit (lsb) comes first. A bit can change at negative edge and is stable on positive edge of SCL. See the middle of Figure 2 above which shows the MSBF=0 case. For one data record, 32 SCL clock cycles must be applied. After that, an internal pointer to data records (G.R.) is automatically incremented in order to select the next data record from Table 5 A PR command would change the group segment of the pointer and preset its record segment to 1. 3.3 - Processing of data record Every data record is 4-byte long. The 1st read out byte of the data record is the Least Significant Byte (LSB) of the data value. Each byte can be further divided into a most and least significant nibble (msn, lsn). This division makes sense with the 4th byte of data value because the msn of it holds the parity code rather than useful data. This means that every data record consists of 4-bit parity code and 28-bit data value where the parity code is computed from the data value which makes a total of 32 bits or 4 bytes. Figure 3 below shows top to down how bits and bytes of data record appear on the SDA and how they should be unpacked by a host. Figure 3 : Construction of data
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3.3.1 - Data integrity checks Each bit of parity nibble is defined as an odd parity of all seven corresponding bits of data nibbles. In order to check the data record integrity, the application might execute the following C code, given as an example: int BadParity (unsigned char *bp) { register unsigned char prty; /* temporary register */ prty = *bp, /* take the 1st byte of data */ prty ^= *(bp+1), /* xor it with the 2nd byte */ prty ^= *(bp+2), /* and with the 3rd byte */ prty ^= *(bp+3), /* and with the 4th byte */ prty ^= prty<<4, prty &= 0xF0; /* combine and remove the lower nibble */ return (prty != 0xF0); /* returns 1, if bad parity */ } if (BadParity(dap) || BadParity(drp) ||/* 1.1. and 1.2. data record */ BadParity(dsp) || BadParity(dfp) ||/* 1.3. and 1.4. data record */ BadParity(dev) || BadParity(dmv) ||/* 2.1. and 2.2. data record */ BadParity(cf1) || BadParity(cf2)) /* 2.3. and 2.4. data record */ /* code for repeat of reading sequence should be entered here */ ; If the check of parity nibble failed, the reading task should be repeated but this time without request for latching, otherwise a new data would be latched into transmission latches and, incorrectly read, one would be lost. In a very hash EMI environment, it would be a good practice to read the data records twice and then compare both readings. This way the probability of detection of bad readings would be improved significantly. Anyway, the bad data can be discarded because no meaningful information is lost as long as the frequency of reading is about 30 readings of all data records per second. If one wants to collect the readings of momentary values in order to compute a FFT, the frequency of reading of the 2.2. data record should be much higher and no bad readings should be detected. 3.3.2 - Unpacking of data records After some data record is read correctly, its parity nibble and possible padding bits should be masked out and then it should be unpacked to several values on the boundaries indicated in Table 5. This is easy because those boundaries are always on some byte boundary. The momentary values of current or A bit complicated case is with configuration read back data records (2.3. and 2.4.). Those values can be stored into a pair of 4-byte registers but actually they would fit into a 7-byte register, if the value of the 2.4. data record was shifted 4 bits and correctly appended to the value of the 2.3. data record. Such a solution would make sense, if the RAM space is critical or if download was conducted later. Let us say that we read from the module the following eight data records represented as hexadecimal bytes while MSBF was cleared: 1.1. 65 7A 7C 82: parity=8, type0_energy=27C7A, sts=65 1.2. 52 7A 0C 90: parity=9, react_energy=00C7A, frqH=52 1.3. 25 00 8C E2: parity=E, appar_energy=28C00, frqL=25 1.4. 00 06 6E 22: parity=2, type1_energy=26E06, mode=00 2.1. BB B3 07 DD: parity=D, iRMS=1B3BB, uRMS=638 2.2. 3F AF AA CA: parity=C, iMOM=AF3F, uMOM=AAA 2.3. 01 00 00 E0: parity=E, cfgL=0 0 001 2.4. 00 00 00 F0: parity=F, cfgH=0 0 000
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Let us check the parity code of the 1.1. data record above. The following steps should be performed using temporary variable named HL: 1. load the 1st byte into HL: HL = 65 2. exor HL with the 2
nd
= 0110 0101 2
byte: HL = 65^7A = 0110 0101 2 ^ 0111 10102
3. exor HL with the 3rd byte: HL = 1F^7C = 0001 1111 2 ^ 0111 11002 4. exor HL with the 4th byte: HL = 63^82 = 0110 0011 2 ^ 1000 00102 5. exor HL with HL<<4: HL = E1^10 = 1110 0001 2 ^ 0001 00002 6. and HL with 0xF0: HL = F1&F0 = 1111 0001 2 & 1111 00002 7. compare HL with 0xF0: HL = F0 = 1111 0000 2 Using the steps above, one can see that the 1.4. data record wasn't read correctly. An alternative way to check the parity is to verify the value of HL after step 4, underlined in the example above. The parity check will pass, if the content of HL is member of set {0F 1E 2D 3C 4B 5A 69 78 87 96 A5 B4 C3 D2 E1 F0}. 3.3.3 - Usage of energy values W ithin the metering device the sources of energy values are implemented as 20-bit Up/Down counters. This means that the value of such a counter will eventually rollover, if the direction of power is not changing too often which is normally the case. For example, if the maximal possible positive power (360V*33A = 12kW) was measured with the module, the internal counter would count up and reach its maximal value (0xFFFFF) in about 1.6 second then the value would rollover to zero (0x0 0 0) at once and start to count up again. A saw tooth shape of values would be produced this way, see Figure 4. For the negative power, the counter would count down, of course. The slope of shape is proportional to the measured power which may change its value and direction in any moment. Also, if the power was absolutely less than No Load Condition limit, selected by LTCH, the counter would stop. The least significant bit of counter represents 2/220 Wh for wide-band active energy, 2/220 VAh for apparent energy, 4/220 varh for reactive energy and 8/220 Wh for fundamental active energy. An application should recognize rollovers. A rollover from high to low should be recognized, if the msn of the energy value of two consecutive readings changed from 0xF to 0x0 or, if a change from 0x0 to 0xF was detected, a low to high rollover should be recognized. To ensure the detection of a change, an application should successfully read the energy values at least every 0.1 second but, for security reasons, at least 30 readings per second should be performed. Figure 4 : Typical profile of output of an energy integrator
Using an msn of energy value as a rollover code is convenient because it is stored in the msb of data record accompanied with the parity code. Therefore it is easily unpacked and checked for the characteristic values. When rollover is detected, a 0x0010 0 0 should be added to the energy reading with rollover code 0x0. This way, a subtraction of both energy readings would give a proper quant value
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which would fit into 2-byte register. Also, if the time difference of two consecutive readings is known, an applied power can be computed easily as: p = quant/t. In order to use the readings of energy, an application should allocate 2-byte registers quant and quot and 4-byte registers old, frac and integ per each type of energy. The integ and frac together form an integrator which would rollover in 980 years, if maximal allowable power (250V*20A = 5kW) was applied all the time. The C code below shows an example of handling an energy value after it was read, unpacked and stored into register new. For signed wide-band Active energy as an example, a pointer e should be loaded with &ActW B then, EnergyQuant() should be called. This function will check for rollover and compute a quant of energy and return its sign. Later, EnergyUpdate() should be called. This function will update the fractional part of the integrator first and if the fractional part reaches a certain limit, it will be subtracted from the fractional part and the integer part of the integrator will increment. The value of limit and direction of subtraction and increment depend on the sign of quant. Some applications may have positive and negative energy integrators or quadrant integrators for Apparent energy. All this influences an implementation of both functions. With a proper limit value for the fractional part, one can prescribe a suitable bit weight of the integer part of the integrator. For example, if limit is set at 0x0050 0 0, then the bit weight of the integer part will be exactly 0.01 kWh of positive wide-band Active energy. The value of quant can be further divided by 16. A reminder of such division can be added to the fractional part immediately, while the quotient quot can be added later 16 times but faster. This means that every call to EnergyQuant() should be followed by 16 calls to EnergyUpdate(). A timer interrupt service routine is the best place to implement these calls. This way, the output pulse generation of the signal LED, which is used for meter accuracy check, with 2 ms resolution is possible. /* definition of constant */ #define LIMIT 0x0050 0 0L /* produces 0.01 kWh resolution */ /* definition of energy_integrator */ typedef struct energ { long int old; /* previous energy value */ int quot; /* quant/16 */ int quant; /* new - old, measure of power */ long int frac; /* fraction part of energy integrator */ long int integ; /* integer part of energy integrator */ } ENERG; /* allocation for all types of energies */ long int new; /* energy value to be handled */ ENERG *e; /* ->energy_integrator */ ENERG ActWB, ActFund, Reactive, Apparent; /* space for energy_integrators */ /* Energy quant computing function (version for signed energy integration) Checks for rollovers and compute quant as difference between new and old value Returns a negative sign of quant */ int EnergyQuant(void) { register unsigned char A; /* local accumulator */ register unsigned char *X; /* local pointer to byte */ A = *(((unsigned char *)(e->old))+2);/* load old rollover code */ X = ((unsigned char *)(&new))+2; /* point to new rollover code */ if (A == 0x0F) /* possible HL rollover? */ { if (*X == 0x00) *X = 0x10; } /* yes, really? Yes, fix new value */ else { A = *X; /* no, load new rollover code */ X = ((unsigned char *)(e->old))+2; /* point to old rollover code */ *X &= 0x0F; /* unfix possibly fixed old */ if (A == 0x0F) /* possible LH rollover? */ { if (*X == 0x00) *X = 0x10; } /* yes, really? Yes, fix old value */
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} e->quant = (int)(new e->old); e->old = new; e->quot = e->quant & 0x000F; if (e->quant < 0) e->quot |= 0xFFF0; e->frac += (long int)e->quot; e->quot = e->quant >> 4; return(e->quant < 0);
/* /* /* /* /* /* /* /*
evaluate the difference */ save the value for next time */ reminder of quant/16 */ is quant negative? */ yes, make reminder negative */ add reminder to frac */ quotient of quant/16 */ return true if quant is negative */
} /* Energy update function (version for signed energy integration) If quant is negative, subtract otherwise add its value from the integrator Returns true when frac reaches the LIMIT */ int EnergyUpdate(void) { e->frac += (long int)e->quot; /* add quot to frac */ if (e->quant < 0) /* is quant negative? */ { if (e->frac > -LIMIT) return(0); /* yes, is within the limit? */ e->frac += LIMIT, (e->integ)--; /* no, subtract it and increment */ } else { if (e->frac < LIMIT) return(0); /* no, is within the limit? */ e->frac -= LIMIT, (e->integ)++; /* no, subtract it and increment */ } return(1); /* return limit has been reached */ } If the RAM space or execution time is critical, a 3-byte registers could replace long int ones and functions above could be written in an assembler language. 3.3.4 - Usage of other values Because all values are measured with an almost ideally linear metering device, it is easy to get all the necessary constants which would convert the integer values into meaningful physical values. This can be done by measuring known signals.
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4 - TECHNICAL PARAMETERS 4.1 - Electrical parameters The following table summarises the electrical parameters, which are specified for VCC=3.6V, TAMB=+25C, unless otherwise noted. Table 7 : Electrical parameters
Symb Parameter Test Conditions or Comments Min Typ Max Units
Target applications VNOM FL INOM IMAX TAMB Nominal line voltage Nominal frequency Nominal line current Maximal line current Ambient temperature Class of accuracy Digital inputs IIL VIL VIH Pull up Voltage input low Voltage input high Valid also for IO pins when they are used as inputs 15 -0.3 0.75VCC 0.25VCC 5.3 A V V -40 140 45 220 50 2 20 25 0.2 30 85 0.5 300 65 VRMS Hz ARMS ARMS C
Digital outputs VOL VOH tTR Voltage output low Voltage output high Transition time IOL=+2mA IOH=+2mA CL=50pF, VCC=3.2V VCC-0.4 5 0.4 V V ns
Stepper outputs VOL VOH tTR Voltage output low Voltage output high Transition time IOL=+14mA IOH=+14mA CL=50pF, VCC=5.0V 0.9VCC 5 0.1VCC V V ns
OTP programming VVOTP VVOTP IVOTP tWE No programming level Programming level Programming current Programming time To program 1 bit at a time To program 1 bit at a time Internally generated 14 1.0 100 1.5 200 VDDA-0.65 20 3.0 300 V V mA s
Power supply VCC ICC V DDA FL VCCPOR Supply level Quiescent current Supply level Nominal frequency Power on reset No loads CL=100nF, VCC=3.2V 3.165 4 2.85 45.0 3.6 5 3 50.0 2.5 5.5 6 3.15 65.0 V mA V Hz V
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Table 7 : Electrical parameters
Symb Parameter Test Conditions or Comments Min Typ Max Units
SPI interface timings fSCL fSCL tDS tDH tON tOFF tSYN Data read speed Data write speed Data set up time Data hold time Data driver on time Data driver off time SYN active width 1000 20 0 20 20 2 32 100 MHz kH z ns ns ns ns ns
4.2 - Mechanical outlines The size of PCB of the module can be seen from an appended drawing. The overall volume is determined by the size of maximal element that is an electrolytic capacitor: L x W x H = 70 mm x 46 mm x 23 mm. The poles of shunt exceed the boundary of PCB by 18 mm.
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5 - APPENDIX 5.1 - Migrate the power line system from 220V, 50 Hz into 110 V, 60 Hz. With capacitive power supply the impedance of capacitor C1 and impedance of load ((Vcc+0.7)/(Icc+Iz)) are used to form a voltage divider. All other elements serve some other reasons, such as spike protection and HF rejection. Therefore, we can use the following guidelines: If the line frequency is changed for some percentage, the Icc is changed for the same percentage, that is df/f = dIcc/Icc. For a 60Hz system there will be 20% more current available because the impedance of C1 is the mayor component of the divider, the change of input voltage must be followed practically with the same change of impedance of C1, that is dU/U = dZc/Zc. For a 110V system, the capacitor C1 needs almost to be doubled, the divider must be designed to work properly at minimal line voltage, frequency and C1 and maximal Icc and therefore, the maximal allowable power consumption (500 mW > Iz*Vcc) of Zener diode D12 must be checked at maximal line voltage, frequency and C1 and minimal Icc. According to the information pointed out below, for the change of power line system from 220V, 50Hz into 110V, 60 Hz, the value of C1 should be changed from 470 nF, 275VAC into 750 nF, 150VAC. With 680 nF, 150VAC element only which means about 10% less Icc. No other change to the metering module is necessary because the voltage measurement range is 20 - 360 Vrms. But, we would like to warn that the current measurement range stays 0.1 - 20 Arms, at most 30 Arms. If you need a wider current range, the current transformers and the cross-section of primary winding wires must be increased, which is a bit difficult because they would become bigger and therefore, would not fit onto board of the module. In this case, the module would need to be recalibrated t oo.
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Figure 5 : Schematic
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Figure 6 : Mechanical dimensions of PCB
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Table 8 : BOM
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 24/27 Code R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R21 R25 R26 V1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C13 C14 D1 D2 Description of component RESISTOR MPL 0102*1K F 50 RESISTOR MPL 0102*1K F 50 RESISTOR MPL 0102*1K F 50 RESISTOR MPL 0102*1K F 50 RESISTOR MPL 0102*475R F 50 RESISTOR MPL 0102*475R F 50 RESISTOR MPL SOD 80*261K F 50 RESISTOR MPL SOD 80*261K F 50 RESISTOR MPL SOD 80*261K F 50 RESISTOR MPL 0102*681K F 50 RESISTOR DPL 0603*6K8 J 200 RESISTOR DPL 0603*2K4 J 200 RESISTOR DPL 0603*6K8 J 200 RESISTOR DPL 0603*6K8 J 200 RESISTOR MPL 0102*100 F 50 RESISTOR MPL 0102*1M F 50 RESISTOR DPL 0603*0R J 200 RESISTOR WIRE SFR0518 P5 2W*82R K RESISTOR MPL 0102*42,2K F 50 RESISTOR MPL 0102*2M F 50 RESISTOR DPL 0603*0R J 200 RESISTOR DPL 0603*0R J 200 VARISTOR MOKS K10*300V CAPACITOR X2 12x21x32/11M*470n 275V K CAPACITOR KER X1/Y2 9X5/3M*1.0N 440/330 CAPACITOR AL-RILL 13x22/2M*1000my 25V CAPACITOR VP 0603X5R*1MY 10V K CAPACITOR VP 0603X5R*1MY 10V K CAPACITOR VP 0603X5R*1MY 10V K CAPACITOR VP 0603X5R*1MY 10V K CAPACITOR VP 0603X7R*10n 50V K CAPACITOR VP 0603X7R*10n 50V K CAPACITOR VP 0603X7R*22n 16V K CAPACITOR VP 0603 NPO*22p 50V J CAPACITOR VP 0603 NPO*22p 50V J DIODE ZENER ZMM SOD 80*5.1V G DIODE LED SMD2,5X2 K30*SRD 200mCD
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Table 8 : BOM
Item 38 39 40 41 42 43 44 45 46 47 Code D3 D4 D5 D6 RS1 L1 L2 Y1 U1 P1 Description of component DIODE LED SMD2,5X2 K30*SRD 200mCD DIODE LED SMD2,5X2 K30*SRD 200mCD DIODE LED SMD2,5X2 K30*SRD 200mCD DIODE RECTIFIER BRIDGE SMD*600V 1A SHUNT 420uOHM, 20A INDUCTOR VF82423 1812*220myH 0,1A INDUCTOR VF82423 1812*1myH 0,145A CRYSTAL 4,194304MHz HC49/US -20/70 INTEGRATED CIRCUIT STPM01FTR*SO20-4,4 P I CONNECTOR G08 PTIV 5,8*10-2
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6 - REVISON AND LEGAL INFORMATION Table 9 : Revision History
Date 22-Feb-2005 Revision 1 First Release. Description of Changes
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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