UM0244 User manual
FlashLINK JTAG programming cable for STR9
Features
Allows PC or Notebook parallel port to program STR91x devices using Configuration and Programming Software (CAPS) development tool. Supports IEEE 1149.1 JTAG signals (JTCK, JTMS, JTDI, JTDO, JTRST). Supports additional signal (JRTCK) to pace the JTCK clock signal coming in from the external JTAG test equipment for debugging. Single FlashLINK Cable assembly supports both 3.3V and 5V target devices with no manual configuration. Target device may operate from 2.7V to 5.5V. "Flying Lead" cable included to adapt to any target connector using 0.025" square posts. "LoopTest" cable included to validate PC parallel port operation.
January 2007
Rev 2
1/11
www.st.com
Contents
UM0244
Contents
1 2 3 4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin definition on FlashLINK adaptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connector definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1 Diagnostic tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1.1 4.1.2 Loop test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Connect test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
Circuit example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Appendix A FlashLINK schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
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UM0244
Overview
1
Overview
The family of STR91x devices offer In-System Programming (ISP) allowing a completely blank device to be programmed while soldered to a circuit board. This simplifies manufacturing and provides an effective way to update products after they are in use. STR91x devices comply to the core requirements of the IEEE 1149.1 JTAG specification. The FlashLINK cable assembly shown in Figure 1 will perform ISP only on STR91x devices, not memory or logic devices from other vendors. The software development tool Configuration and Programming Software (CAPS) is a Windows based program which operates the FlashLINK cable assembly (CAPS may be downloaded at no charge from www.st.com/mcu). CAPS will generate JAM STAPL and SVF files for use with 3rd party JTAG programming equipment. The five basic JTAG pins (JTCK, JTMS, JTDI, JTDO, JRST) on STR91x devices are dedicated to operate as JTAG pin at all times. Figure 1. FlashLINK cable assembly
Mates with PC parallel por t
Flying lead cable
DB-25 Cable
6 feet
FlashLINK Adapter
6 inches
12 WIRES
Target device
DB-25 Cable, M-F straight-through wiring
AI08862
Note:
14-pin ribbon cable may also be used.
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Pin definition on FlashLINK adaptor
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2
Pin definition on FlashLINK adaptor
Table 1.
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Pin Description for 14-pin FlashLINK Adaptor Connector
Description Generic Control Signal JTAG IEEE 1149.1 Reset on target, active-low JTRST Signal Ground Generic Control Signal JTAG IEEE 1149.1 Serial Data Input - JTDI OC Source Source Destination Type(1) OC OC FlashLINK is Signal: Source Source
Signal Name JEN(2) TRST GND(3) CNTL TDI
(2)
TSTAT/JRTCK JTAG-ISP to pace JTCK clock signal - JRTCK VCC
(4)
DC source from target, 2.7V to 5.5V Target system reset, active-low JTAG IEEE 1149.1 Mode Select - JTMS Signal Ground JTAG IEEE 1149.1 Clock - JTCK Signal Ground JTAG IEEE 1149.1 Serial Data Out - JTDO Generic Data Out Signal Destination Destination Source OC Source Source
RST TMS GND TCK GND TDO TERR(2)
Note:
1 2 3 4
OC = Open Collector, pulled-up to VCC inside FlashLINK Adaptor. Not supported by CAPS, signals remain inactive. All signal grounds are tied together inside FlashLINK Adaptor. The target must supply VCC to the FlashLINK Adaptor (2.7V to 5.5VDC, 15mA max at 5.5V). Not all 14 signals are required for all applications. Here is how they are used:
(8) Core signals that must be connected: TDI, TDO, TMS, TCK, TRST, RST, VCC, GND (1) Optional signal to pace TCK: TSTAT/JRTCK (2) Optional generic control signals to target system from FlashLINK: JEN, CNTL (1) Optional generic data out signal from target system to FlashLINK: TERR (2) Two additional ground lines to help reduce EMI if a ribbon cable is used. These ground lines "sandwich" the TCK signal in the ribbon cable. These two ground signals are not present on the flying lead cable.
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UM0244
Connector definition
3
Connector definition
There is no industry standard JTAG connector. Each device manufacturer differs. ST has a specific connector and pinout for the FlashLINK Adaptor. The connector scheme on the FlashLINK connector can accept a standard 14-pin ribbon cable connector (2 rows of 7 pins on 0.1" centers, standard keying) or any other user specific connector that can slide onto 0.025" square posts. The pinout for the FlashLINK Adaptor connector is shown in Figure 2. A standard ribbon cable is a good way to quickly connect to the target circuit board. If a ribbon cable is used, then the receiving connector on the target system should be the same connector type with the same pinout as the FlashLINK Adaptor shown in Figure 2.
Note:
The JTAG signal JTDI is sourced from the FlashLINK Adaptor and should be routed on the target circuit board so that it connects to the JTDI input pin of the STR91x device. The JTAG signal JTDO is an input received by the FlashLINK Adaptor and is sourced by the STR91x device on its JTDO output pin. See Figure 3 on page 8, and Figure 4 on page 9 for more information. Figure 2. Pinout for FlashLINK Adaptor and Target System JTAG connector
14 TERR 12 GND 10 GND 8 RST 6 TSTAT/JRTCK 4 CNTL 2 TRST
13 TDO(1) 11 TCK 9 TMS 7 Vcc 5 TDI(2) 3 GND 1 JEN KEY WAY
AI08867
Note:
This diagram perspective is looking into the face of the shrouded male connector on the FlashLINK Adaptor, 0.025-inch (0.635mm) posts on 0.100-inch (2.54mm) centers. Connector reference: Molex 70247-1401. Recommended ribbon cables for quick connection of the FlashLINK Adaptor to the endproduct: Samtec HCSD-07-D-06.00-01-S-N; Digikey M3CCD-14065-ND.
Note:
1 2
TDO is a signal destination on the FlashLINK and a signal source on the target board. TDI is a signal source on the FlashLINK and a signal destination on the target board.
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Software
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4
Software
The FlashLINK cable assembly is driven by the software development tool CAPS (available at no charge from www.st.com/mcu). With this tool you define the pin functions, memory map, and configuration of STR91x devices, add microcontroller firmware to be programmed into Flash memory, then generate a single file to program into the device (an object file with the filename extension *.obj). CAPS will then use the FlashLINK cable assembly to program this object file into the STR91x device. Other operations include erase, verify, upload, and blank check. See the CAPS User Manual for more detail.
Note:
Be sure to use the latest version of CAPS. Updates are available from www.st.com/mcu.
4.1
Diagnostic tests
CAPS also performs some diagnostic tests for the PC parallel port and FlashLINK cable assembly.
4.1.1
Loop test
Should be run first to test basic operation of the PC parallel port and the FlashLINK cable assembly. "LoopTest" will wrap FlashLINK signal outputs back into FlashLINK signal inputs for signal path verification.
4.1.2
Connect test
Is optional to test system performance and check the JTAG signal path all the way through the target circuit board including STR91x device. To run these tests, install and run CAPS on your PC or laptop: 1. 2. 3. Connect the six foot long DB-25 cable to your PC parallel port on one side, and to the FlashLINK Adaptor on the other side. Click mouse on the "Program Device" box at the bottom-left of the CAPS main flow diagram. Select single or multiple JTAG devices depending on your target configuration (single is most common), then click on the Hardware Setup ("HW Setup") button at the lower part of the JTAG Operations window. Connect the small loop test adaptor cable (not the flying lead cable) to the 14-pin connector on the FlashLINK Adaptor. Connect the red lead of the loop test connector to a VCC source (5V or 3.3V), and connect the black lead of the loop test connector to ground. In the "HW Setup" dialog screen click the "Loop Test" button to run the test. If it fails, be sure that your are supplying VCC and ground, and also make sure that the PC's parallel port is enabled.
For "LoopTest": 1. 2. 3.
For "Connect Test":
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UM0244 1. 2.
Software Connect the "Flying Lead" cable, or a ribbon cable to the FlashLINK Adaptor, and also connect it to your target circuit board just as if you are ready to program the device. Turn on the power on the target device, and then click the "Connect Test" button in the "HW Setup" dialog screen.
This test involves the circuit traces on your circuit board. If there is a failure, it is likely due to signal routing or signal integrity on the target circuit board, or the PC may have compatibility problems with the parallel port driver used by CAPS. Note: If either test fails, you will see a window pop-up that allows you to email in the problem. Please do so and we will assist you.
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Circuit example
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5
Note:
Circuit example
The recommended pull-up resistors and decoupling capacitor are near the JTAG connector. Figure 3. Circuit example
SIGNAL DIRECTION DURING JTAG OPERATION
USER PC BOARD
100k
100k 100k 100k
10k JTAG CONN. JTMS JTCK
JTMS JTCK
JTDI JTDO 0.01 F
JTDI JTDO Vcc
STR91x
GND RST
SYSTEM RESET CIRCUITRY (connect directly to reset input signal on STR91x)
AI08864
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UM0244
Appendix A
Figure 4.
VCC R3 100K 19 G U1B
VCC
R9 10K
J1
R20 R21 R22 R23 47 47 47 47 GND 1 G 74AC240 R43 JEN 47 R10 10K C100 100P C2 100P C3 100P C1 100P 74AC240 11 A1 13 A2 15 A3 17 A4 12 Y4 14 Y3 16 Y2 18 Y1 TCK TMS TDI
2 3 4 5 6 7 10 11 12 14 15 18 VCC 4 2 5 VCC 1 3 6 Q2 9013
PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 PIN10 PIN11 PIN12 PIN14 PIN15 GND
9 Y1 7 Y2 5 Y3 3 Y4 R40 R41 47 2 R4 47 47
U1A 8 A4 6 A3 4 A2 2 A1
DB25-12P
R5 4k7 R7 4k7 U2D DM54ALS05A 47 U2E DM54ALS05A 47 U2F DM54ALS05A 47 U2C DM54ALS05A 47 U2B DM54ALS05A 47 U2A DM54ALS05A 1 R39 47 C4 100P C5 100P C6 100P VCC R8 R11 10K 4K7 1N4148 D1 D2 1N4148 VCCA 47 6 3 R2 470K 4 5 2 Q1 9013 1 47 2 4 3 6 5 R37 47 R38 47 13 12 R35 47 11 10 R34 47 9 8 R36 47 R1 470k R17 100K R15 100K R16 100K R19 10K R18 10K
R6 4k7
R33 10K
VCC
DB25/2 DB25/3 DB25/4 DB25/5 DB25/6 DB25/7 DB25/10 DB25/11 DB25/12 DB25/14 DB25/15 DB25/18
TCK TMS TDI JEN TRSTN RSTN TSTAT VCC TDO CNTL TERR GND
R25
TRSTN
C7 104P
C8 104P
FlashLINK Adaptor Schematic
FlashLINK schematic
R26
RSTN
R27
CNTL
R28
TSTAT
R29
VCCA
TDO
D10 LED
R31
TERR
R32
J2 D3 R14 10 R4 100K D4 6.2V C10 105P 1N5817 JEN GND TDI VCCA TMS TCK TDO 1 3 5 7 9 11 13 2 4 6 8 10 12 14 HEADER 7X2
FlashLINK schematic
R30 470
TRSTN CNTL TSTAT RSTN GND GND TERR
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Revision history
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Revision history
Table 2.
Date 25-May-2006 30-Jan-2007
Document revision history
Version 1 2 Initial revision Figure 4: FlashLINK Adaptor Schematic updated Revision Details
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UM0244
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