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UM0411 User manual
STw5098 evaluation board
Introduction
The STW5098/E01 board is an evaluation board to implement an STw5098 CODEC from STMicroelectronics. On this board, all of the device's resources are made available to permit an easy connection of user devices, inputs and outputs.
All of the digital interfaces are provided on a standard female header to drive the device with a remote programmable device, MCU or part of any other application. All of the analog inputs and outputs are made available on headers or audio 3.5mm jacks for direct connection to headphones and microphones.
Since the power supplies of the device are split and multiple (analog, digital, digital I/O) each section can be powered individually by separate external power supplies. In addition, this evaluation board can be driven with a generic digital board supplied by STMicroelectronics. Figure 1. STw5098 evaluation board
April 2007
Rev 1
1/30
www.st.com
Contents
UM0411
Contents
1 Main components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 1.2 1. 3 1. 4 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Analog outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Digital control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4.1 1.4.2 1.4.3 1.4.4 STw5098 control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 STw5098 audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PLL control (ICS525) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Level shifter control (74LVC4245A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5
Jumpers and switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.1 1.5.2 1.5.3 1.5.4 1.5.5 Power supply jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Analog input jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Analog outputs jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Bias micro jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 HDET jumpers and switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2 3
Board schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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Main components
1
Main components
See Figure 2: Main components. Table 1.
Component IC1 U1000 MK1,MK2, MK3,MK4 IC13 IC14,IC15 IC6, IC7,IC11,IC12 IC2 58EM100T
Main components
Reference STW5098 Description Low power asynchronous stereo audio codec with integrated power amplifiers Socket Microphone
74LVX1G125 Single buffer driver LF27CDT 74LX1G07 ICS525 Regulators Single buffer driver Generate a high quality, high accuracy, high frequency clock output from a clock input.
IC3,IC4,IV5,IC8,IC9,IC10 74LVC4245A Octal dual supply translating ESD1,ESD2,ESD3, ESD4,ESD5,ESD6 ESDA5V3L Dual transit array for ESD protection
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Main components Figure 2. Main components
Clock generator
UM0411
Buffer (IC6, IC7, IC11, IC12)
Buffer (IC13)
Level shifters (IC14, IC15)
Level shifters A_Microphone Optional socket
STw5098
B_Microphone
ESD ESD
PM00131
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UM0411
Main components
1.1
Figure 3.
Power supply
Power supply
VCC_3V3 (Pins 1 & 63)
GND VCC_ANALOG MAIN_VCC VCC_CORE VCC_LS VCC_P
PM00132
Power is supplied to the STW5098 board by an external power supply which must be capable of providing up to 100 mA of current. Connection is made using a standard 2mm female banana jack.
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Main components
UM0411
The power supply connectors (Main_VCC, VCC_ANALOG, VCC_CORE and VCC_P, VCC_LS) can be connected to the same power supply in the range 2.4 V to 2.7 V or each connector can be powered individually by separate external power supplies. Please refer to the STw5098 datasheet for operating ranges. Table 2.
Signal
Power supply
Connector Description
MAIN_VCC (VCC_IO)
Power supply connector for 74LVC4245A, 74LX1G07. Female banana jacks Power supply connector for the STw5098 digital I/O 2mm (VCC_IO) buffers when jumper JP39 is ON. Operating ranges: 1.2 V to 1.8 V and from 1.71 V to VCC. Power supply connector for the STw5098 analog section. Female banana jacks Standard operating range: 2.7 V to 3.3 V 2mm Low voltage (LV) range: 2.4 V to 2.7 V Female banana jacks Power supply connector for the STw5098 digital section. 2mm Operating range: 1.71 V to 2.7 V Power supply connector for the STw5098 left and right Female banana jacks output drivers (headphones and line-out). 2mm Operating range: VCC_ANALOG to 3.3 V Power supply connector for the STw5098 mono differential Female banana jacks output driver. 2mm Operating range: VCCA_ANALOG to 5.5 V HE10 64 F C Pins 1& 63 Power supply connector for the 74LVC4245A, 74LX1G07 and ICS525.(optional for STw5098)
VCC_ANALOG
VCC_CORE
VCC_P
VCC_LS
VCC_3V3
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UM0411
Main components
1.2
Analog inputs
The evaluation board supports ten analog inputs and four inputs can be used simultaneously (AUX1_A, AUX2_A, AUX3_A, LINE_IN_A, MICRO_A, AUX1_B, AUX2_B, AUX3_B, LINE_IN_B, MICRO_B) and one clock signal (AMCK_EXT). All signals are AC coupled before being input to the STw5098 except AMCK_EXT when the digital square wave is applied (see Figure 4).
Figure 4.
Analog inputs
A_Micro_Right Diff A_Micro_Left Diff B_Micro Right Diff B_Micro_Left Diff
AMCK_EXT A_Line_In Right & Left
Jack stereo A_Aux B_Aux1
Jack stereo B_Aux1 B_Line In
Jack stereo B_Line In A_Line In
Jack stereo A_Line In
B_Aux3 Right & Left A_Aux3 Right & Left A_Aux2 Right & Left Diff B_Aux2 Right & Left Diff PM00133
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Main components Table 3.
Signal
UM0411 Master clock input
Connector Description Master clock input connectors. Accepted range: 4 MHz to 32 MHz. According to CR30 configuration the inputs accept digital square wave (operating ranges: 0.5 V to VCC_IO) or analog sine wave. Refer to the STw5098 datasheet for more detail.
AMCK_EXT
SMB
Table 4.
Signal
Analog inputs CODEC A
Connector Description SMB SMB SMB SMB SMB Right and left channel single ended connectors for microphone or line input. AUX2 right channel differential connectors for microphone or line input. AUX2 left channel differential connectors for microphone or line input. Right and left channel single ended connectors for microphone or line input. Right and left channel single ended connectors for line input.
A_AUX1 Right &Left A_AUX2 Right Diff A_AUX2 Left Diff A_AUX3 Right &Left A_Line In Right &Left Jack stereo A_Line In A_Micro Right Diff A_Micro Left Diff
Jack stereo Jack stereo 3.5mm for line input. 3.5mm SMB SMB Right channel differential connectors for microphone input. Left channel differential connectors for microphone input.
Table 5.
Signal
Analog inputs CODEC B
Connector SMB SMB SMB SMB SMB Jack stereo 3.5mm SMB SMB Description Right and left channel single ended connectors for microphone or line input. AUX2 right channel differential connectors for microphone or line input. AUX2 left channel differential connectors for microphone or line input. Right and left channel single ended connectors for microphone or line input. Right and left channel single ended connectors for line input. Jack stereo 3.5mm for line input. Right channel differential connectors for microphone input. Left channel differential connectors for microphone input.
B_AUX1Right &Left B_AUX2 Right Diff B_AUX2 Left Diff B_AUX3 Right &Left B_Line In Right &Left Jack stereo B_Line In B_Micro Right Diff B_Micro Left Diff
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Main components
1.3
Analog outputs
The evaluation board supports six analog outputs (two LS: loudspeaker, two HP: headphone and two Line_out).
Figure 5.
Analog outputs
A_HP Left & Common A_HP_Right & Common Jack stereo A_HP
A_LS Right & Left
Jack stereo A_LS Right & Left B_Line out Left Diff B_LS Right & Left B_Line out Right Diff Jack stereo B_LS Right & Left
Jack stereo B_Line out
A_Line out Left Diff
A_Line out Right Diff
Jack stereo B_HP Jack stereo A_Line Out
B_HP Left & Common B_HP Right & Common
PM00134
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Main components Table 6.
Signal
UM0411 Analog outputs codec A
Connector Description Analog differential loudspeaker amplifier output for left channel or right channel or the sum of both. This output can drive 50nF (with series resistor) or directly an earpiece transductor of 8; it can deliver up to 500mW.
A_LS Right &Left
SMB
Jack stereo A_LS
Jack stereo Single ended audio differential loudspeaker 3.5mm SMB Audio differential line out amplifier for left channels. This output can drive up to 1 K resistive load. Can be used as single ended outputs. Audio differential line out amplifier for right channels. This output can drive up to 1 K resistive load. Can be used as single ended outputs.
A_Line out Left Diff
A_Line out Right Diff
SMB
Jack stereo A_Line Out
Jack stereo Single ended audio differential line out 3.5mm SMB Audio single ended headphones amplifier outputs for left channel. The outputs can drive 50 nF (with series resistor) or directly an earpiece transductor of 16. Audio single ended headphones amplifier outputs for right channel. The outputs can drive 50 nF (with series resistor) or directly an earpiece transductor of 16.
A_HP Left&Common
A_HP Right&Common
SMB
Jack stereo A_HP
Jack stereo Audio single ended headphones amplifier outputs 3.5mm
Table 7.
Signal
Analog outputs codec B
Connector Description Analog differential loudspeaker amplifier output for left channel or Right channel or the sum of both. This output can drive 50nF (with series resistor) or directly an earpiece transductor of 8. It can deliver up to 500 mW.
B_LS Right &Left
SMB
Jack stereo B_LS
Jack stereo Single ended audio differential loudspeaker 3.5mm SMB Audio differential line out amplifier for Left channels. This output can drive up to 1 k resistive load. Can be used as single ended outputs. Audio differential line out amplifier for right channels. This output can drive up to 1 k resistive load. Can be used as single ended outputs.
B_Line out Left Diff
B_Line out Right Diff
SMB
Jack stereo B_Line Out
Jack stereo Single ended audio differential line out 3.5mm SMB Audio single ended headphones amplifier outputs for left channel. The outputs can drive 50 nF (with series resistor) or directly an earpiece transductor of 16.
B_HP Left&Common
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UM0411 Table 7.
Signal B_HP Right&Common
Main components Analog outputs codec B
Connector Description SMB Audio single ended headphones amplifier outputs for right channel. The outputs can drive 50 nF (with series resistor) or directly an earpiece transductor of 16.
Jack stereo B_HP
Jack stereo Audio single ended headphones amplifier outputs 3.5mm
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Main components
UM0411
1.4
Figure 6.
Digital control
Digital control
JH1
J5 JH1: HE10 64
PM00135
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UM0411 Table 8. Digital control
Connector JH1 J5 Header 32x2 Header 8x2 Description HE10 64 F C
Main components
Probes STw5098 digital control signal
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Main components
UM0411
1.4.1
STw5098 control interface
The STw5098 can be programmed by writing to control registers with an SPI or I2C compatible control interface. To select one of them, the CMOD pin is used:
CMOD pin connected to GND: I2C compatible mode selected. CMOD pin connected to VCC_IO: SPI compatible mode selected.
Please refer to the STw5098 datasheet for more detail. Table 9.
Name Irq_a
STw5098 interrupt
N Pin Type 44 Description
Digital output Programmable interrupt output. Active low signal.
Table 10.
Na m e Sda_out_a Sda_in_a As_csb_a Sclk_a
STw5098 I2C pins control
N Pin Type 43 39 51 47 Description
Digital output Control interface serial data output in I2C mode (SDA). Digital input Digital input Digital input Control interface serial data input in I2C mode (SDA). Control interface address select in I2C mode (AS). Control interface serial clock input.
Table 11.
Name Sda_in_a As_csb_a
STw5098 SPI pins control
N Pin Type 39 51 48 50 44 47 Digital input Digital input Description Control interface serial data input in SPI mode (SDIN). Interface enable signal in SPI mode (CSB).
AD_OCK_a or DA_OCK_a or IRQ_a Sclk_a
Digital output Control interface serial data out, if selected. Digital input Control interface serial clock input.
1.4.2
STw5098 audio interface
Master clock
Table 12.
Name Amck_app
STw5098 master clock
N Pin Type 5 Input Description Master clock input.
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UM0411
Main components
Audio interface codec A
Table 13.
Name Ad_ock_a da_ock_a da_data_a ad_data_a da_sync_a ad_sync_a a_da_ck a_ad_ck
STw5098 audio interface pins for codec A
N Pin Type 48 50 15 27 23 35 19 Digital input Digital input Description Oversampled clock out from A/D clock generator. Oversampled clock out from D/A clock generator.
Digital output / input Serial data out for stereo D/A converter. Digital output / input Serial data out for stereo A/D converter. Digital output / input Frame sync for stereo D/A converter. Digital output / input Frame sync for stereo A/D converter. Digital output / input Serial data clock for stereo D/A converter. Digital output / input Serial data clock for stereo A/D converter.
Audio interface codec B
Table 14.
Name Ad_ock_b da_ock_b da_data_b ad_data_b da_sync_b ad_sync_b b_da_ck b_ad_ck
STw5098 audio interface pins for codec B
N Pin Type 52 54 17 29 23 37 21 Digital input Digital input Description Oversampled clock out from A/D clock generator. Oversampled clock out from D/A clock generator.
Digital output / input Serial data out for stereo D/A converter. Digital output / input Serial data out for stereo A/D converter. Digital output / input Frame sync for stereo D/A converter. Digital output / input Frame sync for stereo A/D converter. Digital output / input Serial data clock for stereo D/A converter. Digital output / input Serial data clock for stereo A/D converter.
1.4.3
PLL control (ICS525)
Table 15.
Name R0->R6 S0,S1,S2 V0->V8 PLL_CLK
PLL pins control
N Pin Type 6:18 20:24 28:42 2 Input Input Input Output Description Reference divider word input pins determined by user. Forms a binary number from 0 to 127. Select pins for output divider determined by user. See table above. VCO divider word input pins determined by user. Forms a binary number from 0 to 511. Output clock determined by status of R0-R6, V0-V8, S0-S2 and input frequency.
Please refer to the ICS525 datasheet.
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Main components
UM0411
1.4.4
Level shifter control (74LVC4245A)
Table 16.
Name da_if_dir_a da_if_dir_b ad_if_dir_a ad_if_dir_b
Level shifter pins control
N Pin Type 58 60 56 64 Input Input Input Input Description Direction control Direction control Direction control Direction control
Please refer to the 74LVC4245A datasheet.
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Main components
1.5
Figure 7.
Jumpers and switches
Jumpers
PM00136
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Main components Figure 8. Jumpers and switches positions
UM0411
Jumper
ON 2-3
Switch
2-3
OFF
1-2 1-2
1.5.1
Power supply jumpers
Table 17. Main_VCC jumpers
Default
Jumper Description JP71 JP79 JP73 JP74 JP75 JP76 JP77 Connects the Main_VCC supply voltage to the VCC_IO. Always closed. Connects the regulator on the board to the VCC_ANALOG. Connects the regulator on the board to the VCC_IO. Connects the regulator on the board to the VCC_CORE. Connects the regulator on the board to the VCC_LS. Connects the regulator on the board to the VCC_P.
1.5.2
Analog input jumpers
Table 18. AMCK jumpers
Default
Jumper Description JP69 Connects the AMCK to external /internal clock.
GR7
Connects the AMCK to external /internal clock.
2-3
Table 19.
Aux2 jumpers a
Default
Jumper Description JP21 JP26 ON: single ended signal applied on AUX2_Right. OFF: diff signal applied on AUX2_Right. ON: single ended signal applied on AUX2_Left. OFF: diff signal applied on AUX2_Left.
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UM0411 Table 20. Aux2 jumpers B
Main components
Jumper Description JP22 JP25 ON: single ended signal applied on AUX2_Right. OFF: diff signal applied on AUX2_Right. ON: single ended signal applied on AUX2_Left. OFF: diff signal applied on AUX2_Left.
Default
Table 21.
Line in jumpers A
Default
Jumper Description JP23 Connects capacitor.
Table 22.
Line in jumpers B
Default
Jumper Description JP24 Connects capacitor.
Table 23.
Microphone jumpers codec A
Default
Jumper Description JP1 JP3 JP7 JP9 JP5 JP19 JP11 Connects the microphone to MIC_L_P. Connects the microphone to MIC_L_N. Connects the microphone to MIC_R_P. Connects the microphone to MIC_R_N. ON: single ended signal applied on Mic_Left. OFF: diff signal applied on Mic_Left. We can use this pins to connect the capacitors ON: single ended signal applied on Mic_Right. OFF: diff signal applied on Mic_Right.
Table 24.
Microphone jumpers codec B
Default
Jumper Description JP2 JP4 JP8 JP10 Connects the microphone to MIC_L_P. Connects the microphone to MIC_L_N. Connects the microphone to MIC_R_P. Connects the microphone to MIC_R_N.
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Main components Table 24. Microphone jumpers codec B (continued)
Default
UM0411
Jumper Description JP6 JP20 JP12 ON: single ended signal applied on Mic_Left. OFF: diff signal applied on Mic_Left. Connects capacitor. ON: single ended signal applied on Mic_Right. OFF: diff signal applied on Mic_Right.
1.5.3
Analog outputs jumpers
Table 25. Line out jumpers A
Default
Jumper Description JP56 JP60 JP55 GR4 Always closed. Always closed. Isolates the line-out left positive pin regarding the board. 1-2: diff signal applied on line_out_Left. 2-3: single ended signal applied on line_out_Left.
1-2
JP58 JP64 JP68 JP63 GR6
Connects different impedance loads. Always closed. Always closed. Isolates the line-out right positive pin regarding the board. 1-2: diff signal applied on line_out_Right. 2-3: single ended signal applied on line_out_Right.
1-2
JP66
Connects different impedance loads.
Table 26.
Line out jumpers B
Default
Jumper Description JP53 JP59 JP54 GR3 Always closed. Always closed. Isolates the line out left positive pin regarding the board. 1-2: diff signal applied on line_out_Left. 2-3: single ended signal applied on line_out_Left.
1-2
JP57
Connects different impedance loads.
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UM0411 Table 26. Line out jumpers B
Main components
Jumper Description JP61 JP67 JP62 GR5 Always closed. Always closed. Isolates the line out right positive pin regarding the board. 1-2: diff signal applied on line_out_Right. 2-3: single ended signal applied on line_out_Right.
Default
1-2
JP65
Connects different impedance loads.
Table 27.
LS jumpers A
Default
Jumper Description JP32 JP36 JP34 Connects coupling capacitor. Connects coupling capacitor. Connects different impedance loads.
Table 28.
LS jumpers B
Default
Jumper Description JP31 JP35 J33 Connects coupling capacitor. Connects coupling capacitor. Connects different impedance loads.
Table 29.
HP jumpers A
Default
Jumper Description JP40 JP44 JP46 JP52 JP42 JP48 JP39 JP51 GR2 Shorted when VCM used. Coupling capacitor when VCM is not used. Always closed. Always closed. Shorted when VCM used. Coupling capacitor when VCM is not used. Connects different impedance loads. Connects different impedance loads. Isolates the HP_right pin regarding the board. Isolates the HP_Left pin regarding the board. 1-2: VCM used (JP21 and JP33 are shorted). 2-3: VCM not used (JP21 and JP33 connect coupling capacitor).
1-2
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Main components Table 30. HP jumpers B
Default
UM0411
Jumper Description JP37 JP43 JP45 JP49 JP41 JP47 JP38 JP50 GR1 Shor ted when VCM used. Coupling capacitor when VCM is not used. Always closed. Always closed. Shor ted when VCM used. Coupling capacitor when VCM is not used. Connects different impedance loads. Connects different impedance loads. Isolates the HP_right pin regarding the board. Isolates the HP_Left pin regarding the board. 1-2: VCM used (in this case JP21 and JP33 are shorted). 2-3: VCM not used (in this case JP21 and JP33 connect coupling capacitor).
1-2
1.5.4
Bias micro jumpers
Table 31. Jumpers bias micro A
Default
Jumper Description JP13 JP16 JP15 Connects the MBIAS to microphone on the board. Isolates MBIAS regarding the board. Probes the micro bias or connects different impedance loads.
Table 32.
Jumpers bias micro B
Default
Jumper Description JP14 JP17 JP18 Connects the MBIAS to microphone on the board. Isolates MBIAS regarding the board. Probes the micro bias or connects different impedance loads.
1.5.5
HDET jumpers and switches
Table 33. Jumpers A
Default
Jumper Description JP27 JP29 Connects different impedance loads (microphone biasing resistor equivalent). Connects different impedance loads (microphone impedance equivalent).
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UM0411 Table 34. Jumpers B
Main components
Jumper Description JP28 JP30 Connects different impedance loads (microphone biasing resistor equivalent). Connects different impedance loads (microphone impedance equivalent).
Default
Table 35.
Switch SW1
Switch A
Description Push button Default
Table 36.
Switch SW2
Switch B
Description Push button Default
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Board schematics
UM0411
2
Board schematics
Figure 9: Board schematics: analog inputs Figure 10: Board schematics: audio outputs Figure 11: Board schematics: digital section Figure 12: Board schematics: power supply
24/30
5
a_mic_left_p b_mic_left_p b_mic_bias R2 R4 JP2 5 4 3 2 MK2 WM-64PNT + 1 2 JP4 5 4 3 2 b_mic_left_n R8 a_mic_right_p b_mic_right_p b_mic_bias R10 R12 JP8 G4 2 3 4 5 5 4 3 2 CN7 SSMB 1 5 4 3 2 JP12 b_mic_right_n JP11 JP13 JP14 b_mic_bias b_aux1_l C14 100nF 1 CN10 SSMB G6 JP18 b_aux1_r C16 100nF 1 5 4 3 2 CN12 SSMB 5 4 3 2 a_mic_bias a_aux1_l JP16 a_mbias_src C11 1_MBIAS 1_HDET 1_MIC_L_P 1_MIC_L_N 2_MIC_L_P 2_MIC_L_N 2_MIC_R_P 2_MIC_R_N JP20 F1 D1 D11 H2 G2 H11 G11 E1 E10 G4 H10 JP24 E8 b_aux2_ln a_aux2_ln 100nF 10F 100nF GND_ANA_1 GND_ANA_2 G8 F3 C23 JP25 5 4 3 2 100nF 1 5 4 3 2 CN19 SSMB G9 b_line_in_l b_line_in_r b_aux3_l b_aux3_r b_aux2_lp CN17 SSMB C21 100nF 1 b_aux2_rp b_aux2_rn b_aux2_lp b_aux2_ln b_aux2_rn C20 JP22 5 4 3 2 100nF 1 b_aux1_l b_aux1_r b_aux2_rp C18 100nF 1 CN14 SSMB G8 5 4 3 2 CN16 SSMB 2_CAP_MIC 2_AUX_1_L 2_AUX_1_R 2_AUX_2_L_P 2_AUX_2_L_N 2_AUX_2_R_P 2_AUX_2_R_N 2_AUX_3_L 2_AUX_3_R 2_LINE_IN_L 2_LINE_IN_R 2_CAP_LINE_IN F11 E11 b_mic_rp b_mic_rn 1_MIC_R_P 1_MIC_R_N 1_CAP_MIC 1_AUX_1_L 1_AUX_1_R 1_AUX_2_L_P 1_AUX_2_L_N 1_AUX_2_R_P 1_AUX_2_R_N 1_AUX_3_L 1_AUX_3_R 1_LINE_IN_L 1_LINE_IN_R 1_CAP_LINE_IN F4 E4 b_mic_lp b_mic_ln 2_HDET B1 b_hardware_detect 2_MBIAS C2 E3 D3 F9 E9 F2 a_aux2_rp a_aux1_l a_aux1_r D2 D10 H1 G1 G9 G10 E2 F10 G3 J11 F8 JP23 VCC_ANALOG a_aux2_lp a_aux2_ln a_aux2_rn a_aux2_rp a_aux2_rn a_aux3_l a_aux3_r a_line_in_l a_line_in_r a_aux2_lp C10 a_hardware_detect a_mic_lp a_mic_ln a_mic_rp a_mic_rn b_mbias_src JP17 IC1B Analog Input Section C13 100nF JP15 C15 100nF a_aux1_r C11 100nF 1 C12 100nF CN8 SSMB JP10 R14 R16 680U 1.2K 2 3 4 5 a_mic_rn b_mic_rn MK4 WM-64PNT + 1 2 C10 CN5 SSMB 1 1 C7 100nF a_mic_rp b_mic_rp C8 100nF CN6 SSMB 1.2K 680U 1.2K R6 680U 4.7F C4 G2 2 3 4 5 CN3 SSMB 1 1 JP5 JP6 C6 CN4 SSMB 100nF 2 3 4 5 C5 100nF a_mic_ln b_mic_ln 680U 1.2K 1 1 a_mic_lp b_mic_lp C2 100nF CN2 SSMB
4 2
3 1
UM0411
Figure 9.
R1 CN1 SSMB C1 100nF
1.2K
a_mic_bias
R3 G1
680U
JP1
+
C3
4.7F
MK1 WM-64PNT 1 2
R5
680U
JP3
R7
1.2K
a_mic_left_n
D
D
R9
1.2K
a_mic_bias
R11 G3
680U
JP7
+
C9
4.7F
R13
680U
JP9
R15
1.2K
a_mic_right_n
J1
4 2 3 1
4 2 3 1
J2
a_mbias_sense
CN9 SSMB
1
b_mbias_sense
jack_stereo_3_5
jack_stereo_3_5
G5
2 3 4 5
CN11 SSMB
1
C
JP19
2 3 4 5
4.7F
MK3 WM-64PNT 1 2
C
G7
CN13 SSMB
1
C17 100nF
2 3 4 5
Board schematics: analog inputs
CN15 SSMB
1
C19 100nF
2 3 4 5
JP21
CN18 SSMB
1
C22 100nF
G10
2 3 4 5
CN20 SSMB + STw5098_bga C27
1
C24 100nF
C3 C1 D9 VCC_ANA_1 VCC_ANA_2 VCC_ANA_3
G11 VCC_ANALOG a_aux3_l JP27
CN21 SSMB
1
C28 100nF
a_aux3_r
C26
C25
B
2 3 4 5
JP26
B
b_aux3_r
C29
100nF
1
CN22 SSMB G12 b_aux3_l C31 100nF 1 5 4 3 2 CN24 SSMB
2 3 4 5
CN23 SSMB
1
C30 100nF
JP28
2 3 4 5
Microphone biasing resistor equivalent
b_left_line_in a_hardware_detect 1 2 SW1 BP a_line_in_r a_line_in_l 2 JP29 JP30 SW2 BP 1 C34 100nF 1 1 b_line_in_r C35 100nF 1 CN28 SSMB 5 4 3 2 5 4 3 2 b_hardware_detect 2 b_line_in_l C33 100nF 1 CN26 SSMB G14 1 ESD2 K2 K1 jack_stereo_3_5 J4 4 2 3 1
J3
a_left_line_in
1
4 2 3 1 C32 100nF 2 3 4 5
2
K1
K2
ESD1
jack_stereo_3_5
G13
CN25 SSMB
C
ESDAxxL
3
2 3 4 5
A
ESDAxxL
C
CN27 SSMB
5 4 3 2
A
a_right_line_in
Microphone impedance equivalent
b_right_line_in
Title STw5098 Validation Platform: Analog Inputs section A3 Date: Wednesday, August 10, 2005 Sheet 1 of 4 Rev 1.0
Board schematics
5
4
3
3
2
1
25/30
2 3 4 5
a_ls_n JP33 JP34 J7 K8 1_LS_N 1_LS_N_F 2_LS_N 2_LS_N_F 2_CAP_LS G16 b_lsp_n_o a_hp_l_src K3 1_HP_L JP36 L4 K4 L11 J3 H3 J9 H9 K11 K6 K7 3 L2 H4 K1 JP42 b_hp_l_com 2 STw5098_bga b_hp_lr_common SEL SEL a_hp_r_com b_hp_r_com JP48 JP46 5 4 3 2 G18 b_hp_l_src JP51 b_hp_l_decoup JP52 5 4 3 2 b_hp_l 1 CN40 SSMB 1 22F 10F 100nF 100nF 10F 100nF JP45 + C41 C39 C42 C40 C43 + + JP50 JP49 C38 a_hp_l a_hp_l_decoup a_hp_l_src JP47 CN38 SSMB 3 JP44 5 4 3 2 1 2 1 3 2 4 J8 1 GR2 b_vcm_hp 1 CN36 SSMB JP39 JP40 5 4 3 2 b_hp_r_src b_hp_r b_hp_r_decoup 1 CN34 SSMB ESD4 C b_line_out_r_p b_line_out_r_n b_line_out_l_p b_line_out_l_n b_hp_r_src b_vcm_hp 5 4 3 2 1_VCM_HP 1_VCM_HP_F 2_VCM_HP 2_VCM_HP_F 2_HP_R 2_LINE_OUT_L_P 2_LINE_OUT_L_N 2_LINE_OUT_R_P 2_LINE_OUT_R_N GND_P_1 GND_P_2 GND_P_3 GND_P_4 L1 1_VCC_P_1 1_VCC_P_2 2_VCC_P_1 2_VCC_P_2 2_GND_CM 1_GND_CM L10 JP43 JP41 H7 a_vcm_hp K2 3 GR1 1 2 a_hp_lr_common a_hp_l_com 1_HP_R 1_LINE_OUT_L_P 1_LINE_OUT_L_N 1_LINE_OUT_R_P 1_LINE_OUT_R_N VCC_LS_1 VCC_LS_2 VCC_LS_3 2_HP_L J5 L3 H8 J2 J1 K10 J10 K5 VCC_LS J8 K9 JP37 a_hp_r a_hp_r_decoup a_hp_r_src JP38 VCC_P J4 a_vcm_hp a_hp_r_src a_line_out_l_p a_line_out_l_n a_line_out_r_p a_line_out_r_n b_hp_l_src 1 CN32 SSMB L7 C37 + 10F 1_CAP_LS J6 L8 L9 C36 10F 5 4 3 2 + 4 2 3 1
2 3 4 5
C
3
ESDAxxL
2 3 4 5
K2
K1
K1
ESD3
2
1
C
2 3 4 5
K2
CN35 SSMB
1
ESDAxxL
2 3 4 5
B
JP53 a_line_out_l_p JP54 b_line_out_l_p JP55 JP57 JP58 JP56 5 4 3 2 ESD6 GR4 a_line_out_l_n b_line_out_l_n 1 2 3 SEL b_left_line_out b_right_line_out JP61 a_line_out_r_p JP62 b_line_out_r_p JP63 JP65 JP66 JP64 5 4 3 2 1 CN46 SSMB 4 2 3 1 3 JP60 SEL 5 4 3 2 1 CN44 SSMB G20 2 1 K1 C K2 ESDAxxL J10 3 1 CN42 SSMB
2 3 4 5
ESD5 JP59 2 GR3 1
3
K1
1
C
K2
2
2 3 4 5
J9
4 2 3 1
a_left_line_out a_right_line_out
2 3 4 5
2 3 4 5
2 3 4 5
SEL SEL
Title STw5098 Validation Platform: Audio outputs section A3 Date: Thursday, August 11, 2005 Sheet 2 of 4 Rev 1.0
UM0411
5
4
3
5 4 3 2
26/30
4 2
JP31 a_ls_p H6 H5 1_LS_P 1_LS_P_F 2_LS_P 2_LS_P_F JP32 b_ls_n J6 L6 L5 1 b_lsp_p_o CN30 SSMB b_ls_p IC1C Power Output Section
5
3 1
CN29 SSMB
1
a_lsp_p_o
J5
4 2 3 1 JP35
jack_stereo_3_5
G15
Board schematics
D
CN31 SSMB
1
a_lsp_n_o
jack_stereo_3_5
D
CN33 SSMB
1
J7
C
1 3 2 4
jack_stereo_3_5
1
Figure 10. Board schematics: audio outputs
jack_stereo_3_5
G17
CN37 SSMB
CN39 SSMB
1
B
CN41 SSMB
1
CN43 G19 SSMB
1
ESDAxxL
jack_stereo_3_5
CN45 SSMB
1
jack_stereo_3_5
GR6 a_line_out_r_n b_line_out_r_n 1 2
JP67 2 3
GR5 1
A
CN47 G21 SSMB
1
1 3 JP68
CN48 SSMB
G22
A
2
1
5
4 3 2
1
VCC_3V3 J11 1_IRQ 1_AD_OCK 1_DA_OCK ad_sync_ls_a ad_ck_ls_a ad_data_ls_a C8 A6 C7 1_AD_SYNC 1_AD_CK 1_AD_DATA 2_IRQ 2_AD_OCK B3 C9 1_DA_SYNC 1_DA_CK 1_DA_DATA A10 D6 A11 A5 da_ock_ls_a A3 ad_ock_ls_a D8 irq_ls_a pll_power_down amck_app C44 amck_ena IC2 3 2 5 R18 15pF 21 CLK Y1 8MHz 7 X/ICLK X2 REF amck_app_ls 2 1 VCC_CORE B7 1_2_AMCK VCC_CORE_1 VCC_CORE_2 VCC_IO STw5098_bga C51 C52 + 10F 100nF GND_D1 GND_D2 A1 B11 D4 B8 + D5 VCC_IO 10F JP69 2 3 4 5 C49 DOUBLE_GRAIN CN49 SMB 1 amck_ext nPD VDD VDD C50 S0 S1 S2 HEADER 15X2 GR7 3 3 4 5 2_AD_SYNC 2_AD_CK 2_AD_DATA S0 S1 S2 A9 C6 A8 ad_sync_ls_b ad_ck_ls_b ad_data_ls_b amck_actual 4 1 6 8 22 19 VCC_3V3 23 6 ad_ck_ls_a da_ock_ls_a ad_ck_ls_b sclk_ls_b sclk_ls_a cmod_ls_b sclk_ls_b sda_sdin_ls_b as_csb_ls_b C4 B2 A4 A7 2_CMOD 2_SCLK 2_SDA / SDIN 2_AS / CSB 2_DA_OCK 2_DA_SYNC 2_DA_CK 2_DA_DATA B5 B9 B6 B10 R17 50U as_csb_ls_a irq_ls_b ad_data_ls_a da_data_ls_b da_sync_ls_a ad_data_ls_b sda_sdin_ls_b cmod_ls_b cmod_ls_a sclk_ls_a sda_sdin_ls_a as_csb_ls_a B4 A2 C5 D7 1_CMOD 1_SCLK 1_SDA / SDIN 1_AS / CSB da_sync_ls_a da_ck_ls_a da_data_ls_a irq_ls_b ad_ock_ls_b
D
pll_clk IC1A Digital Section cmod_ls_a irq_ls_a ad_sync_ls_a da_sync_ls_b da_data_ls_a ad_sync_ls_b as_csb_ls_b sda_sdin_ls_a
UM0411
Global Clock ONLY! pll_clk
JH1
D
1M
C45 15pF
R0 R1 R2 R3 R4 R5 R6 amck_app_ls da_ck_ls_b da_ck_ls_a da_ock_ls_b ad_ock_ls_b ad_ock_ls_a
24 25 26 27 28 1 2
R0 R1 R2 R3 R4 R5 R6
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 da_ock_ls_b da_sync_ls_b da_ck_ls_b da_data_ls_b
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
10F
100nF
R19 47K + 100nF C46 OSCaR C47 C48 9 20 GND GND
100nF
R0 R1 R2 R3 R4 R5 R6 S0 S1 S2 V0 V1 V2 V3 V4 V5 V6 V7 V8 irq_a irq_b ad_ock_a da_ock_a ad_ock_b da_ock_b ad_if_dir_a da_if_dir_a da_if_dir_b da_data_a da_data_b a_da_ck b_da_ck a_da_sync b_da_sync ad_data_b ad_data_a a_ad_ck b_ad_ck a_ad_sync b_ad_sync a_sda_in b_sda_in a_sda_out b_sda_out sclk_a sclk_b as_csb_a as_csb_b cmod_a V0 V1 V2 V3 V4 V5 V6 V7 V8 10 11 12 13 14 15 16 17 18 V0 V1 V2 V3 V4 V5 V6 V7 V8 cmod_b
ad_if_dir_b
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63
HEADER 32x2
C
C
Bidir D_A Part A Bidir A_D Part A
VCC_3V3 IC4 1 VCCA VCCB VCCB 1 C54 R24 100nF GND 100nF a_ad_sync a_ad_ck 4 3 2 1 RR2 RR4 10K LVC4245_MONO 10K RR3 10K 5 6 7 8 4 3 2 1 4 3 2 1 3 4 5 6 7 8 9 10 A0 A1 A2 A3 A4 A5 A6 A7 ad_sync_ls_a ad_ck_ls_a 5 6 7 8 da_data_a cmod_a sclk_a as_csb_a da_data_b cmod_b sclk_b as_csb_b 11 12 GND GND GND 13 C58 R25 4.7K 2 22 DIR nOE 13 4.7K VCCA VCCB VCCB 24 23 C57 IC5 DIR nOE GND GND R21 C53 C56 100nF 13 100nF 11 12 R23 4.7K 2 22 4.7K 24 23 VCC_3V3 ad_if_dir_a MAIN_VCC MAIN_VCC
VCC_3V3
da_if_dir_a
IC3
To_Codec
MAIN_VCC
Figure 11. Board schematics: digital section
1
VCCA
R20
4.7K
VCCB VCCB
24 23
2 22
C55
R22
4.7K
DIR nOE
VCC_3V3
MAIN_VCC
VCC_3V3
100nF
11 12
GND GND
GND
5
IC6 74_1G_07 VCC
5 R26 470U a_sda_out
100nF
IC7 74_1G_07 VCC
R27 470U
a_da_sync a_da_ck da_sync_ls_a da_ck_ls_a 5 6 7 8 3 4 5 6 7 8 9 10 A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 21 20 19 18 17 16 15 14
NC
GND
NC
RR1
10K
3 4 5 6 7 8 9 10
1
3
1
LVC4245_MONO
B0 B1 B2 B3 B4 B5 B6 B7 LVC4245_MONO
21 20 19 18 17 16 15 14
da_data_ls_a cmod_ls_a sclk_ls_a as_csb_ls_a da_data_ls_b cmod_ls_b sclk_ls_b as_csb_ls_b
B
3
A0 A1 A2 A3 A4 A5 A6 A7
B0 B1 B2 B3 B4 B5 B6 B7
21 20 19 18 17 16 15 14
GND
5 6 7 8
4 3 2 1
2
A
Y
4
2
A
Y
4
5 6 7 8 5 6 7 8 RR6 10K
4 3 2 1
4 3 2 1
sda_sdin_ls_a a_sda_in
B
RR5
10K
Bidir D_A Part B Bidir A_D Part B
VCC_3V3 IC9 1 VCCA DIR nOE C60 C64 100nF GND 13 100nF GND GND R29 C59 C63 100nF 13 100nF 11 12 R34 4.7K 2 22 4.7K VCCB VCCB 24 23 ad_if_dir_b MAIN_VCC MAIN_VCC 24 23
VCC_3V3
da_if_dir_b
IC8
VCC_3V3
From_Codec
IC10 1 R30 R35 4.7K 4.7K 11 12 2 22 VCCA DIR nOE GND GND GND VCCB VCCB
VCC_3V3 MAIN_VCC 24 23 C61 100nF 13 b_sda_out 2 A NC
MAIN_VCC
VCC_3V3
1
VCCA
5
R28
4.7K
2 22
VCCB VCCB
VCC
100nF
11 12
GND GND
GND
Y GND
4
2
VCC
C62
R33
4.7K
DIR nOE
IC11 74_1G_07
5 R31 470U
IC12 74_1G_07
R32 470U
A NC
Y GND 1 3 1 4 3 2 1 RR10 10K sda_sdin_ls_b b_sda_in LVC4245_MONO IC13 amck_ena amck_app 1 2 3 n1G 1A GND VCC 1Y 74LX1G125 C65 100nF A3 Date: Wednesday, August 10, 2005
3 2
4
b_da_sync b_da_ck da_sync_ls_b da_ck_ls_b 5 6 7 8 4 3 2 1 RR8 RR9 10K 10K 5 6 7 8 4 3 2 1 3 4 5 6 7 8 9 10 A0 A1 A2 A3 A4 A5 A6 A7 LVC4245_MONO B0 B1 B2 B3 B4 B5 B6 B7 21 20 19 18 17 16 15 14
b_ad_sync b_ad_ck
5 6 7 8
4 3 2 1
ad_sync_ls_b ad_ck_ls_b 5 6 7 8
RR7
10K
3 4 5 6 7 8 9 10
A0 A1 A2 A3 A4 A5 A6 A7
B0 B1 B2 B3 B4 B5 B6 B7
21 20 19 18 17 16 15 14
irq_a ad_ock_a da_ock_a ad_data_a irq_b ad_ock_b da_ock_b ad_data_b
3 4 5 6 7 8 9 10
A0 A1 A2 A3 A4 A5 A6 A7
B0 B1 B2 B3 B4 B5 B6 B7
21 20 19 18 17 16 15 14
irq_ls_a ad_ock_ls_a da_ock_ls_a ad_data_ls_a irq_ls_b ad_ock_ls_b da_ock_ls_b ad_data_ls_b
A
3
LVC4245_MONO
A
5 6 7 8 5 6 7 8 RR12 10K 4 3 2 1
4 3 2 1
MAIN_VCC 5 4 amck_app_ls Title R36 470U STw5098 Validation Platform: Digital section Rev 1.0 Sheet
1
RR11 10K
3
of
4
Board schematics
5
4
27/30
JP73
JP74
JP75
JP76
JP77
GND/TAB
C66 100nF +
GND/TAB
3
3
28/30
VCC_ANALOG VCC_IO VCC_CORE VCC_LS VCC_P VCC_3V3 JP79 IC15 REGULATOR_FIXED_TAB 2 + OUT IN 1 C69 100nF C68 22uF 16V OUT C67 22uF 16V 2
Board schematics
Figure 12. Board schematics: power supply
VCC_3V3
IC14 REGULATOR_FIXED_TAB
1
IN
UM0411
UM0411
Revision history
3
Revision history
Table 37.
Da te 11-Apr-2007
Document revision history
Revision 1 Cha nge s Initial release.
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UM0411
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