ST's 65nm Design Platform offers two standard cell libraries, optimized for performance and density, which provide a rich portfolio of more than 1500 cells, multiple voltage I/O cells, multiple memories and analog IPs.
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more than 800,000 gates per mm2 |
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core supply of 1.0V or 1.2V |
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metal pitches of 0.20micron |
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from 6 to 10 metal routing layers |
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The 65nm CMOS design platform takes full advantage of the multiple features and modularity of the process technology developed by the Crolles2 Alliance of STMicroelectronics, Freescale Semiconductor and Philips Semiconductors.
For example several services are available to ease access to the technology, including: |
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fast prototype cycle time, which is down to less than one week and has been proven for 130-nm ICs |
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cost reduction in mask sets |
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use of e-beam technology which allows customization without the need for masks |
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a shuttle multi-project reticle service started for 65nm designs |
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Core Process Features |
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65nm poly length |
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Dual or tripple Vt MOS transistors |
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Dual or tripple gate oxyde |
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Dedicated process flavors for high performance or low power |
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Dual-damascene copper for interconnect |
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Low-k (k = 2.9) dielectric |
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6 to 10 metal layers for interconnect |
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0.20micron metalization pitch |
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Analog/RF capabilities |
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Fully compatible with e-DRAM |
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Various power supplies supported: 2.5V, 1.8V, 1.2V, 1V |
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Library Features |
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Full range of 1.2V, 1.8V, 2.5V I/O cells |
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Extremely dense embedded memories, including single-port memories using 6T-SRAM of 0.5-square-micron area, dual-port memories, and Read-Only-Memories |
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Core lib supply voltage of 1.0V or 1.2V |
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Fully compatible, low-cost process variant, allowing up to 64-Mbit of embedded DRAM with a memory cell area of 0.12-square-micron |
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Power reduction techniques such as adaptive and low Vdd operation, power shutdown, and low standby current in standby mode |
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Broad portfolio of analog and RF IP is under development to cover the need for single system super-integration |
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Complex IP modules such as microcontrollers and digital signal processors |
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Design Tools Platform |
| The 65nm design platform is fully supported by the industry's leading CAD tools from Cadence, Mentor Graphics, and Synopsys. These tools have all been developed in close cooperation with the R&D teams of the EDA partners. |
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