STi7100Low cost HDTV set-top box decoder for H.264/AVC and MPEG-2
The STi7100 is a new generation, high-definition set-top box decoder chip, and provides very high performance for low-cost HD systems. With enhanced performances over the STi7710, it includes an H.264/AVC decoder for new low-bitrate applications, as well as dual-decode MPEG-2 capability.
Based on the Omega2 (STBus) architecture, this system on chip is a full back-end processing solution for digital terrestrial, satellite and cable high-definition set-top boxes compliant with ATSC, DVB, DIRECTV, DCII, OpenCable and ARIB BS4 specifications.
The STi7100 demultiplexes, decrypts and decodes a single HD or SD video stream with associated multichannel audio. Video is output to two independently formatted displays: a full resolution display intended for a TV monitor, and a downsampled display intended for a VCR, or alternatively a second SD TV. Connection to a TV or display panel can be via an analog component interface or a copy protected DVI/HDMI interface. Composite outputs are provided for connection to the VCR with Macrovision protection. Audio is output with optional PCM mixing to an S/PDIF interface, PCM interface or via integrated stereo audio DACs.
Digitized analog programs can also be input to the STi7100 for reformatting and display.
The STi7100 includes a graphics rendering and display capability with a 2D graphics accelerator, two graphics planes and a cursor plane. A dual display compositor provides mixing of graphics and video with independent composition for each of the TV and VCR outputs.
The STi7100 includes a stream merger to allow five different transport streams from different sources to be merged and processed concurrently. Applications include DVR time shifted viewing of a terrestrial program while acquiring an EPG/data stream from a satellite or cable front end.
The flexible descrambling engine is compatible with required standards including DVB, DES, AES and Multi2.
The STi7100 embeds a 266 MHz ST40 CPU for applications and device control. A dual DDR1 SDRAM memory interface is used for higher performance, to allow the video decoder the required memory bandwidth for HD H.264 decoding and sufficient bandwidth for the CPU and the rest of the system. A second memory bus is also provided for flash memory storing resident software and for connection of peripherals.
A hard-disk drive (HDD) can be connected either to the serial ATA interface or as an expansion drive via the USB 2.0 port. The USB port can also be used to connect to a DOCSIS 2.0 CM gateway for interactive cable applications.
The STi7100 is supported by STMicroelectronics’ STAPI software, and is compatible with several other related devices such as the STi7109.
- The STi7100 is a single-chip, high-definition STB decoder including:
ST40 CPU core, 266 MHz dual ST231 CPU cores for audio and video decoding, both 400 MHz transport filtering and descrambling video decoder: H.264/AVC and MPEG-2 graphics engine and dual display: high-definition (HD) and standard definition (SD) audio decoder
- The STi7100 also Features the following embedded interfaces:
USB 2.0 DVI/HDMI output digital audio and video auxiliary input modem serial ATA
DB0150: Low cost HDTV set-top box decoder for H.264/AVC and MPEG-2
Sample & BuyTop
|Part Number||Marketing Status||General Description||Demodulation integrated||Core||Memory Technology||Video output format||Connectivity supported|
|STI7100EWC||NRND||Low cost HDTV set-top box decoder for H.264/AVC and MPEG-2||None||ST40||DDR1-DRAM||SD;HD|
|STI7100HWC||NRND||Low cost HDTV set-top box decoder for H.264/AVC and MPEG-2||None||ST40||DDR1-DRAM||SD;HD|
|STI7100NWC||NRND||Low cost HDTV set-top box decoder for H.264/AVC and MPEG-2||None||ST40||DDR1-DRAM||SD;HD|
|STI7100PWC||NRND||Low cost HDTV set-top box decoder for H.264/AVC and MPEG-2||None||ST40||DDR1-DRAM||SD;HD|
|STI7100YWC||NRND||Low cost HDTV set-top box decoder for H.264/AVC and MPEG-2||None||ST40||DDR1-DRAM||SD;HD|
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